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IS25C32B
32K-BIT SPI AUTOMOTIVE EEPROM
Advanced Information SEPTEMBER 2009
FEATURES
* Serial Peripheral Interface (SPI) Compatible -- Supports SPI Modes 0 (0,0) and 3 (1,1) * Wide Voltage Operation -- Vcc = 2.7V to 3.6V * Low power CMOS -- Active current: 4 mA (max) -- Standby current: 5 A (max) * Block Write Protection -- Protect 1/4, 1/2, or Entire Array * 32 byte page write mode -- Partial page writes allowed * 10 MHz Clock Rate (3.6V) * Self timed write cycles -- 5 ms max @ 2.7V * High-reliability -- Endurance: 1 million cycles -- Data retention: 100 years * Temperature: -40oC to 125oC * Packages (8-pin): SOIC/SOP and TSSOP
DESCRIPTION
The IS25C32B is an electrically erasable PROM device that uses the Serial Peripheral Interface (SPI) for communications. The IS25C32B is 32Kbit (4096 x 8). It is offered in a wide operating voltage range of 2.7V to 3.6V to be compatible with most application voltages. ISSI designed the IS25C32B to be an efficient SPI EEPROM solution. The devices are packaged in 8-pin SOIC (JEDEC) and 8-pin TSSOP. The functional features of the IS25C32B allows them to be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin, and a 3-wire interface of Serial Data In (SI), Serial Data Out (SO), and Serial Clock (SCK). While the 3-wire interface of the IS25C32B provides for high-speed access, a HOLD pin allows the memories to ignore the interface in a suspended state; later the HOLD pin reactivates communication without re-initializing the serial sequence. A Status Register facilitates a flexible write protection mechanism, and a device-ready bit (RDY).
Copyright (c) 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace systems, or for other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Advanced Information Rev. 00B 08/27/09
Integrated Silicon Solution, Inc. -- www.issi.com
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IS25C32B-Automotive
PIN CONFIGURATION 8-Pin SOIC and TSSOP
CS SO WP GND
1 2 3 4
8 7 6 5
VCC HOLD SCK SI
PIN DESCRIPTIONS
CS SCK SI SO GND Vcc WP HOLD Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Write Protect Suspends Serial Input
Chip Select (CS): The CS pin activates the device. Upon power-up, CS should follow Vcc. When the device is to be enabled for instruction input, the signal requires a High-to-Low transition. While CS is stable Low, the master and slave will communicate via SCK, SI, and SO signals. Upon completion of communication, CS must be driven High. At this moment, the slave device may start its internal write cycle. When CS is high, the device enters a power-saving standby mode, unless an internal write operation is underway. During this mode, the SO pin becomes high impedance. Write Protect (WP): The purpose of this input signal is to initiate Hardware Write Protection mode. This mode prevents the Block Protection bits and the WPEN bit in the Status Register from being altered. To cause Hardware Write Protection, WP must be Low at the same time WPEN is 1. WP may be hardwired to Vcc or GND. HOLD (HOLD): This input signal is used to suspend the device in the middle of a serial sequence and temporarily ignore further communication on the bus (SI, SO, SCK). Together with Chip Select, the HOLD signal allows multiple slaves to share the bus. The HOLD signal transitions must occur only when SCK is Low, and be held stable during SCK transitions. (See Figure 8 for Hold timing) To disable this feature, HOLD may be hardwired to Vcc.
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides synchronization between the microcontroller and IS25C32B. Op-Codes, byte addresses, and data are latched on SI with a rising edge of the SCK. Data on SO is refreshed on the falling edge of SCK for SPI modes (0,0) and (1,1). Serial Data Input (SI): This is the input pin for all data that the IS25C32B is required to receive. Serial Data Output (SO): This is the output pin for all data transmitted from the IS25C32B.
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SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal. SLAVE: The IS25C32B is a slave because the clock signal is an input. TRANSMITTER/RECEIVER: The IS25C32B has both data input (SI) and data output (SO). MSB: The most significant bit. It is always the first bit transmitted or received. OP-CODE: The first byte transmitted to the slave following CS transition to LOW. If the OP-CODE is a valid member of the IS25C32B instruction set (Table 3), then it is decoded appropriately. If the OP-CODE is not valid, and the SO pin remains in high impedance.
BLOCK DIAgRAM
VCC GND
STATUS REGISTER
4096 x 8 MEMORY ARRAY
DATA REGISTER SI MODE DECODE LOGIC ADDRESS DECODER OUTPUT BUFFER
CS WP
SCK
CLOCK
SO
HOLD
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STATUS REgISTER
The status register contains 8-bits for write protection control and write status. (See Table 1). It is the only region of memory other than the main array that is accessible by the user. Bit 6 Bit 5 Bit 4 X X X Bit 3 Bit 2 Bit1 Bit 0 BP1 BP0 WEN RDY
Table 1. Status Register Format
Bit 7 WPEN
Block Protect (BP1, BP0), Bits 2-3: Together, these bits represent one of four block protection configurations implemented for the memory array. (See Table 2 for details.) BP0 and BP1 are non-volatile cells similar to regular array cells, and factory programmed to 0. The block of memory defined by these bits is always protected, regardless of the setting of WPEN, WP , or WEN.
Notes: 1. X = Don't care bit. 2. During internal write cycles, bits 0 to 7 are temporarily 1's.
Table 2. Block Protection
Status Register Bits
0 0 1 1 0 1 0 1
Level
BP1 BP0
IS25C32B None 0C00h -0FFFh 0800h -0FFFh
Array Addresses Protected
The Status Register is Read-Only if either: a) Hardware Write Protection is enabled or b) WEN is set to 0. If neither is true, it can be modified by a valid instruction. Ready (RDY), Bit 0: When RDY = 1, it indicates that the device is busy with a write cycle. RDY = 0 indicates that the device is ready for an instruction. If RDY = 1, the only command that will be handled by the device is Read Status Register. Write Enable (WEN), Bit 1: This bit represents the status of device write protection. If WEN = 0, the Status Register and the entire array is protected from modification, regardless of the setting of WPEN, WP pin, or block protection. The only way to set WEN to 1 is via the Write Enable command (WREN). WEN is reset to 0 upon power-up.
0 1(1/4) 2(1/2) 3(All)
-0FFFh
0000h
Don't Care, Bits 4-6: Each of these bits can receive either 0 or 1, but values will not be retained. When these bits are read from the register, they are always 0. Write Protect Enable (WPEN), Bit 7: This bit can be used in conjunction with WP pin to enable Hardware Write Protection, which causes the Status Register to be read-only. The memory array is not protected by this mode. Hardware Write Protection requires that WP = 0 and WPEN = 1; it is disabled otherwise. Note: WPEN cannot be changed from 1 to 0 if the WP pin is already set to Low. (See Table 4 for data protection relationship)
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DEVICE OPERATION The operations of the IS25C32B are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal programming were underway.
Table 3. Instruction Set
Name
WREN WRDI RDSR WRSR READ WRITE 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010
Op-code
Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Array Write Data to Array
Operation
Address
A15-A0 A15-A0
Data(SI)
D7-D0 D7-D0,...
Data (SO)
D7-D0,... D7-D0,... -
1. X = Don't care bit. For consistency, it is best to use "0". 2. Some address bits are don't care. See Table 5. 3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or Status Register to be ignored. WRITE ENABLE (WREN) When Vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. Upon completion of Write Disable (WRDI), Write Status Register (WRSR), or Write Data to Array (WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a WREN instruction is necessary to set WEN to 1. (See Figure 2 for timing). WRITE DISABLE (WRDI) The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing). READ STATUS REgISTER (RDSR) The Read Status instruction tells the user the status of Write Protect Enable, the Block Protection setting (see Table 2), the Write Enable state, and the RDY status. RDSR is the only instruction accepted when a write cycle is underway. It is recommended that the status of Write Enable and RDY be checked, especially prior to an attempted modification of data. The 8 bits of the Status Register can be repeatedly output on SO after the initial Op-code. (See Figure 4 for timing).
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IS25C32B-Automotive
WRITE STATUS REgISTER (WRSR) This instruction lets the user choose a Block Protection setting, and set or reset the WPEN bit. The values of the other data bits incorporated into WRSR can be 0 or 1, and are not stored in the Status Register. WRSR will be ignored unless both the following are true: a) WEN = 1, due to a prior WREN instruction; and b) Hardware Write Protection is not enabled. (See Table 4 for details). Except for the RDY status, the values in the Status Register remain unchanged until the moment when the write cycle is complete and the register is updated. Note: WPEN can be changed from 1 to 0 only if WP is already set High. Once completed, WEN is reset for complete chip write protection. (See Figure 5 for timing). READ DATA (READ) This instruction begins with the op-code and the 16bit address, and causes the selected data byte to be shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the highest address is output, the address rolls-over to the lowest address in the array, and the output could loop indefinitely. At any time, a rising CS signal completes the operation. (See Figure 6 for timing).
WRITE DATA (WRITE) The WRITE instruction begins with the op-code, the 16-bit address of the first byte to be modified, and the first data byte. Additional data bytes may be written sequentially to the array after the first byte. Each WRITE instruction can affect the contents of a 32 byte page, but no more. The page begins at address XXXXXXXX XXX00000, and ends with XXXXXXXX XXX11111. If the last byte of the page is input, the address rolls over to the beginning of the same page. More than 32 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 32 bytes. The region of the array defined within Block Protection cannot be modified as long as that block configuration is selected. The region of the array outside the Block Protection can only be modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction occur prior to WRITE. Hardware Write Protection has no affect on the memory array. Once Write is completed, WEN is reset for complete chip write protection. (See Figure 7 for timing).
Table 5. Address Key
Name AN Don't Care Bits IS25C32B A11-A0 A15-A12
Table 4. Write Protection
WPEN
0 0 1 1
WP X X
0 0
Hardware Write Protection
Not Enabled Not Enabled Enabled Enabled Not Enabled Not Enabled
WEN
0 1 0 1 0 1
Inside Block
Read-only Read-only Read-only Read-only Read-only Read-only
Outside Block
Read-only Unprotected Read-only Unprotected Read-only Unprotected
Status Register (WPEN, BP1, BP0)
Read-only Unprotected Read-only Read-only Read-only Unprotected
X X
1 1
Note: X = Don't care bit.
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IS25C32B-Automotive
ABSOLUTE MAXIMUM RATINgS
Symbol Vs Vp Tbias TsTg iouT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to + 6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA
Notes: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATINg RANgE (IS25C32B-3)
Vcc 2.7V to 3.6V Ambient Temperature -40C to +125C grade Automotive (A3)
CAPACITANCE(1,2)
Symbol cin couT Parameter Input Capacitance Output Capacitance Conditions Vin = 0V VouT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. Test conditions: Ta = 25c, f = 1 MHz, Vcc = 3.3V.
DC ELECTRICAL CHARACTERISTICS
Ta = -40C to +125C (Automotive) Symbol Parameter* Vol Output LOW Voltage VoH Output HIGH Voltage ViH Input HIGH Voltage Vil Input LOW Voltage ili Input Leakage Current ilo Output Leakage Current icc Operating Current isb Standby Current Test Conditions Vcc = 3.3V, iol = 2 mA Vcc = 3.3V, ioH = -2 mA Min. Max. -- 0.4 0.8 x Vcc -- 0.7x Vcc Vcc + 1 -0.3 0.3 x Vcc -2 2 -2 2 -- 4.0 -- 5.0 Unit V V V V A A mA A
Vin = 0V To Vcc VouT = 0V To Vcc, CS = Vcc Read/Write at 10 MHz Vcc =3.3V, Vin = Vcc or GND CS = Vcc Note: The parameters are characterized but not 100% tested
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AC Characteristics
Ta = -40C to +125C (Automotive) Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time
2.7V Vcc < 3.6V
Min 0 -- -- 40 40 50 50 50 10
Max 10 2 2 -- -- -- -- -- -- -- -- -- 40 -- 40 40 40 5
Units MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Data In Hold Time 10 tHD Hold Setup Time 10 tCD Hold Hold Time 10 tV Output Valid 0 tHO Output Hold Time 0 tLZ Hold to Output Low Z 0 tHZ Hold to Output High Z -- tDIS Output Disable Time -- tWC Write Cycle Time -- Note: The parameters are characterized but not 100% tested
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TIMINg DIAgRAMS
Figure 1. Synchronous Data Timing
tCS tCSS SK VIH VIL VIH VIL tSU tH tWH tWL tCSH
CS
VIH VIL
DIN
VALID IN tV tHO tDIS
HIGH-Z
VOH DOUT VOL
HIGH-Z
Figure 2. WREN Timing
CS SK DIN DOUT
WREN OP-CODE HIGH-Z
Figure 3. WRDI Timing
CS SK DIN DOUT
WRDI OP-CODE HIGH-Z
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IS25C32B-Automotive
Figure 4. RDSR Timing
CS SK Din Dout Instruction DATA OUT 76543210
Figure 5. WRSR Timing
CS SK Din Dout
Figure 6. READ Timing
Instruction
DATA IN 76543210
CS SK Instruction Din Dout
10
BYTE Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA OUT 76543210
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Advanced Information Rev. 00B 08/27/09
IS25C32B-Automotive
Figure 7. WRITE Timing
CS SK Instruction Din Dout BYTE Address DATA IN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Figure 8. HOLD Timing
CS tCD SCK tHD HOLD tHZ DOUT tLZ tHD tCD
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IS25C32B-Automotive
ORDERINg INFORMATION Automotive (A3): -40C to +125C, Lead-free*
Voltage Range 2.7V to 3.6V Part Number* IS25C32B-3GLA3-TR IS25C32B-3ZLA3-TR Package (8-pin) 150 mil SOIC 3 x 4.4 mm TSSOP
* 1. Contact ISSI Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel "-TR" (4K per reel). 3. Samples are only available in tube, IS25C32B-3GLA3. 4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.
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IS25C32B-Automotive
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IS25C32B-Automotive
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REVISION HISTORY
Rev. 00A 00B Date July 2009 Aug 2009 Description Initial version Updated to A3 Grade
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