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PCF2119x
LCD controllers/drivers
Rev. 05 -- 13 August 2009 Product data sheet
1. General description
The PCF2119x is a low power CMOS1 LCD controller and driver, designed to drive a dot matrix LCD display of 2-lines by 16 characters or 1-line by 32 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2119x interfaces to most microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter `x' in PCF2119x characterizes the built-in character set. Various character sets can be manufactured on request. In addition 16 user defined symbols (5 x 8 dot format) are available.
2. Features
I Single-chip LCD controller and driver I 2-line display of up to 16 characters plus 160 icons or 1-line display of up to 32 characters plus 160 icons I 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese) and user defined symbols I Reduced current consumption while displaying icons only I Icon blink function I On-chip: N Configurable 4, 3 or 2 times voltage multiplier generating LCD supply voltage, independent of VDD, programmable by instruction (external supply also possible) N Temperature compensation of on-chip generated VLCDOUT: -0.16 %/K to -0.24 %/K (programmable by instruction) N Generation of intermediate LCD bias voltages N Oscillator requires no external components (external clock also possible) I Display Data RAM (DDRAM): 80 characters I Character Generator ROM (CGROM): 240 characters (5 x 8) I Character Generator RAM (CGRAM): 16 characters (5 x 8); 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application I 4-bit or 8-bit parallel bus and 2-wire I2C-bus interface I CMOS compatible I 18 row and 80 column outputs I Multiplex rates 1:18 (2-line display or 1-line display), 1:9 (for 1-line display of up to 16 characters and 80 icons) and 1:2 (for icon only mode)
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
NXP Semiconductors
PCF2119x
LCD controllers/drivers
I Uses common 11 code instruction set (extended) I Logic supply voltage: VDD1 - VSS1 = 1.5 V to 5.5 V (chip may be driven with two battery cells) I LCD supply voltage: VLCDOUT - VSS2 = 2.2 V to 6.5 V I VLCD generator supply voltage: VDD2 - VSS2 = 2.2 V to 4 V and VDD3 - VSS2 = 2.2 V to 4 V I Direct mode to save current consumption for icon mode and multiplex drive mode 1:9 (depending on VDD2 value and LCD liquid properties) I Very low current consumption (20 A to 200 A): N Icon mode: < 25 A N Power-down mode: < 2 A I Icon mode is used to save current. When only icons are displayed, a much lower LCD operating voltage can be used and the switching frequency of the LCD outputs is reduced; in most applications it is possible to use VDD as LCD supply voltage
3. Applications
I Telecom equipment I Portable instruments I Point-of-sale terminals
4. Ordering information
Table 1. Ordering information Package Name PCF2119AU/2DA/2 PCF2119x PCF2119DU/2/2 PCF2119FU/2/F2 PCF2119RU/2/F2 PCF2119SU/2/F2 PCF2119VU/2/F2 PCF2119x PCF2119x PCF2119x PCF2119x PCF2119x Description bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm Version PCF2119x PCF2119x PCF2119x PCF2119x PCF2119x PCF2119x Type number
5. Marking
Table 2. Marking codes Marking code PC2119-2 PC2119-2 PC2119-2 PC2119-2 PC2119-2 PC2119-2 Type number PCF2119AU/2DA/2 PCF2119DU/2/2 PCF2119FU/2/F2 PCF2119RU/2/F2 PCF2119SU/2/F2 PCF2119VU/2/F2
PCF2119X_5
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6. Block diagram
C1 to C80 60 to 99, 101 to 140 80 44 to 49 BIAS VOLTAGE GENERATOR COLUMN DRIVERS 80 DATA LATCHES VLCDOUT VLCDSENSE 37 to 43 VLCD 36 GENERATOR 80 SHIFT REGISTER 5 x 12 BIT 5 OSCILLATOR CURSOR AND DATA CONTROL VDD1 VDD2 VDD3 1 to 6 7 to 14 15 to 18 CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS 8 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS 5 168 OSC R17DUP 100 R1 to R18 51 to 59, 141 to 149 18 ROW DRIVERS 18 SHIFT REGISTER 18-BIT
VLCDIN
VSS1 VSS2
22 to 29 30 to 35
TIMING GENERATOR
T1 T2 T3
20 7 21 153
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
155
PD
DATA REGISTER (DR) 8 163 DB3/SA0
8 BUSY FLAG INSTRUCTION REGISTER 8 I/O BUFFER 151, 152 SCL 156, 157 SDA
PCF2119X
154 POR
160 to 162 DB0 to DB2
164 to 167 E
19
158
159 RS
DB4 to DB7
R/W
mgw571
Fig 1.
Block diagram
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7. Pinning information
7.1 Pinning
49 50 VLCDIN 44
dummy R8
R1 R17 C80
VLCDOUT 60 37 35 34 VSS2 30 VLCDSENSE VSS2
C66 C65
74 75 22 21 20 19
VSS1
T2 T1 E VDD3
15
VDD2 7 C41 R17DUP C40 100 VDD1 1 168 OSC DB7 DB6 DB5 DB4 DB3/SA0 C16 C15 125 126 DB2 DB1 DB0 RS 158 R/W
PC2119
C1 R18 R9 142 SDA PD POR T3 151 SCL
mgw572
R16 dummy
149 150
Top view. For mechanical details, see Figure 49.
Fig 2.
Pinning diagram of PCF2119x (bare die)
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PCF2119x
LCD controllers/drivers
7.2 Pin description
Table 3. Symbol VDD1 VDD2 VDD3 E Pin description Pin 1 to 6 7 to 14 15 to 18 19
[1] [1] [2]
Description supply voltage 1 (logic) supply voltage 2 (for high voltage generator) supply voltage 3 (for high voltage generator) data bus clock input
* *
T1 and T2 VSS1 VSS2 VLCDSENSE 20 and 21 22 to 29 30 to 35 36
[3]
set HIGH to signal the start of a read or write operation data is clocked in or out of the chip on the negative edge of the clock must be connected to VSS1 for all circuits, except of high voltage generator for high voltage generator
test pins
* *
[3]
ground supply voltage 1 ground supply voltage 2
* * *
VLCDOUT 37 to 43
input for voltage multiplier regulation circuitry and for the bias level generation if VLCD is generated internally then this pin must be connected to VLCDOUT and VLCDIN if VLCD is generated externally then this pin must be connected to VLCDIN only if VLCD is generated internally then this pin must be connected to VLCDIN and to VLCDSENSE if VLCD is generated externally then this pin must be left open-circuit
VLCD output
* *
VLCDIN dummy R8 to R1, R17, R17DUP, R18, R9 to R16 C80 to C41, C40 to C1 dummy SCL T3 44 to 49 50 51 to 58, 59, 100 141, 142 to 149 60 to 99, 101 to 140 150 151 and 152 153
[4] [5] [4]
input for LCD bias level generator LCD row driver output
* *
R17 has two pins: R17 and R17DUP R17 and R18 drive the icons
LCD column driver output I2C-bus serial clock input test pin
* *
POR PD SDA 154 155 156 and 157
[5]
open-circuit not user accessible
external Power-On Reset (POR) input power-down mode select
*
for normal operation pin PD must be LOW serial data input/output
I2C-bus
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PCF2119x
LCD controllers/drivers
Pin description ...continued Pin 158 Description read/write input
Table 3. Symbol R/W
* * *
RS DB0 to DB2, DB3/SA0, DB4 to DB7 159 160 to 162, 163, 164 to 167
[6][7 ]
pin R/W = HIGH selects the read operation pin R/W = LOW selects the write operation this pin has an internal pull-up resistor this pin has an internal pull-up resistor the 8-bit bidirectional data bus (3-state) transfers data between the microcontroller and the PCF2119x pin DB7 may be used as the busy flag, signalling that internal operations are not yet completed 4-bit operations the 4 higher order lines DB7 to DB4 are used, DB3 to DB0 must be left open-circuit data bus line DB3 has an alternative function (SA0) as the I2C-bus address pin each data line has its own internal pull-up resistor when the on-chip oscillator is used this pin must be connected to VDD1
register select pin;
* * * * * *
OSC 168
8 bit bidirectional data bus (bit 0 to bit 7)
oscillator or external clock input
*
[1] [2] [3] [4] [5] [6] [7] Always put VDD2 = VDD3.
When the I2C-bus is used, the parallel interface pin E must be LOW. The substrate (rear side of the die) is wired to VSS but should not be electrically connected. On the device connected to VSS1. When the parallel bus is used, the pins SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit. In the I2C-bus read mode, ports DB7 to DB4 and DB2 to DB0 should be connected to VDD1 or left open-circuit. When the 4-bit interface is used without reading out from the PCF2119x (bit R/W is set permanently to logic 0), the unused ports DB4 to DB0 can either be set to VSS1 or VDD1 instead of leaving them open-circuit.
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PCF2119x
LCD controllers/drivers
8. Functional description
8.1 Oscillator and timing generator
The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency fclk which equals either the built in oscillator frequency fosc or an external clock frequency fclk(ext).
8.1.1 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.
8.1.2 Internal clock
To use the on-chip oscillator, pin OSC must be connected to VDD1. The on-chip oscillator provides the clock signal for the display system. No external components are required.
8.1.3 External clock
If an external clock will be used, the input is at pin OSC. The resulting display frame frequency is given by: f osc f fr = ----------3072 (1)
Remark: Only in the power-down mode the clock is allowed to be stopped (pin OSC connected to VSS), otherwise the LCD is frozen in a DC state, which is not suitable for the liquid crystals.
8.2 Reset function and Power-On Reset (POR)
The PCF2119x must be reset externally when power is turned on. If no external reset is performed, the chip might start-up in an unwanted state. For the external reset, pin POR has to be active HIGH. The reset has to be active for at least 3 oscillator periods in order for the reset to be executed. If the internal oscillator is used, the minimum reset activity time follows from the lowest possible oscillator frequency (fosc = 140 kHz, Tosc ~ 71 s, 3 x Tosc ~ 215 s). The internal oscillator start-up time is 200 s (typ) up to 300 s (max) after power-on. In case that an external oscillator is used, Tosc is dependent from fosc(ext). Afterwards the chip executes the Clear_display instruction, which requires 165 oscillator cycles. After the reset the chip has the state shown in Table 4 and is then ready for use.
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LCD controllers/drivers
Table 4.
State after reset Control bit and register state bit I_D = 1 bit S = 0 bit D = 0 bit C = 0 bit B = 0 Description Reference Table 16 incremental cursor move direction no display shift display off cursor off cursor character blink off 8-bit interface 1-line display 1:18 multiplex drive mode normal instruction set Table 22 character mode, full display icon blink disabled default configuration default configurations VLCD generator off Table 23 Table 24 Table 28 Table 32 Table 25 Table 12 Table 19 Table 18
Step Function 1 2 3 Clear_display Entry_mode_set Display_ctl
4
Function_set
bit DL = 1 bit M = 0 bit SL = 0 bit H = 0
5 6 7 8 9 10 11
default address pointer to DDRAM Icon_ctl Screen_conf Disp_conf Temp_ctl VLCD_set I2C-bus interface reset HV_gen
[1]
bit IM = 0 bit IB = 0 bit L = 0 bit P = 0; bit Q = 0 register VA = 0; register VB = 0 bit S1 = 1; bit S0 = 0
bit TC1 = 0; bit TC2 = 0 default temperature coefficient
VLCD generator set to 3 internal stages (4 voltage multipliers)
Table 30
[1]
The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software (see Table 43 and Table 44).
8.3 Power-down mode
The chip can be put into power-down mode by applying a HIGH-level to pin PD. In power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked.
8.4 LCD supply voltage generator
The LCD supply voltage may be generated on-chip. The VLCD generator is controlled by two internal 6-bit registers: VA and VB. Register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. The nominal LCD operating voltage at room temperature is given by Equation 2: V LCD ( nom ) = V x x 0.08 + 1.82 Where Vx is the integer value of the register VA or VB. It should be noted that VLCD is sometimes referred as the LCD operating voltage (Voper).
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8.4.1 Programming ranges
Possible values for VA and VB are between 0 to 63. Remarks:
* Values producing more than 6.5 V at operating temperature are not allowed.
Operation above this voltage may damage the device. When programming the operating voltage the temperature coefficient of VLCDOUT must be taken into account.
* Values below 2.2 V are below the specified operating range of the chip and are
therefore not allowed.
Table 5. Values of VA and VB and the corresponding VLCD values All values at Tref = 27 C; allowed values are highlighted. Integer values of VA and VB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Corresponding value of VLCD in V VLCD switched off 1.90 1.98 2.06 2.14 2.22 2.30 2.38 2.46 2.54 2.62 2.70 2.78 2.86 2.94 3.02 3.10 3.18 3.26 3.34 3.42 3.50 Integer values of VA and VB 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Corresponding value of VLCD in V 3.58 3.66 3.74 3.82 3.90 3.98 4.06 4.14 4.22 4.30 4.38 4.46 4.54 4.62 4.70 4.78 4.86 4.94 5.02 5.10 5.18 5.26 Integer values of VA and VB 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Corresponding value of VLCD in V 5.34 5.42 5.50 5.58 5.66 5.74 5.82 5.90 5.98 6.06 6.14 6.22 6.30 6.38 6.46 6.54 6.62 6.70 6.78 6.86
When the LCD supply voltage is generated on-chip, the VLCD pins should be decoupled to VSS with a suitable capacitor. The generated VLCDOUT is independent of VDD and is temperature compensated. In Equation 2 the internal charge pump is not considered. However, if the supplied voltage to VDD2 and VDD3 is below the required VLCD it is necessary to use the internal charge pump. The multiplication factor has to be set such, that VDD2 and VDD3 (which are equal) multiplied with the programmed multiplication factor exceeds the required VLCD under all circumstances (i.e. at low temperatures and along with the temperature compensation PCF2119X_5 (c) NXP B.V. 2009. All rights reserved.
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PCF2119x
LCD controllers/drivers
see Section 10.2.3.4). If still a higher multiplication factor is chosen, VLCD will not increase (it is set by Equation 2) but the current that can be delivered will be higher. Also current consumption increases (see Section 16.6). When the VLCD generator and the direct mode are switched off, an external voltage may be supplied at connected pins VLCDIN and VLCDOUT. VLCDIN and VLCDOUT may be higher or lower than VDD2. In direct mode (see Icon_ctl instruction, Section 10.2.3.3) the internal VLCD generator is turned off and the VLCDOUT output voltage is directly connected to VDD2. This reduces the current consumption depending on VDD2 value and LCD liquid properties. The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to 4 V), the required peak voltage VLCD = 6.5 V can be generated at any time.
8.5 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for the 1:18 multiplex rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 6. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate.
Table 6. Multiplex rate 1:18 1:9 1:2 Bias levels as a function of multiplex rate Number of bias levels 5 5 4 Bias voltages V1 VLCD VLCD VLCD V2 3 -- ( V LCD - V SS ) 4 3 -- ( V LCD - V SS ) 4 2 -- ( V LCD - V SS ) 3 V3 1 -- ( V LCD - V SS ) 2 1 -- ( V LCD - V SS ) 2 2 -- ( V LCD - V SS ) 3 V4 1 -- ( V LCD - V SS ) 2 1 -- ( V LCD - V SS ) 2 1 -- ( V LCD - V SS ) 3 V5 1 -- ( V LCD - V SS ) 4 1 -- ( V LCD - V SS ) 4 1 -- ( V LCD - V SS ) 3 V6 VSS VSS VSS
8.6 LCD row and column drivers
The PCF2119x contains 18 row and 80 column drivers, which drive the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. Unused outputs should be left open. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figure 3 to Figure 5 show typical waveforms.
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VLCD V2 ROW 17 V3/V4 V5 VSS VLCD V2 ROW 18 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS
frame n
frame n +1
state 1 (on)
state 2 (off) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
ROW 1
ROW 9
ROW 2
R17 R18 C1 C2 C3 C4 C5
VLCD V2 ROW 10 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD state 1 0.5VLCD 0.25VLCD 0 -0.25VLCD -0.5VLCD -VLCD VLCD state 2 0.5VLCD 0.25VLCD 0 -0.25VLCD -0.5VLCD -VLCD 12 3 18 1 2 3 18
COL 1
COL 2
013aaa140
Vstate(t) = VCOL(t) - VROW(t).
Fig 3.
Waveforms for the 1:18 multiplex drive mode; character mode
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LCD controllers/drivers
frame n VLCD V2 ROW 17 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD state 1 0.5VLCD 0.25VLCD 0 -0.25VLCD -0.5VLCD -VLCD VLCD state 2 0.5VLCD 0.25VLCD 0 -0.25VLCD -0.5VLCD -VLCD
frame n +1
state 1 (off)
state 2 (on) R1 R2 R3 R4 R5 R6 R7 R8
ROW 1
ROW 2
ROW 3
R17 C1 C2 C3 C4 C5
ROW 4
COL 1
COL 2
1
2
3
9
1
2
3
9
013aaa141
Vstate(t) = VCOL(t) - VROW(t).
Fig 4.
Waveforms for the 1:9 multiplex drive mode; character mode, R9 to R16 and R18 open
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frame n VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS VLCD 2/3 1/3 VSS
frame n +1
only icons are driven (MUX 1: 2)
ROW 17
ROW 18
ROW 1 to 16
COL 1 ON/OFF
COL 2 ON/OFF
COL 3 ON/OFF
COL 4 ON/OFF
state 1 COL 1 - ROW 17
VLCD 0.66VLCD 0.33VLCD 0 -0.33VLCD -0.66VLCD -VLCD VLCD 0.66VLCD 0.33VLCD 0 -0.33VLCD -0.66VLCD -VLCD
state 1 (ON) state 2 (OFF)
state 3 (OFF) COL 2 COL 1
state 2 COL 2 - ROW 17
VLCD 0.66VLCD 0.33VLCD state 3 0 COL 3 - ROW 1 to ROW 16 -0.33VLCD -0.66VLCD -VLCD
013aaa142
Vstate(t) = VCOL(t) - VROW(t). Von(RMS) = 0.745VLCD. Voff(RMS) = 0.333VLCD.
V on D = --------- = 2.23 V off Fig 5. Waveforms for the 1:2 multiplex drive mode; icon mode
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9. Display data RAM and ROM
9.1 DDRAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Figure 6, Figure 7 and Figure 8. With no display shift the characters represented by the codes in the first 32 RAM locations starting at address 00h are displayed in line 1.
display position DDRAM address
non-displayed DDRAM addresses 12345 30 31 32
00 01 02 03 04
1D 1E 1F 20 21
4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345 14 15 16
00 01 02 03 04
DDRAM address 12345
0D 0E 0F 10 11
14 15 16
24 25 26 27
line 1
40 41 42 43 44
2-line display/MUX 1 : 9 mode
4D 4E 4F 50 51
64 65 66 67
line 2
mgk892
All addresses are shown in hex.
Fig 6.
DDRAM to display mapping: no shift
1 DDRAM address
23
4
5
14 15 16
27 00 01 02 03
1 23 4 5
0C 0D 0E
14 15 16
line 1
67 40 41 42 43
2-line display/MUX 1 : 9 mode
4C 4D 4E
line 2
mgl536
All addresses are shown in hex.
Fig 7.
DDRAM to display mapping: right shift
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display position DDRAM address
1
2
3
4
5
30 31 32
01 02 03 04 05
1E 1F 20
1-line display 1 DDRAM address 2 3 4 5 14 15 16
01 02 03 04 05
1 2 3 4 5
0E 0F 10
14 15 16
line 1
41 42 43 44 45
2-line display/MUX 1 : 9 mode
4E 4F 50
line 2
mgk894
All addresses are shown in hex.
Fig 8.
DDRAM to display mapping: left shift
When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 7.
Table 7. Mode Address space Read/write wrap-around (moves to next line) Display shift wrap-around (stays within line) Address space and wrap-around operation 1 x 32 00h to 4Fh 4Fh to 00h 4Fh to 00h 2 x 16 00h to 27h; 40h to 67h 27h to 40h; 67h to 00h 27h to 00h; 67h to 40h 1 x 16 00h to 27h 27h to 00h 27h to 00h
9.2 CGROM
The Character Generator ROM (CGROM) contains 240 character patterns in a 5 x 8 dot format from 8-bit character codes. Figure 9 to Figure 14 show the character sets that are currently implemented.
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mce190
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 9.
Character set `A' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mce173
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 10. Character set `D' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgu552
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 11. Character set `F' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgl535
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 12. Character set `R' in CGROM
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lower 4 bits xxxx
upper 4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgl534
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 13. Character set `S' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgl597
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 14. Character set `V' in CGROM
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9.3 CGRAM
Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Figure 21) are also used to drive icons:
* 6 CGRAM characters if icons blink and both icon rows are used in the application * 3 CGRAM characters if no icons blink but both icon rows are used in the application * 0 CGRAM characters if no icons are driven by the icon rows
When the icons blink option is enabled, double the number of CGRAM characters are used since both the on and off state of an icon is defined. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Figure 9 to Figure 14). Figure 15 shows the addressing principle for the CGRAM.
character codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0
(4)
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
(2)
0
(3)
0
0
0
0
0
0
(1)
0
1
0
0
(1)
0
1
(5)
0
0
0
0
0
0
0
1
0
0
0
1
0
coa072
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
(1) Character code bit 0 to bit 3 correspond to CGRAM address bit 3 to bit 6. (2) CGRAM address bit 0 to bit 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Lines are numbered from 0 to 7. (3) Character pattern column positions correspond to CGRAM data bit 0 to bit 4, as shown in Figure 9 to Figure 14. (4) As shown in Figure 9 to Figure 14, CGRAM character patterns are selected when character code bit 4 to bit 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. (5) Only bit 0 to bit 5 of the CGRAM address are set by the Set_CGRAM command. Bit 6 can be set using the Set_DDRAM command in the valid address range or by using the auto-increment feature during CGRAM write. All bits from bit 0 to bit 6 can be read using the BF_AC instruction.
Fig 15. Relationship between CGRAM addresses, data and display patterns
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9.4 Cursor control circuit
The cursor control circuit generates the cursor underline and/or cursor blink as shown in Figure 16 at the DDRAM address contained in the address counter.
cursor 5 x 7 dot character font cursor display example alternating display blink display example
013aaa139
Fig 16. Cursor and blink display examples
icon 1
icon 5
row 18
row 17
row 17
row 8
row 8
row 2
row 2
row 1 cursor
row 1
013aaa156
Fig 17. Example of a displays with icons
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10. Registers
The PCF2119x has two 8-bit registers, an instruction register and a data register. Only these two registers can be directly controlled by the microcontroller. Before an internal operation, the control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The instruction set for the parallel interface is shown in Table 11 together with their execution time. Details about the parallel interface can be found in Section 11.1. Examples of operations on a 4-bit bus are given in Table 38, on a 8-bit bus in Table 39, Table 40 and Table 41. When using the I2C-bus, the instruction has to be commenced with a control byte as shown in Table 8. Details about the I2C-bus interface can be found in Section 11.2. An example of operations on the I2C-bus is given in Table 42.
Table 8. Instruction set for I2C-bus commands Command byte 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 I2C-bus command
[1]
Control byte CO
[1]
RS
0
R/W is set together with the slave address (see Figure 30).
Table 9. Bit 7 6 4 to 0
Control byte bit description Symbol CO RS Value 0 1 0 1 0 Description last control byte another control byte follows after data/command instruction register selected data register selected default logic 0
Instructions are of 4 types, those that: 1. Designate PCF2119x functions like display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others, like read `busy flag' and read `address counter' In normal use, type 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the BF_AC instruction will be executed. Because the busy flag is set to logic 1 while an instruction is being executed, check to ensure it is logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 11. An instruction sent while the busy flag is logic 1 will not be executed.
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The RS bit determines which register will be accessed and the R/W bit indicates if it is a read or a write operation (see Table 10).
Table 10. Symbol RS 0 1 R/W 0 1
[1] [2]
Register access selection Value Description register select instruction register[1] data register[2] read/write write operation read operation
There is only write access to the instruction register, but read access to the busy flag (BF) and the address counter (AC) of the BF_AC instruction (see Section 10.2.1.2). Write and read access.
Details of the instructions are explained in subsequent sections.
10.1 Data register
The data register temporarily stores data to be read from the DDRAM and CGRAM. Prior to being read by the Read_data instruction, data from the DDRAM or CGRAM, corresponding to the address in the instruction register, is written to the data register.
10.2 Instruction register
The instruction register stores instruction codes such as Clear_display, Curs_disp_shift, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to but not read from by the system controller. The instruction register is sectioned into basic, standard and extended instructions. Bit H = 1 of the Function_set instruction (see Section 10.2.1.1) sets the chip into extended instruction set mode.
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Table 11.
Instruction register overview Bits[1] RS R/W 7 6 5 4 3 2 1 0 Required clock cycles[2] 3 3 0 3 3 0 0 0 0 0 ACG 0 0 0 0 1 0 0 0 1 SC 0 0 1 D RL 0 1 I_D C 0 1 0 S B 0 165 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 IM 0 0 0 1 P IB TC1 S1 1 L Q DM TC2 S0 3 3 3 3 3 3 Reference
Instruction
Basic instructions (bit H = 0 or 1) NOP Function_set BF_AC Read_data Write_data Clear_display Return_home Entry_mode_set Display_ctl Curs_disp_shift Set_CGRAM Set_DDRAM Reserved Screen_conf Disp_conf Icon_ctl Temp_ctl HV_gen VLCD_set
[1] [2] [3] [4]
[4] [3]
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 BF
0 0 AC
0 1
0 DL
0 0
0 M
0 SL
0 H
Section 10.2.1.1 Section 10.2.1.2 Section 10.2.1.3 Section 10.2.1.4 Section 10.2.2.1 Section 10.2.2.2 Section 10.2.2.3 Section 10.2.2.4 Section 10.2.2.5 Section 10.2.2.6 Section 10.2.2.7 Section 10.2.3.1 Section 10.2.3.2 Section 10.2.3.3 Section 10.2.3.4 Section 10.2.3.5 Section 10.2.3.6
READ_DATA WRITE_DATA 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 ADD 0 0 0 0 0 1 V
Standard instructions (bit H = 0)
Extended instructions (bit H = 1)
VA or VB
The bits 0 to 7 correspond with the data bus lines DB0 to CB7. fosc cycles. No operation. Do not use.
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10.2.1 Basic instructions (bit H = 0 or 1)
10.2.1.1 Function_set
Table 12. Bit RS R/W 7 to 5 4 DL 0 1 3 2 M 0 1 1 SL 0 1 0 H 0 1
[1] [2] [3] [4]
[4] [4][5] [4] [1] [2]
Function_set bit description Symbol Value 0 0 001 fixed value interface data length (for parallel mode only) 2 x 4 bits (DB7 to DB4) 8 bits (DB7 to DB0) unused
[3]
Description see Table 10
0
number of display lines 1 line x 32 characters 2 line x 16 characters multiplex mode 1:18 multiplex drive mode, 1 x 32 or 2 x 16 character display 1:9 multiplex drive mode, 1 x 16 character display instruction set control basic instruction set plus standard instruction set basic instruction set plus extended instruction set
When 4-bit width is selected, data is transmitted in two cycles using the parallel-bus. In a 4-bit application ports DB3 to DB0 should be left open-circuit (internal pull-ups). Default value after power-on in I2C-bus mode. No impact if SL = 1. Due to the internal pull-ups on DB3 to DB0 in a 4-bit application, the first Function_set after power-on sets bits M, SL and H to logic 1. A second Function_set must be sent to set bits M, SL and H to the required values. Independent of bit M and bit L of the Screen_conf instruction (see Section 10.2.3.1). Only row 1 to row 8 and row 17 are used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2 x 16 character display mode, however, the second line cannot be displayed.
[5]
10.2.1.2
BF_AC instructions
Table 13. Bit RS R/W 7 BF 0 1 6 to 0
[1]
BF_AC bit Symbol Value 0 1
[1]
Description see Table 10 read busy flag next instruction will be executed internal operation is in progress; next instruction will not be executed until BF = 0 read address counter
AC
0000000 to 1111111
It is recommended that the BF status is checked before the next write operation is started.
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Busy flag: The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be started after checking that the busy flag is at logic 0 or after waiting for the required number of cycles. Address counter: The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous Set_CGRAM and Set_DDRAM instruction. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter value is output to the bus (DB6 to DB0) when bit RS = 0 and bit R/W = 1. 10.2.1.3 Read_data
Table 14. Bit RS R/W 7 to 0 READ_DATA Read_data bit description Symbol Value 1 1 00000000 to 11111111 read data from CGRAM or DDRAM Description see Table 10
Read_data from CGRAM or DDRAM: Read_data reads binary 8-bit data from the CGRAM or DDRAM. The most recent `set address' command (Set_CGRAM or Set_DDRAM) determines whether the CGRAM or DDRAM is to be read. The Read_data instruction gates the content of the data register to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the address counter and stores RAM data corresponding to the new address counter into the data register. There are only three instructions that update the data register:
* Set_CGRAM * Set_DDRAM * Read_data from CGRAM or DDRAM
Other instructions (e.g. Write_data, Curs_disp_shift, Clear_display and Return_home) do not modify the value of the data register. 10.2.1.4 Write_data
Table 15. Bit RS R/W 7 to 0 Write_data bit description Symbol Value 1 0 write data to CGRAM or DDRAM Description see Table 10
WRITE_DATA 00000000 to 11111111
Write_data to CGRAM or DDRAM: Write_data writes binary 8-bit data to the CGRAM or the DDRAM.
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The previous Set_CGRAM or Set_DDRAM command determines if data is written into CGRAM or DDRAM. After writing, the address counter automatically increments or decrements by 1, in accordance with the Entry_mode_set (see Section 10.2.2.3). Only bit 4 to bit 0 of CGRAM data are valid, bit 7 to bit 5 are `don't care'.
10.2.2 Standard instructions (bit H = 0)
10.2.2.1 Clear_display
Table 16. Bit RS R/W 7 to 0 Clear_display bit description Symbol Value 0 0 00000001 fixed value Description see Table 10
Clear_display: writes usually the character code 20h (blank pattern) into all DDRAM addresses except for the character sets `R' and `V' where the character code 20h is not a blank pattern. In addition Clear_display
* sets the DDRAM address counter to logic 0 * returns the display to its original position, if it was shifted. Thus, the display
disappears and the cursor or blink position goes to the left edge of the display
* sets entry mode bit I_D = 1 (increment mode); bit S of entry mode does not change
The instruction Clear_display requires extra execution time. This may be allowed by checking the busy flag bit BF or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. Remark: When using the character sets `R' or `V', where the character code 20h is not the blank pattern, the following alternative instruction set has to be used: 1. Switch display off (Display_ctl, bit D = 0). 2. Write a blank pattern into all DDRAM addresses (Write_data). 3. Switch display on (Display_ctl, bit D = 1). 10.2.2.2 Return_home
Table 17. Bit RS R/W 7 to 0 Return_home bit description Symbol Value 0 0 00000010 fixed value Description see Table 10
Return_home: Sets the DDRAM address counter to logic 0 and switches a shifted display back to an unshifted state. The DDRAM content remain unchanged. The cursor or blink position goes to the left of the first display line. Bit I_D and bit S of the Entry_mode_set instruction remain unchanged.
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10.2.2.3
Entry_mode_set
Table 18. Bit RS R/W 7 to 2 1 I_D 0 1 0 S 0 1 Entry_mode_set bit description Symbol Value 0 0 000001 fixed value address increment or decrement DDRAM or CGRAM address decrements by 1, cursor moves to the left DDRAM or CGRAM address increments by 1, cursor moves to the right shift display to the left or right display does not shift display shifts Description see Table 10
Bit I_D: When bit I_D = 1 the DDRAM or CGRAM address increments by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right. When bit I_D = 0 the DDRAM or CGRAM address decrements by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the left. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. Bit S: When bit S = 0, the display does not shift. During DDRAM write, when bit S = 1 and bit I_D = 0, the entire display shifts to the right; when bit S = 1 and bit I_D = 1, the entire display shifts to the left. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. 10.2.2.4 Display_ctl instructions
Table 19. Bit RS R/W 7 to 3 2 D 0 1 1 C 0 1 0 B 0 1
PCF2119X_5
Display_ctl bit description Symbol Value 0 0 00001 fixed value display on or off display is off; chip is in power-down mode display is on cursor on or off cursor is off cursor is on character blink on or off character blink is off character blink is on
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Bit D: The display is on when bit D = 1 and off when bit D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting bit D = 1. When the display is off (bit D = 0) the chip is in partial power-down mode:
* The LCD outputs are connected to VSS * The VLCD generator and bias generator are turned off
Three oscillator cycles are required after sending the `display off' instruction to ensure all outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running during partial power-down mode (`display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (pin OSC to VSS). To ensure IDD < 1 A:
* the parallel bus ports DB7 to DB0 should be connected to VDD * pins RS and R/W should be connected to VDD or left open-circuit * pin PD should be connected to VDD
Recovery from power-down mode:
* pin PD should be connected back to VSS * if necessary pin OSC should be connected back to VDD * a Display_ctl instruction with bit D = 1 should be sent
Bit C: The cursor is displayed when bit C = 1 and inhibited when bit C = 0. Even if the cursor disappears, bit I_D and bit S (see Section 10.2.2.3) remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Figure 16). Bit B: The character indicated by the cursor blinks when bit B = 1. The character blink is displayed by switching between display characters and all dots on with a period of f osc approximately 1 second, with f blink = -------------52224 10.2.2.5 Curs_disp_shift
Table 20. Bit RS R/W 7 to 4 3 SC 0 1 2 RL 0 1 1 to 0 00 Curs_disp_shift bit description Symbol Value 0 0 0001 fixed value cursor move or display shift move cursor shift display shift or move to the right or left left shift or move right shift or move fixed value Description see Table 10
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Bits SC and RL: Curs_disp_shift moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The address counter content does not change if the only action performed is shift display (SC = 1) but increments or decrements with the shift cursor (SC = 0). 10.2.2.6 Set_CGRAM
Table 21. Bit RS R/W 7 to 6 5 to 0 ACG Set_CGRAM bit description Symbol Value 0 0 01 000000 to 111111 fixed value set CGRAM address Description see Table 10
Set_CGRAM: Sets the CGRAM address bits ACG[5:0] into the address counter. Data can then be written to or read from the CGRAM. Remark: The CGRAM address uses the same address register as the DDRAM address. This register consists of 7 bits. But with the Set_CGRAM command, only bit 5 to bit 0 are set. Bit 6 can be set using the Set_DDRAM command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the BF_AC instruction. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write). 10.2.2.7 Set_DDRAM
Table 22. Bit RS R/W 7 6 to 0 ADD Set_DDRAM bit description Symbol Value 0 0 1 0000000 to 1111111 fixed value set DDRAM address Description see Table 10
Set_DDRAM: Sets the DDRAM address bits ADD[6:0] into the address counter. Data can then be written to or read from the DDRAM.
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10.2.3 Extended instructions (bit H = 1)
10.2.3.1 Screen_conf
Table 23. Bit RS R/W 7 to 1 0 L 0 1 Screen_conf bit description Symbol Value 0 0 0000001 fixed value screen configuration split screen standard connection split screen mirrored connection Description see Table 10
Screen_conf:
* If bit L = 0, then the two halves of a split screen are connected in a standard way i.e.
column 1/81, 2/82 to 80/160.
* If bit L = 1, then the two halves of a split screen are connected in a mirrored way i.e.
column 1/160, 2/159 to 80/81. This allows single layer PCB or glass layout. 10.2.3.2 Disp_conf
Table 24. Bit RS R/W 7 to 2 1 P 0 Disp_conf bit description Symbol Value 0 0 000001 fixed value display column configuration column data: left to right; column data is displayed from column 1 to column 80 1 column data: right to left; column data is displayed from column 80 to column 1 0 Q 0 display row configuration row data: top to bottom; row data is displayed from row 1 to row 16 and icon row data in row 17 and row 18 in single line mode (SL = 1) row data is displayed from row 1 to row 8 and icon row data in row 17 1 row data: bottom to top; row data is displayed from row 16 to row 1 and icon row data in row 18 and row 17 in single line mode (SL = 1) row data is displayed from row 8 to row 1 and icon row data in row 17 Description see Table 10
Bit P: The P bit is used to flip the display left to right by mirroring the column data, as shown in Figure 18. This allows the display to be viewed from behind instead of front and enhances the flexibility in the assembly of equipment and avoids complicated data manipulation within the controller.
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0 P= =0 Q
1 P= =0 Q
013aaa122
Fig 18. Use of bit P
Bit Q: The Q bit flips the display top to bottom by mirroring the row data, as shown in Figure 19.
0 P= =0 Q
0 P= =1 Q
013aaa113
Fig 19. Use of bit Q
Combination of bit P and bit Q: A combination of P and Q allows the display to be rotated horizontally and vertically by 180 degree, as shown in Figure 20. This is useful for viewing the display from the opposite edge.
0 P= 0 = Q
1 P= =1 Q
013aaa123
Fig 20. Use of bit P and bit Q
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LCD controllers/drivers
10.2.3.3
Icon_ctl
Table 25. Bit RS R/W 7 to 3 2 IM 0 1 1 IB 0 1 0 DM 0 1 Icon_ctl bit description Symbol Value 0 0 00001 fixed value icon mode character mode, full display icon mode, only icons displayed icon blink icon blink disabled icon blink enabled direct mode off on Description see Table 10
The PCF2119x can drive up to 160 icons. See Figure 21 and Figure 22 for CGRAM to icon mapping. Bit IM: When bit IM = 0, the chip is in character mode. In the character mode characters and icons are driven (multiplex drive mode 1:18 or 1:9). The VLCD generator, if used, produces the VLCDOUT voltage programmed with register VA. When bit IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (multiplex drive mode 1:2). The VLCD generator, if used, produces the VLCDOUT voltage as programmed with register VB.
Table 26. Bit IM 0 1 Normal/icon mode operation Mode character mode icon mode VLCDOUT generated from VA generated from VB
Bit IB: Icon blink control is independent of the cursor/character blink function. When bit IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 3 (4 x 8 x 5 = 160 bits for 160 icons). When bit IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 3 (4 x 8 x 5 = 160 bits for 160 icons). These bits also define icon state when icon blink is not used (see Table 27). Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for the 160 icons). When icon blink is disabled CGRAM characters 4 to 7 may be used as normal CGRAM characters.
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Blink effect for icons and cursor character blink Even phase block (all on) state 1; CGRAM character 0 to 3 Odd phase normal (display character) state 2; CGRAM character 4 to 7
Table 27. Parameter
cursor character blink icons
display:
COL 1 to 5
COL 6 to 10
COL 76 to 80
ROW 17 -
1
2
3
4
5
6
7
8
9
10
76
77
78
79
80
ROW 18 -
81
82
83
84
85
86
87
88
89
90
156 157 158 159 160
mgl249
block of 5 columns
Fig 21. CGRAM to icon mapping (a)
icon no.
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
76-80 81-85
even even
17/76-80 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 0
156-160 1-5
even odd (blink)
18/76-80 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
1 0
0 0
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
156-160
odd (blink)
18/76-80
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
mgk999
CGRAM data: logic 1 of a data bit turns the icon on and logic 0 turns the icon off. Character codes: bits 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Bits 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled)
Fig 22. CGRAM to icon mapping (b)
Bit DM: When DM = 0, the chip is not in the direct mode. Either the internal VLCD generator or an external voltage may be used to achieve VLCD. When DM = 1, the chip is in direct mode. The internal VLCD generator is turned off and the output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage).
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Remark: In direct mode, no external VLCD is possible. The direct mode can be used to reduce the current consumption when the required output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in icon mode or in MUX 1:9 (depending on LCD liquid properties). 10.2.3.4 Temp_ctl
Table 28. Bit RS R/W 7 to 2 1 to 0 TC[1:0] Temp_ctl bit description Symbol Value 0 0 000100 00 to 11 temperature coefficient Description see Table 10
The bit-field TC[1:0] selects the temperature coefficient for the internally generated VLCDOUT (see Table 29).
Table 29. TC[1:0] 00 10 01 11 TC[1:0] selection of VLCD temperature coefficient Typical value -0.16 %/K -0.18 %/K -0.21 %/K -0.24 %/K Description VLCD temperature coefficient 0 (default value) VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3
10.2.3.5
HV_gen
Table 30. Bit RS R/W 7 to 2 1 to 0 S[1:0] HV_gen bit description Symbol Value 0 0 010000 00 to 11 fixed value voltage multiplier Description see Table 10
A software configurable voltage multiplier is incorporated in the VLCD generator and can be set via the HV_gen command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required VLCDOUT output voltage (see Table 31).
Table 31. S[1:0] 00 01 10 11 Voltage multiplier control bits Description set VLCD generator stages to 1 (2 x voltage multiplier) set VLCD generator stages to 2 (3 x voltage multiplier) set VLCD generator stages to 3 (4 x voltage multiplier) do not use
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10.2.3.6
VLCD_set
Table 32. Bit RS R/W 7 6 V 0 1 5 to 0 VA or VB 000000 to 111111 VLCD_set bit description Symbol Value 0 0 1 fixed value set register VA or VB set register VA set register VB factor for calculating VLCD Description see Table 10
The VLCD value is calculated with the Equation 2 on page 8. The multiplication factor is programmed by instruction. Two on-chip registers (VA and VB) hold the multiplication factor for the character mode and the icon mode, respectively. The generated VLCDOUT value is independent of VDD, allowing battery operation of the chip. Vx programming: 1. Send Function_set instruction with bit H = 1. 2. Send VLCD_set instruction to write to the voltage register: a. Bit 7 = 1 and bit 6 = 0: bit 5 to bit 0 are the multiplication factor for VLCD of character mode (VA). b. Bit 7 = 1 and bit 6 = 1: bit 5 to bit 0 are the multiplication factor for VLCD of icon mode (VB). c. Bit 5 to bit 0 = 0 switches VLCD generator off (when selected). d. During `display off'/power-down the VLCD generator is also disabled. 3. Send Function_set instruction with bit H = 0 to resume normal programming.
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11. Basic architecture
11.1 Parallel interface
The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 ports DB7 to DB0. Three further control lines E, RS and R/W are required. In 4-bit mode data is transferred in two cycles of 4 bits each using ports DB7 to DB4 for the transaction. The higher order bits (corresponding to range of bit 7 to bit 4 in 8-bit mode) are sent in the first cycle and the lower order bits (bit 3 to bit 0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction (see Figure 23 to Figure 25 for examples of bus protocol). In 4-bit mode, ports DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
mga804
Fig 23. 4-bit transfer example
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RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
mga805
IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit.
Fig 24. An example of 4-bit data transfer timing sequence
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
mga806
Fig 25. Example of busy flag checking timing sequence
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11.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 26. System configuration
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 27. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 28. Definition of START and STOP conditions
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data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 29. Acknowledgement on the I2C-bus
11.2.1 I2C-bus protocol
One I2C-bus slave address is reserved for the PCF2119x (see Figure 30).
S 011101A0 0
slave address R/W
013aaa143
Fig 30. PCF2119x I2C-bus slave address
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2119x read and write cycles is shown in Figure 31 to Figure 33. The slow down feature of the I2C-bus protocol (receiver holds SCL line LOW during internal operations) is not used in the PCF2119x.
11.2.2 I2C-bus definitions
Definitions:
* Transmitter: the device which sends the data to the bus. * Receiver: the device which receives the data from the bus. * Master: the device which initiates a transfer, generates clock signals and terminates a
transfer.
* Slave: the device addressed by a master. * Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message.
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* Arbitration: procedure to ensure that if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted.
* Synchronization: procedure to synchronize the clock signals of two or more devices.
acknowledgement from PCF2119x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
mgk899
Fig 31. Master transmits to slave receiver; write mode
acknowledgement
S
S 0 1 1 1 0 1 A 0 A 1 RSCONTROL BYTE A
0
DATA BYTE
A 0 RSCONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n 0 bytes Co
1 byte
n 0 bytes
acknowledgement
acknowledgement
no acknowledgement
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
mgg003
Last data byte is a dummy byte (may be omitted).
Fig 32. Master reads after setting word address; writes word address, set RS; Read_data
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acknowledgement from PCF2119x
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
013aaa155
Fig 33. Master reads slave immediately after first byte; read mode (RS previously defined)
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12. Internal circuitry
Table 33. Symbol VDD1 Device protection circuits Pin 1 to 6
VDD1 VSS1
013aaa169
Internal circuit
VDD2
7 to 14
VDD2 VSS2
013aaa170
VSS1
VDD3
15 to 18
VDD3 VSS1
013aaa171
VSS1 VSS2
22 to 29 30 to 35
VSS2 VSS1
013aaa172
VLCDSENSE VLCDIN VLCDOUT SCL SDA OSC PD POR T1 T2 T3 E RS R/W DB0 to DB7 R1 to R18
36 44 to 49 37 to 43 151 to 152 156 to 157 168 155 154 20 21 153 19 159 158 160 to 167 58, 57 to 51, 142 to 149, 59, 100, 141 140 to 101, 99 to 60
VSS1
013aaa175
VSS1
013aaa173
VDD1
VSS1
013aaa174
VLCDIN
C1 to C80
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13. Limiting values
Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 VDD3 VLCD VI/O(n) II IO IDD ISS IDD(LCD) Ptot Po VESD Ilu Tstg
[1] [2] [3] [4]
Parameter supply voltage 1 supply voltage 2 supply voltage 3 LCD supply voltage input/output voltage on any other pin input current output current supply current ground supply current LCD supply current total power dissipation output power
Conditions logic VLCD generator
Min -0.5 -0.5 -0.5
Max +6.5 +4.5 +7.5 VDD + 0.5 +10 +10 +50 +50 +50 400 100 3000 300 200 +150
Unit V V V V mA mA mA mA mA mW mW V V mA C
VDD related VLCD related DC level DC level
-0.5 -0.5 -10 -10 -50 -50 -50 -
VLCD + 0.5 V
dissipation per output
[1] [2] [3] [4]
-65
electrostatic discharge voltage HBM MM latch-up current storage temperature
Pass level; Human Body Model (HBM) according to Ref. 5 "JESD22-A114". Pass level; Machine Model (MM), according to Ref. 6 "JESD22-A115". Pass level; latch-up testing, according to Ref. 7 "JESD78". According to the NXP store and transport conditions (see Ref. 9 "SNW-SQ-623") the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
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14. Static characteristics
Table 35. Static characteristics VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD1 VDD2 VDD3 VLCD ISS supply voltage 1 supply voltage 2 supply voltage 3 LCD supply voltage ground supply current VDD = 3 V; VLCD = 5 V icon mode; VDD = 3 V; VLCD = 2.5 V power-down mode; VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 Ground supply current using internal VLCD[1][3] ISS ground supply current VDD = 3 V; VLCD = 5 V icon mode; VDD = 2.5 V; VLCD = 2.5 V Logic VIL VIH VIL VIH LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage VSS1 0.7VDD1 VSS1 VDD1 - 0. 1 1.6 -1 0.04 -1 0.3VDD1 VDD1 VDD1 - 1. 2 VDD1 V V V V
[2] [2] [2] [2]
Parameter
Conditions logic internal VLCD generation; VLCD > VDD2 = VDD3
Min 1.5 2.2 2.2 -
Typ 70 35 25 0.5
Max 5.5 4.0 6.5 120 80 45 5
Unit V V V A A A A
Ground supply current using external VLCD[1]
-
190 135 85
400 400 -
A A A
Oscillator input; pin OSC
Data bus; pins DB7 to DB0 IOL IOH Ipu IL LOW-level output current VOL = 0.4 V; VDD1 = 5 V HIGH-level output current pull-up current leakage current VOH = 4 V; VDD1 = 5 V VI = VSS1 VI = VDD1, 2, 3 or VSS1, 2 4 -8 0.15 1 +1 mA mA A A
I2C-bus; pins SDA and SCL Inputs: pins SDA and SCL VIL VIH ILI Ci
PCF2119X_5
LOW-level input voltage HIGH-level input voltage input leakage current input capacitance VI = VDD1, 2, 3 or VSS1, 2
0 0.7VDD1 -1 -
5
0.3VDD1 5.5 +1 -
V V A pF
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Table 35. Static characteristics ...continued VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IOL LCD outputs RO Vbias VLCD output resistance bias voltage variation LCD voltage variation row output, pins R1 to R18 column output, pins C1 to C80 on pins R1 to R18 and C1 to C80 Tamb = 25 C VLCD < 3 V VLCD < 4 V VLCD < 5 V VLCD < 6 V
[1] [2] [3] [4] [5] LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive. Tamb = 25 C; fosc = 200 kHz. LCD outputs are open-circuit; VLCD generator is on; load current ILCD = 5 A. Resistance of output pins (R1 to R18 and C1 to C80) with a load current of 10 A; outputs measured one at a time; external LCD supply VLCD = 3 V; VDD1 = VDD2 = VDD3 = 3 V. LCD outputs open-circuit; external LCD supply.
[4] [4] [5]
Parameter
Conditions
Min 3 2 -
Typ 10 15 20
Max 30 40 130
Unit mA mA k k mV
Output: pin SDA LOW-level output current VOL = 0.4 V; VDD1 > 2 V VOL = 0.2 VDD1; VDD1 < 2 V
[3]
-
-
160 200 260 340
mV mV mV mV
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15. Dynamic characteristics
Table 36. Dynamic characteristics VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ffr(LCD) fosc fosc(ext) td(startup)(OSC) Parameter LCD frame frequency oscillator frequency external oscillator frequency start-up delay time on pin OSC oscillator, after power-down
[1]
Conditions internal clock; VDD = 5.0 V not available at any pin
Min 45 140 140 -
Typ 95 250 200
Max 147 450 450 300
Unit Hz kHz kHz s
Clock and oscillator
Timing characteristics of parallel interface[2] Write operation (writing data from microcontroller to PCF2119x); see Figure 34 tcy(en) tw(en) tsu(A) th(A) tsu(D) th(D) tcy(en) tw(en) tsu(A) th(A) td(DV) th(D) fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA enable cycle time enable pulse width address set-up time address hold time data input set-up time data input hold time enable cycle time enable pulse width address set-up time address hold time data input valid delay time data input hold time SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line set-up time for a repeated START condition hold time (repeated) START condition
[1][3]
500 220 50 25 60 25 500 220 50 25 VDD1 > 2.2 V VDD1 > 1.5 V 20 1.3 0.6 100 0 15 + 0.1 Cb 15 + 0.1 Cb 0.6 0.6
-
150 250 100 400 300 300 400 -
ns ns ns ns ns ns ns ns ns ns ns ns ns kHz s s ns ns ns ns pF s s
Read operation (reading data from PCF2119x to microcontroller); see Figure 35
Timing characteristics of I2C-bus interface[2]; see Figure 36
[1][3]
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Table 36. Dynamic characteristics ...continued VDD1 = 1.5 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tSU;STO tSP Parameter set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter bus free time between a STOP and START condition
Tested on sample base. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Cb = total capacitance of one bus line in pF.
Conditions
Min 0.6 -
Typ -
Max 50
Unit s ns
tBUF
1.3
-
-
s
[1] [2] [3]
RS
VIH VIL
VIH VIL
tsu(A) R/W
th(A)
VIL
VIL
tw(en)
E VIH VIL VIH VIL
th(A)
VIL
tsu(D)
DB0 to DB7 VIH valid data VIL tcy(en)
th(D)
VIH VIL
mbk474
Fig 34. Parallel bus write operation sequence; writing data from microcontroller to PCF2119x
RS
VIH VIL
VIH VIL
tsu(A) R/W
VIH
th(A)
VIH
tw(en)
E VIL VIH VIH VIL
th(A)
VIL
td(DV)
DB0 to DB7 VOH VOL
th(D)
VOH VOL
tcy(en)
mbk475
Fig 35. Parallel bus read operation sequence; writing data from PCF2119x to microcontroller
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SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 36. I2C-bus timing diagram
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16. Application information
16.1 General application information
The required minimum value for the external capacitors in an application with the PCF2119x are: Cext from pins VLCD to VSS = 100 nF and for pins VDD to VSS = 470 nF. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 for the supply and below 100 for the I/O connections. Higher track resistance reduce performance and increase current consumption. To avoid accidental triggering of Power-On Reset (POR) (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be risen above the specified minimum. When external LCD supply voltage is supplied, VLCDOUT should be left open-circuit to avoid any stray current, and VLCDIN must be connected to VLCDSENSE.
16.2 Power supply connections for internal VLCD generation
1.5 V to 5.5 V VDD1 VDD2 VDD3 VSS1 VSS2
013aaa114
VDD1 2.2 V to 4.0 V VDD2 VDD3 VSS1 VSS2
013aaa115
2.2 V to 4.0 V
GND
GND
Decoupling capacitors are not shown in the drawings.
Fig 37. Recommended VDD connections for internal VLCD generation
VLCDIN VLCDOUT VSS2 VLCDSENSE
013aaa116
Fig 38. Recommended VLCD connections for internal VLCD generation
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16.3 Power supply connections for external VLCD generation
1.5 V to 5.5 V VDD1 VDD2 VDD3 VSS1 VSS2
013aaa114
2.2 V to 4.0 V
VDD1 VDD2 VDD3
2.2 V to 4.0 V
GND
GND
VSS1 VSS2
013aaa117
Decoupling capacitors are not shown in the drawings. Remark: When using an external VLCD, the internal VLCD generator must never be switched on otherwise damages will occur.
Fig 39. Recommended VDD connections for external VLCD generation
VLCDIN n.c. VSS2 VLCDOUT VLCDSENSE
013aaa118
Fig 40. Recommended VLCD connections for external VLCD generation
16.4 Information about VLCD connections
VLCDIN -- This input is used for generating the 5 LCD bias levels. It is the power supply for the bias level buffers. VLCDOUT -- This is the VLCD output if VLCD is generated internally. In this case pin VLCDOUT must be connected to VLCDIN and to VLCDSENSE. VLCDSENSE -- This input is used for the voltage multiplier's regulation circuitry. When using the internal VLCD generation, this pin must be connected to VLCDOUT and VLCDIN. When using an external VLCD supply it must be connected to VLCDIN only.
16.5 Reducing current consumption
Reducing current consumption can be achieved by one of the options given in Table 37. When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip VLCD generator than an external regulator.
Table 37. Reducing current consumption Alternative mode icon mode (control bit IM) display off (control bit D) direct mode power-down mode (pin PD)
Original mode character mode display on VLCD generator operating any mode
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16.6 Charge pump characteristics
Typical graphs of the total power consumption of the PCF2119x using the internal charge pump are illustrated in Figure 41, Figure 42 and Figure 43. The graphs were obtained under the following conditions:
* * * * * *
Tamb = 25 C VDD1 = VDD2 = VDD3 = 2.2 V (minimum), 2.7 V (typical) and 4.0 V (maximum) Normal mode fosc = internal oscillator multiplex drive mode 1:18 Typical current load for ILCD = 10 A.
For each multiplication factor there is a separate line. The line ends where it is not possible to get a higher voltage under its conditions (a higher multiplication factor is needed to get higher voltages). Connecting different displays may result in different current consumption. This affects the efficiency and the optimum multiplication factor to be used to generate a certain output voltage.
400 IDD (A) 300
(2)
mgw573
200
(3) (1)
100
0 1.25
2.75
4.25
5.75 VLCD (V)
7.25
(1) 2 x multiplication factor. (2) 3 x multiplication factor. (3) 4 x multiplication factor.
Fig 41. Typical charge pump characteristics (a), VDD = 2.2 V
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300 IDD (A)
(3)
mgw574
200
(2)
(1)
100
0 1.25
2.75
4.25
5.75 VLCD (V)
7.25
(1) 2 x multiplication factor. (2) 3 x multiplication factor. (3) 4 x multiplication factor.
Fig 42. Typical charge pump characteristics (b), VDD = 2.7 V
300 IDD (A) 200
(3) (2) (1)
mgw575
100
0 1.25
2.75
4.25
5.75 VLCD (V)
7.25
(1) 2 x multiplication factor. (2) 3 x multiplication factor. (3) 4 x multiplication factor.
Fig 43. Typical charge pump characteristics (c), VDD = 4.0 V
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16.7 Interfaces
OSC R17, R18
2
VDD
VDD
PCF2119X
470 nF 100 nF
R1 to R16
16
VLCD
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS
C1 to C80
VSS
VSS
80
4,8
DB7 to DB4 DB3 to DB0
E
RS R/W
013aaa119
Fig 44. Typical application using parallel interface, 4 or 8 bit bus possible
VDD VDD
VDD
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16
PCF2119X
100 nF 100 nF
16
VLCD C1 to C80 VSS SCL SDA
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
VSS
VSS
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16
PCF2119X
100 nF 100 nF
16
VLCD C1 to C80 VSS SCL SDA
1 x 32 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
VSS
SCL SDA
I2C MASTER, MICROCONTROLLER
mgk898
Fig 45. Application using I2C-bus interface
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16.8 Connections with LCD modules
R17 Icons R1 to R8
8
Character row 1 Character row 2
PCF2119X
C1 to C80 80 R9 to R16 R18
8
013aaa120
Fig 46. Connecting PCF2119x with 2 x 16 character LCD
C1 to C80 R17
8
Icons
Icons
R1 to R8
Character row 1
Character row 1
PCF2119X
C1 to C80 80 R9 to R16 R18
8
013aaa121
Fig 47. Connecting PCF2119x with 1 x 32 character LCD
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16.9 4-bit operation, 1-line display using external reset
The program must set functions prior to a 4-bit operation (see Table 38). When power is turned on, 8-bit operation is automatically selected and the PCF2119x attempts to perform the first write as an 8-bit operation. Since nothing is connected to ports DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 38 step 3). Thus, DB4 to DB7 of the Function_set are written twice.
Table 38. Step 1 2 4-bit operation, 1-line display example; using external reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 initialized by the external reset; no display appears 0 1 0 sets to 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed power supply on Function_set 0 3 0 0 Display Operation
Function_set 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 P
4
Display_ctl 0 0
turns display and cursor on; entire display is blank after initialization
5
Entry_mode_set 0 0
sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
Write_data to CGRAM/DDRAM 1 1
16.10 8-bit operation, 1-line display using external reset
Table 39 and Table 40 show an example of a 1-line display in 8-bit operation. The PCF2119x functions must be set by the Function_set instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the Return_home operation is performed.
Table 39. Step 1 2 3 8-bit operation, 1-line display example; using external reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialized by the external reset; no display appears 0 0 1 0 1 0 0 1 0 1 0 1 0 0 sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization power supply on Function_set 0 0 0 0 0 0 Display_ctl Display Operation
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Table 39. Step 4
8-bit operation, 1-line display example; using external reset (character set `A') ...continued Instruction RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM/CGRAM; display is not shifted P writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `H' 1 0 0 0 PH PHILIP 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS PHILIPS HILIPS writes `M' ILIPS M writes `ICROK' writes `O' 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 MICROKO shifts only the cursor position to the left 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 MICROKO shifts only the cursor position to the left MICROKO ICROCO MICROCO MICROCO writes `M' ICROCOM PHILIPS M returns both display and cursor to the original position (address 0) writes `C' correction; display moves to the left shifts the display and cursor to the right shifts only the cursor to the right MICROK sets mode for display shift at the time of write writes space writes `ILIP' writes `S' Entry_mode_set Display Operation
5
Write_data to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
6 7 to 10 11 12 13 14 15 to 19 20 21 22 23 24 25 26 27
Write_data to CGRAM/DDRAM 1 0 0 1 0 0 : Write_data to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 : Write_data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Curs_disp_shift Curs_disp_shift Write_data to CGRAM/DDRAM Curs_disp_shift Curs_disp_shift Write_data to CGRAM/DDRAM Return_home Entry_mode_set Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM
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Table 40. Step 1 2 3 4
8-bit operation, 1-line display and icon example; using external reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialized by the external reset; no display appears 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 1 1 0 0 0 sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted sets the CGRAM address to position of character 0; the CGRAM is selected writes data to CGRAM for icon even phase; icons appears power supply on Function_set 0 0 0 0 0 0 0 0 0 Display_ctl Entry_mode_set Display Operation
5 6 7 8 9 10 11 12 13 14 15 16 17 to 21 22
Set_CGRAM 0 1 0 0 0 0 1 0 0 0 0 0 : Set_CGRAM 0 1 0 0 0 0 1 0 1 0 1 0 : Function_set 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 0 : Return_home 0 0 0 0 0 0 0 0 1 0 PHILIPS 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 Icon_ctl 0 Function_set 1 0 0 0 P PH PHILIPS Set_DDRAM Write_data to CGRAM/DDRAM Write_data to CGRAM/DDRAM 0 1 0 0 0 1 0 0 Write_data to CGRAM/DDRAM 0 1 0 0 0 1 0 0 Write_data to CGRAM/DDRAM
sets the CGRAM address to position of character 4; the CGRAM is selected writes data to CGRAM for icon odd phase
sets bit H = 1 icons blink sets bit H = 0 sets the DDRAM address to the first position; DDRAM is selected writes `P'; the cursor is incremented by 1 and shifted to the right writes `H' writes `ILIPS' returns both display and cursor to the original position (address 0)
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16.11 8-bit operation, 2-line display
For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 41). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other.
Table 41. Step 1 2 3 4 8-bit operation, 2-line display example; using external reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Operation initialized by the external reset; no display appears 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 sets to 8-bit operation; selects 2-line display and VLCD generator off turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted P writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `HILIP' writes `S' 0 0 0 0 1 0 1 0 PHILIPS PHILIPS sets DDRAM address to position the cursor at the head of the 2nd line writes `M' 1 1 0 1 PHILIPS M PHILIPS MICROC 1 1 1 1 PHILIPS MICROCO PHILIPS MICROCO HILIPS ICROCOM sets mode for display shift at the time of write writes `M'; display is shifted to the left; the first and second lines shift together writes `ICROC' writes `O' power supply on Function_set 0 0 0 0 0 0 0 0 0 display mode on/off control Entry_mode_set
5
Write_data to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
6 to 10 11 12 1 0 13 0 0 0 1 1 1 0 0
: Write_data to CGRAM/DDRAM 1 0 Set_DDRAM
PHILIP
Write_data to CGRAM/ DDRAM 1 0 0 1 0 0 : Write_data to CGRAM/DDRAM 1 0 0 1 0 0
14 to 18 19
20
Write_data to CGRAM/DDRAM 0 0 0 0 0 0 0 1 1 1
21
Write_data to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1
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Table 41. Step 22 23
8-bit operation, 2-line display example; using external reset (character set `A') ...continued Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display : Return_home 0 0 0 0 0 0 0 0 1 0 PHILIPS MICROCOM : returns both display and cursor to the original position (address 0) Operation
16.12 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 42).
Table 42. Step 1 2 Example of I2C-bus operation; 1-line display (using external reset, assuming pin SA0 = VSS)[1] I2C-bus byte I2C-bus start slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 CO 0 4 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 control byte sets RS for following data bytes Ack 1 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction turns on display and cursor; entire display shows character code 20h (blank in ASCII-like character sets) sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed send a control byte for Function_set Display Operation initialized; no display appears during the acknowledge cycle SDA will be pulled-down by the PCF2119x
Function_set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1
5
Display_ctl DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1
6
Entry_mode_set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 1 1 0 1
7 8
I2C-bus start slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 RS 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 P
9
send a control byte for Write_data CO 0
10
Write_data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 PH PHILIP
writes `P'; the DDRAM has been selected at power-on; the cursor is incremented by 1 and shifted to the right writes `H'
11
Write_data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 : 0 0 0 1
12 to 15
PCF2119X_5
writes `ILIP'
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Table 42. Step 16
Example of I2C-bus operation; 1-line display (using external reset, assuming pin SA0 = VSS)[1] ...continued I2C-bus byte Write_data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 l2C-bus 1 STOP 0 0 1 1 1 PHILIPS PHILIPS PHILIPS PHILIPS Display Operation writes `S'
17 18 19
optional
I2C-bus start slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1
20
control byte CO 1 PHILIPS sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the data register during the acknowledge cycle the content of the data register is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a `set address' nor a Read_data has been performed; therefore the content of the data register was unknown; bit R/W has to be set to logic 1 while still in I2C-write mode DDRAM content will be read from following instructions
21
Return_home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS PHILIPS PHILIPS
22 23
I2C-bus start slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
24
control byte for read CO 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS PHILIPS
25
Read_data: 8 x SCL + master X X X X X
acknowledge[2] X X X 0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface 8 x SCL; code of letter `H' is read first; during master acknowledge code of `I' is loaded into the I2C-bus interface no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted
26
Read_data: 8 x SCL + master acknowledge[2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS PHILIPS
27
Read_data: 8 x SCL + no master acknowledge[2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1
28
[1] [2]
I2C-bus STOP
X = don't care.
PHILIPS
SDA is left at high-impedance by the microcontroller during the read acknowledge.
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16.13 Initialization
Table 43. Step 1 2 3 4 5 6 7 Initialization by instruction, 8-bit interface ([1]) Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 after internal reset has been applied 0 0 1 1 X X X X interface is 8 bits long; BF cannot be checked before this instruction power-on or unknown state wait 2 ms Function_set 0 0 wait 2 ms Function_set 0 0 0 0 1 1 X X X X wait more than 40 s Function_set 0 0 0 0 1 1 X X X X interface is 8 bits long; BF cannot be checked before this instruction interface is 8 bits long; BF cannot be checked before this instruction Description
BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 11) 8 9 10 11 12
[1]
Function_set (interface is 8 bits long) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 M 0 0 1 0 0 0 I_D H Display_ctl 0 1 S Clear_display Entry_mode_set initialization ends
X = don't care.
specify number of display lines display off
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Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation Instruction RS R/W DB7 DB6 DB5 DB4 power-on or unknown state wait 2 ms after internal reset has been applied Function_set 0 0 0 0 1 1 wait 2 ms Function_set 0 0 0 0 1 1 wait more than 40 s Function_set 0 0 0 0 1 1 interface is 8 bits long; BF cannot be checked before this instruction interface is 8 bits long; BF cannot be checked before this instruction interface is 8 bits long; BF cannot be checked before this instruction Description
Table 44. Step 1 2 3 4 5 6 7
BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 11) 8 Function_set 0 9 0 0 0 1 0 set interface to 4 bit long interface is 8 bit long set interface to 4 bits long specify number of display line
Function_set 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 M 0 0 0 0 0 1 : 1 0 0 0 0 0 0 I_D 0 H 0 0 0 1 0 S display off
10
Display_ctl 0 0
11
Clear_display 0 0
12
Entry_mode_set 0 0
13
Initialization ends
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16.14 User defined characters and symbols
Up to 16 user defined characters may be stored in the CGRAM. The content of the CGRAM is lost during power-down, therefore the CGRAM has to be rewritten after every power-on.
0 0 0 1 1 0 0 0
0 1 1 1 1 1 1 0
1 0 0 1 1 0 0 1
1 0 0 1 1 0 0 1
0 1 0 0 0 0 1 0
013aaa144
Fig 48. User defined euro currency sign
Below some source code is printed, which shows how a user defined character is defined - in this case the euro currency sign. The display used is a 2 lines by 16 characters display and the interface is the I2C-bus: // Write a user defined character into the CGRAM startI2C(); // PCF2119 slave address for write, SA0 is connected to Vdd SendI2CAddress(0x70); // MSB (Continuation bit Co) = 0, more than one byte may follow. Bit6, RS=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, basic instruction set. Next byte will be another command. i2c_write(0x24); // Set CGRAM address to 0 i2c_write(0x40); // Repeated Start condition startI2C(); SendI2CAddress(0x70); // RS=1, next byte is a data byte i2c_write(0x40); // Here the data bytes to define the character // Behind the write commands the 5x8 dot matrix is shown, the 1 represents a on pixel. // The Euro currency character can be recognized by the 0/1 pattern (see Figure 48) i2c_write(0x06); // 00110 i2c_write(0x09); // 01001 i2c_write(0x08); // 01000 i2c_write(0x1E); // 11110 i2c_write(0x1E); // 11110 i2c_write(0x08); // 01000 i2c_write(0x09); // 01001
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i2c_write(0x06); // 00110 i2c_stop(); // Until here the definition of the character and writing it into the CGRAM. Now it // still needs to be displayed. See below. // PCF2119, setting of proper display modes startI2C(); // PCF2119 slave address for write, SA0 is connected to Vdd SendI2CAddress(0x70); // MSB (Continuation bit Co) = 0, more than one byte may follow. Bit6, RS=0, next byte // is command byte i2c_write(0x00); // 2 lines x 16, 1/18 duty, extended instruction set. Next byte will be another // command. i2c_write(0x25); // Set display configuration to right to left, column 80 to 1. Row data displ. top to // bottom,1 to 16. i2c_write(0x06); // Set to character mode, full display, icon blink disabled i2c_write(0x08); // Set voltage multiplier to 2 i2c_write(0x40); // Set Vlcd and store in register VA i2c_write(0xA0); // Change from extended instruction set to basic instruction set i2c_write(0x24); // Display control: set display on, cursor off, no blink i2c_write(0x0C); // Entry mode set, increase DDRAM after access, no shift i2c_write(0x06); // Return home, set DDRAM address 0 in address counter i2c_write(0x02); // Clear entire display, set DDRAM address to 0 in address counter i2c_write(0x01); // Repeated Start condition because RS needs to be changed from 0 to 1 startI2C(); SendI2CAddress(0x70); // RS=1, next byte is data i2c_write(0x40); // Write the character at address 0, which is the previously defined Euro currency // character i2c_write(0x00); i2c_stop();
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17. Bare die outline
Bare die: 168 bumps; 7.59 x 1.71 x 0.38 mm PCF2119X
D AM4 AM3 Z
75 74
150 149
126 125
y 0
100
x E 0 10 19 22 34 35 49 A A1 detail Z 5 mm
PC2119-2
151 155 160 168 1
AM1
Y
X
e1 e b b1
L
detail X
detail Y
0
2.5 scale
Dimensions Unit mm A(1) A1(1) b(1) b1(1) 0.100 D 7.59 E 1.71 e(1) e1(1) L(1)
max 0.0225 nom 0.380 0.0175 0.050 min 0.0125
0.070 0.350 0.090
Note 1. Dimension not drawn to scale Outline version PCF2119X References IEC JEDEC JEITA European projection
AM1
50
pcf2119x_do
Issue date 09-07-16 09-08-03
Fig 49. Bare die outline of PCF2119x
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PCF2119x
LCD controllers/drivers
Table 45. Pin location All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 E T1 T2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VLCDSENSE VLCDOUT VLCDOUT VLCDOUT VLCDOUT
PCF2119X_5
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
X +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745
Y -274 -204 -134 -64 +6 +76 +146 +216 +286 +356 +426 +496 +566 +636 +706 +776 +846 +916 +986 +1196 +1406 +1616 +1686 +1756 +1826 +1896 +1966 +2036 +2106 +2176 +2246 +2316 +2386 +2456 +2666 +2736 +2806 +2876 +2946 +3016
Description logic supply voltage 1
VLCD generator supply voltage 2
data bus clock input test pin 1 test pin 2 ground 1
ground 2
input for voltage multiplier regulation VLCD output
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Product data sheet
Rev. 05 -- 13 August 2009
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NXP Semiconductors
PCF2119x
LCD controllers/drivers
Table 45. Pin location ...continued All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol VLCDOUT VLCDOUT VLCDOUT VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN R8 R7 R6 R5 R4 R3 R2 R1 R17 C80 C79 C78 C77 C76 C75 C74 C73 C72 C71 C70 C69 C68 C67 C66 C65 C64 C63 C62 C61 C60
PCF2119X_5
Pin 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
X +745 +745 +745 +745 +745 +745 +745 +745 +745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745
Y +3086 +3156 +3226 +3296 +3366 +3436 +3506 +3576 +3646 +3576 +3506 +3436 +3366 +3296 +3226 +3156 +3086 +3016 +2946 +2876 +2806 +2736 +2666 +2596 +2526 +2456 +2386 +2316 +2246 +2176 +2106 +2036 +1966 +1896 +1756 +1686 +1616 +1546 +1476 +1406
Description VLCD output
input for generation of LCD bias levels
dummy (VSS1) 50
dummy LCD row driver output
LCD column driver output
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
70 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
Table 45. Pin location ...continued All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 R17DUP C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21
PCF2119X_5
Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
X -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745
Y +1336 +1266 +1196 +1126 +1056 +986 +916 +846 +776 +706 +636 +566 +496 +426 +356 +286 +216 +146 +76 +6 -64 -134 -204 -274 -344 -414 -484 -554 -624 -694 -764 -834 -904 -974 -1044 -1114 -1184 -1254 -1324 -1394
Description LCD column driver output
LCD row driver output LCD column driver output
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
71 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
Table 45. Pin location ...continued All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 R18 R9 R10 R11 R12 R13 R14 R15 R16 SCL SCL T3 POR PD SDA SDA R/W RS DB0
PCF2119X_5
Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 151 152 153 154 155 156 157 158 159 160
X -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 -745 +745 +745 +745 +745 +745 +745 +745 +745 +745 +745
Y -1464 -1534 -1604 -1674 -1744 -1884 -1954 -2024 -2094 -2164 -2234 -2304 -2374 -2444 -2514 -2584 -2654 -2724 -2794 -2864 -2934 -3004 -3074 -3144 -3214 -3284 -3354 -3424 -3494 -3704 -3704 -3634 -3494 -3424 -3214 -3004 -2934 -2584 -2374 -2164
Description LCD column driver output
LCD row driver output
dummy (VSS1) 150
dummy I2C-bus serial clock input test pin 3 external Power-On Reset (POR) input power-down mode select input I2C-bus serial data input/output read/write input register select input 8-bit bidirectional data bus; bit 0
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
72 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
Table 45. Pin location ...continued All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol DB1 DB2 DB3/SA0 DB4 DB5 DB6 DB7 OSC Pin 161 162 163 164 165 166 167 168 X +745 +745 +745 +745 +745 +745 +745 +745 Y -1954 -1744 -1534 -1324 -1114 -904 -694 -484 Description 8-bit bidirectional data bus; bit 1 8-bit bidirectional data bus; bit 2 8-bit bidirectional data bus; bit 3 8-bit bidirectional data bus; bit 4 8-bit bidirectional data bus; bit 5 8-bit bidirectional data bus; bit 6 8-bit bidirectional data bus; bit 7 oscillator or external clock input
Table 46. Alignment mark location All X and Y coordinates are referenced to the center of the chip (dimensions in m). Symbol AM1 AM2 AM3 AM4 Pin X +745 +745 -745 -745 Y -2689 +2561 +3681 -3599
18. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.
PCF2119X_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
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NXP Semiconductors
PCF2119x
LCD controllers/drivers
19. Packing information
A C
1.1 1.2 1.3
2.1 2.2
3.1
x.1 D
F
1.y
B
y E x
001aai624
For dimensions see Table 47.
Fig 50. Tray details Table 47. A B C D E F x y Tray dimensions Description pocket pitch x direction pocket pitch y direction pocket width x direction pocket width y direction tray width x direction tray width y direction pockets in x direction pockets in y direction Value 10.16 mm 4.45 mm 7.74 mm 1.91 mm 50.8 mm 50.8 mm 4 10
Dimension
PCF2119X_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
74 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
marking code
001aaj623
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pin location diagram for the orientating and position of the type name on the die surface.
Fig 51. Tray alignment
PCF2119X_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
75 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
20. Abbreviations
Table 48. Acronym CGRAM CGROM CMOS COG DC DDRAM HBM I2C IC ITO LCD LSB MM MSB MSL MUX PCB POR RAM RMS ROM SCL SDA Abbreviations Description Character Generator RAM Character Generator ROM Complementary Metal Oxide Semiconductor Chip-On-Glass Direct Current Display Data RAM Human Body Model Inter-Integrated Circuit Integrated Circuit Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Moisture Sensitivity Level Multiplexer Printed-Circuit Board Power-On Reset Random Access Memory Root Mean Square Read Only Memory Serial Clock Line Serial Data Line
PCF2119X_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
76 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
21. References
[1] [2] [3] [4] [5] [6] [7] [8] [9] AN10170 -- Design guidelines for COG modules with NXP monochrome LCD drivers AN10706 -- Handling bare die IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices SNW-SQ-623 -- NXP store and transport conditions
[10] UM10204 -- I2C-bus specification and user manual
22. Revision history
Table 49. Revision history Release date 20090813 Data sheet status Product data sheet Change notice Supersedes PCF2119X_4 Document ID PCF2119X_5 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. The entire data sheet has been reworked for better readability and understandability Product specification Product specification Product specification Objective specification PCF2119X_3 PCF2119X_2 PCF2119X_1 -
PCF2119X_4 PCF2119X_3 PCF2119X_2 PCF2119X_1
20030130 20020116 19990302 19971121
PCF2119X_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
77 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
23. Legal information
23.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
23.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2119X_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 13 August 2009
78 of 79
NXP Semiconductors
PCF2119x
LCD controllers/drivers
25. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Oscillator and timing generator. . . . . . . . . . . . . 7 8.1.1 Timing generator. . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.2 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Reset function and Power-On Reset (POR) . . . 7 8.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 8 8.4 LCD supply voltage generator . . . . . . . . . . . . . 8 8.4.1 Programming ranges . . . . . . . . . . . . . . . . . . . . 9 8.5 LCD bias voltage generator . . . . . . . . . . . . . . 10 8.6 LCD row and column drivers . . . . . . . . . . . . . 10 9 Display data RAM and ROM . . . . . . . . . . . . . . 14 9.1 DDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2 CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.3 CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4 Cursor control circuit. . . . . . . . . . . . . . . . . . . . 23 10 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.2 Instruction register . . . . . . . . . . . . . . . . . . . . . 25 10.2.1 Basic instructions (bit H = 0 or 1) . . . . . . . . . . 27 10.2.1.1 Function_set . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2.1.2 BF_AC instructions . . . . . . . . . . . . . . . . . . . . . 27 10.2.1.3 Read_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.1.4 Write_data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.2 Standard instructions (bit H = 0) . . . . . . . . . . . 29 10.2.2.1 Clear_display . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.2.2 Return_home . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.2.3 Entry_mode_set . . . . . . . . . . . . . . . . . . . . . . . 30 10.2.2.4 Display_ctl instructions . . . . . . . . . . . . . . . . . . 30 10.2.2.5 Curs_disp_shift . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.2.6 Set_CGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.2.7 Set_DDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.3 Extended instructions (bit H = 1) . . . . . . . . . . 33 10.2.3.1 Screen_conf . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.3.2 Disp_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.3.3 Icon_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.3.4 Temp_ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2.3.5 HV_gen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3.6 VLCD_set. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 11.1 Parallel interface. . . . . . . . . . . . . . . . . . . . . . . 11.2 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 11.2.1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 I2C-bus definitions . . . . . . . . . . . . . . . . . . . . . 12 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 14 Static characteristics . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Application information . . . . . . . . . . . . . . . . . 16.1 General application information . . . . . . . . . . . 16.2 Power supply connections for internal VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 16.3 Power supply connections for external VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 16.4 Information about VLCD connections . . . . . . . 16.5 Reducing current consumption . . . . . . . . . . . 16.6 Charge pump characteristics . . . . . . . . . . . . . 16.7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8 Connections with LCD modules . . . . . . . . . . . 16.9 4-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.10 8-bit operation, 1-line display using external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11 8-bit operation, 2-line display . . . . . . . . . . . . . 16.12 I2C-bus operation, 1-line display . . . . . . . . . . 16.13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16.14 User defined characters and symbols . . . . . . 17 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Handling information . . . . . . . . . . . . . . . . . . . 19 Packing information . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information . . . . . . . . . . . . . . . . . . . . . . 23.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information . . . . . . . . . . . . . . . . . . . . 25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 38 39 39 41 42 42 45 46 47 49 52 52 52 53 53 53 54 56 57 58 58 61 62 64 66 68 73 74 76 77 77 78 78 78 78 78 78 79
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 August 2009 Document identifier: PCF2119X_5

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