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W232
Ten Output Zero Delay Buffer
Features
* * * * Well-suited to both 100- and 133-MHz designs Ten/eleven LVCMOS/LVTTL outputs 3.3V power supply Available in 24-pin TSSOP package
Key Specifications
Operating Voltage: .............................................. 3.3V 10% Operating Range: ........................25 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter: ...............................................< 150 ps Output to Output Skew: ...........................................< 100 ps Phase Error Jitter: ....................................................< 125 ps Static Phase Error: ...................................................< 150 ps
Block Diagram
Pin Configurations
FBIN CLK
PLL
FBOUT Q0 Q1 Q2
AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE0:4 FBOUT
1 2 3 4
24 23 22 21
CLK AVDD VDD Q8 Q7 GND GND Q6 Q5 VDD OE5:8 FBIN
W232-09
5 6 7 8 9 10 11 12
20 19 18 17 16 15 14 13
OE0:4 Q3 OE Q4 Q5 OE5:8 Q6 Q7 Q8 Q9 Configuration of these blocks dependent upon specific option being used.
AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE FBOUT
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
CLK AVDD VDD Q9 Q8 GND GND Q7 Q6 Q5 VDD FBIN
W232-10
Cypress Semiconductor Corporation Document #: 38-07167 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 15, 2002
W232
Pin Definitions
Pin Name CLK FBIN Pin No. (-09) 24 13 Pin No. (-10) 24 13 Pin Type I I Pin Description Reference Input: Output signals Q0:9 will be synchronized to this signal. Feedback Input: This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. Feedback Output: Typically this is connected directly to the FBIN input with a trace equal in length to the traces between outputs Q0:9 and the destination points of these output signals. Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Analog Ground Connection: Connect to common system ground plane. Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. Ground Connections: Connect to common system ground plane. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state. Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Q0:8
3, 4, 5, 8, 9, 16, 17, 20, 21 12
3, 4, 5, 8, 9, 15, 16, 17, 20, 21 12
O
FBOUT
O
AVDD AGND VDD GND OE0:4 OE OE5:8
23 1 2, 10, 15, 22 6, 7, 18, 19 11 - 14
23 1 2, 10, 14 22 6, 7, 18, 19 - 11 -
P G P G I I I
Overview
The W232 is a PLL-based clock driver designed for use in systems requiring a large number of synchronous timing signals. The clock driver has output frequencies of up to 140 MHz and output-to-output skews of less than 100 ps. The W232 provides minimum cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications. The W232 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay buffers which are not designed to pass this feature through may cause skewing failures. Output enable pins allow for shutdown of output when they are not being used. This reduces EMI and power consumption.
Document #: 38-07167 Rev. *B
Page 2 of 6
W232
1
AGND VDD Q0 Q1 Q2 GND GND Q3 Q4 VDD OE FBOUT
GND AVDD VDD Q9 Q8 GND GND Q7 Q6 Q5 VDD FBIN
24 23 22 21 20 19 18 17 16 15 14 13
VDD
0.1F
2 3 4 5 6 7 8 9
0.1F
FB
3.3V
0.1F
10F 10F
VDD FB
W232-10
VDD
0.1F
10 11 12
0.1F
VDD
Figure 1. Schematic
Spread AwareTM
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for.
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. Since the PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL.
Reference Signal
Zero Delay Buffer
Feedback Input
ASIC/ Buffer A
Figure 2. 6 Output Buffer in the Feedback Path
Document #: 38-07167 Rev. *B
Page 3 of 6
W232
Absolute Maximum Ratings[1]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi.
tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
Parameter VDD, VIN TSTG TA TB PD
Description Voltage on any Pin with Respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation
DC Electrical Characteristics: TA = 0C to 70C, VDD = 3.3V 10%
Parameter IDD VIL VIH VOL VOH IIL IIH Description Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current IOL = 12 mA IOH = -12 mA VIN = 0V VIN = VDD 2.1 50 50 2.0 0.8 Test Condition Unloaded, 100 MHz Min. Typ. Max. 200 0.8 Unit mA V V V V A A
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 10%
Parameter fOUT tR tF tICLKR tICLKF tPEJ tSK tD tLOCK tJC Description Output Frequency Output Rise Time Output Fall Time Input Clock Rise Time Input Clock Fall Time
[2] [2] [3, 4]
Test Condition 30-pF load
[5]
Min. 25
Typ.
Max. 140 2.1 2.5 4.5 4.5
Unit MHz ns ns ns ns ps ps % ms ps
0.8V to 2.0V, 30-pF load 2.0V to 0.8V, 30-pF load
CLK to FBIN Skew Variation Output to Output Skew Duty Cycle PLL Lock Time Jitter, Cycle-to-Cycle
[5]
Measured at VDD/2 All outputs loaded equally 30-pF load Power supply stable
-350 -100 43
0 0 50
350 100 58 1.0 150
Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. 3. Skew is measured at VDD/2 on rising edges. 4. Duty cycle is measured at VDD/2. 5. Production tests are run at 133 MHz. 6. For frequencies below 40 MHz, Cycle-to-Cycle Jitter degrades to 175 ps.
Ordering Information
Ordering Code W232 -09, -10 Option Number X = 24-pin TSSOP Package Type
Document #: 38-07167 Rev. *B
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W232
Package Diagram
24-Pin Thin Shrink Small Outline Package (TSSOP)
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07167 Rev. *B
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W232
Document Title: W232 Ten Output Zero Delay Buffer Document Number: 38-07167 REV. ** *A *B ECN NO. 110277 111278 122808 Issue Date 10/25/01 03/22/02 12/15/02 Orig. of Change SZV IKA RBI Description of Change Change from Spec number: 38-00827 to 38-07167 Put package type in order information table for TSSOP Add Power up Requirements to Operating Conditions Information
Document #: 38-07167 Rev. *B
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