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BB506M
Built in Biasing Circuit MOS FET IC UHF RF Amplifier
REJ03G1604-0100 Rev.1.00 Nov 26, 2007
Features
* Built in Biasing Circuit; To reduce using parts cost & PC board space. * High gain PG = 24 dB typ. (f = 900 MHz) * Low noise NF = 1.4 dB typ. (f = 900 MHz) * Low output capacitance Coss = 1.1 pF typ. (f = 1 MHz) * Provide mini mold packages: CMPAK-4 (SOT-343mod)
Outline
RENESAS Package code: PLSP0004ZA-A (Package name: MPAK-4)
2 3 1 4
1. Source 2. Gate1 3. Gate2 4. Drain
Notes:
1. Marking is "FS-". 2. BB506M is individual type number of RENESAS BBFET.
Absolute Maximum Ratings
(Ta = 25C)
Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature Symbol VDS VG1S VG2S ID PchNote3 Tch Tstg Ratings 6 +6 -0 +6 -0 30 300 150 -55 to +150 Unit V V V mA mW C C
Notes: 3. Value on the glass epoxy board (50 mm x 40 mm x 1 mm).
This device is sensitive to electro static discharge.
An adequate careful handling procedure is requested.
REJ03G1604-0100 Page 1 of 8
Rev.1.00
Nov 26, 2007
BB506M
Electrical Characteristics
(Ta = 25C)
Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss PG NF Min 6 +6 +6 -- -- 0.5 0.4 12 27 1.2 0.7 19 -- Typ -- -- -- -- -- 0.8 0.7 16 32 1.6 1.1 24 1.4 Max -- -- -- +100 +100 1.1 1.0 20 38 2.0 1.5 29 2.1 Unit V V V nA nA V V mA mS pF pF dB dB Test Conditions ID = 200 A, VG1S = VG2S = 0 IG1 = +10 A, VG2S = VDS = 0 IG2 = +10 A, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 A VDS = 5 V, VG1S = 5 V, ID = 100 A VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 k VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 k, f = 1 kHz VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 k, f = 1 MHz VDS = 5 V, VG1 = 5V, VG2S = 4 V RG = 100 k, f = 900 MHz
Bias Circuit for Operating Items (ID(op), |yfs|, Ciss, Coss, NF, PG)
VG2 Gate 2 Gate 1 RG VG1
Drain A ID
Source
REJ03G1604-0100 Page 2 of 8
Rev.1.00
Nov 26, 2007
BB506M
900 MHz Power Gain, Noise Figure Test Circuit
VG1 VG2 C4 C5 VD C6
R1
R2 C3 G2
R3 D L3
RFC Output (50 ) L4
Input (50 ) L1 L2
G1 S
C1
C2
C1, C2 C3 C4 to C6 R1 R2 R3
: : : : : :
Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 100 k 47 k 4.7 k
L1: 10
L2:
10
26
(1 mm Copper wire) Unit : mm
8
21 L4: 29
3
L3:
18
10
7
7
RFC : f1 mm Copper wire with enamel 4 turns inside dia 6 mm
REJ03G1604-0100 Page 3 of 8
Rev.1.00
Nov 26, 2007
10
3
BB506M
Main Characteristics
Maximum Channel Power Dissipation Curve
Channel Power Dissipation Pch* (mW)
400 25
Typical Output Characteristics
VG2S = 4 V VDS = VG1 20
82 k
68 k
300
ID (mA)
15
100 k
120 k
200
Drain Current
10
k
150 k
100
5
RG
=1
80
0
50
100
150
200
0 0
1
2
3
4
5
Ambient Temperature Ta (C)
* Value on the glass epoxy board (50 mm x 40 mm x 1 mm)
Drain to Source Voltage VDS (V) Forward Transfer Admittance vs. Gate1 Voltage
|yfs| (mS)
50 VDS = 5 V VG2S =4 V RG = 100 k f = 1 kHz
Drain Current vs. Gate1 Voltage
25 VDS = 5 V VG2S = 4 V RG = 100 k
ID (mA)
20
40
Forward Transfer Admittance
4V
15
4V 3V
3V 2V
30 20
Drain Current
10 5
VG2S = 1 V
0 0 1 2 3 4 5
10 V G2S = 0
2V 1V
0
0
1
2
3
4
5
Gate1 Voltage VG1 (V)
Gate1 Voltage VG1 (V)
Drain Current vs. Gate Resistance
25
5
Input Capacitance vs. Gate2 to Source Voltage
VDS = 5 V VG1 = 5 V RG = 100 k f = 1 MHz
Input Capacitance Ciss (pF)
100 1000
Drain Current ID (mA)
20
4
15
3
10 5 VDS = VG1 = 5 V VG2S = 4 V 0 10
2
1
0 0 1 2 3 4
Gate Resistance RG (k)
Gate2 to Source Voltage VG2S (V)
REJ03G1604-0100 Page 4 of 8
Rev.1.00
Nov 26, 2007
BB506M
Power Gain vs. Gate Resistance
50
VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz
Noise Figure vs. Gate Resistance
5
VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz
Power Gain PG (dB)
NF (dB) Noise Figure
40
4
30
3
20
2
10
1
0 10
0 100 1000 10 100 1000
Gate Resistance RG (k) Power Gain vs. Gate2 to Source Voltage
25
5
Gate Resistance RG (k)
Noise Figure vs. Gate2 to Source Voltage
VDS = 5 V VG1 = 5 V RG = 100 k f = 900 MHz
NF (dB) Noise Figure
4 VDS = 5 V VG1 =5 V RG = 100 k f = 900 MHz 1 2 3
Power Gain PG (dB)
20
4
15
3 2
10
5
1
0
0 1 2 3 4
Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage
40 VDS = 5 V VG1 = 5 V RG = 100 k f = 900 MHz
Gate2 to Source Voltage
VG2S (V)
Gain Reduction GR (dB)
35 30 25 20 15 10 5 0 0 1 2
3
4
Gate2 to Source Voltage VG2S (V)
REJ03G1604-0100 Page 5 of 8
Rev.1.00
Nov 26, 2007
BB506M
S11 Parameter vs. Frequency
.8 .6 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 -10 -.2 -5 -4 -3 -.4 -2 -.6 -.8 -1 -1.5 -120 -90 -60 180 0 150 30 1 1.5 2 120
S21 Parameter vs. Frequency
90
Scale: 5 / div.
60
-150
-30
Test condition: VDS = 5 V, VG1 = 5 V, VGS2 = 4 V, RG = 100 k 0.05 to 1.05 GHz (0.05 GHz step)
Test condition: VDS = 5 V, VG1 = 5 V, VGS2 = 4 V, RG = 100 k 0.05 to 1.05 GHz (0.05 GHz step)
S12 Parameter vs. Frequency
90 120
S22 Parameter vs. Frequency
.8 .6 .4 3 1 1.5 2 30 .2
Scale: 0.05 / div.
60
150
4 5 10
180
0
0
.2
.4
.6 .8 1
1.5 2
3 45 -10
-.2 -150 -30 -.4 -2 -120 -90 -60 -.6 -.8 -1 -1.5
-5 -4 -3
Test condition: VDS = 5 V, VG1 = 5 V, VGS2 = 4 V, RG = 100 k 0.05 to 1.05 GHz (0.05 GHz step)
Test condition: VDS = 5 V, VG1 = 5 V, VGS2 = 4 V, RG = 100 k 0.05 to 1.05 GHz (0.05 GHz step)
REJ03G1604-0100 Page 6 of 8
Rev.1.00
Nov 26, 2007
BB506M
S parameter
(VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 100 k, Zo = 50 )
Freq (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 S11 Mag 0.995 0.991 0.992 0.987 0.984 0.981 0.975 0.967 0.964 0.958 0.951 0.939 0.933 0.922 0.916 0.900 0.892 0.883 0.866 0.858 Deg -3.3 -6.2 -9.3 -12.4 -15.5 -18.6 -21.7 -24.8 -27.9 -30.8 -33.9 -37.0 -40.3 -43.5 -46.5 -49.6 -52.8 -56.2 -59.2 -62.0 Mag 3.28 3.26 3.28 3.26 3.27 3.24 3.23 3.24 3.22 3.22 3.22 3.20 3.20 3.20 3.19 3.19 3.18 3.18 3.17 3.16 S21 Deg 177.9 175.5 173.7 171.3 170.0 167.3 165.8 163.3 161.9 159.4 157.9 155.4 154.1 150.7 150.7 146.7 146.4 142.8 142.3 139.8 Mag 0.001 0.001 0.002 0.002 0.004 0.003 0.004 0.004 0.004 0.006 0.006 0.004 0.004 0.007 0.007 0.006 0.005 0.005 0.006 0.006 S12 Deg 17.6 75.6 73.8 79.5 116.5 89.6 76.3 87.0 91.9 89.0 100.4 84.2 85.4 80.4 93.5 108.8 122.9 120.3 104.0 121.3 Mag 0.991 0.996 0.995 0.997 0.995 0.993 0.992 0.989 0.991 0.987 0.988 0.985 0.984 0.983 0.981 0.979 0.978 0.975 0.970 0.970 S22 Deg -1.8 -3.6 -5.2 -7.0 -8.6 -10.3 -11.8 -13.9 -15.5 -17.0 -18.9 -20.4 -22.2 -23.7 -25.5 -27.2 -28.9 -30.6 -32.3 -33.8
REJ03G1604-0100 Page 7 of 8
Rev.1.00
Nov 26, 2007
BB506M
Package Dimensions
Package Name MPAK-4 JEITA Package Code SC-61AA RENESAS Code PLSP0004ZA-A Previous Code MPAK-4 / MPAK-4V MASS[Typ.] 0.013g
D e2 b1 B B e
A Q c
E
HE
L A A xM S A b
L1 A3 e2
LP
Reference Dimension in Millimeters Symbol Min Nom Max
e
A2
A
I1
b5 yS A1 S e1
b
b1
I1
c
c
b4
A-A Section
B-B Section
Pattern of terminal position areas
A A1 A2 A3 b b1 c D E e e2 HE L L1 LP x y b4 b5 e1 I1 Q
1.0 0 1.0 0.35 0.55 0.1 2.7 1.35
1.1 0.25 0.4 0.6 0.16 1.5 0.95 0.85 2.8
1.3 0.1 1.2 0.5 0.7 0.26 3.1 1.65
2.2 0.35 0.15 0.25
3.0 0.75 0.55 0.65 0.05 0.05 0.55 0.75 1.05
1.95 0.3
Ordering Information
Part Name BB506MFS-TL-E Note: Quantity 3000 Emboss Taping Shipping Container
For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.
REJ03G1604-0100 Page 8 of 8
Rev.1.00
Nov 26, 2007
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon .7.2

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