View ICS9DB102YFLFT_4536954.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATASHEET
2 Output PCI Express* Buffer with CLKREQ# Function
Description
1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without SpreadSpectrum clocking.
ICS9DB102
Features/Benefits
* * * * * CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled
Output Features
* 2 - 0.7V current mode differential output pairs (HSCL)
Key Specifications
* * Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps
Funtional Block Diagram
CLKREQ0# CLKREQ1#
PCIEX0 CLK_INT SPREAD COMPATIBLE PLL PCIEX1
C LK_IN C
PLL_BW SMBDAT SMBCLK CONTROL LOGIC
IREF
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
1
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Pin Configuration
PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA GNDA IREF **CLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK
Power Groups
Note: Pins preceeded by '**' have internal 120K ohm pull down resistors
20-pin SSOP & TSSOP Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NAME PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD **CLKREQ1# PIN TYPE INPUT INPUT INPUT INPUT POWER POWER OUTPUT OUTPUT POWER I/O INPUT POWER OUTPUT OUTPUT POWER POWER INPUT DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complementary" reference clock input. Output enable for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for SRC/PCI Express output pair '1' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
18 19 20
IREF GNDA VDDA
ICS9DB102
Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19
Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core
OUTPUT POWER POWER
Note: Pins preceeded by '**' have internal 120K ohm pull down resistors
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
2
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Absolute Max
Symbol VDDA VDD Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current IIL2 Operating Supply Current Input Frequency3 Pin Inductance1 Input Capacitance1 Clk Stabilization1,2 IDD3.3OP Fi Lpin CIN COUT TSTAB SYMBOL VIH VIL IIH IIL1 CONDITIONS MIN TYP MAX VDD + 0.3 0.8 5 UNITS NOTES V V uA uA uA 75 27 100 100 50 101 7 5 4.5 1.8 30 25 2.7 4 1000 300 33 45 5.5 0.4 mA mA MHz nH pF pF ms kHz KHz V V mA ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3.3 V +/-5% 2 VSS - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V 99 Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock
Triangular Modulation Modulation Frequency Spread Spectrum Modulation fMOD Lexmark Modulation Frequency VDD SMBus Voltage VOLSMBUS @ IPULLUP Low-level Output Voltage IPULLUP SMBus SDATA pin Current sinking at VOL = 0.4 V SCLK/SDATA TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) Clock/Data Rise Time SCLK/SDATA TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) Clock/Data Fall Time 1 Guaranteed by design and characterization, not 100% tested in production.
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
3
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER SYMBOL CONDITIONS MIN Current Source Output VO = Vx 3000 Zo Impedance Statistical measurement on single VHigh 660 Voltage High ended signal using oscilloscope Voltage Low VLow -150 Measurement on single ended Max Voltage Vovs signal using absolute value. Min Voltage Vuds -300 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Input to Output Delay Duty Cycle Output-to-Output Skew Jitter, Cycle to cycle
1 2
TYP
MAX
UNITS NOTES 1 1,3 1,3 1,3 1,3 1,3 1,3 1,2 2 2 1,2 1 1 1 1 1 1 1 1 1 1
850 150 1150 350 12 550 140 0 10.0030 10.0533 700 700 125 125 185 3.7 55 25 35 30
mV mV mV mV ppm ns ns ns ps ps ps ps ps ns % ps ps ps
250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf tpd tpdbyp dt3 tsk3 tjcyc-cyc tjcyc-cycbyp
9.9970 9.9970 9.8720 175 175 30 30
PLL Mode. Bypass mode Measurement from differential wavefrom VT = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode
135 3.2 45
. Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
4
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Electrical Characteristics - PLL Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% Group PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Parameter jpeak-hibw jpeak-lobw pllHIBW pllLOBW Description (PLL_BW = 1) (PLL_BW = 0) (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz Min 0 0 2 0.4 Typ 1 1 2.5 0.5 40 2.7 Max 2.5 2 3 1 108 3.1 Units dB dB MHz MHz ps ps rms Notes 1,4 1,4 1,5 1,5 1,2,3 1,2,3
Jitter, Phase
t jphasePLL
2.2 1.3
3.1 3
ps rms ps rms
1,2,3 1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production. 2. See http://www.pcisig.com for complete specs 3. Device driven by 932S421BGLF or equivalent 4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking. 5. Measured at 3 db dow n or half pow er point.
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
5
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
Figure 1 1 1 1 1 Figure 1 1 Figure 2 2
Figure 1 Down device routing.
L1 Rs L1' Rs HSCL Output Buffer
L2 L2 Rt L3' Rt L3
L4 L4'
PCI Ex Board Down Device REF_CLK Input
Figure 1
Figure 2 PCI Express Connector Routing.
L1 L1'
Rs
L2 L2'
L4 L4' Rt L3' Rt L3 PCI Ex Add In Board REF_CLK Input
Rs HSCL Output Buffer
Figure 2
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
6
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note
ICS874003i-02 input compatible Standard LVDS
L1 L1'
R1a
L2 L2'
R3
L4 L4'
R4
R1b HSCL Output Buffer
R2a L3'
R2b L3 Down Device REF_CLK Input
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note
3.3 Volts
R5a L4 L4'
Cc Cc
R5b
R6a
R6b PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
7
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
General SMBus serial interface information for the ICS9DB102 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D4(H) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D4(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D5(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
Not acknowledge stoP bit
ICS9DB102 REV F 08/06/07
8
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Control Function Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SW_EN Enables SMBus Control RW RW RW RW RW RW RW RW
0 Functions controlled by SMBus registers Low BW PLL bypassed (fan out mode)
1 Functions controlled by device pins
PWD 1 X X X X X 1 1
RESERVED RESERVED RESERVED RESERVED RESERVED PLL BW #adjust Selects PLL Bandwidth Bypasses PLL for board PLL Enable test
High BW PLL enabled (ZDB mode)
SMBus Table: Output Enable Register Byte 1 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Function Select Register Byte 2 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type RW RW RW RW RW RW RW RW
0 -
1
PWD X X X X X X X X
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type RW RW RW RW RW RW RW RW
0 -
1
PWD X X X X X X X X
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
9
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
SMBus Table: Vendor & Revision ID Register Byte 3 Pin # Name Control Function RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 0 0 0 0 1
Name
Control Function
Device ID = 06 Hex
Type R R R R R R R R
0 -
1
PWD 0 0 0 0 0 1 1 0
SMBus Table: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 1 0
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function
ICS9DB102
REV F 08/06/07
10
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
SYMBOL A A1 A2 b c D E E1 e L N a ZD
20-Lead, 150 mil SSOP (QSOP) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 SEE VARIATIONS SEE VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 SEE VARIATIONS SEE VARIATIONS
Ordering Information
ICS 9DB102yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function ICS9DB102 REV F 08/06/07
11
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 20 D mm. MIN 6.40 MAX 6.60 MIN .252 D (inch) MAX .260
-Ce
b SEATING PLANE
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS 9DB102yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM 2 Output Express* Buffer with CLKREQ# Function ICS9DB102 REV F 08/06/07
12
ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function
Revision History
Rev. Issue Date Description 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. 08/06/07 3. Added terminations tables. Page #
F
Various
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS9DB102YFLFT

	To Download ICS9DB102YFLFT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .