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PD -96175 IRFP4568PBF HEXFET(R) Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free D G S VDSS RDS(on) typ. max. ID (Silicon Limited) D 150V 4.8m: 5.9m: 171 G D S TO-247AC IRFP4568PBF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Max. 171 121 684 517 3.45 30 18.5 -55 to + 175 300 10lbxin (1.1Nxm) 763 See Fig. 14, 15, 22a, 22b, Units A W W/C V V/ns e C Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentA Repetitive Avalanche Energy d f mJ A mJ Thermal Resistance Symbol RJC RCS RJA Junction-to-Case Case-to-Sink, Flat Greased Surface Junction-to-Ambient j Parameter Typ. --- 0.24 --- Max. 0.29 --- 40 Units C/W ij www.irf.com 1 09/08/08 IRFP4568PBF Static @ TJ = 25C (unless otherwise specified) Symbol V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Min. Typ. Max. Units 150 --- --- 3.0 --- --- --- --- --- --- 0.17 4.8 --- --- --- --- --- 1.0 Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 5mA 5.9 m VGS = 10V, ID = 103A 5.0 V VDS = VGS, ID = 250A VDS =150V, VGS = 0V 20 A 250 VDS = 150V, VGS = 0V, TJ = 125C 100 VGS = 20V nA VGS = -20V -100 --- f Dynamic @ TJ = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)g Min. Typ. Max. Units 162 --- --- --- 151 227 --- 52 --- --- 55 --- --- 96 --- --- 27 --- --- 119 --- --- 47 --- --- 84 --- --- 10470 --- --- 977 --- --- 203 --- --- 897 --- --- 1272 --- S Conditions h VDS = 50V, ID = 103A ID = 103A VDS = 75V nC VGS = 10V ID = 103A, VDS =0V, VGS = 10V VDD = 98V ID =103A ns RG =1.0 VGS = 10V VGS = 0V VDS = 50V pF = 1.0MHz, (See Fig 5) VGS = 0V, VDS = 0V to 120V VGS = 0V, VDS = 0V to 120V f f f h(SeeFig.11) g D Diode Characteristics Symbol IS ISM VSD trr Qrr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- 171 684 A A Conditions MOSFET symbol showing the integral reverse G S --- --- 1.3 V --- 110 --- ns --- 133 --- --- 515 --- nC TJ = 125C --- 758 --- --- 8.8 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) p-n junction diode. TJ = 25C, IS = 103A, VGS = 0V TJ = 25C VR = 100V, TJ = 125C IF = 103A di/dt = 100A/s TJ = 25C f f Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.144mH RG = 25, IAS = 103A, VGS =10V. Part not recommended for use above this value. ISD 103A, di/dt 360A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C. mended footprint and soldering techniques refer to application note #AN-994. Coss while VDS is rising from 0 to 80% VDSS. 2 www.irf.com IRFP4568PBF 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 1000 TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V ID, Drain-to-Source Current (A) 100 ID, Drain-to-Source Current (A) 100 BOTTOM 10 BOTTOM 1 60s PULSE WIDTH Tj = 25C 4.5V 0.01 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) 10 4.5V 0.1 60s PULSE WIDTH Tj = 175C 1 0.1 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 1000 RDS(on) , Drain-to-Source On Resistance (Normalized) Fig 2. Typical Output Characteristics 3.0 ID = 103A VGS = 10V ID, Drain-to-Source Current (A) 100 T J = 175C 2.5 T J = 25C 10 2.0 1.5 1 VDS = 50V 60s PULSE WIDTH 0.1 3 4 5 6 7 8 9 1.0 0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 1000000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd Fig 4. Normalized On-Resistance vs. Temperature 14.0 VGS, Gate-to-Source Voltage (V) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 ID= 103A VDS= 120V VDS= 75V VDS= 30V 100000 C, Capacitance (pF) 10000 Ciss Coss 1000 Crss 100 10 1 10 100 1000 VDS, Drain-to-Source Voltage (V) 0 50 100 150 200 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 IRFP4568PBF 1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100sec T J = 175C 100 T J = 25C ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 1msec 10 DC 10msec 10 1 VGS = 0V 1.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VSD, Source-to-Drain Voltage (V) 0.1 0.1 Tc = 25C Tj = 175C Single Pulse 1 10 100 1000 Fig 7. Typical Source-Drain Diode Forward Voltage 180 160 140 ID, Drain Current (A) Fig 8. Maximum Safe Operating Area V(BR)DSS , Drain-to-Source Breakdown Voltage (V) VDS, Drain-to-Source Voltage (V) 190 185 180 175 170 165 160 155 150 145 140 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C ) Id = 5mA 120 100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature EAS , Single Pulse Avalanche Energy (mJ) Fig 10. Drain-to-Source Breakdown Voltage 3500 3000 2500 2000 1500 1000 500 0 ID TOP 21.5A 29.3A BOTTOM 103A 12.0 10.0 8.0 Energy (J) 6.0 4.0 2.0 0.0 0 20 40 60 80 100 120 140 160 25 50 75 100 125 150 175 Fig 11. Typical COSS Stored Energy VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com IRFP4568PBF 1 Thermal Response ( Z thJC ) C/W 0.1 D = 0.50 0.20 0.10 0.01 0.05 0.02 0.01 J R1 R1 J 1 2 R2 R2 R3 R3 3 Ri (C/W) C 0.06336 1 0.001 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 2 3 0.11088 0.11484 i (sec) 0.000278 0.005836 0.053606 Ci= i/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 0.01 0.1 0.0001 1E-006 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01 Fig 14. Typical Avalanche Current vs.Pulsewidth 900 800 EAR , Avalanche Energy (mJ) 700 600 500 400 300 200 100 0 25 50 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 103A Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) 175 75 100 125 150 Starting T J , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFP4568PBF 6.0 VGS(th), Gate threshold Voltage (V) 60 50 40 IRR (A) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C ) 0 0 IF = 68A V R = 100V TJ = 25C TJ = 125C 30 20 10 ID = 250A ID = 1.0mA ID = 1.0A 200 400 600 800 1000 diF /dt (A/s) Fig 16. Threshold Voltage vs. Temperature 70 60 50 IRR (A) Fig. 17 - Typical Recovery Current vs. dif/dt 3600 3200 2800 2400 QRR (A) IF = 103A V R = 100V TJ = 25C TJ = 125C IF = 68A V R = 100V TJ = 25C TJ = 125C 40 30 20 10 0 0 200 400 600 800 1000 diF /dt (A/s) 2000 1600 1200 800 400 0 200 400 600 800 1000 diF /dt (A/s) Fig. 18 - Typical Recovery Current vs. dif/dt 4000 3600 3200 2800 QRR (A) Fig. 19 - Typical Stored Charge vs. dif/dt IF = 103A V R = 100V TJ = 25C TJ = 125C 2400 2000 1600 1200 800 400 0 200 400 600 800 1000 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFP4568PBF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Body Diode Forward Drop Inductor Curent Inductor Current Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V tp DRIVER VDS L RG VGS 20V D.U.T IAS tp + V - DD A 0.01 I AS Fig 22a. Unclamped Inductive Test Circuit VDS VGS RG RD Fig 22b. Unclamped Inductive Waveforms VDS 90% D.U.T. + - VDD V10V GS Pulse Width 1 s Duty Factor 0.1 % 10% VGS td(on) tr t d(off) tf Fig 23a. Switching Time Test Circuit Current Regulator Same Type as D.U.T. Fig 23b. Switching Time Waveforms Id Vds Vgs 50K 12V .2F .3F D.U.T. VGS 3mA + V - DS Vgs(th) IG ID Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr www.irf.com Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7 IRFP4568PBF TO-247AC Package Outline Dimensions are shown in millimeters (inches) TO-247AC Part Marking Information @Y6HQG@) UCDTADTA6IADSAQ@"A XDUCA6TT@H7GA GPUA8P9@A$%$& 6TT@H7G@9APIAXXA"$A! DIAUC@A6TT@H7GAGDI@AACA Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S ,5)3( A "$C $%AAAAAAAAAAA$& 96U@A8P9@ @6SA A2A! X@@FA"$ GDI@AC TO-247AC package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. 8 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/2008 www.irf.com |
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