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| Freescale Semiconductor Order this document by MC68HC11EA9TS/D MC68HC11EA9 MC68HC711EA9 Technical Summary 8-Bit Microcontrollers 1 Introduction The MC68HC11EA9 and MC68HC711EA9 microcontroller units (MCUs) are high-performance members of the M68HC11 family of MCUs. The MC68HC(7)11EA9 MCUs have a multiplexed external address and data bus and are characterized by high speed and low power consumption. Their fully static design allows operation at frequencies from 3 MHz to dc. The addition of a phase-locked loop (PLL) frequency synthesizer to the timer circuitry further enhances low-power operation and allows the use of lower frequency crystals while maintaining a clock speed of up to 3 MHz. This document contains information concerning standard and custom-ROM devices. Standard devices are those with ROM or with EPROM replacing ROM (MC68HC711EA9). Custom-ROM devices have a ROM array that is programmed at the factory to customer specifications. Where information in this document refers to both the ROM and EPROM versions, the device is referred to as MC68HC(7)11EA9. 1.1 Features * M68HC11 CPU * 512 Bytes RAM (Data Retained During Standby, by use of VSTBY) * 12 Kbytes Mask-Programmed ROM or EPROM * 512 Bytes Electrically Erasable Programmable ROM (EEPROM) * PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint) * Multiplexed Address and Data Buses Reduce Pin Count * Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler -- Three Input Capture (IC) Channels -- Four Output Compare (OC) Channels -- One Additional Channel, Selectable as Fourth IC or Fifth OC * 8-Bit Pulse Accumulator * Phase-Locked Loop (PLL) Frequency Synthesizer for Reduced Power Consumption * Power Saving STOP and WAIT Modes * Real-Time Interrupt Circuit * Computer Operating Properly (COP) Watchdog Timer * Clock Monitor Circuit * Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI) * Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter * Five Input/Output (I/O) Ports (34 Pins) -- Four Bidirectional I/O Ports (26 Pins) -- One Fixed Input-Only Port (8 Pins) * Two Alternate, Fixed Input-Only Pins (XIRQ pin/XPIN bit and IRQ pin/IPIN bit) * Available in 52-Pin Plastic Leaded Chip Carrier (PLCC), 52-Pin Windowed Ceramic Leaded Chip Carrier (CLCC), and 56-Pin SDIP (0.070" Lead Spacing) Freescale Semiconductor, Inc... (c) Freescale Semiconductor, Inc., 2004. All rights reserved. (c) MOTOROLA INC., 1995, 1997 Freescale Semiconductor, Inc. TABLE OF CONTENTS Section Page 1 2 3 1.1 2.1 2.2 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 Introduction Freescale Semiconductor, Inc... 1 Features ......................................................................................................................................1 Device Package Options and Ordering Information 5 Available Device Packages .........................................................................................................5 Ordering Information ...................................................................................................................7 Central Processing Unit 8 Programming Model ....................................................................................................................8 CPU Registers .............................................................................................................................8 Accumulators A, B, and D ................................................................................................8 Index Register X (IX) .......................................................................................................8 Index Register Y (IY) .......................................................................................................9 Stack Pointer (SP) ............................................................................................................9 Program Counter (PC) ......................................................................................................9 Condition Code Register (CCR) .......................................................................................9 Addressing Modes ............................................................................................................9 4 Operating Modes and On-Chip Memory 10 4.1 Single-Chip Mode ......................................................................................................................10 4.2 Expanded Mode ........................................................................................................................10 4.3 Test Mode .................................................................................................................................11 4.4 Bootstrap Mode .........................................................................................................................11 4.5 Mode Selection ..........................................................................................................................11 4.6 RAM ..........................................................................................................................................12 4.7 Bootstrap ROM ..........................................................................................................................12 4.8 Memory Map and Register Block ..............................................................................................12 4.9 ROM/EPROM/OTPROM ...........................................................................................................15 4.9.1 EPROM Emulation Mode ...............................................................................................15 4.9.2 Programming an Individual EPROM Address ................................................................16 4.9.3 Programming EPROM with Downloaded Data ...............................................................17 4.10 EEPROM ...................................................................................................................................18 4.10.1 Programming and Erasing EEPROM .............................................................................18 4.10.2 CONFIG Register ...........................................................................................................20 4.10.3 EEPROM Security ..........................................................................................................21 Resets and Interrupts Parallel Input/Output Timing System 22 26 31 Phase-Locked Loop Synthesizer ...............................................................................................32 Main Timer ................................................................................................................................34 Real-Time Interrupt ...................................................................................................................42 Pulse Accumulator ....................................................................................................................43 Serial Communications Interface 47 Analog-to-Digital Converter 54 5 6 7 7.1 7.2 7.3 7.4 8 9 2 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. Register Index ADCTL . . . . . . . . . ADR1-ADR4 . . . . BPROT . . . . . . . . . CFORC . . . . . . . . . CONFIG . . . . . . . . COPRST . . . . . . . . DDRA . . . . . . . . . . DDRB . . . . . . . . . . DDRC . . . . . . . . . . DDRD . . . . . . . . . . HPRIO . . . . . . . . . INIT . . . . . . . . . . . . OC1D . . . . . . . . . . OC1M . . . . . . . . . . OPTION . . . . . . . . PACNT . . . . . . . . . PACTL . . . . . . . . . PPROG . . . . . . . . . PIOC . . . . . . . . . . . PLLCR . . . . . . . . . PORTA . . . . . . . . . PORTB . . . . . . . . . PORTC . . . . . . . . . PORTCL . . . . . . . . PORTD . . . . . . . . . PORTE . . . . . . . . . SCBDH/L . . . . . . . SCCR1 . . . . . . . . . SCCR2 . . . . . . . . . SCDRH/L . . . . . . . SCSR1 . . . . . . . . . SCSR2 . . . . . . . . . SYNR . . . . . . . . . . TCNT . . . . . . . . . . TCTL1 . . . . . . . . . . TCTL2 . . . . . . . . . . TFLG1 . . . . . . . . . TFLG2 . . . . . . . . . TI4/O5 . . . . . . . . . . TIC1-TIC3 . . . . . . TMSK1 . . . . . . . . . TMSK2 . . . . . . . . . TOC1-TOC4 . . . . . A/D Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1030 . . . . . . . . . . . . . . 62 A/D Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1031-$1034 . . . . . . . . 63 EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . .$1035 . . . . . . . . . . . . . . 21 Timer Compare Force . . . . . . . . . . . . . . . . . . . . . . . . . . .$100B . . . . . . . . . . . . . . 41 Security, COP, ROM/EPROM/EEPROM Enables . . . . . .$103F . . . . . . . . . . . 23, 28 Arm/Reset COP Timer Circuitry . . . . . . . . . . . . . . . . . . . .$103A . . . . . . . . . . . . . . 27 Port A Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1001 . . . . . . . . . . . . . . 32 Port B Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1006 . . . . . . . . . . . . . . 32 Port C Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1007 . . . . . . . . . . . . . . 33 Port D Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1009 . . . . . . . . . . . . . . 34 Highest Priority I-bit Interrupt and Miscellaneous. . . . . . .$103C . . . . . . . . . . . 12, 27 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .$103D . . . . . . . . . . . . . . 14 Output Compare 1 Data . . . . . . . . . . . . . . . . . . . . . . . . . .$100D . . . . . . . . . . . . . . 41 Output Compare 1 Mask . . . . . . . . . . . . . . . . . . . . . . . . .$100C . . . . . . . . . . . . . . 41 System Configuration Options . . . . . . . . . . . . . . . . . . . . .$1039 . . . . . . . . 26, 47, 63 Pulse Accumulator Counter . . . . . . . . . . . . . . . . . . . . . . .$1027 . . . . . . . . . . . . . . 51 Pulse Accumulator Control. . . . . . . . . . . . . . . . . . . . . . . .$1026 . . . . . . . . 46, 49, 50 EPROM and EEPROM Programming Control Register. .$103B . . . . . . . . . . . 19, 22 Port I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1002 . . . . . . . . . . . . . . 30 PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1036 . . . . . . . . . . . . . . 37 Port A Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1000 . . . . . . . . . . . . . . 31 Port B Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1004 . . . . . . . . . . . . . . 32 Port C Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1003 . . . . . . . . . . . . . . 32 Port C Latched Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1005 . . . . . . . . . . . . . . 33 Port D Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1008 . . . . . . . . . . . . . . 33 Port E Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100A . . . . . . . . . . . . . . . 34 SCI Baud Rate Select High/Low . . . . . . . . . . . . . . . . . . .$1028, $1029 . . . . . . . . 56 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102A . . . . . . . . . . . . . . 57 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102B . . . . . . . . . . . . . . 57 SCI Data High, SCI Data Low . . . . . . . . . . . . . . . . . . . . .$102E, $102F . . . . . . . . 59 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102C . . . . . . . . . . . . . . 58 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102D . . . . . . . . . . . . . . 59 Frequency Synthesizer Control . . . . . . . . . . . . . . . . . . . .$1037 . . . . . . . . . . . . . . 38 Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100E-$100F . . . . . . . . 41 Timer Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1020 . . . . . . . . . . . . . . 43 Timer Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1021 . . . . . . . . . . . . . . 43 Timer Interrupt Flag 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1023 . . . . . . . . . . . . . . 44 Timer Interrupt Flag 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1025 . . . . . . . . 45, 48, 52 Timer Input Capture 4/Output Compare 5 . . . . . . . . . . . .$101E-$101F . . . . . . . . 42 Timer Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1010-$1015 . . . . . . . . 42 Timer Interrupt Mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1022 . . . . . . . . . . . . . . 43 Timer Interrupt Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1024 . . . . . . . . . . . 44, 51 Timer Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . .$1016-$101D . . . . . . . . 42 Freescale Semiconductor, Inc... MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MODA/ LIR MODB/ VSTBY VDDSYN XFC XTAL EXTAL E IRQ/ XIRQ/ VPPEE VPPE * RESET OSC MODE CONTROL PLL CLOCK LOGIC IPIN XPIN INTERRUPT LOGIC 12 KBYTES ROM/EPROM PULSE ACCUMULATOR COP PAI OC2 OC3 OC4 OC5/IC4/OC1 IC1 IC2 PERIODIC INTERRUPT IC3 TIMER SYSTEM M68HC11 CPU 512 BYTES EEPROM 512 BYTES RAM SERIAL COMMUNICATION INTERFACE SCI Freescale Semiconductor, Inc... BUS EXPANSION ADDRESS ADDRESS/DATA R/W AS A/D CONVERTER VDD VSS STROBE AND HANDSHAKE PARALLEL I/O VRH VRL STRB STRA CONTROL PORT A CONTROL PORT B CONTROL PORT C CONTROL PORT D PORT E PA7/PAI PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PD1/TxD PD0/RxD TxD RxD PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 * VPPE APPLIES ONLY TO DEVICES WITH EPROM/OTPROM. Figure 1 MC68HC(7)11EA9 Block Diagram STRB/R/W STRA/AS EA9 BLOCK 4 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 2 Device Package Options and Ordering Information 2.1 Available Device Packages The MC68HC(7)11EA9 MCUs are available in a 52-pin plastic leaded chip carrier (PLCC) and a 52-pin ceramic leaded chip carrier (CLCC). Refer to Figure 2. A plastic 56-pin shrink DIP (SDIP) package is also available. Refer to Figure 3. The EPROM-based MC68HC711EA9 is available in a windowed 52-pin ceramic leaded chip carrier (CLCC). A one-time-programmable (OTP) version of the MC68HC711EA9 is available by ordering the device in a non-windowed package. Refer to Table 1. STRB/R/W STRA/AS MODA/LIR PE7/AN7 PE6/AN6 48 VRH Freescale Semiconductor, Inc... 52 51 50 PE3/AN3 1 49 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 PA0/IC3 6 4 5 XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET 8 9 10 11 12 13 14 15 16 17 18 19 7 MC68HC(7)11EA9 * XIRQ/VPPE IRQ/VPPEE PD0/RxD 28 22 24 26 30 21 25 23 29 27 31 32 PA2/IC1 MODB/VSTBY PD1/TxD * VPPE APPLIES ONLY TO DEVICES WITH EPROM/OTPROM. EA9 52-PIN PLCC Figure 2 MC68HC(7)11EA9 PLCC/CLCC Pin Assignments MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com PA3/OC5/IC4/OC1 PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 VDDSYN PA4/OC4/OC1 PA1/IC2 XFC VDD VSS 33 20 3 2 PE2/AN2 EXTAL VDD VSS E VRL 5 Freescale Semiconductor, Inc. VDD MODA/LIR STRA/AS E STRB/R/W EXTAL NC XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VSS VRH VRL PE7/AN7 PE3/AN3 PE6/AN6 PE2/AN2 PE5/AN5 PE1/AN1 PE4/AN4 PE0/AN0 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14 PB7/ADDR15 NC PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 Freescale Semiconductor, Inc... MC68HC(7)11EA9 (0.070" SPACING) * XIRQ/VPPE IRQ/VPPEE PD0/RxD VSS PD1/TxD MODB/VSTBY VDDSYN XFC VSS VDD * VPPE APPLIES ONLY TO MC68HC711EA9. EA9 56-PIN DIP Figure 3 MC68HC(7)11EA9 56-Pin SDIP Pin Assignments 6 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 2.2 Ordering Information The MC68HC(7)11EA9 MCUs are available in a combination of packages, speeds, and temperature ranges. Refer to Table 1. Table 1 Device Ordering Information Description Buffalo ROM 12 Kbytes ROM, 512 Bytes RAM - 40 to + 105 C - 40 to + 125 C Package 52-Pin PLCC Temperature - 40 to + 85 C Frequency 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 56-PIN SDIP (.070" Spacing) - 40 to + 105 C - 40 to + 125 C 12 Kbytes OTPROM, 512 Bytes RAM - 40 to + 105 C - 40 to + 125 C 56-PIN SDIP (.070" Spacing) - 40 to + 105 C - 40 to + 125 C 12 Kbytes EPROM, 512 Bytes RAM 52-PIN CLCC (Windowed) - 40 to + 105 C - 40 to + 125 C - 40 to + 85 C - 40 to + 85 C 52-Pin PLCC - 40 to + 85 C - 40 to + 85 C 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 3 MHz MC Order Number MC68HC11EA9BCFN2 MC68HC11EA9CFN2 MC68HC11EA9CFN3 MC68HC11EA9VFN2 MC68HC11EA9VFN3 MC68HC11EA9MFN2 MC68HC11EA9MFN3 MC68HC11EA9CP2 MC68HC11EA9CP3 MC68HC11EA9VP2 MC68HC11EA9VP3 MC68HC11EA9MP2 MC68HC11EA9MP3 MC68HC711EA9CFN2 MC68HC711EA9CFN3 MC68HC711EA9VFN2 MC68HC711EA9VFN3 MC68HC711EA9MFN2 MC68HC711EA9MFN3 MC68HC711EA9CP2 MC68HC711EA9CP3 MC68HC711EA9VP2 MC68HC711EA9VP3 MC68HC711EA9MP2 MC68HC711EA9MP3 MC68HC711EA9CFS2 MC68HC711EA9CFS3 MC68HC711EA9VFS2 MC68HC711EA9VFS3 MC68HC711EA9MFS2 MC68HC711EA9MFS3 Freescale Semiconductor, Inc... MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. 3 Central Processing Unit A full description of the CPU and instruction set of M68HC11 MCUs is beyond the scope of this summary. The programming model for the M68HC11 CPU and a brief description of the CPU registers is provided here. For more detailed information refer to the M68HC11 Reference Manual (M68HC11RM/ AD) or the programming reference guide or technical data book for the appropriate device. 3.1 Programming Model Figure 4 shows a graphic representation of the internal registers of the M68HC11 CPU. 7 15 15 ACCUMULATOR A 0 7 ACCUMULATOR B 0 0 0 0 0 0 A:B D IX IY SP PC DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER Freescale Semiconductor, Inc... 15 15 15 CONDITION CODE REGISTER S X H I N Z V C CCR HC11 PROG MODEL CARRY OVERFLOW ZERO NEGATIVE I INTERRUPT MASK HALF CARRY (FROM BIT 3) X INTERRUPT MASK STOP DISABLE Figure 4 M68HC11 Programming Model 3.2 CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed briefly in the following paragraphs, are shown in Figure 4. For a complete description of the CPU registers, addressing modes, and instruction set refer to the M68HC11 Reference Manual (M68HC11RM/AD). 3.2.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Most instructions can use accumulators A or B interchangeably, however some exceptions apply. 3.2.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can also be used as a counter or as a temporary storage register. 8 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 3.2.3 Index Register Y (IY) The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most instructions using the IY register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented. 3.2.4 Stack Pointer (SP) The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system. Normally the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that grows downward from high memory to low memory. Each time a new byte is pushed onto the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. 3.2.5 Program Counter (PC) Freescale Semiconductor, Inc... The program counter, a 16-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. 3.2.6 Condition Code Register (CCR) This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU, condition codes are automatically updated by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags. 3.2.7 Addressing Modes Six addressing modes can be used to access memory: immediate, direct, extended, indexed, inherent, and relative. These modes are not detailed in this manual. For a complete description of the CPU registers, addressing modes, and instruction set refer to the M68HC11 Reference Manual (M68HC11RM/ AD). MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. 4 Operating Modes and On-Chip Memory 4.1 Single-Chip Mode In single-chip mode, ports B and C are available for general-purpose parallel I/O. Strobe pins A (STRA) and B (STRB) can be used to control handshaking of parallel I/O on ports B and C. In this mode, all software needed to control the MCU is contained in internal resources. ROM/EPROM (if present) will always be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations $FFC0-$FFFF. 4.2 Expanded Mode In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes the same on-chip memory addresses used for single-chip mode as well as addresses for external peripherals and memory devices. The expansion bus is made up of ports B and C, and control signals AS and R/W. R/W (read/write) and AS (address strobe) allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. During the first half of each bus cycle address information is present. During the second half of each bus cycle the pins become the bidirectional data bus. AS is an active-high latch enable signal for an external address latch. Address information is allowed through the transparent latch while AS is high and is latched when AS drives low. Figure 5 shows an example of address and data demultiplexing. Freescale Semiconductor, Inc... PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AS DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 LE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q0 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 MCU R/W E MC54/74HC373 WE ADDR/DATA DEMUX DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Figure 5 Address/Data Demultiplexing 10 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 4.3 Test Mode Test mode, a variation of the expanded mode, is primarily used during Freescale's internal production testing; however, it is accessible for programming the CONFIG register, programming calibration data into EEPROM, and supporting emulation and debugging during development. Refer to Figure 6. 4.4 Bootstrap Mode Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode allows special-purpose programs to be entered into internal RAM. When boot mode is selected at reset, a small bootstrap ROM becomes present in the memory map. Reset and interrupt vectors are located in this ROM at $BFC0- $BFFF. The bootstrap ROM contains a small program which initializes the SCI and allows the user to download a program into on-chip RAM. The size of the downloaded program can be as large as the size of the on-chip RAM. After a four-character delay, or after receiving the character for the highest address in RAM, control passes to the loaded program at $0000. Refer to Figure 6. Freescale Semiconductor, Inc... 4.5 Mode Selection The four mode variations are selected by the logic levels present on the MODA and MODB pins during reset. The MODA and MODB logic levels determine the logic state of SMOD and the MDA control bits in the highest priority I-bit interrupt and miscellaneous (HPRIO) register. See Table 2 for further information. After reset is released, the mode select pins no longer influence the MCU operating mode. In singlechip operating mode, the MODA pin is connected to a logic level zero. In expanded mode, MODA is normally connected to VDD through a pull-up resistor of 4.7 k. The MODA pin also functions as the load instruction register (LIR) pin when the MCU is not in reset. The LIR signal is useful during program debugging. The open-drain active low LIR output pin drives low during the first E cycle of each instruction. The MODB pin also functions as standby power input (VSTBY), which allows RAM contents to be maintained in absence of VDD. HPRIO -- Highest Priority I-bit Interrupt and Miscellaneous BIT 7 RBOOT* 0 6 SMOD* 0 5 MDA* 0 4 IRVNE 0 3 PSEL3 0 2 PSEL2 0 1 PSEL1 0 BIT 0 PSEL0 0 $103C RESET: *The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up. RBOOT -- Read Bootstrap ROM/EPROM Valid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes. 0 = Bootstrap ROM disabled and not in map 1 = Bootstrap ROM enabled and in map at $BF00-$BFFF SMOD and MDA -- Special Mode Select and Mode Select A These two bits can be read at any time. They can be written anytime in special modes. MDA can only be written once in normal modes. SMOD cannot be set once it has been cleared. Table 2 Operating Mode Selection Inputs MODA MODB 0 1 0 1 1 1 0 0 Mode Single Chip Expanded Bootstrap Special Test Latched at Reset MDA 0 1 0 1 SMOD 0 0 1 1 MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. IRV(NE) -- Internal Read Visibility(Not E) IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on or off. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero. 0 = No internal read visibility on external bus 1 = Data from internal reads is driven out the external data bus. In single-chip modes this bit determines whether the E clock drives out from the chip. 0 = E is driven out from the chip. 1 = E pin is driven low. Refer to the following table. Table 3 IRVNE Control vs. Operating Mode Operating Mode Single Chip Expanded Bootstrap IRVNE Bit Out of Reset 0 0 0 1 E Clock Out of Reset On On On On IRV Function Out of Reset Off Off Off On IRVNE Bit Affects Only E IRV E IRV Freescale Semiconductor, Inc... Special Test PSEL[3:0] -- Priority Select Bits [3:0] Refer to 5 Resets and Interrupts 4.6 RAM In all modes RAM is enabled and present at locations $0000-$01FF. The RAM can be mapped to any 1-Kbyte boundary by writing an appropriate value to the INIT register. The INIT register must be written during the first 64 cycles after reset in expanded and single-chip modes. If RAM and the register block are placed at the same 1-Kbyte boundary, the first 64 bytes of RAM are inaccessible. This is due to an on-chip hardware priority scheme which eliminates conflicts which could arise from multiple resources sharing address locations. Figure 6 shows the location of the RAM array. 4.7 Bootstrap ROM When operating in normal modes (SMOD = 0), the bootstrap ROM is disabled and removed from the memory map. In bootstrap and special test modes, bootstrap ROM is present at $BF00-$BFFF. Bootstrap ROM cannot be remapped to other locations. Figure 6 shows the location of the bootstrap ROM array. The bootstrap ROM contains a small program that allows program code to be downloaded into on-chip RAM. When the MC68HC(7)11EA9 enters bootstrap mode, bootloader firmware residing in bootstrap ROM begins the downloading procedure by initializing the SCI system and transmitting a break out the SCI TxD pin. The SCI then waits for the first character to be received. After the first character is received on the RxD pin of the SCI, bootloader firmware begins counting the number of bytes received. When an idle time of four characters or the character for address $01FF is received, the bootloader program terminates the download and control is passed to the loaded program at $0000. For a detailed description of the M68HC11 bootstrap mode, refer to application note M68HC11 Bootstrap Mode (AN1060/D). 4.8 Memory Map and Register Block The operating mode determines memory mapping and whether external addresses can be accessed. Memory locations for on-chip resources are the same for both expanded and single-chip modes. Control bits in the CONFIG register allow ROM/EPROM and EEPROM to be disabled from the memory map. The RAM is mapped to $0000 after reset. It can be placed at any 4 Kbyte boundary ($x000) by writing an appropriate value to the INIT register. The 64-byte register block is mapped to $1000 after reset and can also be placed at any 4 Kbyte boundary ($x000) by writing an appropriate value to the INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be inaccessible. Table 4 shows the arrangement of control registers and bits within the register block. 12 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. $0000 EXT $1000 EXT EXT EXT 0000 512 BYTES RAM 01FF 1000 64-BYTE REGISTER BLOCK 103F B600 512 BYTES EEPROM $B600 EXT EXT B7FF BF00 BFFF $D000 BOOT ROM BFC0 BFFF 12 KBYTES ROM/EPROM FFC0 FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST EA9 MEM MAP SPECIAL MODES INTERRUPT VECTORS Freescale Semiconductor, Inc... D000 $FFFF FFFF NORMAL MODES INTERRUPT VECTORS Figure 6 MC68HC(7)11EA9 Memory Map INIT -- RAM and I/O Mapping Register BIT 7 RAM3 0 6 RAM2 0 5 RAM1 0 4 RAM0 0 3 REG3 0 2 REG2 0 1 REG1 0 BIT 0 REG0 1 $103D RESET: RAM[3:0] -- RAM Map Position These four bits, which specify the upper hexadecimal digit of the RAM address, control position of RAM in the memory map. RAM can be positioned at the beginning of any 4 Kbyte page in the memory map. It is initialized to address $0000 out of reset. REG[3:0] -- 64-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. The register block, positioned at the beginning of any 4 Kbyte page in the memory map, is initialized to address $1000 out of reset. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. Table 4 MC68HC(7)11EA9 Registers (Sheet 1 of 2) $1000 $1001 $1002 $1003 $1004 $1005 $1006 $1007 $1008 $1009 $100A $100B $100C $100D $100E $100F $1010 $1011 $1012 $1013 $1014 $1015 $1016 $1017 $1018 $1019 $101A $101B $101C $101D $101E $101F $1020 $1021 $1022 $1023 $1024 $1025 $1026 $1027 $1028 $1029 $102A $102B $102C $102D $102E BIT 7 PA7 DDA7 STAF PC7 PB7 PCL7 DDB7 DDC7 XPIN DISX PE7 FOC1 OC1M7 OC1D7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 OM2 EDG4B OC1I OC1F TOI TOF 0 Bit 7 BTST SBR7 LOOPS TIE TDRE 0 R8 6 PA6 DDA6 STAI PC6 PB6 PCL6 DDB6 DDC6 IPIN DISI PE6 FOC2 OC1M6 OC1D6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 OL2 EDG4A OC2I OC2F RTII RTIF PAEN 6 BSPL SBR6 WOMS TCIE TC 0 T8 5 PA5 DDA5 CWOM PC5 PB5 PCL5 DDB5 DDC5 0 0 PE5 FOC3 OC1M5 OC1D5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 OM3 EDG1B OC3I OC3F PAOVI PAOVF PAMOD 5 BRST SBR5 0 RIE RDRF 0 0 4 PA4 DDA4 HNDS PC4 PB4 PCL4 DDB4 DDC4 0 0 PE4 FOC4 OC1M4 OC1D4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 OL3 EDG1A OC4I OC4F PAII PAIF PEDGE 4 SBR12 SBR4 M ILIE IDLE 0 0 3 PA3 DDA3 OIN PC3 PB3 PCL3 DDB3 DDC3 0 0 PE3 FOC5 OC1M3 OC1D3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 OM4 EDG2B I4/O5I I4/O5F 0 0 0 3 SBR11 SBR3 WAKE TE OR 0 0 2 PA2 DDA2 PLS PC2 PB2 PCL2 DDB2 DDC2 0 0 PE2 0 0 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 OL4 EDG2A IC1I IC1F 0 0 I4/O5 2 SBR10 SBR2 ILT RE NF 0 0 1 PA1 DDA1 EGA PC1 PB1 PCL1 DDB1 DDC1 PD1 DDD1 PE1 0 0 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 OM5 EDG3B IC2I IC2F PR1 0 RTR1 1 SBR9 SBR1 PE RWU FE 0 0 BIT 0 PA0 DDA0 INVB PC0 PB0 PCL0 DDB0 DDC0 PD0 DDD0 PE0 0 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 OL5 EDG3A IC3I IC3F PR0 0 RTR0 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 PORTA DDRA PIOC PORTC PORTB PORTCL DDRB DDRC PORTD DDRD PORTE CFORC OC1M OC1D TCNT (HI) TCNT (LO) TIC1 (HI) TIC1 (LO) TIC2 (HI) TIC2 (LO) TIC3 (HI) TIC3 (LO) TOC1 (HI) TOC1 (LO) TOC2 (HI) TOC2 (LO) TOC3 (HI) TOC3 (LO) TOC4 (HI) TOC4 (LO) TI4/O5 (HI) TI4/O5 (LO) TCTL1 TCTL2 TMSK1 TFLG1 TMSK2 TFLG2 PACTL PACNT SCBDH SCBDL SCCR1 SCCR2 SCSR1 SCSR2 SCDRH Freescale Semiconductor, Inc... 14 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. Table 4 MC68HC(7)11EA9 Registers (Sheet 2 of 2) $102F $1030 $1031 $1032 $1033 $1034 $1035 $1036 $1037 $1038 $1039 $103A $103B $103C $103D $103E BIT 7 R7/T7 CCF Bit 7 Bit 7 Bit 7 Bit 7 0 PLLON SYNX1 ADPU Bit 7 ODD RBOOT RAM3 -- 6 R6/T6 0 6 6 6 6 0 BCS SYNX0 CSEL 6 EVEN SMOD RAM2 -- 5 R5/T5 SCAN 5 5 5 5 0 AUTO SYNY5 IRQE 5 ELAT1 MDA RAM1 -- 0 4 R4/T4 MULT 4 4 4 4 PTCON BWC SYNY4 DLY 4 BYTE IRVNE RAM0 -- 0 3 R3/T3 CD 3 3 3 3 BPRT3 VCOT SYNY3 CME 3 ROW PSEL3 REG3 -- NOSEC 2 R2/T2 CC 2 2 2 2 BPRT2 MCS SYNY2 0 2 ERASE PSEL2 REG2 -- NOCOP 1 R1/T1 CB 1 1 1 1 BPRT1 LCK SYNY1 CR1 1 EELAT PSEL1 REG1 -- ROMON BIT 0 R0/T0 CA Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 WEN SYNY0 CR0 Bit 0 PGM PSEL0 REG0 -- EEON SCDRL ADCTL ADR1 ADR2 ADR3 ADR4 BPROT PLLCR SYNR Reserved Freescale Semiconductor, Inc... OPTION COPRST PPROG HPRIO INIT TEST12 CONFIG $103F 0 0 Notes: 1. MC68HC711EA9 only. 2. Factory test only. 4.9 ROM/EPROM/OTPROM The MC68HC11EA9 contains 12 Kbytes of mask-programmed ROM. The ROM array is programmed at the factory to customer specifications and cannot be altered. The ROM array can be disabled by clearing the ROMON bit in the CONFIG register. The MC68HC711EA9 MCU contains 12 Kbytes of on-chip EPROM/OTPROM. When the MC68HC711EA9 is packaged in a windowed CLCC, the 12 Kbytes of EPROM may be erased by exposing the device to ultraviolet light. An MC68HC711EA9 MCU packaged in a non-windowed case contains 12 Kbytes of one-time-programmable ROM (OTPROM). Using the on-chip EPROM/OTPROM programming feature requires an external 12.25-volt power supply (VPPE). Normal programming is accomplished using the EPROM/OTPROM programming register (PPROG). PPROG is the combined EPROM/OTPROM and EEPROM programming register (MC68HC711EA9 only). For the MC68HC11EA9, PPROG is used for programming EEPROM only. There are three possible methods of programming and verifying EPROM. 4.9.1 EPROM Emulation Mode The EPROM emulation (PROG) mode allows the on-chip EPROM/OTPROM to be programmed as a standard EPROM by adapting the MCU footprint to that of the 27256-type EPROM, as shown in Figure 7. Grounding the RESET, MODA, and MODB pins places the MCU in PROG mode. An appropriate EPROM programmer can then be used to enter data into the on-chip EPROM. Figure 7 shows the MCU pin functions while the device is in PROG mode. If the MCU is operating with programming voltage present on the XIRQ/VPPE pin, the IRQ pin (CE pin in PROG mode) must be pulled high before the address and data are changed to program the next location. NOTE PROG mode is disabled in devices having the security feature. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. EPROM MODE PIN CONNECTIONS MCU PIN FUNCTIONS EPROM PIN FUNCTIONS Freescale Semiconductor, Inc... A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND GND GND GND GND GND GND GND NOTE 1 GND GND GND GND GND GND PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 NC PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 INTERNAL 12-KBYTE EPROM O0 O1 O2 O3 O4 O5 O6 O7 OE VPP CE VCC GND PD0/RxD PD1/TxD PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 STRA/AS STRB/R/W PB7/ADDR15 XIRQ IRQ VDD VSS O0 O1 O2 O3 O4 O5 O6 O7 OE VPP CE VCC GND PA4/OC4/OC1 PA5/OC3/OC1 NC NC NOTE 2 NC NC GND GND GND GND GND GND GND MC68HC711EA9 XTAL E EXTAL PA6/OC2/OC1 PA7/PAI/OC1 V RH V RL VDDSYN XFC MODA/LIR MODB/VSTBY RESET PB6/ADDR14 PA0/IC3 PA1/IC2 NOTE 3 NOTES: 1. UNUSED INPUTS -- GROUNDING IS RECOMMENDED. 2. UNUSED OUTPUTS -- THESE PINS SHOULD BE LEFT UNTERMINATED. 3. THESE PINS MUST BE GROUNDED FOR PROG MODE OPERATION. 7EA9 PROG CONN Figure 7 MC68HC711EA9 PROG Mode Connections 4.9.2 Programming an Individual EPROM Address In the second method, the MCU programs its own EPROM by controlling the PPROG register. Use the following procedure to program the EPROM through the MCU with the ROMON bit set in the CONFIG register. The 12 volt nominal programming voltage must be present on the XIRQ/VPPE pin. Any operating mode can be used. 1. 2. 3. 4. Write to PPROG to set the ELAT bit. Write the data to the desired address. Write to PPROG to set both the ELAT and PGM bits. Delay for 10 ms or more, as appropriate. MC68HC11EA9 MC68HC11EA9TS/D 16 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 5. Clear the PGM bit to turn off the VPPE voltage. 6. Clear all bits in the PPROG register to reconfigure the EPROM address and data buses for normal operation. NOTE PROG mode is initiated when RESET, MODA, and MODB pins are pulled low (the pin state required to enter bootstrap mode). This means that if these three pins are pulled low and VPPE is present on the XIRQ pin, the EPROM will be programmed. To prevent this, place a pull-up resistor on the IRQ pin (CE pin in PROG mode). When the device goes into reset, the PGM bit is forced to the voltage disable state (EPGM = 0) before the address/data latches are enabled to the external input lines. Only after this occurs is voltage control returned to the IRQ pin. 4.9.3 Programming EPROM with Downloaded Data Freescale Semiconductor, Inc... When using this method, the EPROM is programmed by software while in the special test or bootstrap modes. User-developed software can be uploaded through the SCI, or a ROM resident EPROM programming utility can be used. To use the resident utility, bootload a three-byte program consisting of a single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming utility. The utility program sets the X and Y index registers to default values, then receives programming data from an external host and puts it in EPROM. The value in IX determines programming delay time. The value in IY is a pointer to the first address in EPROM to be programmed (default = $D000). When the utility program is ready to receive programming data, it sends the host the $FF character. Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting with the first location in the EPROM array. After the last byte to be programmed is sent and the corresponding verification data is returned, the programming operation is terminated by resetting the MCU. PPROG -- EPROM and EEPROM Programming Control Register BIT 7 ODD 0 6 EVEN 0 5 ELAT* 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 BIT 0 PGM 1 $103B RESET: * MC68HC711EA9 only. ODD -- Program Odd Rows in Half of EEPROM (TEST) Refer to 4.10 EEPROM. EVEN -- Program Even Rows in Half of EEPROM (TEST) Refer to 4.10 EEPROM. ELAT -- EPROM/OTPROM Latch Control When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when EPGM = 1; then the write to ELAT is disabled. For MC68HC711EA9, EPGM enables the high voltage necessary for both EPROM/OTPROM and EEPROM programming. For MC68HC711EA9 ELAT and EELAT are mutually exclusive and cannot both equal one. 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming BYTE -- Byte/Other EEPROM Erase Mode Refer to 4.10 EEPROM. ROW -- Row/All EEPROM Erase Mode Refer to 4.10 EEPROM. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. ERASE -- Erase/Normal Control for EEPROM Refer to 4.10 EEPROM. EELAT -- EEPROM Latch Control 0 = EEPROM address and data bus configured for normal reads 1 = EEPROM address and data bus configured for programming or erasing PGM -- EPROM/OTPROM/EEPROM Programming Voltage Enable 0 = Programming voltage to EPROM/OTPROM/EEPROM array disconnected 1 = Programming voltage to EPROM/OTPROM/EEPROM array connected PGM can be read any time and can only be written when ELAT = 1 (for EPROM/OTPROM programming) or when EELAT = 1 (for EEPROM programming). 4.10 EEPROM Freescale Semiconductor, Inc... MC68HC(7)11EA9 MCUs contain 512 bytes of EEPROM. The 512-byte EEPROM is initially located at $B600 after reset, assuming EEPROM is enabled in the memory map by the EEON bit in the CONFIG register. EEPROM can be placed at any 4 Kbyte boundary ($x600) by writing appropriate values to the INIT register. Note that EEPROM can be mapped such that it contains the vector space. See Figure 6. 4.10.1 Programming and Erasing EEPROM Programming and erasing the EEPROM is controlled by the PPROG register, and is dependent upon the block protect (BPROT) register value. The erased state of an EEPROM bit is one. During a read operation, bit lines are precharged to one. The floating gate devices of programmed bits conduct and pull the bit lines to zero. Unprogrammed bits remain at the precharged level and are read as ones. Programming a bit to one causes no change. Programming a bit to zero changes the bit so that subsequent reads return zero. When appropriate bits in the BPROT register are cleared, the PPROG register controls programming and erasing of the EEPROM. The PPROG register can be read or written at any time, but logic enforces defined programming and erasing sequences to prevent unintentional changes to data in EEPROM. When the EELAT bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM. The on-chip charge pump that generates the EEPROM programming voltage from VDD uses MOS capacitors, which are relatively small in value. The efficiency of this charge pump and its drive capability are affected by the level of VDD and the frequency of the driving clock. The clock source driving the charge pump is software selectable. When the clock select (CSEL) bit in the OPTION register is zero, the E clock is used; when CSEL is one, an on-chip resistor-capacitor (RC) oscillator is used. The RC oscillator should be used when E < 1 MHz. This RC oscillator will drive the A/D circuitry as well as the EEPROM charge pump when CSEL = 1. The EEPROM programming voltage connection to the EEPROM array is not enabled until there has been a write to PPROG with EELAT set and PGM cleared. This must be followed by a write to a valid EEPROM location or to the CONFIG address, and then a write to PPROG with both EELAT and PGM set. Any attempt to set both EELAT and PGM during the same write operation results in neither bit being set. The erased state of an EEPROM byte is $FF (all ones). To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, then complete the following steps using the PPROG register: 1. Set the ERASE, EELAT, and appropriate BYTE and ROW bits in PPROG register. 2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to any location in the row. Bulk erase is done by writing to any location in the array. 3. Set the ERASE, EELAT, EEPGM, and appropriate BYTE and ROW bits in PPROG register. 18 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 4. Delay for 10 ms or more, as appropriate. 5. Clear the EEPGM bit in PPROG to turn off the programming voltage. 6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation. To program the EEPROM, ensure the proper bits of the BPROT register are cleared and use the PROG register to complete the following steps: 1. 2. 3. 4. 5. 6. Set the EELAT bit in PPROG register. Write data to the desired address. Set EEPGM bit in PPROG. Delay for 10 ms or more, as appropriate. Clear the EEPGM bit in PPROG to turn off the programming voltage. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation. CAUTION Since it is possible to perform other operations while the EEPROM programming/ erase operation is in progress, it is common to start the operation then return to the main program until the 10 ms is completed. When the EELAT bit is set at the beginning of a program/erase operation, the EEPROM is electronically removed from the memory map; thus, it is not accessible during the program/erase cycle. Care must be taken to ensure that EEPROM resources will not be needed by any routines in the code during the 10 ms program/erase time. BPROT -- EEPROM Block Protect BIT 7 -- 0 6 -- 0 5 -- 0 4 PTCON 1 3 BPRT3 1 2 BPRT2 1 1 BPRT1 1 BIT 0 BPRT0 1 Freescale Semiconductor, Inc... $1035 RESET: Active bits in BPROT reset to ones in all modes and can only be cleared during the first 64 cycles out of reset. Bits can be set only once in normal modes. In special modes, bits can be set and cleared repeatedly. Bits [7:5] -- Not implemented Always read zero PTCON -- Protect CONFIG Register 0 = CONFIG register can be programmed or erased normally 1 = CONFIG register cannot be programmed or erased BPRT[3:0] -- Block Protect Bits for EEPROM When set, these bits protect a block of EEPROM from being programmed or electronically erased. Ultraviolet light, however can erase the entire EEPROM contents regardless of BPRT[3:0] (windowed packages only). When cleared, they allow programming and erasure of the associated block. Table 5 EEPROM Block Protect Bit Name BPRT0 BPRT1 BPRT2 BPRT3 Block Protected $B600-$B61F $B620-$B65F $B660-$B6DF $B6E0-$B7FF Block Size 32 Bytes 64 Bytes 128 Bytes 288 Bytes MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. PPROG -- EPROM and EEPROM Programming Control Register BIT 7 ODD 0 6 EVEN 0 5 ELAT* 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 BIT 0 PGM 1 $103B RESET: * MC68HC711EA9 only. ODD -- Program Odd Rows in Half of EEPROM (TEST) EVEN -- Program Even Rows in Half of EEPROM (TEST) ELAT -- EPROM/OTPROM Latch Control MC68HC711EA9 only. Refer to 4.9.3 Programming EPROM with Downloaded Data. BYTE -- Byte/Other EEPROM Erase Mode 0 = Row or bulk erase mode used 1 = Erase only one byte of EEPROM ROW -- Row/All EEPROM Erase Mode (only valid when BYTE = 0) 0 = All 512 bytes of EEPROM erased 1 = Erase only one 16-byte row of EEPROM Table 6 BYTE/ROW Control Bits BYTE 0 0 1 1 ROW 0 1 0 1 Action Bulk Erase (All 512 Bytes) Row Erase (16 Bytes) Byte Erase Byte Erase Freescale Semiconductor, Inc... ERASE -- Erase/Normal Control for EEPROM 0 = Normal read or program mode 1 = Erase mode EELAT -- EEPROM Latch Control 0 = EEPROM address and data bus configured for normal reads 1 = EEPROM address and data bus configured for programming or erasing PGM -- EPROM/OTPROM/EEPROM Programming Voltage Enable 0 = Programming voltage to EPROM/OTPROM/EEPROM array disconnected 1 = Programming voltage to EPROM/OTPROM/EEPROM array connected PGM can be read any time and can only be written when ELAT = 1 (for EPROM/OTPROM programming) or when EELAT = 1 (for EEPROM programming). 4.10.2 CONFIG Register The CONFIG register consists of an EEPROM byte and static latches that control the start-up configuration of the MCU. The contents of the EEPROM byte are transferred into static working latches during reset sequences. The operation of the MCU is controlled directly by these latches and not by CONFIG itself. Although the byte is not included in the 512-byte EEPROM array, programming the CONFIG register requires the same procedure as any byte in the array. In normal modes, changes to CONFIG do not affect operation of the MCU until after the next reset sequence. When programming, the CONFIG register itself is accessed. When the CONFIG register is read, the static latches are accessed. 20 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. CONFIG -- Security, COP, ROM/EPROM, and EEPROM Enables BIT 7 -- RESETS: S. Chip: Boot: Exp.: Test: 0 0 0 0 6 -- 0 0 0 0 5 -- 0 0 0 0 4 -- 0 0 0 0 3 NOSEC U U 1 1 2 NOCOP U U(L) U U(L) 1 ROMON 1 U U U BIT 0 EEON U U U U $103F U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset (unchanged), but the function of COP is controlled by DISR bit in TEST1 register. Bits [7:4] -- Not Implemented Always read zero Freescale Semiconductor, Inc... NOSEC -- Security Disable NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If security mask option is omitted NOSEC always reads one. The security feature protects the contents of RAM and EEPROM. 0 = Security enabled 1 = Security disabled NOCOP -- COP System Disable Refer to 5 Resets and Interrupts. ROMON -- ROM/EPROM/OTPROM Enable When this bit is zero, the ROM or EPROM/OTPROM is disabled and that memory space becomes externally addressed. In single-chip mode, ROMON is forced to one to enable ROM/EPROM/OTPROM regardless of the state of the ROMON bit. 0 = ROM/EPROM/OTPROM disabled from the memory map 1 = ROM/EPROM/OTPROM present in the memory map EEON -- EEPROM Enable When this bit is zero, the EEPROM is disabled and that memory space becomes externally addressed. 0 = EEPROM removed from the memory map 1 = EEPROM present in the memory map 4.10.3 EEPROM Security The optional security feature, available only on ROM-based MCUs, protects the EEPROM and RAM contents from unauthorized access. A program, or a key portion of a program, can be protected against unauthorized duplication. To accomplish this, the protection mechanism restricts operation of protected devices to the single-chip modes. This prevents the memory locations from being monitored externally because single-chip modes do not allow visibility of the internal address and data buses. Resident programs, however, have unlimited access to the internal EEPROM and RAM and can read, write, or transfer the contents of these memories. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. 5 Resets and Interrupts All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows: * RESET, or Power-On Reset * Clock Monitor Fail * COP Failure The 18 interrupt vectors service 22 interrupt sources (3 non-maskable, 19 maskable). The 3 nonmaskable interrupt sources are as follows: * Illegal Opcode Trap * Software Interrupt * XIRQ Pin (X Interrupt) On-chip peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized according to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (HPRIO). The HPRIO register can be written at any time, provided bit I in the CCR is set. Eighteen interrupt sources in the MC68HC(7)11EA9 MCUs are subject to masking by the global interrupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in the M68HC11 have separate interrupt vectors; therefore, there is usually no need for software to poll control registers to determine the cause of an interrupt. For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request would be to read the SCI status register to check for receive errors, then to read the received data from the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any special instructions. The computer operating properly (COP) watchdog and the clock monitor are both circuits that force a reset sequence when a malfunctioning clock is encountered. The COP function forces a reset when a timeout occurs. The timeout period is determined by programming CR[1:0] in OPTION register. The clock monitor circuit forces a reset sequence whenever the clock is slow or absent. The CME bit in the OPTION register enables the clock monitor circuit. To use STOP mode the clock monitor must be disabled before the STOP instruction is executed or a reset sequence will occur. Refer to the following table for a list of interrupt and reset vector assignments. Table 7 Interrupt and Reset Vector Assignments Vector Address FFC0, C1 -- FFD4, D5 FFD6, D7 Reserved SCI Serial System * SCI Receive Data Register Full * SCI Receiver Overrun * SCI Transmit Data Register Empty * SCI Transmit Complete * SCI Idle Line Detect FFD8, D9 Reserved -- Interrupt Source CCR Mask -- Bit I RIE RIE TIE TCIE ILIE -- -- Local Mask -- Priority (1 = High) -- 18 Freescale Semiconductor, Inc... 22 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. Table 7 Interrupt and Reset Vector Assignments FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Input Capture 4/Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real-Time Interrupt IRQ (External Pin) XIRQ Pin Software Interrupt Illegal Opcode Trap COP Failure Clock Monitor Fail RESET Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit I Bit X None None None None None PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCOP CME None 17 16 15 14 13 12 11 10 9 8 7 6 5 4 * * 3 2 1 Freescale Semiconductor, Inc... * Same level as an instruction OPTION -- System Configuration Options BIT 7 6 5 4 3 2 1 BIT 0 ADPU CSEL IRQE* DLY* CME -- CR1* CR0* RESET: 0 0 0 1 0 0 0 0 * Can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. $1039 ADPU -- A/D Converter Power up Refer to 9 Analog-to-Digital Converter CSEL -- Clock Select Refer to 4.10 EEPROM. IRQE -- IRQ Select Edge-Sensitive Only 0 = IRQ input is active-low 1 = IRQ input recognizes falling edges only DLY -- Enable Oscillator Start-up Delay 0 = No stabilization delay on exit from STOP mode. 1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode. CME -- Clock Monitor Enable 0 = Clock monitor disabled; slow clock can be used. 1 = Slow or stopped clocks cause COP failure reset. Bit 2 -- Not implemented Always reads zero CR[1:0] -- COP Timer Rate Select Refer to the following table of COP timer rates. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. Table 8 COP Timer Rate Selection Rate CR[1:0] 00 01 10 11 Selected 215 /E 217 / E 219 / E 221 /E 32.768 ms 131.072 ms 524.288 ms 2.097 s Period Length E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz 16.384 ms 65.536 ms 262.140 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms COPRST -- Arm/Reset COP Timer Circuitry BIT 7 7 0 6 6 0 5 5 0 4 4 1 3 3 0 2 2 0 1 1 0 BIT 0 0 0 $103A Freescale Semiconductor, Inc... RESET: Write $55 to COPRST to arm COP watchdog circuit. Write $AA to COPRST to reset COP watchdog circuit. HPRIO -- Highest Priority I-Bit Interrupt and Miscellaneous BIT 7 RBOOT* -- 6 SMOD* -- 5 MDA* -- 4 IRVNE 0 3 PSEL3 0 2 PSEL2 1 1 PSEL1 0 BIT 0 PSEL0 1 $103C RESET: *RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode. RBOOT -- Read Bootstrap ROM Refer to 4.4 Bootstrap Mode SMOD -- Special Mode Select Refer to 4.5 Mode Selection MDA -- Mode Select A Refer to 4.5 Mode Selection IRVNE -- Internal Read Visibility/Not E Refer to 4.5 Mode Selection PSEL[3:0] -- Priority Select Bit 4 through Bit 0 Can be written only while the I-bit in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I-bit related sources. 24 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. Table 9 Highest I-Bit Interrupt Source Selection PSEL3 0 0 0 0 0 0 0 0 1 1 PSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Source Promoted Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Edge Reserved (Default to IRQ) SCI Serial System Reserved (Default to IRQ) IRQ (External Pin) Real-Time Interrupt Timer Input Capture 1 Timer Input Capture 2 Timer Input Capture 3 Timer Output Compare 1 Timer Output Compare 2 Timer Output Compare 3 Timer Output Compare 4 Timer IC4/OC5 Freescale Semiconductor, Inc... 1 1 1 1 1 1 PSEL[3:0] reset to %0101, making IRQ the highest priority I-bit related interrupt source. CONFIG -- Security, COP, ROM/EPROM, and EEPROM Enables BIT 7 -- -- 6 -- -- 5 -- -- 4 -- 0 3 NOSEC 0 2 NOCOP 1 1 ROMON 0 BIT 0 EEON 1 $103F RESET: Bits [7:4] -- Not Implemented Always read zero NOSEC -- EEPROM Security Mode Disable Refer to 4.10.3 EEPROM Security NOCOP -- COP System Disable 0 = COP system enabled (forces reset on timeout) 1 = COP system disabled ROMON -- ROM/EPROM Enable Refer to 4 Operating Modes and On-Chip Memory. EEON -- EEPROM Enable Refer to 4.10 EEPROM MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. 6 Parallel Input/Output The MC68HC(7)11EA9 has up to 36 input/output lines, depending on the operating mode. Table 10 shows the configuration and features of each port. Table 10 I/O Port Configuration Port A B C D E -- Input Pins -- -- -- -- 8 1 1 Output Pins -- -- -- -- -- -- -- Bidirectional Pins 8 8 8 2 -- -- -- Shared Functions Timer High Order Address Multiplexed Low Order Address/Data SCI/PLL Test A/D Converter XPIN (XIRQ pin configured for data input) IPIN (IRQ pin configured for data input) Freescale Semiconductor, Inc... -- Simple and full handshake input and output functions are available on ports B and C lines in single-chip mode. The following is a description of the handshake functions. In simple strobed mode, port B is a strobed output port and port C is a latching input port. The two activities are available simultaneously. The STRB output is pulsed for two E-clock periods each time there is a write to the PORTB register. The INVB bit in the PIOC register controls the polarity of STRB pulses. Port C levels are latched into the alternate port C latch (PORTCL) register on each assertion of the STRA input. STRA edge select, flag, and interrupt enable bits are located in the PIOC register. Any or all of the port C lines can still be used as general-purpose I/O while in strobed input mode. Full handshake modes involve port C pins and the STRA and STRB lines. Input and output handshake modes are supported, and output handshake mode has a three-stated variation. STRA is an edge detecting input, and STRB is a handshake output. Control and enable bits are located in the PIOC register. In full input handshake mode, the MCU uses STRB as a ready line to an external system. Port C logic levels are latched into PORTCL when the STRA line is asserted by the external system. The MCU then negates STRB. The MCU reasserts STRB after the PORTCL register is read. A mix of latched inputs, static inputs, and static outputs is allowed on port C, differentiated by the data direction bits and use of the PORTC and PORTCL registers. In full output handshake mode, the MCU writes data to PORTCL which, in turn, asserts the STRB output to indicate that data is ready. The external system reads port C and asserts the STRA input to acknowledge that data has been received. In the three-state variation of output handshake mode, lines intended as three-state handshake outputs are configured as inputs by clearing the corresponding DDRC bits. The MCU writes data to PORTCL and asserts STRB. The external system responds by activating the STRA input, which forces the MCU to drive the data in PORTCL out on all of the port C lines. The mode variation does not allow part of port C to be used for static inputs while other port C pins are being used for handshake outputs. Refer to PIOC register description for further information. 26 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PIOC -- Port I/O Control BIT 7 STAF 0 6 STAI 0 5 CWOM 0 4 HNDS 0 3 OIN 0 2 PLS 0 1 EGA 0 BIT 0 INVB 0 $1002 RESET: STAF -- Strobe A Interrupt Status Flag This bit is set when a selected edge occurs on Strobe A. Clearing it depends on the state of the HNDS and OIN bits. In simple strobed mode or in full handshake mode, STAF is cleared by a read of the PIOC register followed by a read of PORTCL register. In output handshake mode, STAF is cleared by reading the PIOC register followed by a write to PORTCL register. 0 = No edge detected on strobe A 1 = The selected edge (rising or falling) has been detected on strobe A STAI -- Strobe A Interrupt Enable When bit I in the condition code register is clear and STAI is set, STAF (when set) will request an interrupt. 0 = STAF will not generate an interrupt when set. 1 = STAF will generate an interrupt when set. CWOM -- Port C Wire-OR Mode CWOM affects all eight port A pins. 0 = Port C outputs are normal CMOS outputs 1 = Port C outputs act as open-drain outputs HNDS -- Handshake Mode When clear, strobe A acts as a simple input strobe to latch data into PORTCL, and strobe B acts as a simple output strobe which pulses after a write to port B. When set, a handshake protocol involving port C, STRA, and STRB is selected (see the definition for the OIN bit). 0 = Simple strobe mode 1 = Full input or output handshake mode OIN -- Output or Input Handshaking This bit has no meaning or effect when HNDS = 0. 0 = Input handshake 1 = Output handshake PLS -- Pulse/Interlocked Handshake Operation This bit has no meaning if HNDS = 0. When interlocked handshake operation is selected, strobe B, once activated, stays active until the selected edge of strobe A is detected. When pulsed handshake operation is selected, strobe B is pulsed for two E cycles. 0 = Interlocked handshake selected 1 = Pulsed handshake selected EGA -- Active Edge for Strobe A 0 = Falling edge of strobe A selected. When output handshake is selected, port C lines obey the data direction register while STRA is low, but port C is forced to output when STRA is high. 1 = Rising edge of strobe A selected. When output handshake is selected, port C lines obey the data direction register while STRA is high, but port C is forced to output when STRA is low. INVB -- Invert Strobe B 0 = Active level is logic zero 1 = Active level is logic one Freescale Semiconductor, Inc... MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. Table 11 Strobed and Handshake Parallel I/O Control Bit Summary STAF Clearing Sequence Simple strobed mode Read PIOC with STAF = 1 then read PORTCL HNDS OIN 0 X PLS X 0 EGA Port B Inputs latched into PORTCL on any active edge on STRA Inputs latched into PORTCL on any active edge on STRA Port C STRB pulses on writes to PORTB 1 Freescale Semiconductor, Inc... Full Read PIOC input with STAF = 1 handshake then read mode PORTCL Full Read PIOC output with STAF = 1 handshake then write mode PORTCL 1 0 0 = STRB active level 1 = STRB active pulse 1 0 Normal output port, unaffected in handshake modes 1 1 0 = STRB active level 1 = STRB active pulse 0 1 Follow DDRC Port C Driven STRA Active Edge Follow DDRC Driven as outputs if Normal output STRA at active port, unaffected level; follows in handshake DDRC if STRA not modes at active level Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs. I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the corresponding latches are dependent upon the electrical state of the pins during reset. In port descriptions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset are shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for these bits are indicated with a "U". PORTA -- Port A Data BIT 7 PA7 I PAI OC1 6 PA6 I OC2 OC1 5 PA5 I OC3 OC1 4 PA4 I OC4 OC1 3 PA3 I IC4/OC5 OC1 2 PA2 I IC1 -- 1 PA1 I IC2 -- BIT 0 PA0 I IC3 -- $1000 RESET: Alt. Pin Func.: And/or NOTE The timer forces the I/O state to output for each port A line associated with an enabled output compare. In these cases the data direction bits will not be changed, but have no effect on these lines. The DDRA will revert to controlling data direction when the associated timer compare is disabled. Input captures do not force either the I/O state of the pin or the state of DDRA. To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit in DDRA is set (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/ O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can be configured for general-purpose I/O or output compare. DDA7 bit in DDRA register configures PA7 for either input or output. Note that even when PA7 is configured as an output, the pin still drives the pulse accumulator input. 28 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. DDRA -- Port A Data Direction BIT 7 DDA7 0 6 DDA6 0 5 DDA5 0 4 DDA4 0 3 DDA3 0 2 DDA2 0 1 DDA1 0 BIT 0 DDA0 0 $1001 RESET: DDA[7:0] -- Data Direction for Port A 0 = Corresponding pin configured for input 1 = Corresponding pin configured for output PORTB -- Port B Data BIT 7 PB7 0 ADDR15 6 PB6 0 ADDR14 5 PB5 0 ADDR13 4 PB4 0 ADDR12 3 PB3 0 ADDR11 2 PB2 0 ADDR10 1 PB1 0 ADDR9 BIT 0 PB0 0 ADDR8 $1004 Freescale Semiconductor, Inc... RESET: Alt. Pin Func.: DDRB -- Port B Data Direction BIT 7 DDB7 0 6 DDB6 0 5 DDB5 0 4 DDB4 0 3 DDB3 0 2 DDB2 0 1 DDB1 0 BIT 0 DDB0 0 $1006 RESET: DDB[7:0] -- Data Direction for Port B 0 = Corresponding pin configured for input 1 = Corresponding pin configured for output PORTC -- Port C Data BIT 7 PC7 0 ADDR7 DATA7 6 PC6 0 ADDR6 DATA6 5 PC5 0 ADDR5 DATA5 4 PC4 0 ADDR4 DATA4 3 PC3 0 ADDR3 DATA3 2 PC2 0 ADDR2 DATA2 1 PC1 0 ADDR1 DATA1 BIT 0 PC0 0 ADDR0 DATA0 $1003 RESET: Alt. Pin Func.: Or: PORTCL -- Port C Latched Data BIT 7 PCL7 0 6 PCL6 0 5 PCL5 0 4 PCL4 0 3 PCL3 0 2 PCL2 0 1 PCL1 0 BIT 0 PCL0 0 $1005 RESET: PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into PORTCL and clear STAF flag (following a read of PIOC with STAF set). DDRC -- Port C Data Direction BIT 7 DDC7 0 6 DDC6 0 5 DDC5 0 4 DDC4 0 3 DDC3 0 2 DDC2 0 1 DDC1 0 BIT 0 DDC0 0 $1007 RESET: DDC[7:0] -- Data Direction for Port C 0 = Corresponding pin configured for input 1 = Corresponding pin configured for output MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. PORTD -- Port D Data BIT 7 XPIN 0 -- 6 IPIN 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 PD1 0 TxD BIT 0 PD0 0 RxD $1008 RESET: Alt. Pin Func.: XPIN -- XIRQ Interrupt Pin Status Flag This is a read-only bit. XPIN reflects the logic level present on the XIRQ pin. 0 = XIRQ pin low. 1 = XIRQ pin high. IPIN -- IRQ Interrupt Pin Status Flag This is a read-only bit. IPIN reflects the logic level present on the IRQ pin. 0 = IRQ pin low. 1 = IRQ pin high. XPIN and IPIN are read-only status bits that reflect the logic levels present on the XIRQ and IRQ pins. XPIN and IPIN provide the data bits that allow the XIRQ and IRQ pins to be used as general-purpose inputs. However, to use XIRQ and IRQ as data inputs, the interrupts normally generated by these two pins must be disabled with the DISX and DISI bits in the DDRD register. After reset PD[1:0] are configured as high-impedance inputs. PD[1:0] share functions with the SCI system. 8 Serial Communications Interface details information regarding port D SCI functions. DDRD -- Port D Data Direction BIT 7 DISX 0 6 DISI 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 DDD1 0 BIT 0 DDD0 0 Freescale Semiconductor, Inc... $1009 RESET: DISX -- Disable XIRQ Pin Interrupts Can be read anytime. Can be written only once. Any write to the DDRD register will prevent modification of this bit. This bit must be set to use the XIRQ pin as a data input. 0 = Interrupts generated by the XIRQ pin function are enabled 1 = Interrupts generated by the XIRQ pin function are disabled DISI -- Disable IRQ Pin Interrupts Can be read anytime. Can be written only once. Any write to the DDRD register will prevent modification of this bit. This bit must be set to use the IRQ pin as a data input. 0 = Interrupts generated by the IRQ pin function are enabled 1 = Interrupts generated by the IRQ pin function are disabled DDD[1:0] -- Data Direction for PD[1:0] 0 = Corresponding port D pin configured for input 1 = Corresponding port D pin configured for output PORTE -- Port E Data BIT 7 PE7 I 6 PE6 I 5 PE5 I 4 PE4 I 3 PE3 I 2 PE2 I 1 PE1 I BIT 0 PE0 I $100A RESET: Port E has eight general-purpose input pins and shares functions with the A/D converter system. When any port E pins are being used as A/D inputs, PORTE should not be read during the sample portion of an A/D conversion. Refer to 9 Analog-to-Digital Converter for more information. 30 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 7 Timing System The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. A timer overflow function allows software to extend the system's timing capability beyond the counter's 16-bit range. The main timer consists of the timer prescaler, the 16-bit free-running counter, and the capture/compare unit. 7.2 Main Timer details this portion of the timing system. The free-running counter can be driven by either the EXTAL signal, as in other M68HC11 derivatives or it can be driven by a software-controlled phase-locked loop (PLL) frequency synthesizer which has been added to the MC68HC(7)11EA9 MCUs. The PLL allows the MCU to operate in WAIT mode with extremely low power requirements. Refer to 7.1 Phase-Locked Loop Synthesizer. In addition, the timing system includes pulse accumulator and real-time interrupt (RTI) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the COP system. Refer to the appropriate paragraphs within this section for information regarding these functions. Table 12 shows a summary of the crystal-related frequencies and periods. Freescale Semiconductor, Inc... Table 12 Timer Summary Control Bits Common System Frequencies 4.0 MHz 1.0 MHz PR[1:0] 00 1 count -- overflow -- 01 1 count -- overflow -- 10 1 count -- overflow -- 11 1 count -- overflow -- RTR[1:0] 00 01 10 11 CR[1:0] 00 01 10 11 Time-out Tolerance (-0 ms/+...) 16.0 s 1.049 s 8.192 ms 16.384 ms 32.768 ms 65.536 ms 32.768 ms 131.072 ms 524.288 ms 2.098 s 32.8 ms 8.0 s 524.29 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 16.384 ms 65.536 ms 262.14 ms 1.049 s 16.4 ms 5.333 s 349.52 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms 10.923 ms 43.691 ms 174.76 ms 699.05 ms 10.9 ms 16/E 220/E 213/E 214/E 215/E 216/E 215/E 217/E 219/E 221/E 215/E 8.0 s 524.28 ms 4.0 s 262.14 ms 2.667 s 174.76 ms 8/E 219/E 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 32.768 ms 4/E 218/E 1000 ns 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms 1/E 216/E 8.0 MHz 2.0 MHz 12.0 MHz 3.0 MHz Definition XTAL E Main Timer Count Rate (Period Length) Periodic (RTI) Interrupt Rates (Period Length) COP Watchdog Timeout Rates (Period Length) MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. 7.1 Phase-Locked Loop Synthesizer The phase-locked loop synthesizer (PLL) generates clocks for the CPU, bus circuitry, and A/D converter. The clocks for the SCI and timers are derived directly from the EXTAL clock. The EXTAL clock also provides the reference for the synthesizer which generates a frequency that is a multiple of the EXTAL clock frequency. Values written to the SYNR register determine the factor by which the EXTAL clock is scaled. Refer to Figure 8. The PLL has two frequency bandwidths which are automatically selected whenever AUTO = 1 in the PLLCR register. When the PLL is first enabled, the wide bandwidth is selected to provide a fast ramp time. When the desired frequency is nearly reached, the low bandwidth is selected to provide greater stability. Manual control of bandwidth can be accomplished by clearing the AUTO bit. VDDSYN VDDSYN PIN Freescale Semiconductor, Inc... XFC PIN EXTERNAL CRYSTAL XFC EXTAL PIN XTAL PIN EXTAL PHASE DETECT PCOMP LOOP FILTER VCO VCOUT CRYSTAL OSCILLATOR FREQUENCY DIVIDER SYNR EXTAL PHASE-LOCKED LOOP SYNTHESIZER 2(Y + 1)*(2X) Y = SYNY[1:0] X = SYNX[5:0] VCOUT BUS CLOCK SELECT BCS 0 = EXTAL 1 = VCOUT E 4XCLK FOR CPU AND MEMORIES /4 PH2 TIMER CLOCK MODULE CLOCK SELECT MCS 0 = EXTAL 1 = 4XCLK EA9 PLL BLOCK PLLMO FOR SCI AND TIMER /4 SYNCHRONIZE WITH PH2 PLLTO TO TIMER PRESCALER SCI CLOCK /2 SCI BAUD CLOCK TO SCI MODULUS BAUD GENERATOR Figure 8 Phase-Locked Loop Synthesizer Block Diagram 32 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PLLCR -- PLL Control BIT 7 PLLON 1 6 BCS 0 5 AUTO 1 4 BWC 1 3 VCOT 1 2 MCS 0 1 LCK 0 BIT 0 WEN 0 $1036 RESET: PLLON -- PLL System Enable This bit activates the PLL synthesizer circuit without connecting its output to the control circuit. This allows the synthesizer to stabilize before it can drive the CPU clocks. This bit resets to one, allowing the synthesizer to stabilize as the device is being powered up. 0 = PLL is off 1 = PLL is on BCS -- Bus Clock Select This bit determines which signal drives the clock circuitry generating the bus clocks. Refer to Figure 8. Once BCS has been changed, up to 1.5 EXTAL cycles + 1.5 PLLOUT cycles may be required for the transition. During the transition, all CPU activity will cease. BCS is cleared by a STOP or WAIT instruction or when VDDSYN falls to the VSS level. 0 = EXTAL drives the clock circuit 1 = VCOUT drives the clock circuit NOTE PLLON and BCS have built-in protection such that the PLL cannot be selected to drive any clocks if the PLL is off. Similarly, the PLL cannot be turned off if it has been selected as a clock source. Turning the PLL on and selecting its output as a clock source require two separate writes to the PLLCR register. AUTO -- Automatic/Manual Loop Filter Bandwidth Control This bit selects between automatic bandwidth control circuits within the phase detect block and manual bandwidth control. Refer to Table 13. 0 = Automatic bandwidth control is selected 1 = Bandwidth control is manual BWC -- Loop Filter Bandwidth Control/Status Bandwidth control is manual only when AUTO = 0. Since the low bandwidth driver is always enabled, BWC determines if the high bandwidth driver is enabled. When AUTO = 1, BWC is a read-only status bit that indicates which mode has been selected by the internal circuit. During PLL start-up in automatic mode, the high bandwidth driver is enabled by internal circuitry until the PLL is near the selected frequency. The high bandwidth driver is then disabled and BWC is cleared. Refer to Table 13. 0 = Only the low bandwidth driver is enabled 1 = Both low and high bandwidth drivers are selected Table 13 Loop Filter Bandwidth Driver Control AUTO BWC VCOT High Bandwidth Driver 0 0 0 0 1 0 0 1 1 X 0 1 0 1 1 Off Off On On Automatic Low Bandwidth Driver Off On Off On On Freescale Semiconductor, Inc... VCOT -- Voltage Controlled Oscillator (VCO) Test This bit is used to isolate the loop filter from the VCO to aid in factory testing of the PLL. VCOT is always set when AUTO = 1 (automatic bandwidth control mode). This bit can be written only in special test mode. 0 = Loop filter low bandwidth mode is disabled (factory test only) 1 = Loop filter operates according to values of AUTO and BWC control bits MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 33 Freescale Semiconductor, Inc. MCS -- Module Clock Select This bit determines which clock signal drives the SCI and timer. 0 = EXTAL is the clock source for SCI and timer divider chains 1 = 4XCLK is the clock source for the SCI and timer divider chains LCK-- Synthesizer Lock Detect Flag This is a read-only status bit that indicates when the PLL has stabilized. BCS cannot be set (selecting VCOUT as a clock source) until LCK is set. 0 = The PLL is not stable 1 = The PLL has stabilized WEN -- WAIT Enable This bit determines whether the EXTAL signal will be used to drive the CPU clocks while the device is in WAIT mode. When this feature is enabled, entering wait mode clears BCS (selecting EXTAL as the source for CPU clocks) and reduces the PLL frequency to the lowest value, modulus 1. Any interrupt or reset or the assertion of the RAF bit within the SCI (if the receiver is enabled by RE = 1) will allow the PLL to resume operation at the frequency selected in SYNR register. Then the user must set BCS to select VCOUT as the source for CPU clocks. 0 = VCOUT remains connected to the 4XCLK circuit during operation in WAIT mode. 1 = After stacking prior to entering WAIT mode, BCS is cleared and the PLL is maintained at the lowest frequency available (modulus 1). SYNR -- Frequency Synthesizer Control BIT 7 SYNX1 0 6 SYNX0 0 5 SYNY5 0 4 SYNY4 0 3 SYNY3 0 2 SYNY2 1 1 SYNY1 1 BIT 0 SYNY0 0 Freescale Semiconductor, Inc... $1037 RESET: This register resets to $06 for a preset multiplication factor of 14. SYNX[1:0] -- Binary Tap Select Bits These two bits select one of four binary taps. SYNX[1:0] affect the frequency multiplication factor, variable X according to the formula below. SYNY[5:0] -- Modulo Counter Rate Select Bits These six bits select one of 64 binary values that affect the frequency multiplication factor, variable Y according to the formula below. 2 (Y + 1) (2 ) Where X = the value represented by bits SYNX[1:0] Y = the value represented by bits SYNY[5:0] 7.2 Main Timer The main timer consists of the timer prescaler, the free-running counter, and the capture/compare unit. The timer prescaler selects one of four division rates and drives the free-running 16-bit counter. The capture/compare unit has three channels for input capture, four channels for output compare, and one channel that can be configured as a fourth input capture or a fifth output compare. Timer channels configured for input capture (ICx) cause the current value of the free-running counter to be latched into an input capture register (TICx) when a pulse edge is detected on the corresponding pin. Channels configured for output compare allow a pulse to be output when the free-running counter matches a value loaded into an output compare register (TOCx). Figure 9 shows a detailed block diagram of the timer prescaler and the capture/compare unit. X 34 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PLLTO * (PLLMO / 4) PRESCALER DIVIDE BY 1, 4, 8, OR 16 PR1 PR0 TCNT (HI) TCNT (LO) TOI 9 TOF TAPS FOR RTI, COP WATCHDOG, AND PULSE ACCUMULATOR INTERRUPT REQUESTS (FURTHER QUALIFIED BY I BIT IN CCR) TO PULSE ACCUMULATOR 16-BIT FREE RUNNING COUNTER 16-BIT TIMER BUS OC1I 16-BIT COMPARATOR TOC1 (HI) 8 BIT 7 PIN FUNCTIONS PA7/OC1/ PAI = OC1F FOC1 OC2I 7 BIT 6 OC3I 6 BIT 5 OC4I 5 BIT 4 I4/O5I 4 PA3/OC5/ IC4/OC1 PA4/OC4/ OC1 PA5/OC3/ OC1 PA6/OC2/ OC1 TOC1 (LO) Freescale Semiconductor, Inc... 16-BIT COMPARATOR TOC2 (HI) = OC2F FOC2 TOC2 (LO) 16-BIT COMPARATOR TOC3 (HI) = OC3F FOC3 TOC3 (LO) 16-BIT COMPARATOR TOC4 (HI) = OC4F FOC4 OC5 I4/O5F IC4 I4/O5 CFORC FORCE OUTPUT COMPARE TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK FOC5 BIT 3 IC1I 3 BIT 2 PA2/IC1 16-BIT LATCH TIC1 (HI) CLK IC1F IC2I IC2F IC3I IC3F 1 2 TIC1 (LO) CLK 16-BIT LATCH TIC2 (HI) BIT 1 PA1/IC2 TIC2 (LO) CLK 16-BIT LATCH TIC3 (HI) BIT 0 PA0/IC3 TIC3 (LO) TFLG1 STATUS FLAGS TMSK1 INTERRUPT ENABLES PORT A PIN CONTROL * REFER TO PLL BLOCK DIAGRAM. EA9 CC BLOCK Figure 9 Main Timer Block Diagram MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 35 Freescale Semiconductor, Inc. CFORC -- Timer Compare Force BIT 7 FOC1 0 6 FOC2 0 5 FOC3 0 4 FOC4 0 3 FOC5 0 2 -- 0 1 -- 0 BIT 0 -- 0 $100B RESET: FOC[1:5] -- Force Output Compare Write ones to force compare(s) 0 = Not affected 1 = Output x action occurs Bits [2:0] -- Not implemented Always read zero OC1M -- Output Compare 1 Mask $100C 4 OC1M4 0 3 OC1M3 0 2 -- 0 1 -- 0 BIT 0 -- 0 Freescale Semiconductor, Inc... RESET: BIT 7 OC1M7 0 6 OC1M6 0 5 OC1M5 0 Set bit(s) to enable OC1 to control corresponding port A pin(s). If OC1Mx is set, data in OC1Dx is output on port A pin x upon successful OC1 compares. Bits [2:0] -- Not implemented Always read zero OC1D -- Output Compare 1 Data BIT 7 OC1D7 0 6 OC1D6 0 5 OC1D5 0 4 OC1D4 0 3 OC1D3 0 2 -- 0 1 -- 0 BIT 0 -- 0 $100D RESET: Set bit(s) to enable OC1 to control corresponding port A pin(s). If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits [2:0] -- Not implemented Always read zero TCNT -- Timer Counter BIT 15 BIT 7 14 6 13 5 12 4 11 3 10 2 9 1 $100E-$100F BIT 8 BIT 0 TCNT (HI) TCNT (LO) TCNT resets to $0000. In normal modes (SMOD = 0), TCNT is a read-only register. TIC1-TIC3 -- Timer Input Capture $1010 $1011 $1012 $1013 $1014 $1015 BIT 15 BIT 7 BIT 15 BIT 7 BIT 15 BIT 7 14 6 14 6 14 6 13 5 13 5 13 5 12 4 12 4 12 4 11 3 11 3 11 3 10 2 10 2 10 2 9 1 9 1 9 1 $1010-$1015 BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 TIC1 (HI) TIC1 (LO) TIC2 (HI) TIC2 (LO) TIC3 (HI) TIC3 (LO) TICx is not affected by reset. 36 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. TOC1-TOC4 -- Timer Output Compare $1016 $1017 $1018 $1019 $101A $101B $101C $101D BIT 15 BIT 7 BIT 15 BIT 7 BIT 15 BIT 7 BIT 15 BIT 7 14 6 14 6 14 6 14 6 13 5 13 5 13 5 13 5 12 4 12 4 12 4 12 4 11 3 11 3 11 3 11 3 10 2 10 2 10 2 10 2 9 1 9 1 9 1 9 1 $1016-$101D BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 BIT 8 BIT 0 TOC1 (HI) TOC1 (LO) TOC2 (HI) TOC2 (LO) TOC3 (HI) TOC3 (LO) TOC4 (HI) TOC4 (LO) All TOCx register pairs reset to $FFFF. Freescale Semiconductor, Inc... TI4/O5 -- Timer Input Capture 4/Output Compare 5 BIT 15 BIT 7 14 6 13 5 12 4 11 3 10 2 9 1 $101E-$101F BIT 8 BIT 0 TCNT (HI) TCNT (LO) This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. The TI4/O5 register pair resets to $FFFF. TCTL1 -- Timer Control 1 BIT 7 OM2 0 6 OL2 0 5 OM3 0 4 OL3 0 3 OM4 0 2 OL4 0 1 OM5 0 BIT 0 OL5 0 $1020 RESET: Table 14 Output Compare Channel Configuration OMx 0 0 1 1 OLx 0 1 0 1 Action on Successful Compare None -- Output Compare Channel (OCx) disabled Toggle OCx output pin logic level Drive OCx output pin low Drive OCx output pin high TCTL2 -- Timer Control 2 BIT 7 EDG4B 0 6 EDG4A 0 5 EDG1B 0 4 EDG1A 0 3 EDG2B 0 2 EDG2A 0 1 EDG3B 0 BIT 0 EDG3A 0 $1021 RESET: Table 15 Input Capture Channel Configuration EDGxB EDGxA 0 0 1 1 0 1 0 1 Input Capture Configuration Input Capture Channel (ICx) disabled Capture on rising edge on ICx input pin Capture on falling edge on ICx input pin Capture on any edge on ICx input pin MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 37 Freescale Semiconductor, Inc. TMSK1 -- Timer Interrupt Mask 1 BIT 7 OC1I 0 6 OC2I 0 5 OC3I 0 4 OC4I 0 3 I4/O5I 0 2 IC1I 0 1 IC2I 0 BIT 0 IC3I 0 $1022 RESET: OC1I-OC4I -- Output Compare (OCx) Interrupt Enable If the OCxI enable bit is set when a match occurs, an interrupt is generated. 0 = Interrupts from OCx channel disabled 1 = Successful compares on OCx channel generate interrupts I4/O5I -- Input Capture 4/Output Compare 5 Interrupt Enable When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges on the I4/O5 pin generate interrupts. When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit and successful matches generate interrupts. 0 = Interrupts from IC4/OC5 channel disabled 1 = Interrupts from IC4/OC5 channel enabled IC1I-IC3I -- Input Capture (ICx) Interrupt Enable If the ICxI enable bit is set when an edge is detected on the ICx pin, an interrupt is generated. 0 = Interrupts from ICx channel disabled 1 = Edges detected on ICx pin generate interrupts NOTE Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the corresponding interrupt sources. TFLG1 -- Timer Interrupt Flag 1 BIT 7 OC1F 0 6 OC2F 0 5 OC3F 0 4 OC4F 0 3 I4/O5F 0 2 IC1F 0 1 IC2F 0 BIT 0 IC3F 0 Freescale Semiconductor, Inc... $1023 RESET: Clear a flag by writing a one to the appropriate bit. OC1F-OC4F -- Output Compare (OCx) Interrupt Flag If the OCxI enable bit is set when a match occurs, the corresponding flag bit is set and an interrupt is generated. 0 = No match has occurred 1 = A successful compare has occurred on OCx channel I4/O5I -- Input Capture 4/Output Compare 5 Interrupt Enable When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges (rising or falling, depending on configuration) on the I4/O5 pin cause this flag to be set and an interrupt is generated. When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit and successful matches cause this flag to be set and an interrupt generated. 0 = Interrupts from IC4/OC5 channel disabled 1 = Interrupts from IC4/OC5 channel enabled IC1I-IC3I -- Input Capture (ICx) Interrupt Enable If the ICxI enable bit is set when an edge (rising or falling, depending on configuration) is detected on the ICx pin, an interrupt is generated. 0 = Interrupts from ICx channel disabled 1 = Edges detected on ICx pin generate interrupts 38 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. TMSK2 -- Timer Interrupt Mask 2 BIT 7 TOI 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 -- 0 2 -- 0 1 PR1 0 BIT 0 PR0 0 $1024 RESET: Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time. TOI -- Timer Overflow Interrupt Enable If the TOI enable bit is set when the value in the timer counter register (TCNT) changes from $FFFF to $0000, an interrupt is generated. 0 = Timer overflow interrupts disabled 1 = Interrupts are generated each time TCNT rolls over to $0000 Freescale Semiconductor, Inc... RTII -- Real-Time Interrupt Enable If RTII enable bit is set, interrupts are generated at the rate determined by the real-time interrupt rate (RTR[1:0]) bits in PACTL. 0 = Periodic interrupts are disabled 1 = Interrupts are generated at the rate determined by RTR[1:0] PAOVI -- Pulse Accumulator Overflow Interrupt Enable If the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from $FFFF to $0000 an interrupt is generated. 0 = PCNT overflow interrupts are disabled 1 = Interrupts are generated each time PCNT rolls over to $0000 PAII -- Pulse Accumulator Input Edge Interrupt Enable If the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected on the pulse accumulator input pin (PA7/PAI), an interrupt is generated. 0 = Interrupts from edges on PAI pin are disabled 1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) Bits [3:2] -- Not Implemented Always read zero PR[1:0] -- Timer Prescaler Select Table 16 Main Timer Prescaler Selection PR1 0 0 1 1 PR0 0 1 0 1 Prescaler Selected /1 /4 /8 /16 MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 39 Freescale Semiconductor, Inc. TFLG2 -- Timer Interrupt Flag 2 BIT 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 -- 0 2 -- 0 1 -- 0 BIT 0 -- 0 $1025 RESET: TOF -- Timer Overflow Interrupt Flag If the TOI enable bit is set when the timer counter register (TCNT) changes from $FFFF to $0000, this flag is set and an interrupt is generated. 0 = TCNT has not rolled over since either the TOF flag bit was last cleared or the TOI enable bit was set. 1 = TCNT has rolled over to $0000 RTIF -- Real-Time Interrupt Flag If RTII enable bit is set, this flag is set and an interrupt is generated periodically at the rate determined by the real-time interrupt rate (RTR[1:0]) bits in PACTL. 0 = No periodic interrupt has occurred since either the RTIF flag bit was last cleared or when the RTII enable bit was set 1 = A periodic interrupt has occurred PAOVF -- Pulse Accumulator Overflow Interrupt Flag If the PAOVI enable bit is set when the pulse accumulator counter register (PCNT) rolls over to $0000, this flag is set and an interrupt is generated. 0 = PCNT has not rolled over since either the PAOVF flag bit was last cleared or the PAOVI enable bit was set. 1 = PCNT has rolled over to $0000 PAIF -- Pulse Accumulator Input Edge Interrupt Flag If the PAII enable bit is set when an edge is detected on the pulse accumulator input pin (PA7/PAI), this flag is set and an interrupt is generated. 0 = No edge has been detected on the PAI pin 1 = An edge (rising or falling, depending on configuration) has been detected on the PAI pin Bits [3:0] -- Not Implemented Always read zero PACTL -- Pulse Accumulator Control BIT 7 -- 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 -- 0 2 I4/O5 0 1 RTR1 0 BIT 0 RTR0 0 Freescale Semiconductor, Inc... $1026 RESET: Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time. Bit 7 -- Not Implemented Always reads zero PAEN -- Pulse Accumulator Enable Refer to 7.4 Pulse Accumulator. PAMOD -- Pulse Accumulator Mode Select Refer to 7.4 Pulse Accumulator. PEDGE -- Pulse Accumulator Input Edge Select Refer to 7.4 Pulse Accumulator. 40 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. Bit 3 -- Not Implemented Always reads zero I4/O5 -- Input Capture 4/Output Compare 5 Select 0 = Interrupts from edges on PAI pin are disabled 1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) RTR[1:0] -- Real-Time Interrupt Rate Select Table 17 Real-Time Interrupt Rates Rate RTR[1:0] 00 01 10 Selected 2 13 RTI Rate Selected E = 1.0 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = 2.0 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 3.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms /E /E /E 214 / E 2 2 15 16 Freescale Semiconductor, Inc... 11 OPTION -- System Configuration Options BIT 7 6 5 4 3 2 1 BIT 0 ADPU CSEL IRQE* DLY* CME -- CR1* CR0* RESET: 0 0 0 1 0 0 0 0 * Can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. $1039 ADPU -- A/D Converter Power up Refer to 9 Analog-to-Digital Converter CSEL -- Clock Select 0 = A/D and EEPROM use the system E clock 1 = A/D and EEPROM use internal RC clock IRQE -- IRQ Select Edge-Sensitive Only Refer to 5 Resets and Interrupts DLY -- Enable Oscillator Start-up Delay 0 = No stabilization delay on exit from STOP mode. 1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode. CME -- Clock Monitor Enable 0 = Clock monitor disabled; slow clock can be used. 1 = Slow or stopped clocks cause COP failure reset. Bit 2 -- Not implemented Always reads zero CR[1:0] -- COP Timer Rate Select Refer to 5 Resets and Interrupts Table 18 COP Timer Rate Selection CR[1:0] 00 01 10 11 Rate Selected 215 / E 2 2 17 19 Period Length E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz 32.768 ms 131.072 ms 524.288 ms 2.097 s 16.384 ms 65.536 ms 262.140 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms /E /E 221 / E MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 41 Freescale Semiconductor, Inc. 7.3 Real-Time Interrupt The real-time interrupt (RTI) function can generate interrupts at different fixed periodic rates. These rates are a function of the MCU oscillator frequency and the value of the software-accessible control bits, RTR1 and RTR0. These bits determine the rate at which interrupts are requested by the RTI system. The RTI system is driven by an E divided by 213 rate clock compensated so that it is independent of the timer prescaler. The RTR1 and RTR0 control bits select an additional division factor. RTI is set to its fastest rate by default out of reset and can be changed at any time. Table 19 Real-Time Interrupt Rates (Period Length) Period Length RTR[1:0] 00 01 Selected 2 2 2 13 Period Length E = 1.0 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = 2.0 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 3.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms /E /E /E 214 / E 15 16 Freescale Semiconductor, Inc... 10 11 Table 20 Real-Time Interrupt Rates (Frequency) Maximum RTR[1:0] 00 01 10 11 Frequency Possible 2 2 2 13 Maximum Interrupt Frequency E = 1.0 MHz 122.070 Hz 61.035 Hz 30.518 Hz 15.258 Hz E = 2.0 MHz 244.141 Hz 122.070 Hz 61.035 Hz 30.518 Hz E = 3.0 MHz 366.211 Hz 183.105 Hz 91.553 Hz 45.776 Hz /E /E /E 214 / E 15 16 TFLG2 -- Timer Interrupt Flag 2 BIT 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 -- 0 2 -- 0 1 -- 0 BIT 0 -- 0 $1025 RESET: TOF -- Timer Overflow Interrupt Flag Refer to 7.2 Main Timer RTIF -- Real-Time Interrupt Flag If RTII enable bit is set, this flag is set and an interrupt is generated periodically at the rate determined by the real-time interrupt rate (RTR[1:0]) bits in PACTL. 0 = No periodic interrupt has occurred since either the RTIF flag bit was last cleared or the RTII enable bit was set 1 = A periodic interrupt has occurred PAOVF -- Pulse Accumulator Overflow Interrupt Flag Refer to 7.4 Pulse Accumulator PAIF -- Pulse Accumulator Input Edge Interrupt Flag Refer to 7.4 Pulse Accumulator Bits [3:0] -- Not Implemented Always read zero 42 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PACTL -- Pulse Accumulator Control BIT 7 -- 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 -- 0 2 I4/O5 0 1 RTR1 0 BIT 0 RTR0 0 $1026 RESET: Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time. Bit 7 -- Not Implemented Always reads zero PAEN -- Pulse Accumulator Enable Refer to 7.4 Pulse Accumulator Freescale Semiconductor, Inc... PAMOD -- Pulse Accumulator Mode Select Refer to 7.4 Pulse Accumulator PEDGE -- Pulse Accumulator Input Edge Select Refer to 7.4 Pulse Accumulator Bit 3 -- Not Implemented Always reads zero I4/O5 -- Input Capture 4/Output Compare 5 Select Refer to 7.2 Main Timer RTR[1:0] -- Real-Time Interrupt Rate Select Table 21 Real-Time Interrupt Rates Rate RTR[1:0] 00 01 10 11 Selected 213 / E 2 2 2 14 15 16 RTI Rate Selected E = 1.0 MHz 8.192 ms 16.384 ms 32.768 ms 65.536 ms E = 2.0 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms E = 3.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms /E /E /E 7.4 Pulse Accumulator M68HC11-family MCUs have an 8-bit counter within the timing system that can be configured for event counting or for gated time accumulation. The counter (PACNT) can be read or written at any time. The port A bit 7 I/O pin can be configured to act as a clock in event counting mode and edges on the pulse accumulator input pin cause the counter (PACNT) to increment. When the pulse accumulator is configured for time accumulation, an edge on the pulse accumulator input pin enables a free-running clock (E divided by 64) that drives PACNT in gated time accumulation mode. Refer to Figure 10. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 43 Freescale Semiconductor, Inc. PAOVI PAOVF 1 INTERRUPT REQUESTS 2 PAII PAIF TMSK2 INT ENABLES PAI EDGE PAEN TFLG2 INTERRUPT STATUS DISABLE FLAG SETTING OVERFLOW Freescale Semiconductor, Inc... MCU PIN PA7/ PAI/ OC1 INPUT BUFFER AND EDGE DETECTOR DATA BUS OUTPUT BUFFER FROM MAIN TIMER OC1 FROM DATA DIRECTION BIT FOR PORT A PIN 7 2:1 MUX CLOCK ENABLE PAEN PAEN PAMOD PEDGE PACTL CONTROL INTERNAL DATA BUS EA9 PLS ACC BLOCK * REFER TO TIMER AND PLL BLOCK DIAGRAMS. Figure 10 Pulse Accumulator Block Diagram PACTL -- Pulse Accumulator Control BIT 7 -- 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 -- 0 2 I4/O5 0 1 RTR1 0 BIT 0 RTR0 0 PAOVF PAIF PACNT 8-BIT COUNTER PAOVI PAII PLLTO / 64 CLOCK * (FROM MAIN TIMER) $1026 RESET: Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time. Bit 7 -- Not Implemented Always reads zero PAEN -- Pulse Accumulator Enable 0 = Periodic interrupts are disabled 1 = Interrupts are generated at the rate determined by RTR[1:0] PAMOD -- Pulse Accumulator Mode Select 0 = PCNT overflow interrupts are disabled 1 = Interrupts are generated each time PCNT rolls over to $0000 44 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PEDGE -- Pulse Accumulator Input Edge Select 0 = Interrupts from edges on PAI pin are disabled 1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) Bit 3 -- Not Implemented Always reads zero I4/O5 -- Input Capture 4/Output Compare 5 Select Refer to 7.2 Main Timer. RTR[1:0] -- Timer Prescaler Select Refer to 7.3 Real-Time Interrupt. PACNT -- Pulse Accumulator Counter BIT 7 BIT 7 6 6 5 5 4 4 3 3 2 2 1 1 BIT 0 BIT 0 $1027 Freescale Semiconductor, Inc... Can be read and written, unaffected by reset. TMSK2 -- Timer Interrupt Mask 2 BIT 7 TOI 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 -- 0 2 -- 0 1 PR1 0 BIT 0 PR0 0 $1024 RESET: Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time. TOI -- Timer Overflow Interrupt Enable Refer to 7.2 Main Timer. RTII -- Real-Time Interrupt Enable Refer to 7.3 Real-Time Interrupt. PAOVI -- Pulse Accumulator Overflow Interrupt Enable If the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from $FFFF to $0000 an interrupt is generated. 0 = PCNT overflow interrupts are disabled 1 = Interrupts are generated each time PCNT rolls over to $0000 PAII -- Pulse Accumulator Input Edge Interrupt Enable If the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected on the pulse accumulator input pin (PA7/PAI), an interrupt is generated. 0 = Interrupts from edges on PAI pin are disabled 1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration) Bits [3:2] -- Not Implemented Always read zero PR[1:0] -- Timer Prescaler Select Refer to 7.2 Main Timer. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 45 Freescale Semiconductor, Inc. TFLG2 -- Timer Interrupt Flag 2 BIT 7 TOF 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 -- 0 2 -- 0 1 -- 0 BIT 0 -- 0 $1025 RESET: TOF -- Timer Overflow Interrupt Flag Refer to 7.2 Main Timer. RTIF -- Real-Time Interrupt Flag Refer to 7.3 Real-Time Interrupt. PAOVF -- Pulse Accumulator Overflow Interrupt Flag If the PAOVI enable bit is set when the pulse accumulator counter register (PCNT) rolls over to $0000, this flag is set and an interrupt is generated. 0 = PCNT has not rolled over since either the PAOVF flag bit was last cleared or when the PAOVI enable bit was set. 1 = PCNT has rolled over to $0000 PAIF -- Pulse Accumulator Input Edge Interrupt Flag If the PAII enable bit is set when an edge is detected on the pulse accumulator input pin (PA7/PAI), this flag is set and an interrupt is generated. 0 = No edge has been detected on the PAI pin 1 = An edge (rising or falling, depending on configuration) has been detected on the PAI pin Bits [3:0] -- Not Implemented Always read zero Freescale Semiconductor, Inc... 46 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. 8 Serial Communications Interface The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is an independent serial I/O subsystem in MC68HC(7)11EA9 MCUs. The registers and control bits used in previous M68HC11 SCI systems have been rearranged and new features added. New or enhanced features include the following: * A 13-bit modulus prescaler that allows greater baud rate control * A new idle mode detect, independent of preceding serial data * A receiver active flag * Hardware parity for both transmitter and receiver The enhanced baud rate generator is shown in the following diagram. Refer to the table of SCI baud rate control values for standard values. INTERNAL PHASE 2 CLOCK (PH2) RESET SYNCHRONIZE WITH PH2 RECEIVER BAUD RATE CLOCK Freescale Semiconductor, Inc... SCI BAUD CLOCK EXTAL / 2, IF MCS = 0 4XCLK / 2, IF MCS = 1 13-BIT COUNTER 13-BIT COMPARE = /2 SCBDH/L SCI BAUD CONTROL / 16 TRANSMITTER BAUD RATE CLOCK EA9 BAUD GEN BLOCK Figure 11 SCI Baud Generator Circuit Diagram MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 47 Freescale Semiconductor, Inc. TRANSMITTER CLOCK (FROM MODULUS BAUD RATE GENERATOR) R8 T8 -- -- -- -- -- -- SCDRH Tx/Rx DATA HIGH 76543210 $x077 SCDRL Tx/Rx DATA LOW $x076 (WRITE ONLY) DDD1 10 (11) - BIT Tx SHIFT REGISTER H (8) 7 6 5 4 3 2 1 0 L PIN BUFFER AND CONTROL PD1 TxD TRANSFER Tx BUFFER SHIFT ENABLE Freescale Semiconductor, Inc... PARITY GENERATOR PREAMBLE--JAM 1s BREAK--JAM 0s JAM ENABLE SIZE 8/9 FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC LOOPS WOMS M WAKE ILT TDRE TC RDRF IDLE OR PE NF PT SCCR1 SCI CONTROL 1 SCSR1 SCI STATUS 1 TDRE TIE TC TCIE SCI Rx REQUESTS SCI INTERRUPT REQUEST TIE TCIE RIE ILIE TE RE RWU SBK SCCR2 SCI CONTROL 2 FE PF INTERNAL DATA BUS EA9 SCI TX BLOCK Figure 12 SCI Transmitter Block Diagram 48 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. RECEIVER CLOCK (FROM MODULUS BAUD RATE GENERATOR) DDD0 PD0 RxD PIN BUFFER AND CONTROL RE (DISABLES PIN DRIVER) DATA RECOVERY STOP /16 10 (11) - BIT Rx SHIFT REGISTER (8) 7 6 5 4 3 2 1 0 MSB START ALL ONES (READ ONLY) INTERNAL DATA BUS RAF Freescale Semiconductor, Inc... PARITY DETECT SCSR2 SCI STATUS 2 M WAKEUP LOGIC RWU LOOPS WOMS M WAKE ILT TDRE TC RDRF IDLE OR NF FE PF SCCR1 SCI CONTROL 1 SCSR1 SCI STATUS 1 R8 T8 -- -- -- -- -- -- $x076 SCDRH Tx/Rx DATA HIGH 76543210 $x077 SCDRL Tx/Rx DATA LOW PE PT RDRF RIE IDLE ILIE OR RIE TIE TCIE RIE ILIE TE RE RWU SCCR2 SCI CONTROL 2 SCI Tx REQUESTS SCI INTERRUPT REQUEST SBK EA9 SCI RX BLOC Figure 13 SCI Receiver Block Diagram MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 49 Freescale Semiconductor, Inc. SCBDH, SCBDL -- SCI Baud Rate Select High, SCI Baud Rate Select Low $1028 RESET: $1029 RESET: BIT 7 BTST 0 SBR7 0 6 BSPL 0 SBR6 0 5 -- 0 SBR5 0 4 SBR12 0 SBR4 0 3 SBR11 0 SBR3 0 2 SBR10 0 SBR2 1 1 SBR9 0 SBR1 0 $1028, $1029 BIT 0 SBR8 0 SBR0 0 High Low BTST -- Baud Register Test (TEST) Factory test only BSPL -- Baud Rate Counter Split (TEST) Factory test only Bit 5 -- Not implemented Always reads zero SBR[12:0] -- SCI Baud Rate Select Bits Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values for example rates: SCI baud rate = EXTAL / (32 * BR) where BR is the contents of SBR[12:0] in SCBDH,L (BR = 1, 2, 3 ... 8191 decimal, or BR = $0001, $0002, $0003 ... $1FFF hexadecimal) BR = 0 disables the baud rate generator. Table 22 Baud Rate Selection Target Baud Rate 110 312 300 600 1200 2400 4800 9600 19.2K 38.4K 2272 156 833 416 208 104 52 26 13 -- 8 MHz $08E0 78 $0341 $01A0 $00D0 $0068 $0034 $001A $000D -- Crystal Frequency (XTAL) 12 MHz 3409 2500 1250 625 312 156 78 39 20 -- $0D51 $09C4 $04E2 $0271 $0138 $009C $004E $0027 $0014 -- 16 MHz 4545 3333 1666 833 416 208 104 52 26 13 $11C1 $0D05 $0682 $0341 $01A0 $00D0 $0068 $0034 $001A $000D Dec Value Hex Value Dec Value Hex Value Dec Value Hex Value Freescale Semiconductor, Inc... 50 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. SCCR1 -- SCI Control Register 1 BIT 7 LOOPS 0 6 WOMS 0 5 -- 0 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0 BIT 0 PT 0 $102A RESET: LOOPS -- SCI LOOP Mode Enable 0 = SCI transmit and receive operate normally 1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is fed back into the receiver input WOMS -- Wired-Or Mode Option for PD[1:0] (See also DWOM bit in SPCR.) 0 = TxD and RxD operate normally 1 = TxD and RxD are open drains if operating as an output Freescale Semiconductor, Inc... Bit 5 -- Not implemented Always reads zero M -- Mode (Select Character Format) 0 = Start, 8 data bits, 1 stop bit 1 = Start, 9 data bits, 1 stop bit WAKE -- Wake-Up by Address Mark/Idle 0 = Wake-up by IDLE line recognition 1 = Wake-up by address mark (most significant data bit set) ILT -- Idle Line Type 0 = Short (SCI counts consecutive ones after start bit) 1 = Long (SCI counts ones only after stop bit) PE -- Parity Enable 0 = Parity disabled 1 = Parity enabled PT -- Parity Type 0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes parity bit to be one) 1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity bit to be one) SCCR2 -- SCI Control Register 2 BIT 7 TIE 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 BIT 0 SBK 0 $102B RESET: TIE -- Transmit Interrupt Enable 0 = TDRE interrupts disabled 1 = SCI interrupt requested when TDRE status flag is set TCIE -- Transmit Complete Interrupt Enable 0 = TC interrupts disabled 1 = SCI interrupt requested when TC status flag is set RIE -- Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 51 Freescale Semiconductor, Inc. ILIE -- Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE -- Transmitter Enable 0 = Transmitter disabled 1 = Transmitter enabled RE -- Receiver Enable 0 = Receiver disabled 1 = Receiver enabled RWU -- Receiver Wake-Up Control 0 = Normal SCI receiver 1 = Wake-up enabled and receiver interrupts inhibited Freescale Semiconductor, Inc... SBK -- Send Break 0 = Break generator off 1 = Break codes generated as long as SBK = 1 SCSR1 -- SCI Status Register 1 BIT 7 TDRE 0 6 TC 0 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 BIT 0 PF 0 $102C RESET: TDRE -- Transmit Data Register Empty Flag Set if transmit data can be written to SCDR; if TDRE = 0, transmit data register is busy. Cleared by SCSR1 read with TDRE set, followed by SCDR write. 0 = Transmit data register contains data and is busy 1 = Transmit data register is empty and SCDR can be written TC -- Transmit Complete Flag Set if transmitter is idle (no data, preamble, or break transmission in progress). Cleared by SCSR1 read with TC set, followed by SCDR write. 0 = Transmitter is busy 1 = Transmitter is idle and SCDR can be written RDRF -- Receive Data Register Full Flag Set if a received character is ready to be read from SCDR. Cleared by SCSR1 read with RDRF set, followed by SCDR read. IDLE -- Idle Line Detected Flag Once cleared, IDLE is set again until the RxD line has been active and becomes idle once more. IDLE flag is inhibited when RWU = 1. Set if the RxD line is idle. Cleared by SCSR1 read with IDLE set, followed by SCDR read. OR -- Overrun Error Flag Set if a new character is received before a previously received character is read from SCDR. Cleared by SCSR1 read with OR set, followed by SCDR read. NF -- Noise Error Flag Set if majority sample logic detects anything other than a unanimous decision. Cleared by SCSR1 read with NF set, followed by SCDR read. FE -- Framing Error Set if a zero is detected where a stop bit was expected. Cleared by SCSR1 read with FE set, followed by SCDR read. 52 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. PF -- Parity Error Flag Set if received data has incorrect parity. Cleared by SCSR1 read with PE set, followed by SCDR read. SCSR2 -- SCI Status Register 2 BIT 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 BIT 0 RAF 0 $102D RESET: Bits [7:1] -- Not implemented Always read zero RAF -- Receiver Active Flag (Read only) 0 = The receiver circuitry is idle 1 = A character is being received Freescale Semiconductor, Inc... SCDRH, SCDRL -- SCI Data High, SCI Data Low $102E $102F BIT 7 R8 R7/T7 6 T8 R6/T6 5 -- R5/T5 4 -- R4/T4 3 -- R3/T3 2 -- R2/T2 1 -- R1/T1 $102E, $102F BIT 0 -- R0/T0 High Low R8 -- Receiver Bit 8 Ninth serial data bit received when SCI is configured for nine data bit operation (M = 1). T8 -- Transmitter Bit 8 Ninth serial data bit transmitted when SCI is configured for nine data bit operation (M = 1). Bits [5:0] -- Not implemented Always read zero R/T[7:0] -- Receiver/Transmitter Data Bits 7 to 0 SCI data is double buffered in both directions. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 53 Freescale Semiconductor, Inc. 9 Analog-to-Digital Converter The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. The MC68HC(7)11EA9 A/D converter system, a four-channel multiplexed-input successive-approximation converter, is accurate to 1 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge-redistribution technique used. Dedicated pins VRH and VRL provide the reference supply voltage inputs. A multiplexer allows the single A/D converter to select one of 16 analog signals. PE0 AN0 VRH 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD VRL Freescale Semiconductor, Inc... PE1 AN1 PE2 AN2 PE3 AN3 PE4 AN4 PE5 AN5 PE6 AN6 PE7 AN7 ANALOG MUX SUCCESSIVE APPROXIMATION REGISTER AND CONTROL RESULT INTERNAL DATA BUS CCF ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR3 A/D RESULT 3 SCAN MULT CD CC CB CA ADR4 A/D RESULT 4 EA9 A/D BLOCK Figure 14 A/D Block Diagram 54 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. E CLOCK WRITE TO ADCTL 12 E CYCLES 2 CYC SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE END 0 CONVERT FIRST CHANNEL AND UPDATE ADR1 32 CONVERT SECOND CHANNEL AND UPDATE ADR2 64 CONVERT THIRD CHANNEL AND UPDATE ADR3 96 CONVERT FOURTH CHANNEL AND UPDATE ADR4 SET CCF FLAG 128 E CYCLES Freescale Semiconductor, Inc... EA9 A/D CONVERSION TIM Figure 15 A/D Conversion Sequence INPUT PROTECTION DEVICE ANALOG INPUT PIN DIFFUSION AND POLY COUPLER < 4 K < 2 pF + ~20 V - ~0.7 V * ~20 pF DAC CAPACITANCE 400 nA JUNCTION LEAKAGE VRL *THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME. EA9 ANALOG INPUT PIN Figure 16 Electrical Model of an A/D Input Pin (Sample Mode) MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com REPEAT SEQUENCE IF SCAN = 1 MSB 4 CYCLES BIT 6 2 CYC BIT 5 2 CYC BIT 4 2 CYC BIT 3 2 CYC BIT 2 2 CYC BIT 1 2 CYC LSB 2 CYC 55 Freescale Semiconductor, Inc. ADCTL -- A/D Control/Status BIT 7 CCF I 6 -- 0 5 SCAN I 4 MULT I 3 CD I 2 CC I 1 CB I BIT 0 CA I $1030 RESET: CCF -- Conversions Complete Flag Set after an A/D conversion cycle is completed. CCF is cleared by a write to ADCTL. 0 = The A/D converter is currently performing a conversion sequence 1 = The A/D converter has completed a conversion, placed the result in the appropriate result register and is currently idle Bit 6 -- Not implemented Always reads zero Freescale Semiconductor, Inc... SCAN -- Continuous Scan Control 0 = Do four conversions and stop 1 = Convert four channels in selected group continuously MULT -- Multiple Channel/Single Channel Control 0 = Convert single channel selected 1 = Convert four channels in selected group CD-CA -- Channel Select D through A Table 23 A/D Converter Channel Select Control Bits Channel Select Control Bits CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel Signal AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH* VRL* (VRH)/2* Reserved Result in ADRx if MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 -- -- -- -- ADR1 ADR2 ADR3 ADR4 56 For More Information On This Product, Go to: www.freescale.com MC68HC11EA9 MC68HC11EA9TS/D Freescale Semiconductor, Inc. ADR1-ADR4 -- A/D Results $1031 $1032 $1033 $1034 BIT 7 BIT 7 BIT 7 BIT 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 $1031-$1034 BIT 0 BIT 0 BIT 0 BIT 0 ADR1 ADR2 ADR3 ADR4 Table 24 Analog Input to 8-Bit Result Translation % (1) Bit 7 50% 2.5 6 25% 1.250 5 12.5% 0.625 4 6.25% 0.3125 3 3.12% 0.1562 2 1.56% 0.0781 1 0.78% 0.0391 Bit 0 0.39% 0.0195 Freescale Semiconductor, Inc... VOLTS (2) (1) % of VRH - VRL (2) Volts for VRL = 0; VRH = 5.0 V OPTION -- System Configuration Options BIT 7 6 5 4 3 2 1 BIT 0 ADPU CSEL IRQE* DLY* CME -- CR1* CR0* RESET: 0 0 0 1 0 0 0 0 * Can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. $1039 ADPU -- A/D Converter Power-Up 0 = A/D converter disabled and powered down 1 = A/D converter is enabled and powered on CSEL -- Clock Select 0 = A/D and EEPROM use the system E clock 1 = A/D and EEPROM use internal RC clock IRQE -- IRQ Select Edge-Sensitive Only Refer to 5 Resets and Interrupts. DLY -- Enable Oscillator Start-up Delay 0 = No stabilization delay on exit from STOP mode. 1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode. CME -- Clock Monitor Enable Refer to 5 Resets and Interrupts. Bit 2 -- Not implemented Always reads zero CR[1:0] -- COP Timer Rate Select Refer to 5 Resets and Interrupts. MC68HC11EA9 MC68HC11EA9TS/D For More Information On This Product, Go to: www.freescale.com 57 Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com Freescale Semiconductor, Inc... USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. |
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