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FEDL228XXDIGEST-03
Issue Date: March. 24, 2009
ML2282X-XXX/ML2286X-XXX
Speech Synthesis LSI with Built-in P2ROM Including 2-Channel Mixing Function
GENERAL DESCRIPTION
ML2282X(ML22825/ML22824/ML22823-XXX) and ML2286X (ML22865/ML22864/ML22783-XXX) are voice synthesis LSIs with built-in P2ROM that stores speech data. These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker amplifier. Also, ML2282X supports the synchronous serial interface and ML22865/ML22864/ML22863 supports the I2C interface. By integrating all the functions required for voice output into a single chip, these LSIs can be more easily incorporated in compact portable devices. * Built-in memory capacity and maximum vocal reproduction time: (at the case of 4-bit ADPCM2 algorithm)
Product name ML22825-XXX/ML22865 ML22824-XXX/ML22864 ML22823-XXX/ML22863 ROM capacity 16 Mbits 8 Mbits 4 Mbits Maximum vocal reproduction time (sec) FS = 8.0 kHz FS = 16 kHz FS = 4.0 kHz 1,044 522 261 520 260 130 258 129 64
4-bit ADPCM2 8-bit Nonlinear PCM 8-bit PCM , 16-bit PCM Can be specified for each phrase. * Sampling frequency(Fs): 4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 / 48.0 kHz fs can be specified for each phrase. * Built-in low-pass filter and 16-bit DA converter * Speaker driving amplifier: 0.7 W (when 8 , DVDD=5 V, Ta=25C) 2ch analog input (internal: 1ch; external: 1ch) * CPU command interface: 3-wired serial clock-synchronized (ML2282X) I2C interface (ML2286X) * Maximum number of phrases: 4,096 phrases from 000h to 3FFh (1024 phrases/bank) * Memory bank switching: Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins * Volume control: 32 levels (OFF is included) can be set by CVOL command. 50 levels (OFF is included) can be set by AVOL command * Repeat function: LOOP commands * 2-channel mixing function: Available except case using 32kHz as sampling frequencys * Source oscillation frequency: 4.096 MHz * Power supply voltage: 2.7 to 3.6V / 4.5 to 5.5 V * Operating temperature range: -40 to +85C * Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K-MC) * Product name: ML22825-xxxMB, ML22824-xxxMB, ML22823-xxxMB ML22865-xxxMB, ML22864-xxxMB, ML22863-xxxMB (xxx: ROM code No.)
* Voice synthesis method:
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The following table shows the differences among the other speech synthesis LSIs.
Parameter CPU interface Playback method Maximum number of phrases Sampling frequency (kHz) ML2216 Serial 4-bit ADPCM2 8-bit nonlinear PCM 8-bit straight PCM 16-bit straight PCM 256 4.0/5.3/6.4/ 8.0/10.6/12.8 16.0 4.096MHz (with a built-in crystal oscillator circuit) 12 bits 3rd order comb filter Built-in 0.3W (8, DVDD = 5 V) Yes No 16 levels Yes 20 ms to 1024 ms (4 ms/step) Yes No ML22800 series ML22825/ML22824/ ML22823-XXX ML22865/ML22864/ ML22863-XXX I2C
1,024 (256/bank)
4,096 (1,024/bank) 4.0/5.3/6.4/8.0/ 10.6/12.0/12.8/ 16.0/21.3/24.0/ 25.6/32.0/48.0 16 bits FIR interpolation filter Built-in 0.7W (8, DVDD = 5 V) 2-channel 32 levels
Clock frequency DA converter Low-pass filter Speaker driving amplifier Edit ROM function Simultaneous sound production function (mixing function) Volume control Silence insertion Repeat function Interval at which a seam is silent during continuous playback (Note) Memory bank switching Power supply voltage Package
12 bits 3rd order comb filter No

No 2.7 V to 5.5 V 44-pin QFP
Yes 2.7 V to 3.6 V 30-pin SSOP
2.7 to 3.6V 4.5 to 5.5 V
2.7 to 3.6V 4.5 to 5.5 V
*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silence interval
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BLOCK DIAGRAMS
(ML22825/ML22824/ML22823-XXX : Synchronous serial interface)
DVDD DGND VDDL VDDR Phrase Address Latch Address Counter ADPCM Synthesizer Address Controller Multiplexer 16/8/4Mbit ROM
CSB SCK SI SO CBUSYB DIPH SEL0 SEL1 TESTI0,1 TESTO RESETB XT XTB
PCM Synthesizer
I/O Interface
LPF Timing Controller 16bit DAC
SP-AMP OSC PLL SPVDD SPGND SPM SPP AIN
(ML22865/ML22864/ML22863-XXX : I2C interface)
DVDD DGND VDDL VDDR Phrase Address Latch Address Counter ADPCM Synthesizer Address Controller Multiplexer 16/8/4Mbit ROM
SDA2-0 SCL SDA CBUSYB SEL0 SEL1 TESTI0,1 TESTO RESETB I/O Interface
PCM Synthesizer
LPF Timing Controller 16bit DAC
XT XTB
SP-AMP OSC PLL SPVDD SPGND SPM SPP AIN
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PIN CONFIGURATIONS (TOP VIEW)
(ML22825/ML22824/ML22823-XXXMB : Synchronous serial interface)
AIN TESTI0 RESETB TESTO DIPH SEL0 SEL1 DGND CSB SCK SI SO CBUSYB DGND XT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPM SPP SPGND SPVDD DGND SG TESTI1 VDDR DVDD VDDL NC DGND NC DVDD XTB
NC: No Connection
30-Pin Plastic SSOP
(ML22865/ML22864/ML22863-XXXMB : I2C interface)
AIN TESTI0 RESETB TESTO SAD0 SEL0 SEL1 DGND SAD1 SCL SDA SAD2 CBUSYB DGND XT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPM SPP SPGND SPVDD DGND SG TESTI1 VDDR DVDD VDDL NC DGND NC DVDD XTB
NC: No Connection
30-Pin Plastic SSOP
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PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Pin 1 2 Symbol AIN TESTI0 I/O I I Initial value Description (*1) 0 Input pin for speaker amplifier. Input pin for testing. 0 Fix this pin to "L" level (DGND level). This pin has a pull-down resistor built in. Input pin for reset. At the "L" level, the LSI enters initial state. During reset, the entire circuitry stops and enters power down state. Input "L" level when power is 0 supplied. After the power supply voltage is stable, drive this pin to "H" (*2) level. Then the entire circuitry can be powered up. This pin has a pull-up resistor built in. Output pins for testing. Hi-Z Leave these pins open. Memory bank switching pins. 0 Fix these pins to "L" level when the memory bank function is not used. -- 1 Digital ground pin. Also serves as a ground pin for the internal memory. Output pin for command processing status. This pin outputs "L" level during command processing. Any command should be entered when this pin is "H" level. Connect to the crystal or ceramic resonator. A feedback resistor around 1 M is built in between this pin and the XTB pin. Use this pin if need to use an external clock. If the resonator is used, connect it as close to this pin as possible. Connect to the crystal or ceramic resonator. When to use an external clock, leave this pin open. If the resonator is used, connect it as close to this pin as possible. Power supply pins for logic circuitry. Connect a capacitor of 0.1F or more between these pins and DGND pins. Non connected pins. Leave these pins open. Regulator output pin for internal logic circuitry. Connect a capacitor recommended between this pin and DGND pin. Regulator output pin for Built-in ROM. Connect a capacitor recommended between this pin and DGND pin. Test pin. Fix this pin to a DGND level. Reference voltage output pin for the speaker amplifier built-in. Connect a capacitor recommended between this pin and DGND pin. Power supply pin for the speaker amplifier. Connect a bypass capacitor of 0.1F or more between this pin and SPGND pin. Ground pin for the speaker amplifier. Positive(+) output pin of the speaker amplifier built-in. Serves as the LINE output (*3), if built-in speaker amplifier is not used. Negative(-) output pin of the speaker amplifier built-in.
3
RESETB
I
4 6, 7 8, 14, 19, 26 13
TESTO SEL0 SEL1 DGND CBUSYB
O I -- O
15
XT
I
0
16 17, 22 18, 20 21 23 24 25 27 28 29 30
XTB DVDD N.C VDDL VDDR TESTI1 SG SPVDD SPGND SPP SPM
O -- -- -- -- -- -- -- -- O O
1 -- -- 0 0 0 0 -- -- 0 Hi-Z
*1: Indicates the initial value during reset input or power down. *2: "H" during power down. *3: Outputs a voice signal before amplified by the speaker amplifier built-in.
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PIN DESCRIPTION (FOR ML2282X SYNCHRONOUS SERIAL INTERFACE)
Pin Symbol I/O Initial value (*1) Description Set pin of the SCK clock edge. When this pin is "L" level, rising edge is available for input(SI) and falling edge is available for output(SO). When this pin is "H" level, falling edge is available for input(SI) and rising edge is available for output(SO). Chip select pin. At the "L" level, data input/output is available. Synchronous clock input pin for serial interface. Input pin of synchronous serial data. When the DIPH pin is "L" level, data is shifted in at the rising edges of the SCK clock pulses. When the DIPH pin is "H" level, data is shifted in at the falling edges of the SCK clock pulses. Output pin of synchronous serial data. When the DIPH pin is "L" level, data is output at the falling edges of the SCK clock pulses. When the DIPH pin is "H" level, data is output at the rising edges of the SCK clock pulses. When the CSB pin is "H" level, this pin is Hi-Z state.
5
DIPH
I
0
9 10
CSB SCK
I I
1 0
11
SI
I
0
12
SO
O
Hi-Z
*1: Indicate the initial value during reset or power down.
PIN DESCRIPTION (FOR ML2286X I2C INTERFACE)
Pin Symbol SAD0 SAD1 SAD2 SCL I/O Initial value (*1) 0 0 Set pin of the slave address. Clock input pin for I2C serial interface. This pin should be connected to pull-up resistor. Input/output pin for I2C serial data. Use for setting the mode of write/read and writing address, writing data or reading data. This pin should be connected to pull-up resistor. (N-ch MOS) open drain, when output mode. High impedance(Hi-Z), when input mode. Description
5, 9, 12 10
I I
11
SDA
IO
0
*1: Indicate the initial value during reset or power down.
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ABSOLUTE MAXIMUM RATINGS
(DGND = SPGND = 0 V, Ta = 25C) Rating Unit -0.3 to +7.0 -0.3 to DVDD+0.3 938 10 300 50 -55 to +150 V V mW mA mA mA C
Parameter Power supply voltage Input voltage Power dissipation
Symbol DVDD, SPVDD VIN PD
Condition -- -- Applies to all pins except SPM, SPP, VDDL, and VDDR.
Output short-circuit current
IOS
Applies to SPM and SPP pins. Applies to VDDL and VDDR pins. --
Storage temperature
TSTG
RECOMMENDED OPERATING CONDITIONS
(DGND = SPGND = 0 V) Unit V C Max. 4.5 45 MHz
Parameter Power supply voltage Operating temperature Master clock frequency External capacitors for crystal oscillator
Symbol DVDD, SPVDD TOP fOSC
Condition -- -- -- Min. 3.5 15
Range
2.7 to 3.6 4.5 to 5.5 -40 to +85 Typ. 4.096 30
Cd, Cg
--
pF
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ELECTRICAL CHARACTERISTICS
DC Characteristics (for the 3V applications)
Parameter "H" input voltage "L" input voltage "H" output voltage 1 "H" output voltage 2 (*1) "L" output voltage 1 "L" output voltage 2 (*1) "L" output voltage 3 (*2) "H" input current 1 "H" input current 2 (*3) "H" input current 3 (*4) "L" input current 1 "L" input current 2 (*3) "L" input current 3 (*5) "H" output leak current 3 (*6) "L" output leak current 3 (*6) Supply current during playback Power-down supply current Symbol VIH VIL VOH1 VOH2 VOL1 VOL2 VOL3 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 IILOH IILOL IDD IDDS DVDD = SPVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C Condition Min. Typ. Max. Unit -- 0.86xDVDD -- DVDD V -- 0 -- 0.14xDVDD V IOH = -1 mA DVDD-0.4 -- -- V IOH = -50 A DVDD-0.4 -- -- V IOL = 2 mA -- -- 0.4 V IOL = 50 A -- -- 0.4 V IOL = 3 mA -- -- 0.4 V VIH = DVDD -- -- 10 A VIH = DVDD 0.3 2.0 15 A VIH = DVDD 2 30 200 A VIL = GND -10 -- -- A VIL = GND -15 -2.0 -0.3 A VIL = GND -200 -30 -2 A VOH = DVDD VOL = GND fOSC = 4.096 MHz No output load Ta = -40 to +40C Ta = -40 to +85C -- -10 -- -- -- -- -- -- 1 1 10 -- 20 10 20 A A mA A A
*1: Applies to the XTB pin. *2: Applies to the SCL, SDA pin. *3: Applies to the XT pin. *4: Applies to the TESTI0 pin. *5: Applies to the RESETB pin. *6: Applies to the TESTO pin.
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DC Characteristics (for the 5V applications)
Parameter "H" input voltage "L" input voltage "H" output voltage 1 "H" output voltage 2 (*1) "L" output voltage 1 "L" output voltage 2 (*1) "L" output voltage 3 (*2) "H" input current 1 "H" input current 2 (*3) "H" input current 3 (*4) "L" input current 1 "L" input current 2 (*3) "L" input current 3 (*5) "L" output leak current 2 (*6) "L" output leak current 3 (*6) Supply current during playback Power-down supply current Symbol VIH VIL VOH1 VOH2 VOL1 VOL2 VOL3 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 IILOH IILOL IDD IDDS DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = -40 to +85C Condition Min. Typ. Max. Unit -- 0.8xDVDD -- DVDD V -- 0 -- 0.2xDVDD V IOH = -1 mA DVDD-0.4 -- -- V IOH = -50A DVDD-0.4 -- -- V IOL = 2 mA -- -- 0.4 V IOL = 50 A -- -- 0.4 V IOL = 3 mA -- -- 0.4 V VIH = DVDD -- -- 10 A VIH = DVDD 0.8 5.0 20 A VIH = DVDD 20 100 400 A VIL = GND -10 -- -- A VIL = GND -20 -5.0 -0.8 A VIL = GND -400 -100 -20 A VOH = DVDD VOL = GND fOSC = 4.096 MHz No output load Ta = -20 to +40C Ta = -20 to +85C -- -10 -- -- -- -- -- -- 1 1 10 -- 25 15 30 A A mA A A
*1: Applies to the XTB pin. *2: Applies to the SCL and SDA pins. *3: Applies to the XT pin. *4: Applies to the TESTI0 pin. *5: Applies to the RESETB pin. *6: Applies to the TESTO pin.
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Characteristics of Analog Circuitry (for the 3V applications)
Parameter AIN input resistance AIN input voltage range LINE output load resistance LINE output voltage range SG output voltage SG output resistance SPM, SPP output load resistance Speaker amplifier output power Output offset voltage between SPM and SPP with no signal present Symbol RAIN VAIN RLA VAO VSG RSG RLSP PSPO VOF DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = -40 to +85C Condition Min. Typ. Max. Unit 15 20 25 k DVDDx2/3 Vp-p During 1/2 DVDD output No output load During power down SPVDD = 3.3V, f = 1kHz RSPO = 8, THD10% SPIN-SPM gain = 0dB With a load of 8 10 DVDD/6 0.95xVDDL/2 57 8 100 -50 VDDL/2 96 300 DVDDx5/6 1.05xVDDL/2 135 +50 k V V k mW mV
Characteristics of Analog Circuitry (for the 5V applications)
Parameter AIN input resistance AIN input voltage range LINE output load resistance LINE output voltage range SG output voltage SG output resistance SPM, SPP output load resistance Speaker amplifier output power Output offset voltage between SPM and SPP with no signal present Symbol RAIN VAIN RLA VAO VSG RSG RLSP PSPO DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = -20 to +85C Condition Min. Typ. Max. Unit 15 20 25 k DVDDx2/3 Vp-p During 1/2 DVDD output No output load During power down SPVDD = 5.0V, f = 1kHz RSPO = 8, THD10% Ta=25C SPIN-SPM gain = 0dB With a load of 8 10 DVDD/6 0.95xVDDL/2 57 8 500 VDDL/2 96 700 DVDDx5/6 1.05xVDDL/2 135 k V V k mW
VOF
-50
+50
mV
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FUNCTIONAL DESCRIPTION
Synchronous Serial Command Interface The CSB, SCK, SI, and SO pins are used to input the command data or to read the status. Driving the CSB pin to "L" level enables the serial CPU interface. After the CSB pin is driven to "L" level, the command data are input through the SI pin from the MSB synchronized with the SCK clock. The command data shifts in through the SI pin at the rising or falling edge of the SCK clock pulse. Then, a command is executed at the rising or falling edge of the eighth pulse of the SCK clock. As for status reading, status is output from the SO pin, synchronized with the SCK clock after the CSB pin is driven to "L" level. The SCK clock edge is specified by the input level of the DIPH pin. - When the DIPH pin is "L" level, rising edge is available for input from SI pin and falling edge is available for output from SO pin. - When the DIPH pin is "H" level, falling edge is available for input from SI pin and rising edge is available for output from SO pin. It is possible to input command data, even if the CSB pin is fixed by "L" level. However, if unexpected pulses caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in normal recognition of command. Then it is recommended that the CSB pin is "L" level only for command input. The count of the SCK clock pulse is initialized when the CSB pin goes to "H" level.
Command Data Input or Status Read Timing
* When DIPH pin is "L" level CSB SCK SI SO D7
(MSB )
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0
(LS B)
D7
D0
* When DIPH pin is "H" level CSB SCK SI SO D7
(MSB )
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0
(LS B)
D7
D0
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The following table shows the contents of each data output at a status read.
Output status signal MSB 7SB 6SB 5SB 4SB 3SB 2SB LSB Channel 2 BUSYB output (BUSYB1) Channel 1 BUSYB output (BUSYB0) Channel 2 NCR output (NCR1) Channel 1 NCR output (NCR0)
The BUSYB output is "L" level when a command is being processed or the playback of a particular channel is going on. In other states, the BUSYB output is "H" level. The NCR output is "L" level when a command is being processed or particular channel is in standby for playback. In other states, the NCR output is "H" level.
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I2C Command Interface (Applies to ML2286X) The I2C Interface built-in is an serial interface (: slave side) that is compliant with I2C bus specification. It supports Fast mode and enables data transmission/reception at 400 kbps. The SCL and SDA pins are used to input the command data or to read the status. Pins (:SAD0, 1 and 2) are used to set the slave address. Pull-up resister should be connected to SCL pin and SDA pin. For the master on the I2C bus to communicate with this device (: slave), input the slave address with the first seven bits after setting the start condition. The upper three bits of the slave address can be set using the SAD0 to 2 pins. The eighth bit of slave address is used to set the direction (: write or read) of communication. If the eighth bit is "0" level, it is write mode from master to slave. And, if the eighth bit is "1" level, it is read mode from master. The communication is made in the unit of byte. And acknowledge is needed for each byte. The protocol of I2C communication is shown below. - Command flow at data write START condition Slave address +W (0) Write address (ex. 1st byte of a command) Write data (ex. 2nd byte of a command) STOP condition
Data write timing SCL SDA
S
A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave Address
A
1st Command Data
A
2nd Command Data
AP
- Command flow at data read Start condition Slave address +R(1) Read data (ex. Status read) STOP condition
Data read timing SCL SDA
S
A6 A5 A4 A3 A2 A1 A0 R A D7 D6D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave Address
A
Read Data
A
Read Data
A
P
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Setting of the slave address using the SAD0 to 2 pins
SAD2 0 0 0 0 1 1 1 1 SAD1 0 0 1 1 0 0 1 1 SAD0 0 1 0 1 0 1 0 1 Lower 4 bits 0101 0101 0101 0101 0101 0101 0101 0101
The following table shows the contents of each data output at a status read. Status is updated by the RDSTAT command; therefore, be sure to input the RDSTAT command in order to read status.
Output status signal MSB 7SB 6SB 5SB 4SB 3SB 2SB LSB Channel 2 NCR output (NCR1) Channel 1 NCR output (NCR0) Channel 2 BUSYB output (BUSYB1) Channel 1 BUSYB output (BUSYB0)
The BUSYB signal is "L" level when either a command is being processed or the playback of a particular channel is going on. In other states, the BUSYB signal is "H" level. The NCR signal is "L" level when either a command is being processed or a particular channel is in standby for playback. In other states, the NCR signal is "H" level.
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Command List Each command is configured by the unit of byte (8-bit). The following commands, AMODE, AVOL FADR, PLAY, MUON, and CVOL, use two bytes.
Command D7 D6 D5 D4 D3 D2 D1 D0 Description Power-up command. Shifts from the power down state to the command waiting state. Also, sets the number of memory banks. Power-down command. Shifts form the command waiting state to the power down state. Status read command. Reads the command status on each channel. Control command of analog circuitry. Setoperation of power-up/dpwn and input/output. Playback start command. Use the data of the 2nd byte to specify a phrase number. Can be specified for each channel. Playback stop command. Can be set for each channel. Set command of playback phrase. Can be set for each channel. Use START command to start. Playback start command without phrase spec. Use FADR command to set phrase.Can start playback on multiple channels simultaneously. After played back by PLAY command, the same phrase can be played back with this command. Silence insertion command. Set the silent time length for each channel using M7 to M0 bits in the 2nd byte. Set command of repeat playback. Setting is enabled during playback. Can be specified for each channel. Stop command of repeat playback. Can be specified for each channel. Also, repeat playback is released by STOP command automatically.
PUP
0
0
0
0
0
0
S1
S0
PDWN
0
0
1
0
0
0
0
0
RDSTAT
1 0
0 0
1 0
1 0
0 0
0 1
0 0
0 0
AMODE FAD 0 PLAY F7 STOP FADR F7 F6 F5 F4 F3 F2 F1 F0 0 0 F6 1 0 F5 1 1 F4 0 1 F3 0 F9 F2 0 F8 F1 CH1 0 F0 CH0 CH DAG1 DAG0 AIG1 1 0 0 AIG0 DAEN SPEN POP F9 F8 0 CH
START
0
1
0
1
0
0
CH1
CH0
0 MUON M7 SLOOP 1
1 M6 0
1 M5 0
1 M4 0
0 M3 0
0 M2 0
CH1 M1 CH1
CH0 M0 CH0
CLOOP
1
0
0
1
0
0
CH1
CH0
1 CVOL 0 0 AVOL 0
0 0 0 0
1 0 0 AV5
0 CV4 0 AV4
0 CV3 1 AV3
0 CV2 0 AV2
CH1 CV1 0 AV1
CH0 Volume control command. Set volume for each channel using CV0 CV4 to CV0 bits in the 2nd byte. Analog volume control command. Set volume after channel mixing AV0 using AV5 to AV0 bits. 0
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Voice Synthesis Algorithm Four types of voice synthesis algorithm are supported. They are 4-bit ADPCM2, 8-bit non-linear PCM, 8-bit straight PCM and 16-bit straight PCM. Select the best one according to the characteristics of playback voice. The following table shows key features of each algorithm.
Voice synthesis algorithm 4-bit ADPCM2 8-bit Nonlinear PCM 8-bit straight PCM 16-bit straight PCM
Applied waveform
Feature Up version of OKI's specific voice synthesis algorithm (: 4-bit ADPCM). Voice quality is improved. Algorithm, which plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm
Normal voice waveform Waveform including high frequency signals (sound effect, etc.)
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Memory Allocation and Creating Voice Data The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM area. The voice control area manages the voice data in the ROM. It contains data for controlling the start/stop addresses of voice data for 1,024 phrases, use/non-use of the edit ROM function and so on. The test area contains data for testing. The voice area contains actual waveform data. The edit ROM area contains data for effective use of voice data. For the details, refer to the section of "Edit ROM Function." The edit ROM area is not available if the edit ROM is not used. The ROM data is created using a dedicated tool.
Configuration of ROM data
0x00000 0x01FFF 0x02000 0x0205F 0x02060 Voice control area (Fixed 64 Kbits) Test area
Voice area
max: 0x1FFFFF Edit ROM area Depends on creation of ROM data.
max: 0x1FFFFF
Playback Time and Memory Capacity The playback time depends on the memory capacity, sampling frequency, and playback method. The equation to know the playback time is shown below. But this is not applied if the edit ROM function is used.
1.024 x (Memory capacity - 64.75 [Kbits] Sampling frequency [kHz] x Bit length
Playback time [sec] =
(Bit length is 4 at the 4-bit ADPCM2 and 8/16 at the PCM.) Example) In the case that the sampling frequency is 16 kHz, algorithm is 4-bit ADPCM2 and ROM capacity is 16 Mbits, the playback time is approx. 261 seconds, as shown below.
1.024x(16834 - 64.75) [Kbits] 261 [sec] 16 [kHz] x 4 [bits]
Playback time =
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ML2282X-XXX/ ML2286X -XXX
Edit ROM Function The edit ROM function makes it possible to play back multiple phrases in succession. The following functions are set using the edit ROM function: Continuous playback: Silence insertion function: There is no limit to set the number of times of continuous playback. It depends on the memory capacity only. 20ms to 1,024 ms
It is possible to use voice ROM effectively to use the edit ROM function. Below is an example of the ROM structure, case of using the edit ROM function. Example 1) Phrases using the Edit ROM Function
Phrase 1 Phrase 2 Phrase 3 Phrase 4 Phrase 5 A A E E A B C B B C D D D
Silence
D D
E
C
D
Example 2) Structure of the ROM that contents of Example 1 are stored
Address control area A B D E Editing area C
Mixing Function It is possible to perform mixing of two channels simultaneously. And also, it is possible to specify PLAY, STOP, and CVOL commands for each channel respectively. The mixing function is available if the sampling frequency (FS) is 32 kHz or less. - Precautions for Waveform Clamp Adjust the volume of each channel using the CVOL command, if the waveform clamp is increased by channel mixing.
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Memory Bank Switching Function The memory bank switching function enables the the built-in ROM area that is divivided into up to four banks to be used. When four banks are used, the maximum number of phrases per bank is 1,024 so that up to 4096 phrases can be played back. Using this function, multiple ROM codes can be grouped into one code. The settings of SEL1 pin and SEL0 pin determines which memory bank is used. To playback phrases, the number of memory banks must be specified in PUP. When using a memory bank switching function, data must be divided and saved in the specified areas at ROM data creation. - When the number of memory banks is 1
SEL1 0 SEL0 0 ML22825 ML22865 00000h - 1FFFFFh ML22824 ML22864 00000h - FFFFFh ML22823 ML22863 00000h -7FFFFh
- When the number of memory banks is 2
SEL1 0 0 SEL0 0 1 ML22825 ML22865 00000h - FFFFFh 100000h - 1FFFFFh ML22824 ML22864 00000h - 7FFFFh 80000h - FFFFFh ML22823 ML22863 00000h - 3FFFFh 40000h - 7FFFFh
- When the number of memory banks is 4
SEL1 0 0 1 1 SEL0 0 1 0 1 ML22825 ML22865 00000h - 7FFFFh 80000h - FFFFFh 100000h - 17FFFFh 180000h - 1FFFFFh ML22824 ML22864 00000h - 3FFFFh 40000h - 7FFFFh 80000h - BFFFFh C0000h - FFFFFh ML22823 ML22863 00000h - 1FFFFh 20000h - 3FFFFh 40000h - 5FFFFh 60000h - 7FFFFh
The memory (16 Mbits) in the ML22825 is divided as shown below.
Bank 1 Capacity: 16 Mbits Max. Phrase count: 1024 Bank 1 Capacity: 8 Mbits Max. Phrase count: 1024 Bank 1 Capacity: 4 Mbits Max. Phrase count: 1024 Bank 2 Capacity: 4 Mbits Max. Phrase count: 1024 Bank 2 Capacity: 8 Mbits Max. Phrase count: 1024 Bank 3 Capacity: 4 Mbits Max. Phrase count: 1024 Bank 4 Capacity: 4 Mbits Max. Phrase count: 1024
0-7FFFFh 80000-FFFFFh 100000-17FFFFh 180000-1FFFFFh
Memory divide count: 1 16 Mbits x 1 area
Memory divide count: 2 8 Mbits x 2 areas
Memory divide count: 4 4 Mbits x 4 areas
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APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 5V)
MCU RESETB CSB SCK SI SO CBUSYB DIPH TESTI1 AIN TESTI0 VDDL VDDR DVDD SPVDD 0.1F XTB 33pF DGND SPGND
SPM SPP Speaker SG 0.1F
0.1F
33pF XT 4.096MHz
10F 0.1F 5V
10F
APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 3V)
MCU RESETB CSB SCK SI SO CBUSYB DIPH TESTI1
SPM SPP Speaker SG 0.1F
AIN
0.1 F
TESTI0 VDDL VDDR DVDD SPVDD 0.1F XTB 33pF DGND SPGND
33pF XT 4.096MHz
10F
0.1F 0.1F
3V
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APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=5V)
7k MCU 7k SCL SDA (CBUSYB) SPM SPP Speaker SAD2-0 SG 0.1F
TESTI0 TESTI1
AIN
0.1F
33pF XT 4.096MHz XTB 33pF
VDDL VDDR DVDD SPVDD 0.1F DGND SPGND
10F 0.1F 5V
10F
APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=3V)
7k MCU 7k SCL SDA (CBUSYB) SPM SPP Speaker SAD2-0 SG 0.1F
TESTI0 TESTI1
AIN
0.1F
33pF XT 4.096MHz XTB 33pF
VDDL VDDR DVDD SPVDD 0.1F DGND SPGND
0.1F 0.1F
10F 3V
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PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact OKI SEMICONDUCTOR's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No. PEDL2282XFULL-01 FEDL228XXFULL-01 FEDL228XXFULL-02 Date Dec. 17, 2007 Apr. 18, 2008 May. 29, 2008 Page Previous Current Edition Edition - - - 1 2 10 10 FEDL228XXFULL-03 Mar. 24, 2009 10 10 - - - 1 2 10 10 Description Preliminary edition 1 Final edition 1 Final edition 2 2-channel mixing function 48kHz-> 32kHz Power supply voltage 2.7 to 5.5V -> 2.7 to 3.6V / 4.5 to 5.5 V LINE output voltage range MAX. DVDD x 4/6 -> DVDD x 5/6 SG output resistance Min 52 -> Min 57 AIN input voltage range(for the 5V app..) Max. DVDD x 2/4 -> DVDD x 2/3 PUP(AMODE) -> POP(AMODE) Correct ROM address and calculation Modify application circuit
15 17 20,21
15 17 20,21
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. OKI SEMICONDUCTOR assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by OKI SEMICONDUCTOR authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2009 OKI SEMICONDUCTOR CO., LTD.
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