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September 2006 rev 0.2
PCS2P5T915A
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Features
* * * * * * * * * * * * * * Very low Output Skew : < 25 pS (max ) Very low Duty Cycle Distortion : 300 pS (max ) Low Propagation delays : 2nS (max ) DC to 250MHz Operating Range Very low Power Consumption Hot insertable Over-Voltage Tolerant Inputs Very Low Cycle to cycle Jitter 2.5V Supply Voltage Isolated Output Power (VDDQ) 3 level inputs for selectable interface Selectable Inputs : HSTL, eHSTL, 1.8V/2.5V LVTTL or LVPECL Available in Standard 48 pin TSSOP Package Lead Free Option
input, the PCS2P5T915A replicates the input to 10 outputs organised as output pairs for differential signalling. The PCS2P5T915A performs as a translator or converter for a differential HSTL, eHSTL, 1.8V/2.5V LVTTL or CMOS, LVPECL or single ended 1.8V/2.5V LVTTL or CMOS inputs to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs A user interface for configuration/selection is controlled via a three level input that can be wired or conditioned for the appropriate low-mid-high levels. In addition, the PCS2P5T915A true or complementary outputs may be asynchronously enabled and/or disabled. Multiple power pins for power and and returns guarantee the low skews and high accuracy.
Applications
* High Accuracy Clock Signal Fan-out and Distribution
Product Description
The PCS2P5T915A is a versatile user
* Specialty Synchronous Memory Clock Support * Data Communications Switches Routers Hubs.
configurable/selectable 2.5V differential buffer for fanout and distribution of a high accuracy clock reference source. Accepting either a single ended or a differential
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.2
PCS2P5T915A Functional Block Diagram
PCS2P5T915A
TxS GL
G(+)
Output Control
Q1
Output Control
Q1
Output Control RxS A A / VREF Output Control
Q2
Q2
Output Control G(-)
Q3
Output Control
Q3
Output Control
Q4
Output Control
Q4
Output Control
Q5
Output Control
Q5
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.2
Pin Configuration
GL VDD VDD GND GND
G(+)
PCS2P5T915A
48 47 46 45 44 43 42 41 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GND VDDQ VDDQ GND GND GND VDDQ Q2 Q2 GND VDDQ Q3 Q3 VDDQ GND Q4 Q4 VDDQ VDDQ GND GND VDDQ GND TxS
VDDQ Q1 Q1 GND VDDQ A/VREF A VDDQ GND Q5 Q5 VDDQ G(-) GND GND VDD VDD RxS
PCS2P5T915A
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Absolute Maximum Ratings1
Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V.
Symbol
VDD VDDQ VI VO VREF TSTG TJ
Description
Power Supply Voltage2 Output Power Supply Input Voltage Output Voltage
3 2
Max
-0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDDQ +0.5 -0.5 to +3.6 -65 to +165 150
Unit
V V V V V C C
Reference Voltage3 Storage Temperature Junction Temperature
Capacitance1,2 (TA = +25C, F = 1.0MHz) Symbol Parameter
CIN Input Capacitance
Min
Typ
3.5
Max
Unit
pF
Notes: 1. This parameter is measured at characterization but not tested. 2. Capacitance applies to all inputs except RxS and TxS.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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Recommended Operating Range Symbol Description
TA 1 VDD VDDQ1 VT Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage
PCS2P5T915A
Min
-40 2.4 1.4 1.65
Typ
+25 2.5 1.5 1.8 VDD VDDQ/ 2
Max
+85 2.6 1.6 1.95
Unit
C V V V V V
Note: 1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
Pin Description Symbol I/O
A I
Type
Adjustable
1
Description
Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input. Complementary clock input. A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended mode, A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle voltage for A: 2.5V LVTTL VREF = 1250mV 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL , VREF = 1082mV Gate control for "true", Qn, outputs. When G(+)is LOW, the "true" outputs are enabled. When G(+)is HIGH, the "true" outputs are asynchronously disabled to the level designated by GL4. Gate control for "complementary", Qn, outputs. When G(-)is LOW, the "complementary" outputs are enabled. When G(-)is HIGH, the "complementary" outputs are asynchronously disabled to the opposite level as GL4. Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs Complementary clock outputs Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in conjuction with VDDQ to set the interface levels. Power supply for the device core and inputs Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be connected to VDD. Power supply return for all power
A/VREF
I
Adjustable1
G(+) G(-) GL Qn Qn RxS TxS VDD VDDQ GND
I I I O O I I
LVTTL LVTTL
5
5
LVTTL5 Adjustable2 Adjustable 3 Level3 3 Level3 PWR PWR PWR
2
Notes: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels Single-ended 1.8V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant. 4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.2
Input/Output Selection1 Input
2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF
PCS2P5T915A
Output Input
2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF
Output
2.5V LVTTL
eHSTL
1.8V LVTTL
HSTL
Note: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a singleended mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in differential mode.
DC Electrical Characteristics Over Operating Range Symbol Parameter Test Conditions
VIHH VIMM VILL I3 Input HIGH Voltage Level1 Input MID Voltage Level1 Input LOW Voltage Level1 3-Level Input DC Current (RxS, TxS) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN= VDD VIN= VDD/2 VIN= GND HIGH Level MID Level LOW Level
Min
VDD - 0.4 VDD/2 - 0.2
Max
VDD/2 + 0.2 0.4 200 +50
Unit
V V V A
-50 -200
Note: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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DC Electrical Characteristics Over Operating Range for HSTL1 Symbol
IIH IIL VIK VIN VDIF VCM VIH VIL VREF
PCS2P5T915A
Parameter Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ -0.7 -0.3 0.2 680 VREF+ 100 VREF- 100 750 750 900
Min
Typ7
Max
5 5 - 1.2 +3.6
Unit
Input Characteristics Input HIGH Current9 Input LOW Current9 Clamp Diode Voltage DC Input Voltage DC Differential Voltage2,8 DC Common Mode Input 3,8 Voltage DC Input HIGH4,5,8 DC Input LOW4,6,8 Single-Ended Reference Voltage4,8 IOH= -8mA IOH= -100A IOL= 8mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1 0.4 0.1 A V V V mV mV mV mV
VDD= 2.4V, IIN= - 18mA
Output Characteristics
VOH VOL Output HIGH Voltage Output LOW Voltage V V V V
Notes: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Power Supply Characteristics for HSTL Outputs1 Symbol Parameter Test Conditions2
IDDQ IDDQQ IDDD Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF
Typ
20 0.1 20
Max
30 0.3 30
Unit
mA mA A/MHz
IDDDQ ITOT ITOTQ
VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz,CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 1.5V, FREFERENCE CLOCK= 250MHz, CL= 15pF
30 20 35 35 60
50 40 50 70 120
A/MHz mA mA
Note: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.2
Differential Input AC Test Conditions for HSTL Symbol Parameter
VDIF VX VTHI tR, tF Input Signal Swing
1 2
PCS2P5T915A
Value
1 750 Crossing Point 1
Units
V mV V V/nS
Differential Input Signal Crossing Point Input Signal Edge Rate
4
Input Timing Measurement Reference Level3
Notes: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for eHSTL1 Symbol Parameter Test Conditions Input Characteristics
IIH IIL VIK VIN VDIF VCM VIH VIL VREF Input HIGH Current9 Input LOW Current DC Input Voltage DC Differential Voltage2,8 DC Common Mode Input Voltage3,8 DC Input HIGH4,5,8 DC Input LOW Single-Ended Reference 4,8 Voltage IOH= -8mA IOH= -100A IOL= 8mA IOL= 100A
4,6,8 9
Min
Typ7
Max
5 5
Unit
A V V V mV mV mV mV
VDD= 2.6V VDD= 2.6V
VI = VDDQ/GND VI = GND/VDDQ - 0.7 -0.3 0.2 800 VREF+ 100 900
Clamp Diode Voltage
VDD= 2.4V, IIN = -18mA
- 1.2 +3.6 1000 VREF- 100
900
Output Characteristics
VOH VOL Output HIGH Voltage Output LOW Voltage VDDQ- 0.4 VDDQ- 0.1 0.4 0.1 V V V V
Notes: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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Power Supply Characteristics for eHSTL Outputs1 Symbol Parameter Test Conditions2
IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.8V, FREFERENCE VDDQ= 1.8V, FREFERENCE VDDQ= 1.8V, FREFERENCE VDDQ= 1.8V, FREFERENCE
CLOCK=
PCS2P5T915A
Typ
20 0.1 20 40 20 35 40 80
Max
30 0.3 30 60 40 50 80 160
Unit
mA mA A/MHz A/MHz mA mA
100MHz, CL= 15pF CLOCK= 250MHz, CL= 15pF
CLOCK= CLOCK=
100MHz, CL= 15pF 250MHz, CL= 15pF
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for eHSTL Symbol Parameter
VDIF VX VTHI tR, tF Input Signal Swing
1
Value
1 900 Crossing Point 1
Units
V mV V V/nS
Differential Input Signal Crossing Point2 Input Timing Measurement Reference Level3 Input Signal Edge Rate
4
Notes: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for LVEPECL1 Symbol Parameter Test Conditions Input Characteristics
IIH IIL VIK VIN VCM VREF VIH VIL Input HIGH Current6 Input LOW Current
6
Min
Typ2
Max
5 5
Unit
VDD= 2.6V VDD= 2.6V
VI = VDDQ/GND VI = GND/VDDQ -0.7 - 0.3 915 1082 1082 1275 555
A V V mV mV
Clamp Diode Voltage DC Input Voltage DC Common Mode Input Voltage3,5 Single-Ended Reference 4,5 Voltage DC Input HIGH DC Input LOW
VDD= 2.4V, IIN= -18mA
- 1.2 3.6 1248
1620 875
mV mV
Notes: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25C ambient. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation while in differential mode, A/VREF is tied to the DC Voltage VREF. 5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.2
Differential Input AC Test Conditions for LVEPECL Symbol Parameter
VDIF VX VTHI tR, tF Input Signal Swing
1
PCS2P5T915A
Value
732 1082 Crossing Point 1
Units
mV mV V V/nS
Differential Input Signal Crossing Point2 Input Timing Measurement Reference Level3 Input Signal Edge Rate
4
Notes: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
DC Electrical Characteristics Over Operating Range for 2.5V LVTTL1 Symbol
IIH IIL VIK VIN VIH VIL VDIF VCM VIH VIL VREF
Parameter
Input HIGH Current10 Input LOW Current10 Clamp Diode Voltage DC Input Voltage
2
Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ
Min
Typ8
Max
5 5
Unit
Input Characteristics
A V V V V V 1250 1350 VREF- 100 1250 mV mV mV mV
VDD= 2.4V, IIN = -18mA -0.3 1.7
- 0.7
- 1.2 +3.6
Single-Ended Inputs
DC Input HIGH DC Input LOW DC Differential Voltage3,9 DC Common Mode Input 4,9 Voltage DC Input HIGH5,6,9 DC Input LOW Single-Ended Reference Voltage5,9 IOH= -12mA IOH= -100A IOL= 12mA IOL= 100A
5,7,9
0.7 0.2 1150 VREF+ 100
Differential Inputs
Output Characteristics
VOH VOL Output HIGH Voltage Output LOW Voltage VDDQ- 0.4 VDDQ- 0.1 0.4 0.1 V V V V
Notes: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.2
Power Supply Characteristics for 2.5V LVTTL Outputs1 Symbol Parameter Test Conditions2
IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF VDDQ= 2.5V., FREFERENCE VDDQ= 2.5V., FREFERENCE
CLOCK=
PCS2P5T915A
Typ
20 0.1 25 45 25 45 40 100
Max
30 0.3 40 70 40 70 80 200
Unit
mA mA A/MHz A/MHz mA mA
200MHz, CL= 15pF
VDDQ= 2.5V., FREFERENCE CLOCK= 100MHz, CL= 15pF
CLOCK= 200MHz, CL= 15pF
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 2.5V LVTTL Symbol Parameter
VDIF VX VTHI tR, tF Input Signal Swing1 Differential Input Signal Crossing Point Input Signal Edge Rate4
2 3
Value
VDD VDD/2 Crossing Point 2.5
Units
V V V V/nS
Input Timing Measurement Reference Level
Notes: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2.5V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-ended Input AC Test Conditions for 2.5V LVTTL Symbol Parameter
VIH VIL VTHI tR, tF Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level Input Signal Edge Rate
2 1
Value
VDD 0 VDD/2 2
Units
V V V V/nS
Notes: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.2
DC Electrical Characteristics Over Operating Range for 1.8V LVTTL1 Symbol
IIH IIL VIK VIN VIH VIL VDIF VCM VIH VIL VREF
PCS2P5T915A
Parameter Test Conditions
VDD= 2.6V VDD= 2.6V VI = VDDQ/GND VI = GND/VDDQ -0.7 - 0.3 1.07311 0.683 0.2 825 VREF+ 100 VREF- 100 900 900 975
11
Min
Typ8
Max
5 5 - 1.2 VDDQ+ 0.3
Unit
Input Characteristics Input HIGH Current12 Input LOW Current12 Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW DC Differential Voltage3,9 DC Common Mode Input Voltage4,9 DC Input HIGH5,6,9 DC Input LOW Single-Ended Reference 5,9 Voltage IOH= -6mA IOH= -100A IOL= 6mA IOL= 100A VDDQ- 0.4 VDDQ- 0.1 0.4 0.1
5,7,9
A V V V V V mV mV mV mV
VDD= 2.4V, IIN= -18mA
Single-Ended Inputs2
Differential Inputs
Output Characteristics
VOH VOL Output HIGH Voltage Output LOW Voltage V V V V
Notes: 1. See RECOMMENDED OPERATING RANGE table. 2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within 200mV of VREF when VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply. 11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply. 12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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Power Supply Characteristics for 1.8V LVTTL Outputs1 Symbol
IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ
PCS2P5T915A
Parameter
Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current
Test Conditions2
VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDDQ= Max., Reference Clock = LOW3 Outputs enabled, All outputs unloaded VDD= Max., VDDQ= Max., CL= 0pF VDD= Max., VDDQ= Max., CL= 0pF VDDQ= 1.8V., FREFERENCE VDDQ= 1.8V., FREFERENCE VDDQ= 1.8V., FREFERENCE VDDQ= 1.8V., FREFERENCE
CLOCK= CLOCK= CLOCK= CLOCK=
Typ
20 0.1 20 55 25 40 50 120
Max
30 0.3 40 80 40 60 100 240
Unit
mA mA A/MHz A/MHz mA mA
100MHz, CL= 15pF 200MHz, CL= 15pF 100MHz, CL= 15pF 200MHz, CL= 15pF
Notes: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Differential Input AC Test Conditions for 1.8V LVTTL Symbol
VDIF VX VTHI tR, tF Input Signal Swing
1 2 3
Parameter
Differential Input Signal Crossing Point
4
Value
VDDI VDDI /2 Crossing Point 1.8
Units
V mV V V/nS
Input Timing Measurement Reference Level Input Signal Edge Rate
Notes:1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1.8V/nS or greater is to be maintained in the 20% to 80% range of the input waveform.
Single-ended Input AC Test Conditions for 1.8V LVTTL Symbol
VIH VIL VTHI tR, tF Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level Input Signal Edge Rate
3 2 1
Parameter
Value
VDDI 0 VDDI/2 2
Units
V V mV V/nS
Notes: 1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. 2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 3. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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AC Electrical Characteristics Over Operating Range5 Symbo l
Skew Parameters Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes 2 tSK(INV) Inverting Skew Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes tSK(P) Pulse Skew3 Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes 4 tSK(PP) Part-to-Part Skew Single-Ended in Differential Mode (DSE) HSTL and eHSTL Differential True and Complementary VOX Output Crossing Voltage Level Propagation Delay Propagation Delay A to 2.5V / 1.8V LVTTL Outputs tPLH Qn/Qn tPHL HSTL / eHSTL Outputs Output Rise Time 2.5V /1.8V LVTTL Outputs tR (20% to 80%) HSTL / eHSTL Outputs Output Fall Time 2.5V /1.8V LVTTL Outputs tF (20% to 80%) HSTL / eHSTL Outputs tSK(O) Same Device Output 1 Pin-to-Pin Skew fO Frequency Range (HSTL/eHSTL outputs) Frequency Range (2.5V/1.8V LVTTL outputs) Output Gate Enable to Qn/Qn Output Gate Enable to Qn/Qn Driven to GL Designated Level
PCS2P5T915A
Parameter
Min
Typ
Max
Unit
25 pS 25 300 pS 300 300 pS 300 300 pS 300 VDDQ/2 - 200 VDDQ/2 VDDQ/2 + 200 2.5 2 350 350 350 350 1050 1350 1050 1350 250 200 3.5 3 mV
nS pS pS MHz
Output Gate Enable/Disable Delay
tPGE tPGD nS nS
Notes: 1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. For differential LVTTL outputs, the true outputs are compared only with other true outputs and the complementary outputs are compared only with other complementary outputs. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals. 2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between true and complementary outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one device. 3. Skew measured is the difference between propagation delay times tPHL and tPLH of any output or output pair under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. The measurement applies to both true and complementary signals. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals. 4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels and temperature. 5. Guaranteed by design.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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AC Differential Input Specifications1 Symbol
tW
PCS2P5T915A
Parameter
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs) Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL 2 outputs) AC Differential Voltage3 AC Input HIGH AC Input LOW
4,5 4,6 2
Min
1.73 2.17
Typ
Max
Unit
nS
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF VIH VIL 400 Vx + 200 Vx - 200 mV mV mV
LVEPECL
VDIF VIH VIL AC Differential Voltage3 AC Input HIGH AC Input LOW
4
400 1275 875
mV mV mV
4
Notes: 1. For differential input mode, RxS is tied to GND. 2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined by VDIF has been met or exceeded. 3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range. 5. Voltage required to switch to a logic HIGH, single-ended operation only. 6. Voltage required to switch to a logic LOW, single-ended operation only.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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Differential AC Timing Waveforms
1/fo tw A tw
PCS2P5T915A
VIH VTHI VIL VIH
A tPLH Qn Qn Qm Qm tSK(O) tSK(O) tPHL
VTHI VIL VOH VOX VOL VOH VOX VOL
HSTL and eHSTL Output Propagation and Skew Waveforms
1/fo tw A tw VIH VTHI VIL VIH A tPLH Qn comp tPLH Qn comp tPHL VOH VTHO VOL tSK(O) Qm tSK(O) VOH VTHO VOL tSK(O) VOH Qm VTHO VOL tPHL VTHI VIL VOH VTHO VOL
tSK(O)
1.8V or 2.5V LVTTL Output Propagation and Skew Waveforms
Notes: 1. For the HSTL and eHSTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the crossing point of each Qn and Qn. 2. For 1.8V and 2.5V LVTTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the slower of Qn or Qn passing through VTHO. 3. Pulse skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from the rising and falling edges of a single pulse. Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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PCS2P5T915A
VIH A VTHI VIL VIH A VTHI VIL VIH GL tPLH VTHI VIL VIH VTHI G(+) VIL tPGD Qn tPGE VOH VTHO Qn VOL
Differential Gate Disable/Enable Showing Runt Pulse Generation
Notes: 1. The waveforms shown only gate "true" output, Qn. 2. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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SDR AC TIMING WAVEFORMS
1/fo tw A tw
PCS2P5T915A
VIH VTHI VIL VIH
A tPLH Qn tSK(O) Qm tSK(O) tPHL
VTHI VIL VOH VTHO VOL VOH VTHO VOL
Propagation and Skew Waveforms
Notes: 1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO. 2. Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
tPHL
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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PCS2P5T915A
VIH A VTHI VIL VIH A VTHI VIL VIH GL tPLH VTHI VIL VIH VTHI Gx VIL tPGD Qn tPGE VOH VTHO VOL
SDR Gate Disable/Enable Showing Runt Pulse Generation
Note: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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Test Circuits and Conditions
VDDI 3 inch, -50 Transmission Line R1
PCS2P5T915A
VIN
VDD
VDDQ
R2 A VDDI
D.U.T.
R1 A
Pulse Generator
VIN
3 inch, -50 Transmission Line
R2
Test Circuit for Differential Input1 Differential Input Test Conditions Symbol
R1 R2 VDDI
VDD= 2.5V 0.1V
100 100 VCM*2 HSTL: Crossing of A and A eHSTL: Crossing of A and A
Unit
V
VTHI
LVEPECL: Crossing of A and A 1.8V LVTTL: VDDI/2 2.5V LVTTL: VDD/2
V
Note: 1. This input configuration is used for all input interfaces. For single-ended testing, the VIN input is tied to GND. For testing single-ended in differential input mode, the VIN is left floating.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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PCS2P5T915A
VDDQ
VDD
VDDQ VDDQ VDD R1 Qn CL R2 VDDQ CL
R1
R2
D.U.T.
Qn
D.U.T.
Qn
VDDQ R1
CL
R2
Test Circuit for SDR Outputs Test Circuit for Differential Outputs
SDR Output Test Conditions Differential Output Test Contions Symbol
CL R1 R2 VTHO
VDD= 2.5V 0.1V VDDQ= Interface Specified
15 100 100 VDDQ/ 2
Unit
pF V
Symbol
CL R1 R2 VOX VTHO
VDD= 2.5V 0.1V VDDQ= Interface Specified
15 100 100 HSTL: Crossing of Qn and Qn eHSTL: Crossing of Qn and Qn 1.8V LVTTL: VDDQ/2 2.5V LVTTL: VDDQ/2
Unit
pF V V
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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Package Information Package (6.10 mm Body, JEDEC MO-153-ED)
PCS2P5T915A
Dimensions Symbol Min
A A1 A2 b c D E1 E e L N 0 8 0.018 0.004 0.488 0.236 0.319 BSC 0.020 BSC 0.030 48 0 8 0.45 .... 0.002 0.031 0.008 BSC 0.008 0.496 0.244 0.09 12.40 6.00 8.10 BSC 0.50 BSC 0.75
Inches Max
0.047 0.006 0.041
Millimeters Min
... 0.05 0.8 0.20 BSC 0.20 12.60 6.20
Max
1.20 0.15 1.05
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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Ordering Information Part Number
PCS2P5T915AG PCS2I5T915AG
PCS2P5T915A
Marking
2P5T915AG 2I5T915AG
Package Type
48 pin TSSOP Package 48 pin TSSOP Package
Temperature
Commercial Industrial
Device Ordering Information
PCS2P5T915AG-48-TT
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
Notice: The information in this document is subject to change without notice.
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PCS2P5T915A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P5T915A Document Version: v0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Voltage (2.5V) High Accuracy 1:5 Clock Fan-Out Buffer
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