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| SSM9477M/GM N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Simple drive requirement Lower gate charge Fast switching characteristics D D D D BV DSS R DS(ON) ID G 60V 90m 4A SO-8 S S S Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM977M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. D G S Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 60 25 4 3.1 20 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 50 Unit C/W 8/21/2004 Rev.2.01 www.SiliconStandard.com 1 of 5 SSM9477M/GM Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 60 1 Typ. 0.04 6 6 2 3 6 5 16 3 510 55 35 1.4 Max. Units 90 120 3 10 25 100 10 810 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance2 VGS=10V, ID=4A VGS=4.5V, ID=3A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=4A VDS=60V, VGS=0V VDS=48V, VGS=0V VGS=25V ID=4A VDS=48V VGS=4.5V VDS=30V ID=1A RG=3.3 , VGS=10V RD=30 VGS=0V VDS=25V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=2A, VGS=0V IS=4A, VGS=0V, dI/dt=100A/s Min. - Typ. 27 32 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board, t <10sec ; 125C/W when mounted on min. copper pad. 8/21/2004 Rev.2.01 www.SiliconStandard.com 2 of 5 SSM9477M/GM 25 25 T A = 25 C 20 o 10V 7.0 V 5.0V 4.5V ID , Drain Current (A) T A = 150 C 20 o 10V 7.0V 5.0V 4.5V ID , Drain Current (A) 15 15 10 10 V G =3.0V 5 V G =3.0V 5 0 0 2 4 6 8 0 0 2 4 6 8 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 2.0 ID=3A T A =25C RDS(ON) (m ) 90 1.8 ID=4A V G =10V 1.6 Normalized R DS(ON) 1.4 1.2 80 1.0 0.8 70 0.6 2 4 6 8 10 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.8 4 1.5 Normalized VGS(th) (V) 1.2 3 IS(A) 1.2 2 T j =150 o C T j =25 o C 0.9 1 0.6 0 0 0.2 0.4 0.6 0.8 1 0.3 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 8/21/2004 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9477M/GM f=1.0MHz 14 1000 VGS , Gate to Source Voltage (V) ID=4A 12 C iss V DS = 30 V V DS = 38 V V DS = 48 V 10 8 C (pF) 100 6 C oss 4 C rss 2 0 10 0 5 10 15 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 10 Normalized Thermal Response (Rthja) 0.1 100us 1ms ID (A) 1 0.1 0.2 0.05 10ms 100ms 0.01 0.02 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 125C/W 0.1 T A =25 o C Single Pulse 1s DC 0.01 0.1 1 10 100 1000 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 8/21/2004 Rev.2.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9477M/GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 8/21/2004 Rev.2.01 www.SiliconStandard.com 5 of 5 |
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