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| SSM9510GM N- and P-channel Enhancement-mode Power MOSFETs Simple drive requirement Lower gate charge Fast switching characteristics Pb-free; RoHS compliant. D2 D1 D2 D1 D1 D1 D2 N-CH BV DSS R DS(ON) ID G2 G2 S2 G1 S2 S1 G1 S1 30V 28m 6.9A -30V 55m -5.3A D1 D2 P-CH BVDSS RDS(ON) ID SO-8 DESCRIPTION Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM9510GM is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications. It is well suited for low voltage applications requiring complementary N and P MOSFETs. G1 G2 S1 S2 ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 30 20 6.9 5.5 30 2.0 0.016 -55 to 150 -55 to 150 P-channel -30 20 -5.3 -4.2 -30 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 2/10/2005 Rev.2.01 www.SiliconStandard.com 1 of 8 SSM9510GM N-channel Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. 30 1 - Typ. Max. Units 0.02 28 40 3 1 25 100 16 870 - V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=5A VGS=4.5V, ID=3A 4.6 10 2 6 8 7 20 6 540 160 120 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70 C) o VDS=VGS, ID=250uA VDS=10V, ID=5A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=6.9A VDS=24V VGS=4.5V VDS=15V ID=1A RG=3.3 , VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=1.7A, VGS=0V IS=6.9A, VGS=0V dI/dt=100A/s Min. - Typ. Max. Units 20 11 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 2/10/2005 Rev.2.01 www.SiliconStandard.com 2 of 8 SSM9510GM P-channel Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS BV DSS/ Tj Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=-250uA 2 Min. -30 -1 - Typ. -0.023 Max. Units 55 90 -3 -1 -25 100 15 930 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-10V, ID=-5A VGS=-4.5V, ID=-3A VDS=VGS, ID=-250uA VDS=-10V, ID=-5A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 20V ID=-5.3A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3 ,VGS=-10V RD=10 VGS=0V VDS=-25V f=1.0MHz 4.9 9 2 6 10 8 25 13 580 180 120 Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage2 Reverse Recovery Time Reverse Recovery Charge Test Conditions IS=-1.7A, VGS=0V IS=-5.3A, VGS=0V dI/dt=-100A/s Min. Typ. 21 17 Max. Units -1.2 V ns nC Notes: 1.Pulse width limited by maximum junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board; 135C/W when mounted on minimum copper pad. 2/10/2005 Rev.2.01 www.SiliconStandard.com 3 of 8 SSM9510GM N-channel 90 70 80 T A =25 o C 10V ID , Drain Current (A) 60 T A =150 o C 10V 8.0V 70 ID , Drain Current (A) 50 60 8.0V 50 40 6.0V 40 6.0V 30 30 4.5V 20 4.5V 20 10 10 V G =3.0V 0 0 1 2 3 4 5 6 0 V G =3.0V 0 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 40 1.8 ID=5A 36 T A =25 o C Normalized RDS(ON) 1.6 I D =5A V G =10V 1.4 RDS(ON) (m ) 32 1.2 28 1.0 24 0.8 20 3 4 5 6 7 8 9 10 11 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2 5 1.8 4 1.6 T j =150 o C 3 T j =25 o C VGS(th) (V) 1.4 1.2 IS(A) 1 2 0.8 0.6 1 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode 2/10/2005 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 4 of 8 SSM9510GM N-channel f=1.0MHz 14 10000 12 VGS , Gate to Source Voltage (V) I D =5.7A V DS =16V 1000 10 6 C (pF) 8 Ciss Coss Crss 100 4 2 0 0 4 8 12 16 20 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 10 0.1 0.1 0.05 1ms ID (A) 1 10ms 100ms 0.02 0.01 PDM Single Pulse 0.01 t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135C/W 0.1 T A =25 o C Single Pulse 0.01 0.1 1 10 1s 10s DC 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off)tf Charge Q Fig 11. Switching Time Waveform 2/10/2005 Rev.2.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 5 of 8 SSM9510GM P-channel 70 60 60 T A =25 C o -10V 50 T A =150 C -10V -8.0V 40 o -ID , Drain Current (A) 40 -6.0V 30 -ID , Drain Current (A) 50 -8.0V 30 -6.0V 20 20 -4.5V V G =-3.0V -4.5V 10 10 V G =-3.0V 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100 1.8 Fig 2. Typical Output Characteristics I D = -5A 90 T A =25 C Normalized R DS(ON) 80 1.4 o 1.6 I D = -5 A V G = -10 V RDS(ON) (m ) 70 1.2 60 1 50 0.8 40 3 4 5 6 7 8 9 10 11 0.6 -50 0 50 100 150 -V GS ,Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 5 2.8 4 2.6 2.4 3 -VGS(th) (V) T j =150 o C -IS(A) T j =25 o C 2.2 2 2 1.8 1.6 1 1.4 1.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 2/10/2005 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 6 of 8 SSM9510GM P-channel f=1.0MHz 12 10000 -VGS , Gate to Source Voltage (V) 10 I D =-5.3A V DS =-24V 1000 8 Ciss 6 C (pF) Coss 100 4 Crss 2 0 0 2 4 6 8 10 12 14 16 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 10 0.2 1ms -ID (A) 1 0.1 0.1 0.05 0.02 0.01 10ms 100ms 0.1 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135C/W T A =25 o C Single Pulse 0.01 1s 10s DC 1 10 100 0.001 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 2/10/2005 Rev.2.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 7 of 8 SSM9510GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/10/2005 Rev.2.01 www.SiliconStandard.com 8 of 8 |
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