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PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
Rev. 02 -- 6 July 2009 Product data sheet
1. Product profile
1.1 General description
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics
1.3 Applications
High frequency computer motherboard DC-to-DC convertors OR-ing applicationss
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1; see Figure 3 Tmb = 25 C; see Figure 2 Min Typ Max 100 75 230 Unit V A W drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation gate-drain charge Symbol Parameter
Dynamic characteristics QGD VGS = 10 V; ID = 75 A; VDS = 80 V; Tj = 25 C; see Figure 11 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 44 nC
Static characteristics RDSon drain-source on-state resistance 7.5 8.8 m
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain
2 1 3
Simplified outline [1]
mb
Graphic symbol
D
G
mbb076
S
SOT404 (D2PAK)
[1] It is not possible to make connection to pin 2.
3. Ordering information
Table 3. Ordering information Package Name PSMN009-100B D2PAK Description plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) Version SOT404 Type number
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
2 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj VGSM Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature peak gate-source voltage source current peak source current pulsed; tp 50 s; Tj 150 C; = 25 % VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1; see Figure 3 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 175 C Tj 175 C; Tj 25 C; RGS = 20 k Min -20 -55 -55 -30 Max 100 100 20 65 75 400 230 175 175 30 Unit V V V A A A W C C V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode IS ISM EDS(AL)S Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C 75 400 120 A A mJ
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 35 A; Vsup = 15 V; drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 energy non-repetitive VGS = 10 V; Vsup = 15 V; RGS = 50 ; Tj(init) = 25 C; drain-source avalanche unclamped current
IDS(AL)S
-
75
A
120 Ider (%) 100
03ah99
120 Pder (%) 80
03aa16
80
60
40
40
20
0
0
30
60
90
120
150 180 Tmb (C)
0 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
(c) NXP B.V. 2009. All rights reserved.
PSMN009-100B_2
Product data sheet
Rev. 02 -- 6 July 2009
3 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
103 ID (A) 102
03ai01
Limit RDSon = VDS/ID
tp = 10 s
100 s
DC 10
1 ms 10 ms 100 ms
1 1 10
102 VDS (V)
103
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
4 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to mounting base thermal resistance from junction to ambient Conditions see Figure 4 minimum footprint; mounted on a printed-circuit board Min Typ 50 Max 0.65 Unit K/W K/W
1 Zth(j-mb) (K/W) 10-1 = 0.5 0.2 0.1 0.05 0.02 10-2 single pulse
tp P
03af48
=
tp T
t T
10-3 10-6
10-5
10-4
10-3
10-2
10-1
1 tp (s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
5 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 0.25 mA; VGS = 0 V; Tj = -55 C ID = 0.25 mA; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 175 C VDS = 30 V; VGS = 0 V; Tj = 25 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 175 C; see Figure 9; see Figure 10 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 13 VDS = 15 V; RL = 1.25 ; VGS = 10 V; RG(ext) = 6 ; Tj = 25 C; ID = 12 A VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 12 ID = 75 A; VDS = 80 V; VGS = 10 V; Tj = 25 C; see Figure 11 156 31 44 8250 620 300 38 59 120 43 0.8 1.2 nC nC nC pF pF pF ns ns ns ns V Min 90 100 1 2 Typ 3 0.02 10 10 20.25 7.5 Max 4 4.4 500 1 100 100 23.8 8.8 Unit V V V V V A A nA nA m m
Static characteristics
Source-drain diode
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
6 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
50 ID (A) 40 Tj = 25 C
03am54
10 V 6 V 5.6 V 5.4 V
80 ID (A) VDS > ID x R DSon
03am56
5.2 V
60
30
5V 40
20
4.8 V 4.6 V
20 175 C Tj = 25 C
10 4.4 V VGS = 4.2 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0 2
4
VGS (V)
6
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
03aa35
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
5
03aa32
10-1 ID (A) 10-2 min typ max
VGS(th) (V) 4 max
10-3
3
typ
10-4
2
min
10-5
1
10-6 0 2 4 VGS (V) 6
0 -60
0
60
120 Tj (C)
180
Fig 7.
Sub-threshold drain current as a function of gate-source voltage
Fig 8.
Gate-source threshold voltage as a function of junction temperature
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
7 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
15 5V RDSon (m) 12.5
03ai03
3
03aa29
5.5 V
VGS = 6 V
a
2
10
8V
1
7.5 10 V 20 V
5 0 50 100 150 ID (A) 200
0 -60
0
60
120
Tj (C)
180
Fig 9.
Drain-source on-state resistance as a function of drain current; typical values
Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature
105 C (pF) Ciss
03ai07
10 VGS (V) 8
03ai08
104 6
4 103 2 Coss Crss 0 0 50 100 150 QG (nC) 200 102 10-1
1
10
VDS (V)
102
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
8 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
100 IS (A) 80 Tj = 175 C 60 25 C 40
03ai06
20
0
0
0.5
1.0
VSD (V)
1.5
Fig 13. Source current as a function of source-drain voltage; typical values
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
9 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
7. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 05-02-11 06-03-16
Fig 14. Package outline SOT404 (D2PAK)
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
10 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
8. Revision history
Table 7. Revision history Release date Data sheet status 20090706 Product data sheet Change notice Supersedes PSMN009_100P_100B-01 Document ID PSMN009-100B_2 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type number PSMN009-100B separated from data sheet PSMN009_100P_100B-01. Product data -
PSMN009_100P_100B-01
20020429
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
11 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN009-100B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 6 July 2009
12 of 13
NXP Semiconductors
PSMN009-100B
N-channel TrenchMOS SiliconMAX standard level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 July 2009 Document identifier: PSMN009-100B_2

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