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19-5125; Rev 0; 1/10
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
General Description
The MAX2991 power-line communication analog frontend (AFE) is a state-of-the-art integrated circuit that delivers high integration and superb performance, while reducing the total system cost. The MAX2991 is the first AFE specifically designed for OFDM (orthogonal frequency division multiplexing) modulated signal transmission over power lines. Operating in the 10kHz to 490kHz band, the programmable filters allow compliance with CENELEC, FCC, and ARIB standards using the same device. The MAX2991 transceiver provides two main paths: transmit (Tx) path and receive (Rx) path. The transmit path injects an OFDM modulated signal into the AC or DC line. The transmit path is composed of a digital IIR filter, digital-to-analog converter (DAC), followed by a lowpass filter, and a preline driver. The receiver path is for the signal enhancement, filtering, and digitization of the received signal. The receiver is composed of a lowpass and a highpass filter, a two-stage automatic gain control (AGC), and an analog-to-digital converter (ADC). The integrated AGC maximizes the dynamic range of the signal up to 60dB, while the lowpass filter removes any out-of-band noise, and selects the desired frequency band. The ADC converts the enhanced and amplified input signal to a digital format. An integrated offset cancellation loop minimizes the DC offset. The MAX2991, along with the MAX2990 PLC baseband modem, delivers the most cost-effective data communication solution over power-line networks in the market. The MAX2991 is specified over the -40NC to +85NC temperature range and is available in a 48-pin LQFP package. Baseband
S Integrated Band Select Filter, AGC, and 10-Bit
Features
S Optimized to Operate with the MAX2990 PLC
MAX2991
ADC for Rx Path
S Integrated Wave-Shaping Filter, Programmable
Predriver Gain, and 10-Bit DAC for Tx Path
S Variable Sampling Rate Up to 1.2Msps S Built-In 60dB Dynamic Range AGC and DC Offset
Cancellation
S Programmable Filters Operate in the CENELEC,
FCC, and ARIB Frequency Bands
S Single 3.3V Power Supply S 70mA Typical Supply Current (Half-Duplex Mode) S Extended Operating Temperature Range
Applications
Automatic Meter Reading Home Automation Heating Ventilation and Air Conditioning (HVAC) Building Automation Industrial Automation Lighting Control Sensor Control and Data Acquisition (SCADA) Remote Monitoring and Control Security Systems/Keyless Entry Smart Grid
Ordering Information
PART MAX2991ECM+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 48 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Application Circuit
MAX2990 MAX2991
HOST APPLICATION C
MCU INTERFACE PHY
Tx BLOCK AFE Rx BLOCK
LINE DRIVER
LINE COUPLER
AC POWER LINE
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
ABSOLUTE MAXIMUM RATINGS
VDD to GND..........................................................-0.3V to +3.9V All Other Inputs/Outputs.......................................-0.3V to +3.9V Continuous Power Dissipation (TA = +70NC) 48-Pin LQFP (derate 25mW/NC above +70NC) ..........1535mW Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range .......................... -60NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, VGND = 0V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER Supply Voltage Supply Current High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current Shutdown Current SYMBOL VDD IDD VIH VIL VOH VOL IIL ISHDN Global power-down mode Source 5mA Sink 5mA -5 2.4 0.4 +5 +5 Rx mode Tx mode 2 0.8 CONDITIONS MIN 3 TYP 3.3 70 36 MAX 3.6 100 50 UNITS V mA V V V V FA FA DC CHARACTERISTICS (fS = 1200ksps)
AC CHARACTERISTICS (fS = 1200ksps) TRANSMITTER DAC Resolution DAC Sampling Rate DAC Integral Nonlinearity DAC Differential Nonlinearity Lowpass Filter Cutoff-Frequency Accuracy INL DNL FCC, ARIB CEN A Narrowband Full band FCC, ARIB Lowpass Filter -3dB Cutoff Frequency (Note 1) CEN A Narrowband (Note 2) Full band FCC, ARIB Stopband Attenuation Includes digital IIR filter CEN A Narrowband Full band Output-Voltage Swing Total Cascaded IM3 Predriver Gain Range IM3 Predriver gain = 0dB, frequency = 50kHz, 50I single-ended In-band (Note 3) Q2 Q0.5 Q5.0 Q3.0 Q5.0 Q5.0 470 90 134 560 28 28 28 28 1.5 -56 16 -50 VP-P dBc dB dB kHz % 10 1200 Bits ksps LSB LSB
2
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, VGND = 0V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER RECEIVER (Note 4) Input Impedance Receiver Dynamic Range FCC, ARIB Lowpass Filter Cutoff-Frequency Accuracy CEN A Narrowband Full band FCC, ARIB Lowpass Filter -3dB Cutoff Frequency (Note 1) CEN A Narrowband (Note 2) Full band FCC, ARIB Stopband Attenuation CEN A Narrowband Full band ADC Resolution ADC Sampling Rate ADC Integral Nonlinearity ADC Differential Nonlinearity Total Cascaded IM3 INL DNL IM3 Q0.5 Q0.5 -70 -60 At maximum gain 850 60 Q5.0 Q3.0 Q5.0 Q5.0 490 100 140 560 32 32 32 32 10 1200 Bits ksps LSB LSB dBc dB kHz % I dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX2991
3
Note 1: Rx and Tx filter transfer functions for different bands are shown in Figure 1. Note 2: The Applications Information section shows how to configure the Tx and Rx corner frequencies for different bands. Note 3: Devices are tested with each tone at 0.7VP-P differential using the following two input frequencies: fIN1 = 200kHz and fIN2 = 150kHz for FCC and ARIB fIN1 = 50kHz and fIN2 = 80kHz for CENELEC A fIN1 = 60kHz and fIN2 = 100kHz for narrowband fIN1 = 200kHz and fIN2 = 300kHz for full band Note 4: The parameters were tested using the external highpass filter circuit in Figure 10.
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Tx FILTER TRANSFER FUNCTION (CENELEC A)
MAX2991 toc00
Tx FILTER TRANSFER FUNCTION (NARROWBAND)
0 -10 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70
MAX2991 toc01
10 0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60 50 60 70 80 90 100 110
10
120
50
80
110
140
170
200
FREQUENCY (kHz)
FREQUENCY (kHz)
Tx FILTER TRANSFER FUNCTION (FCC)
MAX2991 toc02
Tx FILTER TRANSFER FUNCTION (FULL BAND)
0 -10 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70
MAX2991 toc03
10 0 -10 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70 50 200 350 500 650
10
800
50
200
350
500
650
800
950
FREQUENCY (kHz)
FREQUENCY (kHz)
Rx FILTER TRANSFER FUNCTION (CENELEC A)
MAX2991 toc04
Rx FILTER TRANSFER FUNCTION (NARROWBAND)
0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60
MAX2991 toc05
10 0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60 50 70 90 110 130
10
150
50
80
110
140
170
200
FREQUENCY (kHz)
FREQUENCY (kHz)
Rx FILTER TRANSFER FUNCTION (FCC)
MAX2991 toc06
Rx FILTER TRANSFER FUNCTION (FULL BAND)
0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60
MAX2991 toc07
10 0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60 50 200 350 500 650
10
800
50
150 250 350 450 550 650 750 850 FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 1. Rx and Tx Filter Transfer Functions for Different Bands 4 ______________________________________________________________________________________
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
SPITM TIMING CHARACTERISTICS (Figure 2)
PARAMETER SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to SCLK Setup CS Low After SCLK Hold CS High to SCLK Setup CS High After SCLK Hold CS Pulse-Width High SDIN to SCLK Setup SDIN Hold After SCLK SDOUT Valid Before SCLK SDOUT Valid After SCLK SYMBOL fCLK tCP tCH tCL tCSS0 tCSH0 tCSS1 tCSH1 tCSW tDS tDH tDO1 tDO2 50 20 20 10 10 10 10 20 10 10 20 5 CONDITIONS MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns
MAX2991
tCSW CS tCSS0 tCSH0 SCLK tDH tDS SDIN tDO1 tDO2 SDOUT tCH tCL tCP tCSH1 tCSS1
Figure 2. SPI Interface Timing Diagram
CS SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDIN
X
A6
A5
A4
A3
A2
A1
A0
R/W D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. SPI Communication Protocol SPI is a trademark of Motorola, Inc. _______________________________________________________________________________________ 5
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
AFE INTERFACE TIMING CHARACTERISTICS (Rx) (Figure 4)
PARAMETER RXCLK Frequency RXCLK Clock Period RXCLK Pulse-Width High RXCLK Pulse-Width Low RXCONV Low to RXCLK Setup RXCONV Low After RXCLK Hold RXCONV Pulse-Width High RXDATA Valid Before RXCLK RXDATA Valid After RXCLK SYMBOL fCLK tCP tCH tCL tCSS0 tCSH0 tCSW tDO1 tDO2 50 20 20 10 10 15 20 15 CONDITIONS MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns
tCSW RXCONV
tCSS0 tCSH0 RXCLK tDO1 tDO2 RXDATA tCH tCL tCP
Figure 4. AFE Interface Timing Diagram (Rx)
RXCONV RXCLK RXDATA 16 1 2 3 D9 4 D8 5 D7 6 D6 7 D5 8 D4 9 D3 10 D2 11 D1 12 D0 13 14 15 16 1
Figure 5. Rx Communication Protocol (Slave)
6
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
AFE INTERFACE TIMING CHARACTERISTICS (Tx) (Figure 6)
PARAMETER TXCLK Frequency TXCLK Clock Period TXCLK Pulse-Width High TXCLK Pulse-Width Low TXCONV Low to TXCLK Setup TXCONV Low After TXCLK Hold TXCONV High to TXCLK Setup TXCONV High After RXCLK Hold TXCONV Pulse-Width High TXDATA to TXCLK Setup TXDATA Hold After TXCLK SYMBOL fCLK tCP tCH tCL tCSS0 tCSH0 tCSS1 tCSH1 tCSW tDS tDH 50 10 10 10 10 10 10 15 5 10 CONDITIONS MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns
MAX2991
tCSW TXCONV
tCSS0 tCSH0 TXCLK tCH tCL tCP tCSH1 tCSS1
tDS TXDATA
tDH
Figure 6. AFE Interface Timing Diagram (Tx)
TXCONV TXCLK TXDATA 16 D0 1 C3 2 C2 3 C1 4 C0 5 X 6 X 7 D9 8 D8 9 D7 10 D6 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 1
Figure 7. Tx Communication Protocol (Master)
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7
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Pin Configuration
RBIASRX HPFOUT HPFOUT LPFOUT LPFOUT HPFIN HPFIN SHDN GND6 VDD6 RST
VDD1 GND1 RXINP RXINN I.C. I.C. I.C. I.C. TXOUTP TXOUTN GND2 VDD2
1 2 3 4 5 6 7 8 9 10 11 12
+
I.C.
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25
REF GND5 VDD5 ENTX ENRX GSUB RXCLK TXCLK RXDATA TXDATA RXCONV TXCONV
MAX2991
13 14 15 16 17 18 19 20 21 22 23 24
VDD3
RBIASTX
AGCFRZ
AGCCS
SCLK
SDOUT
REFCLK
GND3
LQFP
GND4
VDD4
SDIN
CS
Pin Description
PIN 1 2 3 4 5, 6, 48 7, 8 9 10 11 12 13 NAME VDD1 GND1 RXINP RXINN I.C. I.C. TXOUTP TXOUTN GND2 VDD2 AGCFRZ FUNCTION Analog Power-Supply 1. Bypass to GND1 with 100nF and 10FF capacitors in parallel located close to VDD1. Connect VDD inputs together. Analog Ground 1. Connect GND1 to the PCB ground. AC Power-Line Positive Input AC Power-Line Negative Input Internal Connection. Connect to the PCB ground. Internal Connection. Leave unconnected. AC Power-Line Positive Output AC Power-Line Negative Output Analog Ground 2. Connect GND2 to the PCB ground. Analog Power-Supply 2. Bypass to GND2 with 100nF and 10FF capacitors in parallel located close to VDD2. Connect VDD inputs together. Active-High AGC Freeze-Mode Enable. Drive AGCFRZ high to place the AGC adaptation in freeze mode. Drive AGCFRZ low to allow continuous AGC adaptation.
8
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Pin Description (continued)
PIN 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME AGCCS SCLK SDIN CS SDOUT VDD3 GND3 RBIASTX REFCLK GND4 VDD4 TXCONV RXCONV TXDATA RXDATA TXCLK RXCLK GSUB ENRX ENTX VDD5 GND5 REF SHDN RBIASRX GND6 VDD6 HPFOUT HPFOUT FUNCTION Active-High AGC Carrier-Select Enable. Drive AGCCS high to initiate the internal AGC adaptation timer. Host SPI Serial-Clock Input Host SPI Serial-Data Input Active-Low Host SPI Chip-Select Input Host SPI Serial-Data Output Analog Power-Supply 3. Bypass to GND3 with 100nF and 10FF capacitors in parallel located close to VDD3. Connect VDD inputs together. Analog Ground 3. Connect GND3 to the PCB ground. Transmitter Bias. Connect a 25kI resistor with 1% accuracy rating between RBIASTX and the PCB ground to set the bias current for the transmitter path. Analog Reference Clock Input Digital Ground. Connect GND4 to the PCB ground. Digital Power Supply. Bypass to GND4 with 100nF and 10FF capacitors in parallel located close to VDD4. Connect VDD inputs together. Transmit DAC Conversion Start. The beginning of the Tx conversion data frame is signaled by the falling edge of TXCONV. Receive ADC Conversion Start. Rx data is sampled by the ADC and conversion begins on the falling edge of RXCONV. Transmit Path Serial-Data Input. Data is latched on the falling edge of the TXCLK. Receive Path Serial-Data Output. Data is clocked out on the falling edge of RXCLK. Transmit Path Serial Clock Receive Path Serial Clock Substrate Ground. Make low resistance and low inductance connection to the PCB ground. Active-Low Receive Enable. Drive ENRX low to enable the receiver. Drive ENRX high to disable the receiver. Active-Low Transmit Enable. Drive ENTX low to enable the transmitter. Drive ENTX high to disable the transmitter and place predriver outputs into three-state. Analog Power-Supply 5. Bypass to GND5 with 100nF and 10FF capacitors in parallel located close to VDD5. Connect VDD inputs together. Analog Ground 5. Connect GND5 to the PCB ground. ADC Reference Voltage Output. Internal 2.0V reference output. Bypass REF with parallel 100nF and 10FF capacitors to the ADC ground. Active-Low Shutdown Input. Drive SHDN low to place the MAX2991 into shutdown mode. Drive SHDN high for normal operation. Receive Bias. RBIASRX is the external resistor connection that sets the bias current for the receive path. Connect a 25kI resistor with 1% accuracy rating between RBIASRX and the PCB ground. Analog Ground 6. Connect GND6 to the PCB ground. Analog Power-Supply 6. Bypass to GND6 with parallel 100nF and 10FF capacitors located close to VDD6. Connect VDD inputs together. Highpass Filter Negative Output Highpass Filter Positive Output
MAX2991
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9
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Pin Description (continued)
PIN 43 44 45 46 47 NAME HPFIN HPFIN LPFOUT LPFOUT RST Highpass Filter Negative Input Highpass Filter Positive Input Lowpass Filter Negative Output Lowpass Filter Positive Output Active-Low Reset Input. Drive RST low to place the MAX2991 in reset mode. Leave Rx and Tx clocks in free-running mode during a reset. The minimum reset pulse width is 100ns. Connect RST to VDD for normal operation. FUNCTION
Functional Diagram
HPFOUT HPFOUT LPFOUT LPFOUT HPFIN HPFIN RXINP RXINN
VGA1 ADAPTATION 2
LPF
VGA2
ADC AFE INTERFACE
RECEIVER PATH
ADAPTATION 1
TXOUTP TXOUTN
PREDRIVER
LPF
DAC
ENTX ENRX RXCLK TXCLK RXDATA TXDATA RXCONV TXCONV
PROCESS TUNING
MAX2991
CONTROL REGISTERS
AGCCS
SCLK SDIN
CS SDOUT
AGCFRZ
10
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Detailed Description
The MAX2991 power-line AFE integrated circuit is a state-of-the-art CMOS device that delivers high performance and low cost. This highly integrated design combines an ADC, DAC, signal conditioning, and predriver as shown in the Functional Diagram. The MAX2991 meets all frequency band requirements of the various popular power-line standards such as FCC, ARIB, and CENELEC. The MAX2991 along with the MAX2990 PLC baseband modem deliver the most cost-effective data communication solution over power-line networks in the market. The advanced design of the MAX2991 allows operation without external controls, enabling simplified connection to a variety of third-party power-line digital PHY devices. The MAX2991 includes various control signals to achieve additional power reduction. The receiver channel consists of a low-noise variablegain amplifier (VGA1) followed by a lowpass filter (LPF), a highpass filter (HPF), and another variable-gain amplifier (VGA2) circuit. An ADC samples the VGA2 output. An AFE interface provides data communication to the digital PHY device. The variable-gain low-noise amplifier reduces the receiver channel input-referred noise by providing additional signal gain to the AFE input. The filter blocks remove any out-of-band noise, provide anti-aliasing, and select a proper AFE bandwidth. Using the adaptation blocks, the VGAs scale the received signal to maintain the optimum signal level at the ADC input. The 10-bit ADC samples the analog signal and converts it to a 10-bit digital stream with a maximum 1.2Msps sampling rate. The transmit channel consists of a 10-bit DAC, an imagereject lowpass filter, and a programmable-gain predriver. The DAC receives the data stream from the digital PHY device through the AFE interface. The 10-bit DAC provides a complementary function to the receive channel with a maximum 1.2Msps sampling rate. The DAC converts the 10-bit digital stream to an analog voltage. The lowpass filter removes spurs and harmonics adjacent to the desired passband to reduce any out-of-band transmitted frequencies and energy from the DAC output. The lowpass filter ensures that the transmitted signal meets bandwidth requirements specified by the different wideband and narrowband standards. The predriver controls the output level of the lowpass filter connected to an external line driver, which, in turn, connects to the power-line medium. The output level is adjustable by the predriver gain control that provides up to 6dB gain and 10dB attenuation. The MAX2991 features two separate serial interfaces: host SPI interface and AFE interface. The host SPI interface provides direct access to the MAX2991 configuration registers, while the AFE interface allows data communication with the PLC baseband modem (MAX2990) and also provides indirect access to the MAX2991 configuration registers.
MAX2991
Serial Interface
Receive Channel
Host SPI Interface The MAX2991 host SPI interface provides access to the configuration registers using CS, SCLK, SDIN, and SDOUT. A host SPI frame consists of a 7-bit register address, a read/write bit, and 16 bits of data. Data is driven on the rising edge of SCLK and sampled on the falling edge of SCLK. Figure 3 shows a valid host SPI communication protocol. AFE Interface The AFE interface allows the MAX2991 to communicate with the PLC baseband modem (MAX2990) through a transmit channel (TXCLK, TXDATA, TXCONV) and a receive channel (RXCLK, RXDATA, RXCONV), and provides indirect access to the MAX2991 configuration registers. See the Interfacing to the MAX2990 Baseband section for connection details. AFE Interface Transmit Enable (ENTX) ENTX enables the transmitter of the MAX2991 AFE circuit. A logic-high on ENTX powers down the MAX2991 transmitter. AFE Interface Receiver Enable (ENRX) ENRX enables the receiver on the MAX2991. A logichigh on ENRX powers down the MAX2991 receiver. AFE Interface Tx Clock (TXCLK) The TXCLK signal provides the clock to the MAX2991 AFE transmitter. Apply a 19.2MHz clock at TXCLK to achieve 1.2Msps data rate. AFE Interface Rx Clock (RXCLK) The RXCLK signal provides the clock to the MAX2991 AFE receiver. Apply a 19.2MHz clock at RXCLK to achieve 1.2Msps data rate.
Transmit Channel
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11
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
AGC Control Signals (AGCCS) The AGCCS signal controls the AGC circuit of the receive path in the MAX2991. A logic-low on AGCCS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the digital PHY raises AGCCS to high. While AGCCS is high, the AGC continues to adapt for an additional programmable delay, then the AGC locks the currently adapted level on the incoming signal. The digital PHY holds AGCCS high while receiving a transmission and then lowers AGCCS for continuous adaptation for maximum sensitivity of other incoming signals. AGC Freeze Mode (AGCFRZ) Use the AGCFRZ signal to instantly lock the VGA1 and VGA2 gains. Reset Input (RST) The RST signal provides reset control for the MAX2991. Drive RST low to place the MAX2991 in reset mode. Leave Rx and Tx clocks in free-running mode during a reset. The minimum reset pulse width is 100ns. Power-Down Modes The MAX2991 features four power-down modes: 1) Global Power-Down Mode: Enter this mode either by setting the SHDN input to logic-low or by setting the CHIPENB bit (bit 0 of RXCONF register) to 1. All clocks to the digital circuitry are gated. Set SHDN to Table 1 shows the MAX2991 register map.
MAX2991
logic-high or set the CHIPENB bit to logic-low to exit this mode. The Tx and Rx blocks are fully operational approximately 20Fs after coming out of global powerdown mode. 2) Idle Mode: Enter this mode by setting the IDLEEN bit to 1. In this mode, all blocks are powered down except for the AFE interface and the bias blocks. RXCLK and TXCLK are not gated. Set IDLEEN to 0 to exit this mode. The Tx and Rx blocks are fully operational approximately 20Fs after coming out of global power-down mode. 3) Transmit Power-Down Mode: Enter this mode by setting ENTX to logic-high while the ENTXBEN bit (bit 0 of register TXCONF) is set to 1. In this mode, the transmit predriver, lowpass filter, and the DAC are powered down. Set ENTX to logic-low to exit this mode. The Tx block is fully operational approximately 15Fs after coming out of global power-down mode. 4) Receive Power-Down Mode: Enter this mode by setting ENRX to logic-high while the ENRXBEN bit (bit 2 of register RXCONF) is set to 1. In this mode, the receiver VGA1, VGA2, lowpass filter, lowpass filter buffer, highpass filter, and the ADC are powered down. Set ENRX to logic-low to exit this mode. The Rx block is fully operational approximately 20Fs after coming out of global power-down mode.
Register Map
Table 1. Register Map
REGISTER RXCONF TXCONF -- PTUN1 PTUN2 -- -- AGC3 -- -- -- -- IIR0CONF IIR0B0 IIR0B1 12 WIDTH <13:0> <15:0> <13:0> <5:0> <13:0> <11:0> <11:0> <13:0> <13:0> <14:0> <15:0> <9:0> <8:0> <15:0> <15:0> ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E FUNCTION Rx configuration and control Tx configuration and control Reserved Process tuner configuration and control Process tuner manual override Reserved Reserved AGC configuration and control Reserved Reserved Reserved Reserved IIR filter configuration of first biquad IIR filter B0 coefficient of first biquad IIR filter B1 coefficient of first biquad DEFAULT 0x0004 0x282B 0x000 0x13 0x0000 0xE8E 0xE00 0x0320 0x0000 0x0200 0x0000 0x000 0x0ED 0x0825C 0xF43A
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Table 1. Register Map (continued)
REGISTER IIR0B2 IIR0A1 IIR0A2 IIR1CONF IIR1B0 IIR1B1 IIR1B2 IIR1A1 IIR1A2 DPTUN1 DPTUN2 FRZTIME WIDTH <15:0> <15:0> <15:0> <8:0> <15:0> <15:0> <15:0> <15:0> <15:0> <11:0> <11:0> <11:0> ADDRESS 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A FUNCTION IIR filter B2 coefficient of first biquad IIR filter A1 coefficient of first biquad IIR filter A2 coefficient of first biquad IIR filter configuration of second biquad IIR filter B0 coefficient of second biquad IIR filter B1 coefficient of second biquad IIR filter B2 coefficient of second biquad IIR filter A1 coefficient of second biquad IIR filter A2 coefficient of second biquad Process tuner digital settings Process tuner digital settings Freeze timer control DEFAULT 0x0825 0xCEFF 0x1613 0x0ED 0x1DAA 0xCBEF 0x1DAA 0xC7F6 0x1F4D 0x3F4 0x006 0x5C6
MAX2991
Address 0x00: Rx Configuration (RXCONF<13:0>), Default: 0x0004
BIT NAME CHIPENB IDLEEN ENRXBEN BYPRXHPF LOCATION (0 = LSB) 0 1 2 3 DEFAULT 0 0 1 0 FUNCTION Active-high global power-down bit. Set to 1 to enable global power-down mode. Active-high idle mode-enable bit. Set to 1 to enable idle mode. Active-high receiver path shutdown bit. Set to 1 to power down the receive path. The receiver is normally shut down in transmit mode. Active-high receiver HPF bypass bit. Set to 1 to allow receive HPF bypass. Receiver lowpass filter mode selection. 00: CENELEC A 01: Narrowband 10: FCC and ARIB 11: Full band Reserved Set to 1 to enable the read configuration mode of the AFE interface. This bit defines the active RXCLK edge used to sample the RXCONV input (0 = rising edge, 1 = falling edge).
RXLPFBW<1:0>
5, 4
00
-- RDCONFMDEN RXCONV_EDGE
11-6 12 13
000000 0 0
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13
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Address 0x01: Tx Configuration (TXCONF<15:0>), Default: 0x282B
BIT NAME ENTXBEN LOCATION (0 = LSB) 0 DEFAULT 1 FUNCTION Active high. Set to 1 to enable the power down of the transmit path. The transmit path is normally powered down in receive mode. Predriver gain settings: 0000: Gain = -10dB 0001: Gain = -8dB 0010: Gain = -6dB 0011: Gain = -4dB 0100: Gain = -2dB 0101: Gain = 0dB 0110: Gain = 2dB 0111: Gain = 4dB 1000: Gain = 6dB Reserved Transmit lowpass filter mode selection. 00: CENELEC A 01: Narrowband 10: FCC and ARIB 11: Full band Reserved Active high. Enables the dynamic control of the predriver gain set by the command bits C<3:0> in the Tx transmit frame. Defines the active TXCLK edge used to sample the TXCONV input (0 = falling edge, 1 = rising edge). Defines the position of the first TXDATA bit relative to the TXCONV active edge (0 = first TXDATA bit is coincident with the first active TXCONV cycle, 1 = first TXDATA bit is one cycle after the first active TXCONV cycle).
PREDRVGAIN <3:0>
4-1
0101
--
5
1
TXLPFBW<1:0>
7, 6
00
-- PREDRDYN TXCONV_EDGE
12-8 13 14
01000 1 0
TXDATA_DLY
15
0
Address 0x03: Process Tuner Configuration (PTUN1<5:0>), Default: 0x13
BIT NAME -- LOCATION (0 = LSB) 1, 0 DEFAULT 11 Reserved Active high. Enables direct programming of process tuner settings from SPI registers. Set to 0 to enable systematic adjustment of the process tuner code by PTUNERXADJ and PTUNETXADJ independently for Rx and Tx filters, respectively. Process tuner clock selection: 00 or 01: REFCLK 10: RXCLK 11: TXCLK Reserved FUNCTION
OVERWRT_NDGE
2
0
PTCLKMUX
4, 3
10
--
5
0
14
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Address 0x04: Process Tuner Adjust (PTUN2<13:0>), Default: 0x0000
BIT NAME PTUNERXADJ <6:0> PTUNETXADJ <6:0> LOCATION (0 = LSB) 6-0 13-7 DEFAULT 0000000 0000000 FUNCTION Adjust bits to set Rx filter process code slightly different from process tuner output code. MSB is used as sign bit. Adjust bits to set Tx filter process code slightly different from process tuner output code. MSB is used as sign bit.
MAX2991
Address 0x07: AGC Control 3 (AGC3<13:0>), Default: 0x0320
BIT NAME -- EN30U -- LOCATION (0 = LSB) 10-0 11 13, 12 DEFAULT 01100100000 0 00 Reserved Enables the programmable freeze signal delay set by FRZTIMEOFF2. When disabled, the default delay is 400 ADC clock cycles (1 = enable). Reserved FUNCTION
Address 0x0C: IIR0 1st Biquad Configuration (IIR0CONF<8:0>), Default: 0x0ED
BIT NAME IIR0_CONF -- LOCATION (0 = LSB) 0 8-1 DEFAULT 1 01110110 FUNCTION Set to 1 to enable the first biquad of the IIR filter. Set to 0 to bypass the first biquad. Reserved
Address 0x0D: IIR0 B0 Coefficient (IIR0B0<15:0>), Default: 0x0825C
BIT NAME IIR0_B0<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 2085 FUNCTION B0 coefficient of the first biquad of the IIR filter.
Address 0x0E: IIR0 B1 Coefficient (IIR0B1<15:0>), Default: 0xF43A
BIT NAME IIR0_B1<15:0> LOCATION (0 = LSB) 15-0 DEFAULT -3014 FUNCTION B1 coefficient of the first biquad of the IIR filter.
Address 0x0F: IIR0 B2 Coefficient (IIR0B2<15:0>), Default: 0x0825
BIT NAME IIR0_B2<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 2085 FUNCTION B2 coefficient of the first biquad of the IIR filter.
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15
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Address 0x10: IIR0 A1 Coefficient (IIR0A1<15:0>), Default: 0xCEFF
BIT NAME IIR0_A1<15:0> LOCATION (0 = LSB) 15-0 DEFAULT -12545 FUNCTION A1 coefficient of the first biquad of the IIR filter.
Address 0x11: IIR0 A2 Coefficient (IIR0A2<15:0>), Default: 0x1613
BIT NAME IIR0_A2<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 5651 FUNCTION A2 coefficient of the first biquad of the IIR filter.
Address 0x12: IIR1 2nd Biquad Configuration (IIR1CONF<8:0>), Default: 0x0ED
BIT NAME IIR1_CONF -- LOCATION (0 = LSB) 0 8-1 DEFAULT 1 01110110 FUNCTION Set to 1 to enable the second biquad of the IIR filter. Set to 0 to bypass the second biquad. Reserved
Address 0x13: IIR1 B0 Coefficient (IIR1B0<15:0>), Default: 0x1DAA
BIT NAME IIR1_B0<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 7594 FUNCTION B0 coefficient of the second biquad of the IIR filter.
Address 0x14: IIR1 B1 Coefficient (IIR1B1<15:0>), Default: 0xCBEF
BIT NAME IIR1_B1<15:0> LOCATION (0 = LSB) 15-0 DEFAULT -13329 FUNCTION B1 coefficient of the second biquad of the IIR filter.
Address 0x15: IIR1 B2 Coefficient (IIR1B2<15:0>), Default: 0x1DAA
BIT NAME IIR1_B2<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 7594 FUNCTION B2 coefficient of the second biquad of the IIR filter.
16
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Address 0x16: IIR1 A1 Coefficient (IIR1A1<15:0>), Default: 0xC7F6
BIT NAME IIR1_A1<15:0> LOCATION (0 = LSB) 15-0 DEFAULT -14346 FUNCTION A1 coefficient of the second biquad of the IIR filter.
MAX2991
Address 0x17: IIR1 A2 Coefficient (IIR1A2<15:0>), Default: 0x1F4D
BIT NAME IIR1_A2<15:0> LOCATION (0 = LSB) 15-0 DEFAULT 8013 FUNCTION A2 coefficient of the second biquad of the IIR filter.
Address 0x18: Process Tuner Digital Settings 1 (DPTUN1<11:0>), Default: 0x3F4
BIT NAME PTUNEUPLIMIT <11:0> LOCATION (0 = LSB) 11-0 DEFAULT FUNCTION Used to set process tune ramp down limit of clock cycles. PTUNEUPLIMIT along with PTUNEHYS set up the RC time constant range for the filters.
001111110100
Address 0x19: Process Tuner Digital Settings 2 (DPTUN2<11:0>), Default: 0x006
BIT NAME PTUNEHYS <11:0> LOCATION (0 = LSB) 11-0 DEFAULT FUNCTION Used to set process tune ramp down hysteresis range of clock cycles. PTUNEHYS along with PTUNEUPLIMIT set up the RC time constant range for the filters.
000000000110
Address 0x1A: AGC Freeze Timer (FRZTIME<11:0>), Default: 0x5C6
BIT NAME -- FRZTIMEOFF2 <5:0> LOCATION (0 = LSB) 5-0 11-6 DEFAULT 00110 10111 Reserved Sets AGC gain freeze time offset. Internal timer is 12 bits and lower 6-bit word is 0x1C (1500 ADC clock-cycle delay). EN30U (bit 11) should be set to use this mode. FUNCTION
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17
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Table 2. Process Tuner Configuration, PTUN1<5:0>, Address: 0x03, Default: 0x13
BIT NAME LOCATION DEFAULT FUNCTION Process tuner clock selection: 00 or 01: REFCLK 10: RXCLK 11: TXCLK
PTCLKMUX
4, 3
10
Table 3. Summary of Calculations Needed when Process Tuner Clock Rate is Changed
CLOCK RATE (MHz) 19.2 9.6 COUNTER LIMIT (52.7 x FREQUENCY) 1011.84 505.92 DPTUN1 0x3F4 0x1F9 HYSTERESIS RANGE (0.3125 x FREQUENCY) 6.0 3.0 DPTUN2 0x006 0x003
ENTX ENRX AGCCS RST TXCONV
P3.7 P3.8 P2.2 P3.6 P3.0 P3.5 P3.2 P3.3 P3.4 P3.1
MAX2991
AFE
RXCONV TXCLK RXCLK RXDATA TXDATA
MAX2990
BASEBAND
Figure 8. Interfacing with the MAX2990
Applications Information
The MAX2991 uses a reference clock to tune Rx and Tx filters. In default mode, Rx clock is used as the reference source for the process tuner. Process tuner clock can be set to any one of RXCLK, TXCLK, or REFCLK clock sources. PTUN1<4:3> sets the clock source.
Programming the Process Tuner Reference Clock
Table 3 summarizes the calculation for the default clock rate and another one. The ADC sampling rate is the clock rate divided by 16. The sampling rate is adjustable from 200ksps to 1.2ksps in 200ksps steps. The interface to the MAX2991 AFE device uses a bidirectional bus to transfer the digital data from the ADC and to the DAC. Handshaking lines help accomplish the data transfer as well as operation of the AFE. Figure 8 shows the interface between the MAX2991 and the MAX2990.
Interfacing to the MAX2990 Baseband
For clock rates other than 19.2MHz, update the DPTUN1 and DPTUN2 registers accordingly.
Programming the MAX2991 for Different Sampling Rates
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
The MAX2990's single write configuration mode allows sending an arbitrary 16-bit SPI frame to the MAX2991's AFE interface. This mode allows configuring the internal registers without using the host SPI.
Indirect Write and Read Configuration Mode
to allow reading and writing from/to its host SPI register space. The MAX2990 does not support the read configuration mode of operation, as it cannot set the R/W bit to the required state. All configuration mode accesses are treated as writes. Set RDCONFMDEN in the RXCONF register to logic-high to enable the read configuration mode. Ensure RXCLK is active during read configuration mode read accesses. The AFE Rx interface must be inactive during read configuration mode transfers.
MAX2991
The SPI frame has 4 command bits labeled C3, C2, C1, and C0. These bits are normally set to 0 when transferring data frames to the DAC. The MAX2991 also responds to other command codes, shown in Table 4,
Table 4. Configuration Bits
COMMAND BITS C3 0 1 1 C2 0 0 0 C1 0 0 1 C0 0 0 0 DESCRIPTION Normal TXDATA packet (C2, C1, and C0 can be used to set the predriver gain dynamically). Set the Indirect Address register and R/W bit. Read most significant 8 bits when R/W = 1. Trigger the indirect register read when R/W = 1. Write most significant 8 bits to Indirect Data register when R/W = 0. Read least significant 8 bits when R/W = 1. Trigger the indirect register read when R/W = 1. Write least significant 8 bits to Indirect Data register and trigger register write when R/W = 0. Post increment the Indirect Address in both cases. Reserved Reserved
1
0
0
1
1 1
0 1
1 X
1 X
TXCONV
TXCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
TXDATA
D0
C3
C2
C1
C0
X
X
X
X
X
X
X
X
X
X
X
X
RXCLK RXCONV RXDATA 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 9. Communication Protocol for Indirect Read Access
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19
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
During normal data transmission bit C3 (= 0) is used to indicate that a normal data packet is received and bits C2, C1, and C0 are used to change the predriver gain dynamically. In this case, C<2:0> maps onto predriver gain-control bits as shown in Table 5. This mode of operation is enabled if the bit PREDRDYN in the Tx configuration register is set to 1.
Dynamic Predriver Gain Programming During the Data Transmission
External Highpass Filter
HPFOUT C C LPFOUT R1 C HPFIN R2
R1 LPFOUT C C C R2 HPFOUT HPFIN
Figure 10. External Highpass Filter Circuitry
Table 5. Predriver Dynamic Gain Programming
C3 0 0 0 0 0 0 0 0 C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 PREDRIVER GAIN (dB) Unchanged -8 -6 -4 0 2 4 6 PREDRVGAIN <3> Unchanged 0 0 0 0 0 0 1 PREDRVGAIN <2> Unchanged 0 0 0 1 1 1 0 PREDRVGAIN <1> Unchanged 0 1 1 0 1 1 0 PREDRVGAIN <0> Unchanged 1 0 1 1 0 1 0
Table 6. External Highpass Filter Components for Different 3dB Frequencies
3dB CORNER (kHz) 9 32 90 125 140 C SELECTION (pF) 1000 270 100 68 68 R1 (kI) 1% TOLERANCE 8.25 8.66 8.25 8.66 7.87 R2 (kI) 1% TOLERANCE 37.4 38.3 37.4 39.2 35.7
20
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Power-Line Communications (PLC) Integrated Analog Front-End Transceiver
Table 7. Rx and Tx Filter Adjustment for Different 3dB Frequencies
Rx 3dB FREQUENCY (kHz) 130 140 146 155 Tx 3dB FREQUENCY (kHz) 125 134 140 148 OFFSET -15 0 9 20 RXADJ/ TXADJ 79 0 9 20 TXADJ 79 0 9 20 PTUN2 0x27CF 0x0000 0x0489 0x0A14
MAX2991
Table 8. IIR Coefficients for CENELEC A Band (MAX2991 Default Mode)
COEFFICIENT NAME IIR0B0 IIR0B1 IIR0B2 IIR0A1 IIR0A2 IIR1B0 IIR1B1 IIR1B2 IIR1A1 IIR1A2 FLOATING POINT VALUE 0.25454609117803 -0.36787775183970 0.25454609117803 -1.53137687683985 0.68982207389294 0.92695273947877 -1.62702269373124 0.92695273947877 -1.75120880788804 0.97809159311434 Q13 FORMAT VALUE 2085 -3014 2085 -12545 5651 7594 -13329 7594 -14346 8013 REGISTER VALUE 0x0825 0xF43A 0x0825 0xCEFF 0x1613 0x1DAA 0xCBEF 0x1DAA 0xC7F6 0x1F4D
To program the Rx and Tx filters for different CENELEC modes, program the filters in narrowband mode and adjust the cutoff frequency by providing a positive or negative offset. Typical PTUN2 register values for Rx and Tx adjustments are given in Table 7. The MAX2991 defaults to the CENELEC A mode.
Programming Rx and Tx Filters for Different CENELEC Standards
H(z) =
B 0 + B1z -1 + B 2z -2 1 + A 1z -1 + A 2z -2
The coefficients are in Q13 format. For stable/minimum phase Butterworth IIR filter, the coefficients are between -2 and +2. Coefficients in the range of -4 to +4 are possible by using a 16-bit word. The example in Table 8 shows the design steps used to generate the coefficients for the filter in CENELEC A band. For this design, it is desired to get a large attenuation with a sharp corner at around 95kHz. A 4th-order elliptic filter is used with the 91.9kHz passband frequency. The passband ripple is 1dB and the stopband attenuation is 12dB. For a 1.2Msps sampling frequency, the coefficients are shown in Table 8. Note that Q13 representation is found by multiplying the floating values by 8192 (213) and rounding the result to an integer.
IIR filters are used in the MAX2991 transmit path to achieve the desired attenuation at corner and out-ofband frequencies that comply with regulatory spectral mask. The filters are implemented as two cascaded second-order sections (SOS). Each filter implements a second-order transfer function:
Programming the Integrated IIR Filters for Different Bands
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21
Power-Line Communications (PLC) Integrated Analog Front-End Transceiver MAX2991
Table 9. Purposed IIR Coefficients for FCC Band
COEFFICIENT NAME IIR0B0 IIR0B1 IIR0B2 IIR0A1 IIR0A2 IIR1B0 IIR1B1 IIR1B2 IIR1A1 IIR1A2 FLOATING POINT VALUE 0.67910441874341 1.27553272646766 0.67910441874341 1.24725754685134 0.54254301592170 0.97169123170169 1.62951057639590 0.97169123170169 1.61392655185432 0.95896648794496 Q13 FORMAT VALUE 5563 10449 5563 10218 4445 7960 13349 7960 13221 7856 REGISTER VALUE 0x15BB 0x28D1 0x15BB 0x27EA 0x115D 0x1F18 0x3425 0x1F18 0x33A5 0x1EB0
The second example shows the design steps used to generate the IIR coefficients for the filter in the FCC band. For this design, a 4th-order elliptic filter is used with the 483kHz passband frequency. The passband ripple is 0.5dB and the stopband attenuation is 12dB. For a 1.2MHz sampling frequency, the coefficients are shown in Table 9. The transmitter lowpass filter band is set by TXCONF<7:6> bits. The aforementioned floating point coefficients were generated using MATLABM "fdatool" GUI.
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 LQFP PACKAGE CODE C48+2 DOCUMENT NO. 21-0054
MATLAB is a registered trademark of The MathWorks, Inc.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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