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LOW SKEW, 1-TO-8, CRYSTAL OSCILLATOR/ LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ICS8538-31 Features
* * * * * * * * * * * *
Eight differential 3.3V LVPECL outputs Selectable LVCMOS/LVTTL clock or crystal inputs CLK can accept the following input levels: LVCMOS, LVTTL Maximum output frequency: 266MHz Crystal frequency range: 14MHz - 40MHz Output skew: 50ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 2.2ns (maximum) 3.3V operating supply mode 0C to 70C ambient operating temperature Industrial temperature information available upon request Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS8538-31 is a low skew, high performance 1-to-8 Crystal Oscillator/LVCMOS-to-3.3V LVPECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS8538-31 has selectable single ended clock or crystal inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8538-31 ideal for those applications demanding well defined performance and repeatability.
Block Diagram
CLK_EN Pullup D Q LE CLK Pulldown XTAL_IN 0 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Pin Assignment
CLK CLK_SEL CLK_EN VEE nQ7 Q7 VCCO nQ6 Q6 nQ5 Q5 VEE nQ4 Q4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC XTAL_IN XTAL_OUT VEE Q0 nQ0 VCCO Q1 nQ1 Q2 nQ2 VCCO Q3 nQ3
OSC
XTAL_OUT CLK_SEL Pulldown
1
28-Lead TSSOP, 173MIL
4.4mm x 9.7mm x 0.925mm package body
G Package Top View
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Table 1. Pin Descriptions
Number 1 2 3 4, 12, 25 5, 6 7, 17, 22 8, 9 10, 11 13, 14 15, 16 18, 19 20, 21 23, 24 26, 27 28 Name CLK CLK_SEL CLK_EN VEE nQ7, Q7 VCCO nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 XTAL_OUT XTAL_IN VCC Input Input Input Power Output Power Output Output Output Output Output Output Output Input Power Type Pulldown Pullup Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Positive supply pin. Description Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Function Tables
Table 3A. Control Input Function Table
Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Selected Source CLK XTAL_IN, XTAL_OUT CLK XTAL_IN, XTAL_OUT Q0:Q7 Disabled; Low Disabled; Low Enabled Enabled Outputs nQ0:nQ7 Disabled; High Disabled; High Enabled Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Disabled
Enabled
CLK CLK_EN
nQ0:nQ7 Q0:Q7
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs CLK 0 1 Q0:Q7 LOW HIGH Outputs nQ0:nQ7 HIGH LOW
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC+ 0.5V 50mA 100mA 49.8C/W (0 lfpm) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C to 70C
Symbol VCC VCCO IEE ICCO Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 110 50 Units V V mA mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C to 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK, CLK_SEL CLK_EN CLK, CLK_SEL CLK_EN VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C to 70C
Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO- 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units A A V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 14 Test Conditions Minimum Typical Fundamental 40 50 7 1 MHz Maximum Units
pF mW
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C to 70C
Parameter Symbol fMAX tPD tsk(o) tsk(pp) tR / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Part-to-Part Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle 20% to 80% 200 45 Test Conditions Minimum Typical Maximum 266 2.2 50 250 700 55 Units MHz ns ps ps ps %
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VCC/2 input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Parameter Measurement Information
2V
Par t 1
VCC, VCCO
Qx
SCOPE
nQx Qx nQy
Par t 2
LVPECL
nQx VEE
Qy
tsk(pp)
-1.3V0.165V
3.3/3.3V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
nQx Qx CLK nQ0:nQ7 Q0:Q7
nQy Qy
tsk(o)
tPD
Output Skew
Propagation Delay
nQ0:nQ7 Q0:Q7
80% Clock Outputs
80% VSW I N G
t PW
t
PERIOD
20% tR tF
20% odc =
t PW t PERIOD
x 100%
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
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Application Information
Crystal Input Interface
The ICS8538-31 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VCC
VCC
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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Recommendations for Unused Input and Output Pins Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
CLK Input
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
RTT =
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8538-31. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8538-31 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.15mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 30mW = 240mW
Total Power_MAX (3.3V, with all outputs switching) = 381.15mW + 240mW = 621.15mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.8C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.621W * 49.8C/W = 100.9C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 7. Thermal Resistance JA for 28 Lead TSSOP, Forced Convection
JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 82.9C/W 49.8C/W 200 68.7C/W 43.9C/W 500 60.5C/W 41.2C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCCO - 2V.
* * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 8. JA vs. Air Flow Table for a 282 Lead TSSOP
JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 82.9C/W 49.8C/W 200 68.7C/W 43.9C/W 500 60.5C/W 41.2C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8430-62 is: 4258
Package Outline and Package Dimension
Package Outline - G Suffix for 28 Lead TSSOP Table 9. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 9.80 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 10. Ordering Information
Part/Order Number ICS8538BG-31 ICS8538BG-31T ICS8538BG-31LF ICS8538BG-31LFT Marking ICS8538BG-31 ICS8538BG-31 ICS8538BG-31LF ICS8538BG-31LF Package 28 Lead TSSOP 28 Lead TSSOP "Lead-Free" 28 Lead TSSOP "Lead-Free" 28 Lead TSSOP Shipping Packaging Tube 1000 Tape & Reel Tube 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table T10 Page 13 5 B T6 9 Description of Change Ordering Information table - added Lead-Free marking. AC Characteristics Table - changed Output Rise/Fall parameters from 500ps min. to 200ps min., and 850ps max. to 700ps max. Power Considerations - updated Junction Temperature equation with worst case thermal resistance of 0 lfpm at 49.8C/W. Date 1/18/08
2/5/08
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