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PAS6311LT Specification
PAS6311LT CMOS VGA DIGITAL IMAGE SESNSOR
General Description
The PAS6311LT is a highly integrated CMOS active-pixel image sensor that has a VGA resolution of 648H x 488V. It embedded the new FinePixelTM sensor technology to perform the excellent image quality. The PAS6311LT outputs 10-bit RGB raw data through a parallel data bus. It is available in 24-pin CSP. The PAS6311LT can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register set, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control.
Features
VGA(640x480) resolution, ~1/6" Lens. Bayer RGB color filter array. 10-bits parallel RGB raw data output. On-Chip 10-bits pipeline A/D converter. On-Chip programmable gain amplifier 3-bits front gain amplifier. 7-bits color gain amplifier. 7-bits global gain amplifier. Digital gain stage. Continuous variable frame time. Continuous variable exposure time. I2CTM interface. Flash light timing 1.8V~3.3V I/O voltage <15mA power dissipation ( 30fps / 2.5v ). 10uA low power-down dissipation. Window-of-Interest (WOI). Sub-sampling. Defect compensation. Lens shading compensation. Companding Automatic background compensation Critical register table backward compatible with PAS6302 Ball to ball compatible with PAS6302CS
Key Specification Analog Supply voltage Resolution Array Diagonal Pixel Size Max. Frame Rate Max. System Clock Max. Pixel Clock Color Filter Exposure Time Scan Mode Sensitivity S/N Ratio Dark Current Chief Ray Angle Package Type Core I/O 1.8V 1.8V ~ 3.3V 640 ( H ) x 480 ( V ) 2.91mm ( ~1/6" Optic ) 3.6 m x 3.6 m 2.5V
~30 fps @ 0.3Mega Up to 48MHz Up to 12MHz RGB Bayer Pattern ~ Frame time to Line time Progressive 1.3V/(Lux*Sec) 41dB 12mV/sec at 6 22 ~ 25 degree 24-ball CSP
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PAS6311LT Specification
1. Pin Assignment
A1 PX0 B1 PX4 C1 PX3 D1 VSSD E1 RESET A2 PX1 B2 PX5 C2 PX2 D2 VDDD E2 SYSCLK D3 PXCLK E3 HSYNC A3 PX7 B3 PX6 A4 PX9 B4 PX8 C4 VSSA D4 VSYNC E4 SCL A5 VDDQ B5 VDDA C5 VDDAY D5 CSB E5 SDA
PAS6311LT
-- Top View --
Figure 1.1 Shows the PAS6311LT pin diagram Pin No. C4 B5 D5 C5 D2 D4 E3 D3 A5 E2 E1 D1 A4 B4 A3 B3 B2 B1 C1 C2 A2 A1 E4 E5 Name VSSA VDDA CSB VDDAY VDDD VSYNC HSYNC PXCLK VDDQ SYSCLK RESET VSSD PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0 SCL SDA Type GND PWR IN IN PWR OUT OUT OUT PWR IN IN GND OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN I/O Analog ground. Analog VDD, 2.5V. Power Down (chip power down if high ). Internal voltage reference. Digital core VDD, 1.8V. Vertical synchronization signal. Horizontal synchronization signal. Pixel clock output. I/O VDD, 1.8V ~ 3.3V. Master clock input. Resets all registers to default ( chip reset if high .) Digital ground. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. I2C clock. I2C data. Internal pull high resister is 10K . Description
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PAS6311LT Specification
2. Sensor Array Format & Output Timing
2.1. Physical Sensor Array Format
Figure 2.1 Physical Sensor Array Format
2.2. Output Timing
VGA mode ( 648 x 488 ) pixel readout: H_Start[9:0] = 0, LPF[13:0] = 508, V_Start[8:0] = 0, Nov_Size[7:0]= 136, H_Size[9:0] = 647, V_Size[8:0]= 487,
Figure 2.2 Inter-line timing
Figure 2.3 Inter-frame timing
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PAS6311LT Specification
3. Block Diagram & Function Description
3.1. Block Diagram
Row Decoder
Figure 3.1 Shows the PAS6311LT sensor block diagram The PAS6311LT is a 1/6" CMOS imaging sensor with 640 ( H ) x 480 ( V ) physical pixels. The active region of sensor array is 648 ( H ) x 488 ( V ). The sensor array is cover with Bayer pattern color filters and -lens. The first pixel location ( 0,0 ) is programmable in 2 direction ( X and Y ) and the default value is at the left-down side of sensor array. After a programmable exposure time, the image is sampled first with CDS ( Correlated Double Sampling ) block to improve S/N ration and reduce fixed pattern noise. Three analog gain stages are implemented before signal transferred by the 10-bits A/D converter. The front gain stage ( FG ) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage ( CG ) is used to balance the luminance response difference between B/G/R. The global gain stage ( GG ) is programmed to adapt the gain to the image luminance. The fine gained signal will be digitized by the on-chip 10-bits A/D converter. After the image data has been digitized, further alteration to the signal can be applied before the data is output.
3.2. Defect Compensation
The defect compensation block can detect the possible defective pixels and replace it with average output of like-colored pixels on either side of defective pixel. It's no limitation on the capability of defective number. This function is also enabled or disabled by user.
3.3. Companding Curves
The companding function is used to simulate the gamma curve and do non-linear transformation before outputting data. There are 8 curves selected by setting register Compand_Sel as shown in Figure 3.2 and this function is also enabled or disabled by user.
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PAS6311LT Specification
Figure 3.2 Companding curves program by Compand_EnH and Compand_Sel
3.4. Power Down Mode
The PAS6311LT can enter power-down mode by setting register "SW_PwrDn" or by enabling CSB pin. PAS6311LT supports two power-down modes : Software Power Down : Setting register "SW_PwrDn" = 0x01 could have power-down effect upon all the internal block except I2CTM. Hardware Power Down : Pulling CSB pin to high could have power-down effect upon the whole chip. The chip will go into standby state.
3.5. Reset Mode
The PAS6311LT can be reset by setting register "SW_Reset" or by enabling Reset pin. PAS6311LT supports two reset modes : Software Reset : Set register "SW_Reset" = 0x01 to reset all the I2CTM registers. It resets the register value only and non-whole chip. HardwareReset : Pull Reset pin to high to reset the whole chip.
3.6. Automatic Background Compensation (ABC)
By setting register "ABC_en" = 0x01, PAS6311LT can do the black-level calibration automatically. The purpose of this function supports user to set Dac value by hardware self-calculation to make dark like real dark.
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PAS6311LT Specification
3.7. Window-of-Interest ( WOI )
Users could be allowed to define window size as well as window location in PAS6311LT. The location of window can be set anywhere in the pixel array. Window size and window location is defined by register "H_Start", "V_Start", "V_Size" and "H_Size". "H_Start" and "V_Satrt" define the starting column and starting row of the window. "H_Size" and "V_Size" define the width and depth of the window.
Figure 3.3
3.7.1. Output timing of WOI
Hardware windowing QVGA ( 320x240 ) pixels readout : H_Start[9:0] = 0, Nov_Size [7:0] = 136, V_Start[8:0] = 0, H_Size[9:0] = 319, V_Size[8:0]= 239,
Figure 3.4 Inter-line timing of W.O.I
Figure 3.5 Inter-frame timing of W.O.I
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PAS6311LT Specification
3.8. Sub-Sampling
PAS6311LT can be programmed to output image in QVGA and QQVGA size. For QVGA sub-sampling mode, both vertical and horizontal pixels are divided by 2; For QQVGA sub-sampling mode, both vertical and horizontal pixels are divided by 4. By programming Skip_Analog and Skip_Digital, the maximum sub-sampling rate is 1/64 ( Skip_Analog + Skip_Digital ).
3.8.1. Skip_Analog
Analog sub-sampling to (1/2) * VGA size readout : H_Start[9:0] = 0, Nov_Size[7:0] = 136, V_Start[8:0] = 0, H_Size[9:0] = 647, V_Size[8:0]= 487,
Skip_Analog = 1 ( sub-sampling 1/2 )
Figure 3.6
Valid pixels = ( H_Size + 1 ) / Skip_Analog = ( 647 + 1 ) / 2 = 324 Valid lines = ( V_Siez + 1 ) / Skip_Analog = ( 487 + 1 ) / 2 = 244
Figure 3.7 Inter-line timing of Skip_Analog = 1
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PAS6311LT Specification
Figure 3.8 Inter-frame timing of Skip_Analog = 1
3.8.2. Skip_Digital
Digital sub-sampling to (1/2) * VGA size readout : H_Start[9:0] = 0, V_Start[8:0] = 0, H_Size[9:0] = 647, V_Size[8:0]= 487,
Nov_Size [7:0] = 136, Skip_Digital = 1
Inter-line timing
Figure 3.9 Inter-line timing of Skip_Digital = 1
Figure 3.10 Inter-frame timing of Skip_Digital = 1
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PAS6311LT Specification
4. I2CTM Bus
PAS6311LT supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is "1000000" and supports receiving / transmitting speed as maximum 400KHz.
4.1. I2C Bus Overview
Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pulled high by external pull-up resistors. Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). Start and stop condition : A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Figure 4.1. Valid data : The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 4.2. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle.
Figure 4.1 Start and Stop conditions
Figure 4.2 Valid Data
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PAS6311LT Specification
4.2. Data Transfer Format 4.2.1. Master transmits data to salve ( write cycle )
S : Start. A : Acknowledge by salve. P : Stop. RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 - Read cycle, RW = 0 - Write cycle. SUBADDRESS : The address values of PAS6311LT internal control registers. ( Please refer to PAS6311LT register description )
During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6311LT ) issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the PAS6311LT acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6311LT control register ( address was assigned by 2nd byte ). After PAS6311LT issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6311LT sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS6311LT can be programming via this way.
4.2.2. Slave transmits data to master ( read cycle )
The sub-address was taken from previous write cycle. The sub-address is automatically increment after each byte read. Am : Acknowledge by master. Note there is no acknowledgment from master after last byte read.
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PAS6311LT Specification
During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS6311LT. The 8 bits data was read from PAS6311LT internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS6311LT place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS6311LT ) must releases SDA line to master to generate STOP condition.
4.3. I2CTM Bus Timing
4.4. I2CTM Bus Timing Specification
Parameter SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Low period of the SCL clock. High period of the SCL clock. Set-up time for a repeated START condition. Symbol fscl tHD:STA tLOW tHIGH tSU;STA Standard Mode Min. 10 4.0 4.7 0.75 4.7 Max 400 KHz s s s s 11 Unit
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PAS6311LT Specification
Data hold time. For I2C-bus device. Data set-up time. Rise time of both SDA and SCL signals. Fall time of both SDA and SCL signals. Set-up time for STOP condition. Bus free time between a STOP and START. Capacitive load for each bus line. Noise margin at LOW level for each connected device. ( Including hysteresis ) Noise margin at HIGH level for each connected device. ( including hysteresis ) Note : It depends on the "high" period time of SCL. tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH 0 250 30 30 4.0 4.7 1
0.1 VDD
3.45 N.D. N.D. 15 -
s ns ns ( notel ) ns ( notel ) s s pF V V
0.2 VDD
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PAS6311LT Specification
5. Specifications
Ambient Storage Temperature VDDD Supply Voltage ( with respect to ground ) VDDA VDDQ All Input / Output Voltage ( with respect to ground ) Lead temperature, Surface-mount process ESD rating, Human Body model -40 to +125 3.0V 4.5V 4.5V -0.3V to VDDQ+0.5V 245 2000V
Absolute Maximum Ratings
DC Electrical Characteristics ( 0 Symbol
< TA < Parameter
) Min. Typ. Max. Unit
Type : POWER VDDA VDDD VDDQ IDD IPWDN DC supply voltage - Analog DC supply voltage - Digital DC supply voltage - I/O Operating Current ( ~ 30fps / 2.5v ) Power Down Current (see Note ) Type : IN & I/O Reset and System Clock(input clock) VIH VIL Input Voltage HIGH Input Voltage LOW VDDQ * 0.7 VDDQ * 0.3 V V
a
2.45 1.7 1.7
2.5 1.8 15 10
2.8 1.98 3.3
V V V mA
20
A
Type : OUT & I/O for PX0~9, SDA, H/VSYNC and PXCLK(output clock) VOH VOL
Notea : VDDA = 2.5V, VDDQ = 2.8V Noteb : For SDA, the minimum VOH is VDDQ * 0.75
Output Voltage HIGH (see Noteb) Output Voltage LOW
VDDQ * 0.9 VDDQ * 0.1
V V
AC Operating Condition ( 0 Symbol fsysclk tsysclk_dc
< TA <
) Min. 10 45 Typ. 24 50 Max. 48 55 Unit MHz % 13
Parameter System clock frequency System clock duty cycle
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PAS6311LT Specification
Sensor Characteristics Parameter Sensitivity Signal to Noise Ratio Dynamic Range Typ. 1.3 41 52 Unit V/(Lux*sec) dB dB
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PAS6311LT Specification
6. Reference Circuit Schematic
C3
0.1uF VDDQ DGND C1
HSYNC
VDDAY
VSYNC
PXCLK
VDDQ
VDDD
0.1uF AGND U1
D3
D4
D2 VDDD
VDDQ
PXCLK
C4 C_N.M.
SY SCLK E2 RESET VSSD E1 D1 A4 B4 A1
HSYNC
VDDAY
VDDQ
VSYNC
C5
A5
E3
SY SCLK RESET VSSD PX9 PX8 PX0 PX7 PX6
CSB VDDA
D5 B5 C4 E5 E4 A2
CSB VDDA VSSA SDA SCL PX1
VDDA
R1 100K
PAS6311LT
VSSA SDA SCL PX1
C2 0.1uF AGND
PX9 PX8 PX0 DGND
PX5
PX4
PX3 C1 PX3
PX7
PX5
PX4
PX6
PX2
C2
A3
B3
B2
B1
PX2
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PAS6311LT Specification
7. Package Information
Symbol Package Body Dimension X Package Body Dimension Y Package Height Ball Height Package Body Thickness Glass Thickness Ball Diameter Total Pin Count Pin Count X axis Pin Count Y axis Pins Pitch X axis Pins Pitch Y axis Edge to Pin Center Distance along X Edge to Pin Center Distance along Y Edge to Optical Center Distance along X Edge to Optical Center Distance along Y A B C C1 C2 C3 D N N1 N2 J1 J2 S1 S2 E F
Nominal 3715 3515 955 130 825 545 250 24 5 5 570 570 803 603 1806 1412
Min. m 3690 3490 895 100 780 525 220
Max. 3740 3540 1015 160 870 565 280
773 573 1781 1387
833 633 1831 1437
PACKAGE MECHANICAL DIAGRAM
NOTCH
E
1 2
A
3 4 5
S1
5
J1
4 3 2 1
S2
F
A
33.1
A
J2
BGA Center
B
B
330.4
Sensor Array Center
C
C
B
Ball Center
D D
E
E
Top view (Bumps down)
Package Center
Buttom view (Bumps up)
C3
C2
C1
Side view
*Note: The formation of image is the result formed by package Top view(A1 : left-up) and general Lens(invert and mirror the image).
C
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PAS6311LT Specification
Recommended Layout PCB
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PAS6311LT Specification
Recommended Condition For Infrared Reflow Carefully observe the mounting conditions, recommended temperature profile when Mounting infrared reflows is show in the figure below. After mounting on the mother board, it must be dispense epoxy in side of the CSP package. Reflow Profile
Melting area
Pre-heat
( Sec )
Recommend Pb-free solder paste vender & type :
1. Almit LFM-48W TM-HP 2. Senju M705-GRN360-K
Programming rate 1.5~2.5 C/sec
o
Pre-heat 170~200oC 90 +/- 30 sec
Melting area >220oC 30~50sec with peak temperature 230~245oC
Dispense Epoxy Epoxy
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