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Single-chip Type with built-in FET Switching Regulator Series
Flexible Step-down Switching Regulators with Built-in Power MOSFET
BD9006F, BD9006HFP, BD9007F, BD9007HFP
No.09027EAT35
Overview The high-accuracy frequency flexible step-down switching regulator is a switching regulator with built-in POWER MOS FET, which withstands high pressure. The operational frequency is freely configurable with external resistance. It features a wide input voltage range (7V~35V) and a high frequency accuracy of 5% (BD9006F, BD9006HFP; f=200~500kHz), Furthermore, an external synchronization input pin enables synchronous operation with external clock.
Features 1) Minimal external components 2) Wide input voltage range: 7V35V 3) Frequency voltage accuracy: 5%(BD9006F,BD9006HFP ; f=200500kHz) 20%(BD9007F, BD9007HFP) 4) Built-in P-ch POWER MOS FET 5) Output voltage setting enabled with external resistor: 0.8VVIN 6) Reference voltage accuracy: 0.8V2% 7) Wide operating temperature range: -40+105 8) Low dropout: 100% ON duty cycle 9) Standby mode supply current: 0A (Typ.) 10) Oscillation frequency variable with external resistor: 50500kHz 11) External synchronization enabled 12) Soft start function: soft start time fixed to 5ms (Typ.) 13) Built-in overcurrent protection circuit 14) Built-in thermal shutdown protection circuit 15) High-power HRP7 package mounted (BD9006HFP,BD9007HFP) 16) Compact SOP8 package mounted (BD9006F,BD9007F)
Applications All fields of industrial equipment, such as Flat TV, printer, DVD, car audio, car navigation, and communication such as ETC, AV, and OA.
Product lineup Item Output Current Input Range Oscillation Frequency Range Oscillation Frequency Accuracy External Synchronous Function Standby Function Operating Temperature Package BD9006F,BD9006HFP 2A 7V35V 50500kHz 5% Provided Provided -40+105 SOP8/HRP7 BD9007F,BD9007HFP 2A 7V35V 50500kHz 20% Provided Provided -40+105 SOP8/HRP7
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1/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Absolute Maximum Ratings (Ta=25oC) Parameter Power Supply Voltage Output Switch Pin Voltage Output Switch Current EN/SYNC Pin Voltage RT, FB, INV Pin Voltage Power Dissipation Operating Temperature Range Storage Temperature Range Maximum Junction Temperature
*1 *2
Technical Note
Symbol VIN VSW ISW VEN/SYNC VRT,VFB,VINV HRP7 SOP8 Pd Topr Tstg Tjmax
Limits 36 VIN 2
*1
Unit V V A V W W
VIN 7 5.5 *2 0.69
*3
-40+105 -55+150 150
*3
Should not exceed Pd-value. Reduce by 44mW/ over 25,when mounted on 2-layerPCB of 70x70x1.6mm3 (PCB incorporates thermal via. Copper foil area on the reverse side of PCB: 10.5x10.5mm2 Copper foil area on the reverse side of PCB: 70x70mm2 Reduce by 5.52mW/ over 25,when mounted on 2-layer PCB of 70x70x1.6mm3
Recommended Operating Range Parameter Operating Power Supply Voltage Output Switch Current Output Voltage (min pulse width) Oscillation Frequency Oscillation Frequency set Resistance Possible Operating Range Parameter Operating Power Supply Voltage BD9006F,BD9006HFP 535 BD9007F,BD9007HFP 535 Unit V BD9006F,BD9006HFP 735 2 250 50500 27360 BD9007F,BD9007HFP 735 2 250 50500 27360 Unit V A ns kHz k
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2/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Electrical Characteristics BD9006F,BD9006HFP (Unless otherwise specified, Ta=25, VIN=13.2V, VEN/SYNC=5V) Parameter Standby Circuit Current Circuit Current SW Block POWER MOS FET ON Resistance Operating Output Current Of Overcurrent Protection Output Leak Current Error Amp Block Reference Voltage 1 Reference Voltage 2 Reference Voltage Input Regulation Input Bias Current Maximum FB Voltage Minimum FB Voltage FB Sink Current FB Source Current Soft Start Time Oscillator Block Oscillation Frequency Frequency Input Regulation Enable/Sync Input Block Output ON Voltage Output OFF Voltage Sink Current External Sync Frequency
*Not designed to be radiation resistant.
Technical Note
Symbol ISTB IQ
Spec Values Min. Typ. 0 4 Max. 10 6.5
Unit A mA
Conditions VEN/SYNC=0V IO=0A,RT=51k,VINV=0.7V
RON IOLIMIT IOLEAK
2 -
0.3 4 0
0.6 30
A A
ISW=50mA
VIN=35V, VEN/SYNC=0V
VREF1 VREF2 VREF IB VFBH VFBL IFBSINK IFBSOURCE TSS
0.784 0.780 -1 2.2 -0.47 1 3
0.800 0.800 0.5 2.4 0.5 -1.16 5 5
0.816 0.820 0.6 -2.45 15 9
V V % A V V mA mA mS
VFB=VINV VIN=1016V,VFB=VINV
VINV=0.6V VINV=0V VINV=2V VFB=1V,VINV=1V VFB=1V,VINV=0.6V Ta=-40105
FOSC FOSC
285 -
300 0.5
315 -
kHz %
RT=51k VIN=1016V VEN/SYNC Sweep Up, Ta=-40105 VEN/SYNC Sweep Down, Ta=-40105 RT=51k, EN/SYNC=500kHz,Duty 50%
VENON VENOFF IEN/SYNC FSYNC
2.6 495
35 500
0.8 90 505
V V A kHz
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3/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Electrical Characteristics BD9007F,BD9007HFP (Unless otherwise specified, Ta=25, VIN=13.2V, VEN/SYNC=5V) Parameter Standby Circuit Current Circuit Current SW Block POWER MOS FET ON Resistance Operating Output Current Of Overcurrent Protection Output Leak Current Error Amp Block Reference Voltage 1 Reference Voltage 2 Reference Voltage Input Regulation Input Bias Current Maximum FB Voltage Minimum FB Voltage FB Sink Current FB Source Current Soft Start Time Oscillator Block Oscillation Frequency Frequency Input Regulation Enable/Sync Input Block Output ON Voltage Output OFF Voltage Sink Current External Sync Frequency
*Not designed to be radiation resistant.
Technical Note
Symbol ISTB IQ
Spec Values Min. Typ. 0 4 Max. 10 6.5
Unit A mA
Conditions VEN/SYNC=0V IO=0A,RT=51k,VINV=0.7V
RON IOLIMIT IOLEAK
2 -
0.3 4 0
0.6 30
A A
ISW=50mA
VIN=35V, VEN/SYNC=0V
VREF1 VREF2 VREF IB VFBH VFBL IFBSINK IFBSOURCE TSS
0.784 0.780 -1 2.2 -0.47 1 3
0.800 0.800 0.5 2.4 0.5 -1.16 5 5
0.816 0.820 0.6 -2.45 15 9
V V % A V V mA mA mS
VFB=VINV VIN=1016V,VFB=VINV
VINV=0.6V VINV=0V VINV=2V VFB=1V,VINV=1V VFB=1V,VINV=0.6V Ta=-40105
FOSC FOSC
240 -
300 0.5
360 -
kHz %
RT=51k VIN=1016V VEN/SYNC Sweep Up, Ta=-40105 VEN/SYNC Sweep Down, Ta=-40105 RT=51k, EN/SYNC=500kHz,Duty 50%
VENON VENOFF IEN/SYNC FSYNC
2.6 495
35 500
0.8 90 505
V V A kHz
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4/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Reference Data
0.816
OSCILATING FREQUENCY:fosc[kHz]
Technical Note
52.5
OSCILATING FREQUENCY:fosc[kHz
105 104 103 102 101 100 99 98 97 96 95 -50 -25 0 25 50 75 100 125
REFERENCE VOLTAGE:VREF[V]
0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE:Ta[]
52.0 51.5 51.0 50.5 50.0 49.5 49.0 48.5 48.0 47.5 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE:Ta[] RT=330k
RT=160k
AMBIENT TEMPERATURE:Ta[]
Fig.1 Output reference voltage vs. Ambient temperature (All series)
315
OSCILATING FREQUENCY:fosc[kHz]
Fig.2 Frequency vs. Ambient temperature (All series)
525
OSCILATING FREQUENCY:fosc[kHz]
10 9 STAND-BY CURRENT:ISTB [A] 8 7 6 5 4 3 2 1 0
Fig.3 Frequency vs. Ambient temperature (All series)
312 309 306 303 300 297 294 291 288 285 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE:Ta[]
520 515 510 505 500 495 490 485 480 475 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE:Ta[]
RT=51k
RT=30k
Ta=105 Ta=25,-
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE:VIN[V]
Fig.4 Frequency vs. Ambient temperature (All series)
8
Fig.5 Frequency vs. Ambient temperature (All series)
1.6
FET ON RESISTANCE:RON[]
Fig.6 Standby Current (All series)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
EN/SYNC INPUT CURRENT:[mA]
7 CIRCUIT CURRENT: ICC[mA] 6 5 4 3 2 1 0 0 5
Ta=105 From Top: Ta=105 Ta=25 Ta=25 Ta=-40 Ta=-40
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE:VEN/SYNC[V]
Inflection Point From Top: VEN=7V (Ta=105) VEN=6.8V (Ta=25) VEN=6.4V(Ta=-40)
From Top: Ta=105 Ta=25 Ta=-40
10
15
20
25
30
35
40
0.0
0.5
1.0
1.5
2.0
INPUT VOLTAGE: VIN[V]
OUTPUT CURRENT:Io[A]
Fig.7 Circuit Current (All series)
1.6 FET ON RESISTANCE:R ON[]
FET ON RESISTANCE:R ON[]
Fig.8 EN/SYNC Input Current (All series)
1.6
Fig.9 ON Resistance VIN=7V (All series)
100 CONVERSION EFFICIENCY [%] 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 5.0V From Top: 5.0V output 3.3V output 3.3V 2.5V output 2.5V 1.5V output 1.5V
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 OUTPUT CURRENT:Io[A]
From Top: Ta=105 Ta=25 Ta=-40
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 OUTPUT CURRENT:Io[A]
From Top: Ta=105 Ta=25 Ta=-40
VIN=13.2V f=100kHz Ta=25 1.5 2.0
OUTPUT CURRENT:Io[A]
Fig.10 ON Resistance VIN=13.2V (All series)
Fig.11 ON Resistance VIN=35V (All series)
Fig.12 Efficiency f=100kHz (All series)
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5/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
100
100
10
From Left: Ta=105 Ta=-40 Ta=25
CONVERSION EFFICIENCY [%]
CONVERSION EFFICIENCY [%]
90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 OUTPUT CURRENT:Io[A]
From Top: 5.0V output 3.3V output 2.5V output 1.5V output
90
OUTPUT VPLTAGE:Vo [V]
80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 OUTPUT CURRENT:Io[A]
From Top: 5.0V output 3.3V output 2.5V output 1.5V output
8
6
4
VIN=13.2V f=300kHz Ta=25
VIN=13.2V f=500kHz Ta=25
2
VIN=13.2V f=300kHz Vo=5V
0 0 1 2 3 4 5 OUTPUT CURRENT:Io[A]
Fig.13 Efficiency f=300kHz (All series)
7 6 INPUT VOLTAGE VIN [V] INPUT VOLTAGE VIN [V] 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 OUTPUT CURRENT:Io[A] Vo=5V f=300kHz Ta=-40 7 6 5 4 3 2 1 0 0.0
Fig.14 Efficiency f=500kHz (All series)
Fig.15 Over-current Protection Operation Current (All series)
7 6 INPUT VOLTAGE VIN [V] 5 4 3 2 1 0 Vo=5V f=300kHz Ta=105 0.5 1.0 1.5 2.0
Vo=5V f=300kHz Ta=25 0.5 1.0 1.5 2.0
0.0
OUTPUT CURRENT:Io[A]
OUTPUT CURRENT:Io[A]
Fig.16 The lowest voltage of possible operation (All series)
Fig.17 The lowest voltage of possible operation (All series)
Fig.18 The lowest voltage of possible operation (All series)
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6/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Block Diagrams / Application circuit / PIN assignment (BD9006F,BD9007F)
PVIN
Technical Note
(BD9006HFP,BD9007HFP)
VIN +
VIN
VREG Internal SOFT START Bias SYNC
EN/SYNC
+
EN/SYNC
220F
2F
220F
2F Internal Bias
Vref
5V + CURRENT LIMIT SDWN Reset DRV Set SDWN
DRIVER
SOFT START
SYNC +
5V
INV
ERROR AMP
PWM COMPARATOR + Slope
+ + 0.8V
INV
ERROR AMP
PWM COMPARATOR + SDWN Reset DRV Set SDWN
CURRENT LIMIT
+ + 0.8V Slope
DRIVER
22000pF
GND EN/SYNC VIN RT
UVLO/ TSD
SW
33H +
Vo
22000pF
SW
UVLO/ TSD
33H +
Vo
330F
330F GND 47 K
30 K OSC
30 K
FB
GND 47k
OSC
SW INV PVIN FB

RT
VIN FB INV EN/SYNC SW GND RT
FB

RT
51 K
51 K 15 K
15 K
Fig.19 No. 1 2 3 4 5 6 7 8 Pin name PVIN SW FB INV Function Power system power supply input Output Error Amp output Output voltage feedback No. 1 2 3 4 5 6 7 FIN Pin name VIN SW FB GND INV RT
Fig.20 Function Power supply input Output Error Amp output Ground Output voltage feedback Frequency setting resistor connection
EN/SYNC Enable/Synchronizing pulse input RT GND VIN Frequency setting resistor connection Ground Power supply input
EN/SYNC Enable/Synchronizing pulse input Ground
*VIN and PVIN must be shorted before use
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7/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Description of operations ERROR AMP The ERROR AMP block is an error amplifier used to input the reference voltage (0.8V Typ.) and the INV pin voltage. The output FB pin controls the switching duty and output voltage Vo. These INV and FB pins are externally mounted to facilitate phase compensation. Inserting a capacitor and resistor between these pins enables adjustment of phase margin. (Refer to recommended examples on pages 11~13.)
SOFT START The SOFT START block provides a function to prevent the overshoot of the output voltage Vo through gradually increasing the normal rotation input of the error amplifier when power supply turns ON to gradually increase the switching Duty. The soft start time is set to 5msec (Typ.).
SYNC By making the "EN/SYNC" terminal less than 0.8V, the circuit can be shut down. Furthermore, by applying pulse with higher frequency than the configured oscillation frequency to the "EN/SYNC" terminal, external sync is possible. (Sync possible with double the configured frequency-configured frequency or 500kHz)
OSC(Oscillator) This circuit generates the pulse wave to be input to the slope, and by connecting resistance to "RT", 50~500kHz oscillating frequency can be configured. (Refer to p.11 Fig.24)
slope This block generates saw tooth waves from the clock generated by the OSC. The generated saw tooth waves are sent to PWM COMPARATOR.
PWM COMPARATOR The PWM COMPARATOR block is a comparator to make comparison between the FB pin and internal saw tooth wave and output a switching pulse The switching pulse duty varies with the FB value. (min Duty width : 250ns.)
TSD (Thermal Shut Down) In order to prevent thermal destruction/thermal runaway of the IC, the TSD block will turn OFF the output when the chip temperature reaches approximately 150 or more. When the chip temperature falls to a specified level, the output will be reset. However, since the TSD is designed to protect the IC, the chip junction temperature should be provided with the thermal shutdown detection temperature of less than approximately.150.
CURRENT LIMIT While the output POWER P-ch MOS FET is ON, if the voltage between drain and source (ON resistancexload current) exceeds the reference voltage internally set with the IC, this block will turn OFF the output to latch. The overcurrent protection detection values have been set as shown below: BD9006F,BD9006HFP, BD9007F,BD9007HFP 4A (Typ.) Furthermore, since this overcurrent protection is an automatically reset, after the output is turned OFF and latched, the latch will be reset with the RESET signal output by each oscillation frequency. However, this protection circuit is only effective in preventing destruction from sudden accident. It does not support for the continuous operation of the protection circuit (e.g. if a load, which significantly exceeds the output current capacitance, is normally connected). Furthermore, since the overcurrent protection detection value has negative temperature characteristics, consider thermal design.
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8/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Timing Chart (All series) Basic Operation
Technical Note
VIN Internal slope FB
SW
VEN/SYNC
Fig.21 External synchronizing function In order to activate the external synchronizing function, connect the frequency setting resistor to the RT pin and then input a synchronizing signal to the EN/SYNC pin. As the synchronizing signal, input a pulse wave higher than a frequency determined with the setting resistor (RT). However, the external sync frequency should be configured at less than double the configured frequency. (ex.) When the configured frequency is 100kHz, the external sync frequency should be less than 200kHz. Furthermore, the pulse wave's LOW voltage should be under 0.8V and the HIGH voltage over 2.6V (when the HIGH voltage is over 6V the EN/SYNC input current increases [see p.4 Fig.8]), the through rate of stand-up (and stand-down) under 20V/S.
VIN=13.2V
VIN
BD9006HFP
1 2 3 4 5 6 7 2F SW 33H L1 R3 30k D1 R1 47k C0 330F C1 22000pF VI N SW FB GND INV RT EN/SY NC CIN 220F C28
REG
C3 open
RT 51k
Ven/sync=05V f=450kHz SR=20V/s Duty=50%
C2 open
GND GND GND
R2 15k
Fig.22 External Sync Sample Circuit (Vo=3.3V, Io=1A, f=300kHz, EN/SYNC=450kHz)
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9/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Description of external components
VIN VIN
Technical Note
L1 SW D1
Vo
C28
CIN
Co R1
RT RT EN/SYNC GND
INV R2 FB R3 C1
Fig.23 Design Procedure Vo=Output voltage, VIN (Max.)=Maximum input voltage Io (Max.)=Maximum load current, f=Oscillation frequency 1. Setting or output voltage Output voltage can be obtained by the formula shown below: Vo=0.8x(1+R1/R2) Use the formula to select the R1 and R2. Furthermore, set the R2 to 30k or less. Select the current passing through the R1 and R2 to be small enough for the output current. Sample Calculations When Vo=3.3V, VIN (Typ.)=13.2V Io(Max.)=1A and f=300kHz When VO=3.3V and R2=15k 3.3=0.8x(1+R1/15k) R1=46.875k47k R1=47k
2. Selection of coil (L1) When VIN=13.2V, Vo=3.3V, Io=1A and f=300kHz, The value of the coil can be obtained by the formula shown L1=(13.2-3.3)x3.3/{13.2x300kx(1x0.3)} below: =27.5H33H L1=(VIN-Vo)xVo / (VINxfxIo) Io: Output ripple current Io should typically be approximately 20 to 30% of Io. If this coil is not set to the optimum value, normal (continuous) L1=33H Oscillation may not be achieved. Furthermore, set the value of the coil with an adequate margin so that the peak current passing through the coil will not exceed the rated current of the coil. 3. Selection of output capacitor (Co) VIN=13.2V, Vo=3.3V, L=33H, f=300kHz The output capacitor can be determined according to the IL=(13.2-3.3)x3.3/(33x10-6x300x103x13.2) output ripple voltage Vo(p-p) required. Obtain the required =0.25 ESR value by the formula shown below and then select the IL=0.25A capacitance. IL=(VIN-Vo)xVo/(LxfxVIN) Vpp=ILxESR+(ILxVo)/(2xCoxfxVIN) Set the rating of the capacitor with an adequate margin to the output voltage. Also, set the maximum allowable ripple current with an adequate margin to IL. Furthermore, the output rise time should be shorter than the soft start time. Select the output capacitor having a value smaller than that obtained by the formula shown below. CMAX = 3.0mx(ILIMIT-Io(Max)) Vo
When ILIMIT: 2A, Io(Max)=1A, Vo=3.3V CMAX =3.0mx(2-1)/3.3 910
ILIMIT2A (BD9006F,BD9006HFP, BD9007F,BD9007HFP) If this capacitances is not optimum, faulty startup may result. (3.0m is soft start time(min).)
CMAX=910F
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10/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
Design Method 4. Selection of diode (D1) Set diode rating with an adequate margin to the maximum load current. Also, make setting of the rated inverse voltage with an adequate margin to the maximum input voltage. A diode with a low forward voltage and short reverse recovery time will provide high efficiency. 5. Selection of input capacitor (CIN, C28) Two capacitors, ceramic capacitor CIN and bypass capacitor C28 should be inserted between the VIN and GND. Be sure to insert a ceramic capacitor of 2 to 10F for the CIN. The capacitor C28 should have a low ESR and a significantly large ripple current. The ripple current IRMS can be obtained by the following formula:
2 IRMS=Iox Vox(VIN-Vo)/VIN
Sample Calculations When VIN(max.)=35V Io=(max.)2A Diode ratings must include: Current over 2A Withstand minimum 35V When VIN=13.2V, Vo=3.3V and Io=1A:
2 IRMS=1x 3.3x(13.2-3.3)/(13.2)
IRMS=0.433A
Select capacitors that can accept this ripple current. If the capacitance of CIN and C28 is not optimum, the IC may malfunction. 6. Setting of oscillating frequenPcy Referring Fig.24 on the following page, select R for the oscillating frequency to be used. 7. Setting of phase compensation (R3 and C1) The phase margin can be set through inserting a capacitor or a capacitor and resistor between the INV pin and the FB pin. Each set value varies with the output coil, capacitance, I/O voltage, and load. Therefore, set the phase compensation to the optimum value according to these conditions. (For details, refer to Application circuit on page.11) If this setting is not optimum, output oscillation may result.
When f=300kHz From p.11 Fig.24, a resistance of RT=51k is selected. RT=51k Please contact us if there are any questions regarding phase compensation configuration.
The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings and the types of parts in use. In the connection, it is recommended to thoroughly verify these values on the actual system prior to use.
Directions for pattern layout of PCB
GND BD9006HFP
R3 C1
C3
RT
SIGNAL GND L1
C28 CIN
D1
POWER GND
L O A D
R1
C2
Arrange the wirings shown by heavy lines as short as possible in a broad pattern. Locate the input ceramic capacitor CIN as close to the VIN-GND pin as possible. Locate the RT as close to the GND pin as possible. Locate the R1 and R2 as close to the INV pin as possible, and provide the shortest wiring from the R1 and R2 to the INV pin. Locate the R1 and R2 as far away from the L1 as possible. Separate POWER GND (Schottky diode, I/O capacitor's GND) and SIGNAL GND (RT, GND), so that SW noise doesn't have an effect on SIGNAL GND at all. Design the POWER wire line as wide and short as possible. Additional pattern for C2 and C3 expand compensation flexibility.
GND
SW
INV
VIN
R2
Fig.24
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EN
FB
RT
11/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
D1 C28
CIN
L1
R3 C3
C28
RT
CIN
R3
C1
C2
R4
C2 R1 R2
L1
Co
Fig.25 BD9006F Reference Layout Pattern
Fig.26 BD9006HFP Reference Layout Pattern
As shown above ,design the GND pattern as large as possible within inner layer. Gray zones indicate GND.
500 450
OSCILATION FREQUENCY:fosc[kHz]
400 350 300 250 200 150 100 50 0 100 200 OSCILATING FREQUENCY SETTEING RESISTANCE:RT[k] 300
RT[k] 27 30 33 36 39 43 47 51 56 62 68 75 82 91
fosc[kHz] 537 489 449 415 386 353 324 300 275 250 229 209 192 174
R4
Co
RT[k] 100 110 120 130 150 160 180 200 220 240 270 300 330 360
RT
R1
R2
C1
D1
C3
fosc[kHz] 160 146 134 124 108 102 91 82 75 69 61 55 50 46
Fig.27 RT Resistance Values vs. Oscillating Frequency Phase Compensation setting procedure 1 Application stability conditions
The values in the graph for oscillating frequency are Typical values, and variance of5% forBD9006F/HFP and 20% for BD9007F/HFP should be considered.
The following section describes the stability conditions of the negative feedback system. Since the DC/DC converter application is sampled according to the switching frequency, GBW (frequency at 0-dB gain) of the overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted characteristics of this application. At a 1 (0-dB) gain, the phase delay is 150 or less (i.e. the phase margin is 30 or more). The GBW for this occasion is 1/10 or less of the switching frequency. Responsiveness is determined with restrictions on the GBW. To improve responsiveness, higher switching frequency should be provided. Replace a secondary phase delay (-180) with a secondary phase lead by inserting two-phase leads, to ensure the stability through the phase compensation. Furthermore, the GBW (i.e., frequency at 0-dB gain) is determined according to phase compensation capacitance provided for the error amplifier. Consequently, in order to reduce the GBW, increase the capacitance value. (1) Typical integrator (low pass filter) (2) Open loop characteristics of integrator
(a) -20dB/decade GBW(b) 0 0 -90 Phase margin -180 f f
Feedback
R
A
FB
Gain [dB]
A
Point (a) fa=
1 2RCA
[Hz]
Phase [ ] 90
Point (b) fb=GBW=
1 [Hz] 2RC
C
-180
Since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. In the case of the DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
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12/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
2 For output capacitors having high ESR, such as electrolyte capacitor
Technical Note
For output capacitors that have high ESR (i.e., several ), the phase compensation setting procedure becomes comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output, a -180 phase-delay occurs in that area. If ESR component is present, however a +90 phase-lead occurs to shift the phase delay to -90. Since the phase delay should be set within 150, it is a very effective method but tends to increase the ripple component of the output voltage. (1) LC resonant circuit (2) With ESR provided Vcc Vcc
L C
Vo
L
Vo RESR C
fr =
1 2LC
[Hz]
At this resonance point, a-180 phase-delay occurs.
1 [Hz]: Resonance 2LC 1 fESR = [Hz]: Phase lead 2RESRC fr = A -90 phase-delay occurs.
According to changes in phase characteristics, due to the ESR, only one phase lead should be inserted. For this phase lead, select either of the methods shows below: (3) Insert Feedback Resistance in the C.
Vo C1 R1 INV A FB C2 R1 INV R2 A FB
(4) Insert the R3 in integrator.
Vo R3 C2
R2
Phase lead fz =
1 2C1R1
[Hz]
Phase lead fz =
1 2C2R3
[Hz]
To cancel the LC resonance, the frequency to insert the phase lead should be set close to the LC resonant frequency. The setting above have is estimated. Consequently, the setting may be adjusted on the actual system. Furthermore, since these characteristics vary with the layout of PCB loading conditions, precise calculations should be made on the actual system. 3For output capacitors having low ESR, such as low impedance electrolyte capacitor or OS-CON In order to use capacitors with low ESR (i.e., several tens of m), two phase-leads should be inserted so that a -180phasedelay, due to LC resonance, will be compensated. The following section shows a typical phase compensation procedure. (1) Phase compensation with secondary phase lead
Vo R1 C1 R3 C2
Phase leadfz2 Phase leadfz1
= =
1 2R1C1 1 2R3C2 1 2LC
[Hz] [Hz]
INV R2
A
FB
LC resonantfr frequency
=
[Hz]
To set phase lead frequency, insert both of the phase leads close to the LC resonant frequency. According to empirical rule, setting the phase lead frequency fZ2 with R3 and C2 lower than the LC resonant frequency fr, and the phase lead frequency fZ1 with the R1 and C1 higher than the LC resonant frequency fr, will provide stable application conditions.
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13/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
VO DC/DC converter controller
+ +

RL
Vm
Load 0 Output voltage
Maximum load
0
Inadequate phase margin
Adequate phase margin
t
Measurement of open loop of the DC/DC converter To measure the open loop of the DC/DC converter, use the gain phase analyzer or FRA to measure the frequency characteristics. 1. Check to ensure output causes no oscillation at the maximum load inclosed loop. 2. Isolate and and insert Vm (with amplitude of approximately.100mVpp). 3. Measure (probe) the oscillation of to that of . Furthermore, the phase margin can also be measured with the load responsiveness. Measure variations in the output voltage when instantaneously changing the load from no load to the maximum load. Even though ringing phenomenon is caused, due to low phase margin, no ringing takes place. Phase margin is provided. However, no specific phase margin can be probed.
Please contact us if you have any questions regarding phase compensation.
Heat Loss For thermal design, be sure to operate the IC within the following conditions. (Since the temperatures described hereunder are all guaranteed temperature, take margin into account.) 1. The ambient temperature Ta is to be 105 or less. 2. The chip junction temperature Tj is to be 150 or less. The chip junction temperature Tj can be considered in the following two patterns: To obtain Tj from the IC surface temperature TC in actual use state, Tj=Ta+jaxW < Reference value > jc :HRP7 7/W SOP8 32.5/W To obtain Tj from the ambient temperature Ta in actual use state,Tj=TC+jcxW < Reference. value > ja : HRP7 89.3/W Single piece of IC 2 54.3/W 2-layer PCB (Copper foil area on the front side of PCB: 15x15mm ) 2 22.7/W 2-layer PCB (Copper foil area on the front side of PCB: 70x70mm ) 3 PCB size: 70x70x1.6mm (PCB incorporates thermal via.) Copper foil area on the front side of PCB: 10.5x10.5mm2 ja : SOP8 222.2/W Single piece of IC 181.8/W 1-layer PCB PCB size: 70x70x1.6mm3 The heat loss W of the IC can be obtained by the formula shown below: Vo 2 + VIN x Icc + Tr x VIN x Io x f W = Ron x Io x VIN Ron: ON resistance of IC (refer to page.4) Io: Load current Vo: Output voltage VIN: Input voltage ICC: Circuit current (refer to page.3) Tr: Switching rise/fall time (approximately 20nsec) f: Oscillation frequency
Tr VIN
1 Ron x Io
2
SW wave from
2x
1 2
x Tr x
1 T
x VIN x Io
=Tr x VIN x Iox f
GND
2 T= 1 f
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14/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
SW
VIN VIN VIN VIN
Technical Note
INV
RT
Internal Power
Internal Power
SW RT 167k INV 1k
EN/SYNC
VIN
Internal Power
FB
VIN
Internal Power
EN/ SYNC
60k
222 k 145 k 221 k 139 k
FB 1k 1k
20
Fig.28 Equivalent circuit Notes for use 1. Absolute maximum ratings If excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. GND potential Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND potential voltage including electric transients. 3. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4. Inter-pin shorts and mounting errors When attaching to the set substrate, pay special attention to the direction and proper placement of the IC. If the IC is attached incorrectly, it may be destroyed. Furthermore, when using the IC with VIN and EN/SYNC terminals shorted, and the 5-pin (SOP8 package) or 7-pin (HRP7 package) EN/SYNC terminal and 6-pin RT terminal are shorted, the IC may also be damaged when VIN>7V. 5. Operation in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6. Inspection with set printed circuit board When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting and storing the IC. 7. IC pin input (Fig. 26) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND>pin A and GND>pin B, the P-N junction operates as a parasitic diode. When pin B >GND>pin A, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor (Terminal A) (Terminal B) Transistor (NPN) (Terminal A) Parasitic Element
(Terminal B)
P Substrate
Parasitic Element Parasitic Element
P Substrate
Parasitic Element
Fig.29 Typical simple construction of monolithic IC
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15/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Technical Note
8. GND wiring pattern It is recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB, so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause on fluctuations in voltages of the small-signal GND. Prevent fluctuations in the GND wiring pattern of external parts. 9. Temperature protection (thermal shut down) circuit This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above, be sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range continue, the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output power element. Then, when the tip temperature Tj falls, the circuit will be automatically reset. Furthermore, if the temperature protection circuit is activated under the condition exceeding the absolute maximum ratings, do not attempt to use the temperature protection circuit for set design. 10. On the application shown below, if there is a mode in which VIN and each pin potential are inverted, for example, if the VIN is short-circuited to the Ground with external diode charged, internal circuits may be damaged. To avoid damage, it is recommended to insert a backflow prevention diode in the series with VIN or a bypass diode between each pin and VIN.
Bypass diode
Backflow prevention diode
Vcc
Pin
Fig.30
Thermal reduction characteristics HRP7
10
POWER DISSIPATIONPD [W] POWER DISSIPATIONPD [W]
SOP8
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 50 75 100 125 150

9 8 7 6 5 4 3 2 1 0
1.4W 2.3W 5.5W 7.3W
25
50
75
100
125
150
AMBIENT TEMPERATURETa []
AMBIENT TEMPERATURETa []
Single piece of IC 3 PCB Size: 70x70x1.6mm (PCB incorporates thermal via) Copper foil area on the front side of PCB: 10.5x10.5mm2 2-layer PCB (Copper foil area on the reverse side of PCB: 15x15mm2) 2-layer PCB (Copper foil area on the reverse side of PCB: 70x70mm2) 4-layer PCB (Copper foil area on the reverse side of PCB: 70x70mm2) Fig.31
Single piece of IC When mounted on ROHM standard PCB
(Glass epoxy PCB of 70mmx70mmx1.6mm)
Fig.32
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16/17
2009.05 - Rev.A
BD9006F, BD9006HFP, BD9007F, BD9007HFP
Ordering part number
Technical Note
B
D
9
0
0
6
H
F
P
-
T
R
Part No.
Part No. 9006, 9007
Package F : SOP8 HFP : HRP7
Packaging and forming specification E2: Embossed tape and reel (SOP8) TR: Embossed tape and reel (HRP7)
SOP8

5.00.2 (MAX 5.35 include BURR)
8 7 6 5
+6 4 -4
Tape Quantity
0.90.15 0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.20.3
4.40.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
12
3
4
0.595
1.50.1
+0.1 0.17 -0.05 S
0.11
1.27 0.420.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
HRP7

9.3950.125 (MAX 9.745 include BURR)
1.0170.2
Tape
1.9050.1
Embossed carrier tape 2000pcs TR
The direction is the 1pin of product is at the upper right when you hold
8.820.1 (5.59)
Quantity Direction of feed
1.5230.15
0.8350.2
10.540.13
8.00.13
(7.49)
( reel on the left hand and you pull out the tape on the right hand
1pin
)
0.8875
12 34 5 6 7
+5.5 4.5 -4.5 0.730.1 +0.1 0.27 -0.05 S
0.080.05
1.27
0.08 S
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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http://www.rohm.com/contact/
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