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| PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 FEATURES: . Patented technology . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 400MHz with 5pf load . Operating frequency up to 250MHz with 50pf load . Very low output pin to pin skew < 100ps . Very low pulse skew < 300ps . VCC = 1.65V to 3.6V . Propagation delay < 2.5ns max with 50pf load . Low input capacitance: 3pf typical . 4x1:4 fanout . Available in 28pin 50mil PLCC package DESCRIPTION: Potato Semiconductor's PO49FCT1816G is designed for world top performance using submicron CMOS technology to achieve 500MHz TTL output frequency with less than 100ps output pin to pin skew. PO49FCT1816G is a 1.65V to 3.3V CMOS 1 input to 4 outputs Buffered driver in 4 groups to achieve 500MHz output frequency. Typical applications are clock and signal distribution. Pin Configuration Logic Block Diagram Pin Description Pin Name INA, INB, INC, IND A[0-3], B[0-3], C[0-3], D[0-3] Description Inputs Outputs 1 Copyright (c) 2005, Potato Semiconductor Corporation PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 Unit C C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -24mA Vcc=3V Vin=VIH or VIL, IOH=24mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 3.6V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ Max Unit VOH VOL VIH VIL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.46 2 -0.5 -0.7 0.44 Vcc 0.8 1 -1 -1.2 V V V V uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc - 0.6V at rated current 2 Copyright (c) 2005, Potato Semiconductor Corporation PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND Min Typ Max Unit IccQ Notes: 1. 2. 3. 4. 5. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc - 0.6V at rated current Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ Max Unit Cin Cout Notes: 3 - 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics (Vcc = 3.3V0.3V, TA=85C) Symbol Description Propagation Delay A to Bn Propagation Delay A to Bn Rise/Fall Time Measured between 0.8V - 2.0V Pulse Skew (Same Package) Output Pin to Pin Skew (Same Bank) Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Pulse Width Duration Duty Cycle Input Frequency Input Frequency Input Frequency Test CL = 50pF CL = 50pF CL = 50pf CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 5pF CL = 2pF Min M ax Unit tPLH tPHL tr/tf tsk(p) tsk(o) tsk(o) tsk(pp) tLOW/tHIGH tDC fmax fmax fmax Notes: 2.5 2.5 2.0 0.3 0.1 0.15 0.4 5 45 55 250 400 500 ns ns ns ns ns ns ns ns % MHz MHz MHz 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 Copyright (c) 2005, Potato Semiconductor Corporation PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Test Waveforms Test Circuit 1 50 4 Copyright (c) 2005, Potato Semiconductor Corporation PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Test Circuit 2 50 Packaging Mechanical Drawing: 28 pin PLCC 5 Copyright (c) 2005, Potato Semiconductor Corporation PO49FCT1816 4X1:4 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip Ordering Information Ordering Code PO49FCT1816P Package Code Package Description Pb-free & Green, 28-pin PLCC 01/05/06 6 Copyright (c) 2005, Potato Semiconductor Corporation |
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