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ST1S09
2 A, 1.5 MHz PWM step-down switching regulator with synchronous rectification
Features

1.5 MHz fixed frequency PWM with current control mode 2 A output current capability Typical efficiency: > 90% 2 % DC output voltage tolerance Two versions available: power good or inhibit Integrated output over-voltage protection Non switching quiescent current: (typ) 1.5 mA over temperature range RDSON (typ) 100 m Utilizes tiny capacitors and inductors Operating junction temp. -30 C to 125 C Available in DFN6 (3x3 mm) exposed pad Moreover, since the required synchronous rectifier is integrated, the number of the external components is reduced to minimum: a resistor divider, an inductor and two capacitors. The power good function continuously monitors the output voltage. An open drain power good flag is released when the output voltage is within regulation. In addition, a low output ripple is guaranteed by the current mode PWM topology and by the use of low E.S.R. SMD ceramic capacitors. The device is thermally protected and the output current limited to prevent damages due to accidental short circuit. The ST1S09 is available in the DFN6 3x3 mm package.
DFN6 (3x3mm)
Description
The ST1S09 is a step-down DC-DC converter optimized for powering low output voltage applications. It supplies a current in excess of 2 A over an input voltage range from 2.7 V to 6 V. A high PWM switching frequency (1.5 MHz) allows the use of tiny surface-mount components.
Table 1.
Device summary
Order codes ST1S09PU ST1S09APU (1) ST1S09IPU Packaging ST1S09PUR ST1S09APUR ST1S09IPUR Package DFN6D (3x3 mm) DFN6D (3x3 mm) DFN6D (3x3 mm)
1. Available on request.
January 2008
Rev 3
1/18
www.st.com 18
ST1S09
Contents
1 2 3 4 5 6 7 8 9 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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ST1S09
Diagram
1
Figure 1.
Diagram
Schematic diagram
(*) Only for ST1S09IPU (**) Only for ST1S09PU
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Pin configuration
ST1S09
2
Figure 2.
Pin configuration
Pin connections (top view)
ST1S09
ST1S09A
ST1S09I
Table 2.
Pin n 1 2 3 4 5 6 Exposed Pad
Pin description
Symbol FB GND SW VIN_SW VIN_A INH/PG/NC GND Feedback voltage System ground Switching pin Power supply for the MOSFET switch Power supply for analog circuit Inhibit (to turn off the device) / Power Good / Not Connected. To be connected to PCB ground plane for optimal electrical and thermal performance. Name and function
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ST1S09
Maximum ratings
3
Table 3.
Maximum ratings
Absolute maximum ratings
Parameter Positive power supply voltage Positive power supply voltage Inhibit voltage (I version) Max. voltage of output pin Feedback voltage Power Good open drain Max junction temperature Storage temperature range Lead temperature (soldering) 10 sec Value -0.3 to 7 -0.3 to 7 -0.3 to VI + 0.3 -0.3 to 7 -0.3 to 3 -0.3 to 7 -40 to 150 -65 to 150 260 Unit V V V V V V C C C
Symbol VIN_SW VIN_A VINH SWITCH Voltage VFB PG TJ TSTG TLEAD
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Thermal data
Parameter Thermal resistance junction-case Thermal resistance junction-ambient Value 10 55 Unit C/W C/W
Table 4.
Symbol RthJC RthJA
Table 5.
Symbol ESD ESD
ESD performance
Parameter ESD protection voltage ESD protection voltage HBM MM Test conditions Value 2 500 Unit KV V
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Electrical characteristics
ST1S09
4
Table 6.
Electrical characteristics
Electrical characteristics for ST1S09PU Refer to Figure 21 application circuit VIN_SW = VIN_A = 5 V, VO = 1.2 V, C1 = 4.7 F, C2 = 22 F, L1 = 2.7 H, TJ = -30 to 125 C (unless otherwise specified. Typical values are referred to 25 C)
Parameter Feedback voltage VFB pin bias current Input voltage Under voltage lock out threshold Over voltage protection threshold OVP Over voltage protection hysteresis IOVP IQ IO Overvoltage clamping current Quiescent current Output current Output line regulation Output load regulation PWM switching frequency Maximum duty cycle Power good output threshold PG Power good output voltage low ISINK = 6mA open drain output ISW = 750 mA ISW = 750 mA Note 1 IO = 10mA to 100mA, VO = 3.3V IO = 100mA to 2A, VO = 3.3V Thermal shutdown Thermal shutdown hysteresis Load transient response Short circuit removal response IO = 100mA to 1A, TA = 25C tR = tF 200ns, Note 1 IO = 10mA to IO = short, TA = 25C Note 1 -10 -10 2.5 65 % 82 87 150 20 +10 +10 C C %VO %VO 0.1 0.1 2.9 3.5 VO falling VO = 1.2V Not switching VI = 4.5 to 5.5V Note 1 VI = 4.5V to 5.5V, IO = 100mA Note 1 IO = 10mA to 2A Note 1 VFB = 0.65V 1.2 80 2 0.16 0.2 1.5 87 0.92 VO 0.4 0.6 1.8 5 300 1.5 2.5 % mA mA A %VO/ VI % MHz % V V A IO = 10mA to 2A VI Rising Hysteresis VO rising 4.5 3.5 3.7 150 1.05 VO 1.1 VO Test conditions Min. 784 Typ. 800 Max. 816 600 5.5 3.9 Unit mV nA V V mV V
Symbol FB IFB VI UVLO
%VO/VI %VO/IO PWMfS DMAX
RDSON-N RDSON-P ISWL
NMOS switch on resistance PMOS switch on resistance Switching current limitation Efficiency Note 1
TSHDN THYS %VO/IO %VO/IO
Note:
1
Guaranteed by design, but not tested in production.
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ST1S09
Electrical characteristics
Table 7.
Electrical characteristics for ST1S09IPU Refer to Figure 22 application circuit VIN_SW = VIN_A = VINH = 5 V, VO = 1.2 V, C1 = 4.7 F, C2 = 22 F, L1 = 2.7 H, TJ = -30 to 125 C (unless otherwise specified. Typical values are referred to 25 C)
Parameter Feedback voltage VFB pin bias current Minimum input voltage Over voltage protection threshold IO = 10mA to 2A VO rising VO falling VINH > 1.2V, not switching VINH < 0.4V, T = - 30C to 85C Output current VI = 2.7 to 5.5V Note 1 Device ON, VI = 2.7 to 5.5V 2 1.3 1.2 0.4 2 VI = 2.7V to 5.5V, IO = 100mA Note 1 IO = 10mA to 2A Note 1 VFB = 0.65V 1.2 80 ISW = 750 mA ISW = 750 mA Note 1 IO = 10mA to 100mA, VO = 3.3V IO = 100mA to 2A, VO = 3.3V Thermal shutdown Thermal shutdown hysteresis Load transient response Short circuit removal response IO = 100mA to 1A, TA = 25C tR = tF 200ns, Note 1 IO = 10mA to IO = short, TA = 25C Note 1 -10 -10 2.5 65 % 82 87 150 20 +10 +10 C C %VO %VO 0.16 0.2 1.5 87 0.1 0.1 2.9 3.5 0.6 1.8 A %VO/ VI %VO/ IO MHz % A V 2.7 1.05 VO 1.1 VO 5 1.5 2.5 1 Test conditions Min. 784 Typ. 800 Max. 816 600 Unit mV nA V V % mA A A
Symbol FB IFB VI
OVP Over voltage protection hysteresis IQ IO Quiescent current
VINH
Inhibit threshold
Device ON, VI = 2.7 to 5V Device OFF
IINH %VO/VI %VO/IO PWMfS DMAX RDSON-N RDSON-P ISWL
Inhibit pin current Output line regulation Output load regulation PWM switching frequency Maximum duty cycle NMOS switch on resistance PMOS switch on resistance Switching current limitation Efficiency Note 1
TSHDN THYS %VO/IO %VO/IO
Note:
1
Guaranteed by design, but not tested in production.
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Typical performance characteristics
ST1S09
5
Figure 3.
Typical performance characteristics
(L = 3.3 H, CI = 4.7 F, CO = 22 F, unless otherwise specified) Voltage feedback vs temperature Figure 4. Feedback pin bias current vs temp.
840 830 820 810 800 790 780 770 760 -75
VI=5V, IO=10mA VO@1.2V
840 740 640 540 440 340 240 140 40 -60 -75 -50 -25 0 25 50 T [C] 75
VI=5V
VFBK [mV]
IFBK [nA]
-50
-25
0
25
50 T [C]
75
100 125 150 175
100 125 150 175
Figure 5.
Quiescent current non switching vs Figure 6. temperature
Inhibit voltage vs temperature
3 2.5 Iq [mA]
VI=5V
VO@1.2V
1.5 1 0.5 0 -75 -50 -25 0 25 50 T [C] 75 100 125 150 175
VINH [V]
2
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75
ON
OFF
VI=5V, IO=from 10mA to 2A
-50
-25
0
25
50 T [C]
75
100
125
150
175
Figure 7.
Inhibit voltage vs input voltage
Figure 8.
Output voltage vs input voltage
1.40
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2
VI=from 2.7 to 5.5V, IO=2A
VO@1.2V
ON
OFF
1.20 1.00
VO [V]
VINH [V]
0.80 0.60 0.40 0.20
VCC =VINH=from 0 to 5.5V, IO=2A
3
4 VI [V]
5
6
7
0.00 0 1 2 3 4 5 6
VI [V]
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ST1S09
Typical performance characteristics
Figure 9.
Line regulation vs temperature
Figure 10. Load regulation vs temperature
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1
VO@1.2V
VI = from 2.7V to 5.5V, IO = 100mA
1.1 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5
VO@1.2V
VI = 5V, IO from10mA to 2A
line [%VOt/ VI]
load [%VO/ IO]
-75 -50 -25
0
25
50 T [C]
75
100 125 150 175
-75 -50 -25
0
25
50 T [C]
75
100 125 150 175
Figure 11. PWM Switching frequency vs temperature
Figure 12. Maximum duty cycle vs temperature
2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 -75
PWM freq.[MHz]
VO@1.2V
VI=5V, VFB=0.6V
Dmax[%]
90 88 86 84 82 80 78 76 74 72 70 -75
VO@3.3V
-50 -25 0 25 50 75
VI=5V, VFB=0.6V
100 125 150 175
-50
-25
0
25
50 T [C]
75
100 125 150 175
T [C]
Figure 13. Under voltage lock out threshold vs temperature
Figure 14. Efficiency vs output current
4 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 -75
95 85
Efficiency [%]
VO=3.3V VO=1.2V
UVLO [V]
75 65 55 45 35 25 0
VIN=5V
VO@1.2V -50 -25 0 25 50 75
IO=10mA 100 125 150 175
500
1000 Iout [mA]
1500
2000
T [C]
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Typical performance characteristics
ST1S09
Figure 15. Efficiency vs temperature
Figure 16. Over voltage protection vs temperature
100 95 90 85 80 75 70 65 60 55 50 45 40
1.4
VO=3.3V
Resistor 1.2k
from VI and VSW VI=5V, VO=3.3V, CFB=100nF
1.3
VSW=1.2V
VO=1.2V
Efficiency [%]
OVP %VO
1.2 1.1
OVP ON
1 0.9 0.8
VI=5V, IO=100mA
-75 -50 -25
0
25
50
T [C]
75 100 125 150 175
-75
-50
-25
0
25
50
75
100 125 150 175
T [C]
Figure 17. Over voltage protection vs temperature
Figure 18. Over voltage protection hyst. vs temperature
1.4
14
OVP % Hysteresis
Resistor 1.2k
from VI and VSW VI=5V, VO=3.3V, CFB=100nF
1.3
VSW=0.8V
12 10 8 6 4
Resistor 1.2k VSW=0.8V
from VI and VSW VI=5V, VO=3.3V, CFB=100nF
OVP %VO
1.2 1.1
OVP ON
1 0.9 0.8 -75 -50 -25 0 25 50 75 100 125 150 175
OVP ON
2 0 -75 -50 -25 0 25 50 75 100 125 150 175
T [C]
T [C]
Figure 19. Load transient
Figure 20. Inhibit transient
VO
VINH
VO
IO
IO
VI=5V, VO=1.2V, IO=100mA to1A, L=3.3H, CI=4.7F, CO=22F
VI=5V, VINH=0 to 2V, IO=2A, L=3.3H, CI=4.7F, CO=22F, VO=3.3V
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ST1S09
Typical application
6
Typical application
Figure 21. Application circuits
Figure 22. Application circuits
11/18
Application information
ST1S09
7
Application information
The ST1S09 is an adjustable current mode PWM step-down DC/DC converter with internal 2 A power switch, packaged in a DFN6 3x3 mm. The device is a complete 2 A switching regulator with its internal compensation eliminating the need for additional components. The constant frequency, current mode, PWM architecture and stable operation with ceramic capacitors results in low, predictable output ripple. The over-voltage protection circuit acts when the output voltage is over 10 % of the rated voltage and within 200 ns the low side MOSFET will be turned on to clamp the output transient. The current limit for clamping is about 400 mA. When the output voltage drops to about 5 % above the nominal level, the device returns to nominal closed loop switching operation. The open drain Power Good (PG) pin is released when the output voltage is higher than 0.92 x VO_NOM. If the output voltage is below 0.92 x VO, the PG pin goes to low impedance. Other circuits fitted to the device protection are the Thermal Shut-down block, which turns off the regulator when the junction temperature exceeds 150 C (typ), and the cycle-by-cycle Current Limiting, which provides protection against shorted outputs. As an adjustable regulator, the ST1S09's output voltage is determined by an external resistor divider. The desired value is given by the following equation: VO = VFB[1+R1/R2] To utilize the device, only a few components are required: an inductor, two capacitors and the resistor divider. The inductor chosen must be able to reach peak current level without saturating. Its value can be selected while taking into account that a large inductor value increases the efficiency at low output current and reduces output voltage ripple, while a smaller inductor can be chosen when it is important to reduce package size and the total cost of the application. Finally, the ST1S09 has been designed to work properly with X5R or X7R SMD ceramic capacitors both at the input and at the output. These types of capacitors, due to their very low series resistance (ESR), minimize the output voltage ripple. Other low ESR capacitors can be used according to the need of the application without compromising the correct functioning of the device.
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ST1S09
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
ST1S09
DFN6D (3x3) Mechanical Data
mm. Dim. Min. A A1 A3 b D D2 E E2 e L 0.30 0.23 2.90 2.23 2.90 1.50 0.95 0.40 0.50 0.012 3.00 3.00 0.80 0 0.02 0.20 0.45 3.10 2.50 3.10 1.75 0.009 0.114 0.088 0.114 0.059 0.037 0.016 0.020 0.118 0.118 Typ. Max. 1.00 0.05 Min. 0.031 0 0.001 0.008 0.018 0.122 0.098 0.122 0.069 Typ. Max. 0.039 0.002 inch.
7946637B
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ST1S09
Package mechanical data
Figure 23. DFN6 (3x3 mm) footprint recommended data
15/18
Package mechanical data
ST1S09
Tape & Reel QFNxx/DFNxx (3x3) Mechanical Data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 3.3 3.3 1.1 4 8 12.8 20.2 60 18.4 0.130 0.130 0.043 0.157 0.315 Typ. Max. 330 13.2 0.504 0.795 2.362 0.724 Min. Typ. Max. 12.992 0.519 inch.
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ST1S09
Revision history
9
Table 8.
Date
Revision history
Document revision history
Revision 1 2 3 First Issue. Removed incorrect watermark. Modified: Table 6 on page 6. Changes
18-Jun-2007 05-Jul-2007 31-Jan-2008
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ST1S09
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