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STRUCTURE PRODUCTNAME
Silicon Monolithic Integrated Circuit
BU7964GUW
Serial Interface for Mobile Devices Application MSDL3(Mobile Shrink Data Link 3) Deserializer LSI
FUNCTION
FEATURES
*Maximum transmission rate of highspeed differential interface MSDL3 is 1350Mbps. *Support LCD interface with 24bit parallel RGB video mode. *Pixel clock frequency is 4~45MHz
1. Absolute maximum
Parameter Power supply voltage for DVDD Power supply voltage for MSVDD Input voltage Symbol DVDD MSVDD VIN Rated values -0.3 ~ +2.5 -0.3 ~ +2.5 -0.3 ~ DVDD+0.3 -0.3 ~ MSVDD+0.3 -10 ~ +10 300 * -55 ~ +125 Unit V V V V mA mW Remarks
I/O terminals of IOVDD line I/O terminals of MSVDD line
Input current IIN Package power dissipation Pd Without board mounted Preservation temperature Tstg C o *When it uses by Ta=25 C or higher, reduce by 3.0 mW/C (for a single package).
2. Operating Condition
Parameter Supply voltage for DVDD Supply voltage for MSVDD SubLVDS data rate Operating temperature range Symbol VDVDD VMSVDD DR Topr Min 1.65 1.65 120 -30 Typ 1.80 1.80 25 Max 1.95 1.95 450 +85 Unit Remarks V VDVDD=VMSVDD V Mbps/ch
C
These goods are specific machines. Because the exclusive goods which are specially designed for the device are considered. Whether that machine, device corresponds to strategic goods to decide as the foreign exchange and foreign trade control law. You must have it judged. As for contents of mention of these materials. A service in the foreign exchange and foreign trade control law (Technology in the design, the manufacture and the use). Be careful of handling because it is likely to correspond. This product is not designed against radioactive ray. S
REV. A
2/4 3. ELECTRICAL CHARACTERISTICS 3.1 CMOS INOUT CHARACTERISTICS Ta=25, DVDD=MSVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted Symbol Min Typ Max Unit Conditions Parameter `L' input voltage1 `H' input voltage1 `L' output voltage1 `H' output voltage1 `L' output voltage2 `H' output voltage2 `L' output voltage3 `H' output voltage3 PCLK frequency1 PCLK frequency2 PCLK frequency3 PCLK duty cycle Data setup to PCLK Data hold to PCLK VIL1 VIH1 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 fPCLK1 fPCLK2 fPCLK3 DPCLKO tDSO tDHO DGND 0.7xDVDD DGND 0.7xDVDD DGND 0.7xDVDD DGND 0.85xDVDD 4.0 8.0 12.0 45 9.0 9.0 50 0.3xDVDD DVDD 0.3xDVDD DVDD 0.3xDVDD DVDD 0.15xDVDD DVDD 15.0 30.0 45.0 55 V V V V V V V V MHz MHz MHz % ns ns XSD, PLL_BW[1:0], LS[1:0], F_XS terminals IO=1mA IO=-1mA IO=3mA IO=-3mA IO=100uA IO=-100uA LS[1:0]=LL LS[1:0]=LH LS[1:0]=HL PCLK terminals, CL=10pF PD[26:0] terminals, CL=10pF PCLK terminals F_XS=L, PCLK,CPO, PD[26:0] terminals F_XS=H, PCLK,CPO, PD[26:0] terminals PCLK,CPO, PD[26:0] terminals
3.2
MSDL3 RX CHARACTERISTICS Ta=25, DVDD=MSVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted Symbol Min Typ Max Unit Conditions Parameter Vdiff_rx Vcm_rx Ipull_rx Vlink_rx DR_rx 70 0.6 12 0.2 120 100 0.9 30 0.3 200 1.2 90 0.4 450 mVpp V A V Mbps/ch
Differential voltage range Common mode voltage range RX pull down current Threshold voltage of RX link detection SubLVDS data rate
3.3
CURRENT COMSUMPTION Parameter Ta=25, DVDD=MSVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted Symbol Min Typ Max Unit Conditions Iop_sht_x Iop_stb_x 0.2 41.8 10.0 90.0 A A XSD=L XSD=H
Shutdown current Standby current
Active current of LS[1:0]=LL, PLL_BW[1:0]=HL, Iop_act_x1 17.6 24.0 mA 1ch27bit format fPCLK=15MHz, CL=10pF, *1 Active current of LS[1:0]=LH, PLL_BW[1:0]=HL, Iop_act_x2 28.0 36.8 mA 2ch27bit format fPCLK=30MHz, CL=10pF, *1 Active current of LS[1:0]=HL, PLL_BW[1:0]=HL, Iop_act_x3 36.0 48.6 mA 3ch27bit format fPCLK=45MHz, CL=10pF, *1 *1 : Total operating current(IDVDD+IMSVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555.
REV. A
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4. PACKAGE VIEW
1PIN MARK
5. PIN LIST
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8 Pin name TEST0 PD19 PD17 PD16 PD14 PD13 PD10 CPO PCLK PD18 PD15 PD12 PD11 PD9 PD8 PD22 PD20 PLL_BW0 DVDD N.C. F_XS PD7 PD6 Pin No. D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 Pin name PD23 PD21 N.C. DGND DGND DVDD PD4 PD5 PD25 PD24 DVDD DGND MSGND N.C. PD1 PD3 PD26 LS0 MSVDD MSGND MSVDD N.C. XSD PD2 Pin No. G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Pin name LS1 PLL_BW1 D2D1CLKD0N.C. PD0 N.C. N.C. D2+ D1+ CLK+ DO+ DRVR TEST1
LOT NO.
5.00.1
0.9 MAX
5.00.1
S
BU7964
0.08
S
0.750.1 63-0.2950.05 0.05 M S AB
H G E D C B A 1 2 F
P = 0.5x7 0.5
B 3 4 5 6 7 8 (UNIT:mm)
VBGA063W050
6. SYSTEM BLOCK DIAGRAM
P = 0.5x7
0.750.1
A
0.10
REV. A
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(1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operatingconditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor
7. USAGE PRECAUTIONS
These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter.
(12) No Connecting input terminals In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line. (13) Rush current at power supply turning on Because the rush current might flow momentarily in CMOS IC when internal logic is irregular at the power supply Note the capacity of the power supply coupling, the power supply, and width and drawing the GND pattern wiring. (14) Rush current of the order of turning on the power supply Because the rush current might flow momentarily by the order of turning on the power supply and the delay in IC with two or more power supplies Note the capacity of the power supply coupling, the power supply, and width and drawing the GND pattern wiring.
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
REV. A
Notice
Notes
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