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L5953
Multiple switching voltage regulator
Features

PWM: adjustable 2.5/10V - 1A switching voltage regulator External POWER MOS ability for output current enhancement Synchronization function REG1- Linear low drop 3.3/5V - 250mA STBY voltage regulator (low current consumption) with RESET REG2- Linear voltage regulator 1.5V to 3.3V externally adjustable - 300mA maximum current HSD1 : 500mA High side driver HSD2 : 200mA High side driver SPI Interface SPI Diagnostics HSD1, HSD2 Double switching frequency SPI selectable Double inpuT LVW
PowerSO36

Protections

Over voltage protection Internal current limiting Thermal shutdown ESD
SPI functions
Description
The L5953 is the integration of one switching regulator, two linear voltage regulators, two low voltage warnings and two high side drivers. It has a stand-by operation mode (low current consumption) where only the stand-by voltage regulator plus the low voltage warnings are active. The other regulators and high side drivers are controlled by the SPI interface.
Input controls - Turn-on/off PWM - Turn-on/off REG2 - Turn-on/off HSD1 - Turn-on/off HSD2 - Switching frequency selection f1- f2 Output functions: - HSD1 & HSD2 short to gnd, open load and short to battery (Test mode) - Thermal warning Device summary
Part number L5953
Table 1.
Package PowerSO36
Packing Tray
September 2007
Rev 2
1/31
www.st.com 1
Contents
L5953
Contents
1 2 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 2.2 2.3 2.4 2.5 2.6 REG1 stand-by regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low voltage warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REG2 linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM step down voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . 15
3 4
Internal pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Enable (WREN and Write Disable (WRDI)) . . . . . . . . . . . . . . . . . . 18
5
Summary of the main operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Operation A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operation H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IRQ - Interrupt Request Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 6.2 REG1 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Feedback resistors for REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/31
L5953
Contents
6.3
External components for PWM regulator . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1 6.3.2 6.3.3 Bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 6.5
Free-wheeling diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of tables
L5953
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Diagnostic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Diagnostic register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Diagnostic register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/31
L5953
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low voltage warning block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 HSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI & IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write enable latch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Test mode diagnostic procedure start (after a write enable latch sequence. . . . . . . . . . . . 22 Read the diagnostic registerCase1: after a test mode diagnostic procedure start . . . . . . . 22 Diagnostic procedure start (after write enable latch sequence operation A) . . . . . . . . . . . 23 Read the diagnostic RegisterCase2: after a diagnostic procedure start. . . . . . . . . . . . . . . 23 Write the status register (after a write enable latch sequence operation A) . . . . . . . . . . . . 23 Read the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block and application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block diagram and application with external Power MOS . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSO36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5/31
Block diagram and electrical specifications
L5953
1
Block diagram and electrical specifications
Figure 1. Block diagram
S1 W1 S2 W2 VDD-LIN VDD-SW STCAP CT RES FGND REC1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
VOLTAGE WARNING
VSTBY ADJ
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP
HSD2 HSD2
DRAINOUT
VSW GATEIN GATEOUT FB REC2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP OSCILLATOR & SYNC
VSPI IRQ
SPI INTERFACE
SWGND GND
Q
D
S
C
VLR
FBLR
VIN
SYNC
DGND
D01AU1330A
Table 2.
Symbol VDD VSPI IO Vinlog RESR Top Tstg Tj
Absolute maximum ratings
Parameter DC operating supply voltage Transient supply over voltage (250ms) Supply voltage for SPI I/O Voltage regulator output current Input voltage (C, D, Q, S, SYNC) Output capacitor series e.g. resistance (linear reg.) (allowed range) Operating temperature range Storage temperature ranges Operative junction temperature Value -0.6 to 30 50 -0.6 to 6 Internally limited 0 to 6 From 0.2 to 10 -40 to 85 -55 to 150 -40 to 150 V W C C C Unit V V V
Table 3.
Symbol Rthj-case
Thermal data
Parameter Thermal resistance junction to case Value 1.7 Unit C/W
6/31
L5953 Figure 2. PIN connections
FGND S2 S1 W2 W1 RES CT D C Q S DGND IRQ HSD2 VDD-LIN N.C. HSD1 SWGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Block diagram and electrical specifications
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D02AU1345A
ADJ VSTBY VSPI STCAP FB COMP FBLR VIN VLR SYNC STRAP GATEOUT GATEIN VSW GND N.C. DRAINOUT VDD-SW
Table 4.
Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PIN function
Pin name FGND S2 S1 W2 W1 RES CT D C Q S DGND IRQ HSD2 VDD-LIN N.C. HSD1 SWGND VDD-SW DRAINOUT Analog ground Input voltage for LVW2 Input voltage for LVW1 LVW2 output LVW1 output Reset Timing capacitor SPI serial input SPI clock SPI serial output SPI chip select SPI ground Interrupt HSD2 output Battery Not connected HSD1 output Switching ground PWM battery Drain of the external MOS Function
7/31
Block diagram and electrical specifications Table 4.
Pin number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 N.C. GND VSW GATEIN GATEOUT STRAP SYNC VLR VIN FBLR COMP FB STCAP VSPI VSTBY ADJ
L5953
PIN function (continued)
Pin name Not connected Ground Source of the external MOS Gate of the internal MOS Switching output for power mos gate Bootstrap Synchronization REG2 linear voltage regulator output REG2 linear voltage regulator input REG2 linear voltage regulator feedback PWM compensation PWM feedback ST-CAP Supply voltage for SPI I/O REG1 stand-by linear voltage regulator output 3.3V/5V REG1 voltage select Function
Table 5.
Symbol
Electrical characteristics (Tamb = 25C, VDD = 14.4V)
Parameter Test condition W1, W2, RES, IRQ, not active; REG2, HSD1, HSD2, PWM off; S, C, D fixed at high/low logic level 150 Min. Typ. Max. Unit
IQ,STBY
Quiescent current with regulators and high-side drivers off Thermal shutdown junction temperature
100
A
Tsd
C
SMPS.PWM (Tamb = 25C, VDD = 14.4V, Vo = 5V; unless otherwise specified.) Vo,min Vo,max Vref,PWM Vi Vo Vo Vd ILim Minimum output voltage Maximum output voltage Voltage reference Input voltage range Line regulation Load regulation Dropout voltage between Pin 19 and Pin 23 Current limit Vo = 5V; Io = 0.5A Io = 0.5A Vo = 5V; Io = 0.2A to 0.5A Io = 0.5A, Vo = 5V Io = 1A, Vo = 5V 1.2 6 Io = 200mA Io = 200mA 2.4 9.6 2.5 10 1.275 18 100 50 0.5 1 2.6 10.4 V V V V mV mV V V A
8/31
L5953
Block diagram and electrical specifications
Table 5.
Symbol h SVR Oscillator f1 f2
f -------V i f -------T j
Electrical characteristics (continued) (Tamb = 25C, VDD = 14.4V)
Parameter Efficiency Supply voltage ripple rejection Test condition f = 260kHz; Io = 0.5A f = 400kHz; Io = 0.5A Vi = 1Vrms; fripple = 300Hz; Io = 0.4A Min. Typ. 90 86 50 Max. Unit % % dB
Switching frequency Switching frequency Voltage stability of switching frequency Temperature stability of switching frequency VDD = 8 to 18V Tj = -40C to 85C
240 375
260 400 Tbd Tbd
280 425
kHz kHz % %
Sync VIL VIH VOL VOH ISLAVE TW Low input voltage High input voltage Low output voltage High output voltage Slave sink current Output pulse width ISOURCE=1.5mA 4 100 300 2 0.4 0.8 V V V V A ns
REG1 - 3.3V/5V STBY linear voltage regulator VSTBY Vline Vload Vdropout Ilim SVR Output voltage Line regulation Load regulation VSTCAP - VSTBY Current limit Supply voltage rejection no load; ADJ pin = open no load; ADJ pin = VSTBY pin no load; 7 < Vdd < 26V 5mA < Io < 250mA Io = 100mA, Vo = 5V Io = 100mA, Vo = 3.3V Out short to GND VDD = 1Vrms: f = 300Hz Io = 250mA 300 55 4.9 3.20 5 3.3 5 12 0.36 0.47 5.1 3.4 50 80 0.5 0.65 V V mV mV V mA dB
REG2 - Linear voltage regulator 1.5V to 3.3V no load; 4.75 VIN 16V; 1+ (R5/R6) = 2.588 VLR Linear regulator output voltage no load; 3.135 VIN 16V; 1+ (R5/R6) = 1.176 3.2 1.45 3.3 1.5 3.4 V 1.55
9/31
Block diagram and electrical specifications
L5953
Table 5.
Symbol
Electrical characteristics (continued) (Tamb = 25C, VDD = 14.4V)
Parameter Test condition IO = 150mA 1.5V VLR 2V IO = 300mA 1.5V VLR 3.3V Load regulation 5mA IO 300mA 4.75V VIN 16V; 1.5V VLR 3.3V no load; 4.75V VIN 16V; 1.5V VLR 3.3V Min. 3.135 4.75 Typ. Max. 16 16 Unit V V
VIN
Input voltage
Vload
12
mV
Vline Vref,REG2 ILim
Line regulation Voltage reference Current limit
1 1.275
mV V mA
Out short to ground VIN = 5Vdc, 0.5Vacpp, 300Hz IO = 300mA; 1.5V VLR 3.3V VIN = 3.3Vdc, 0.5Vacpp, 300Hz IO = 150mA; 1.5V VLR 2V
400 55 55
dB dB
SVR
Supply voltage rejection
HSD1 Vsat, peak Ilim Lload HSD2 Vsat, peak Ilim Lload Saturation voltage Current limit Load inductance IO = 0.2A 300 100 300 mV mA mH Saturation voltage Current limit Load inductance IO = 0.5A 600 100 350 mV mA mH
Voltage warning Vst Vsth VSL ISH ISI Reset VRT VRTH VRL Reset threshold voltage Reset threshold hysteresis Reset output voltage Io = 1mA 0.95 x VSTBY 0.02 x VSTBY 0.4 V V V Sense low threshold Sense threshold hysteresis Sense output low voltage Sense output leakage Sense input current Io = 1mA VW = 5V; VSI 1.5V VSI=5V 1 1.245 1.275 1.305 35 45 60 0.4 10 V mV V A A
10/31
L5953
Block diagram and electrical specifications
Table 5.
Symbol IRH VCTth VCThy ICT1 RCT2
Electrical characteristics (continued) (Tamb = 25C, VDD = 14.4V)
Parameter Reset output leakage Delay comparator threshold Delay comparator threshold hysteresis Timing capacitor output source current Timing capacitor output pull-down equivalent resistor Test condition VRT = VSTBY 0.5 x VSTBY 180 7.5 150 mV A Min. Typ. Max. 10 Unit A
Table 6.
Symbol HSD1W1 HSD1W2 HSD1W2 TEST HSD2W1 HSD2W2 HSD2W3 THW
Diagnostic parameters
Parameter High side driver 1 overcurrent warning activation High side driver 1 open load warning activation High side driver 1 vdd short warning activation in test mode High side driver 2 overcurrent warning activation High side driver 2 open load warning activation High side driver 2 vdd short warning activation in test mode Thermal warning activation HSD2 output voltage in test mode HSD2 in test mode measure VVDD-LIN-VHSD1 1 HSD1 output voltage in test mode HSD1 in test mode measure VVDD-LIN-VHSD1 1 Test condition Min. Typ. 1 3 1.5 0.5 3 1.5 145 2 2 Max. Unit A V V A V V C
IRQ - Interrupt request pin IRQ-L IRQ-H IRQ low voltage IRQ leakage Io = 1mA Virq = 5V 0.4 1 V A
Table 7.
Symbol
SPI interface
Alt Parameter Test conditions Min. Max. Unit
Recommended DC operating voltage VSPI Supply voltage for SPI I/O 3 5.5 V
Input parameters (Tamb = 25C, f = 1MHz) CIN CIN tLPF Input capacitance (D) Input capacitance (others pins) Input signal pulse width 8 6 10 pF pF ns
11/31
Block diagram and electrical specifications Table 7.
Symbol
L5953
SPI interface (continued)
Alt Parameter Test conditions Min. Max. Unit
DC characteristics (Tamb = -40 to 85C, VSPI = 3V to 5.5V) ILI ILO VIL VIH VOL VOH Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2mA IOH = -2mA 0.8VSPI -0.3 0.7VSPI 5 2 0.3VSP
I
A A V V V V
VSPI+1 0.2VSPI
AC characteristics (Tamb = -40 to 85C, VSPI = 3V to 5.5V tSCLH tCLSH tCH tCL tCLCH tCHCL tDVCH tCHDX tDLDH tDHDL tSHSL tSHQZ tQVCL tCLQX tQLQH tQHQL tSU tSH tWH tWL tRC tFC tDSU tDH tRI tFI tCS tDIS tV tHO tRO tFO S setup time S hold time Clock high time Clock low time Clock rise time Clock fall time Data In setup time Data In hold time Data In rise time Data in fall time S deselect time Output disable time Clock low to output valid Output hold time Output rise time Output fall time 0 100 100 4.5V < VSPI < 5.5V 3V < VSPI < 4.5V 200 250 150 250 50 50 1 1 50 50 200 300 1 1 ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns
Figure 3.
AC testing input output waveforms
0.8VSPY 0.7VSPY
0.2VSPY
0.3VSPY
D03AU1479
12/31
L5953 Figure 4. SPI clocking scheme
Block diagram and electrical specifications
S
(MODE 0: CPOL=0,CPHA=0)
C
C
(MODE 3: CPOL=1,CPHA=1)
D Q
MSB
6
5
4
3
2
1
0
Figure 5.
S
Output timing
tCH C tCLQX tQVCL Q MSB OUT MSB-1 OUT tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
(CPOL=0, CPHA=0)
AI01070B
Figure 6.
Serial input timing
tSHSL
S tSLCH C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tCLSH
HIGH IMPEDANCE Q
(CPOL=0, CPHA=0)
AI01071
13/31
Functional description
L5953
2
2.1
Functional description
REG1 stand-by regulator
The stand-by regulator (Figure 7.) output voltage can be 5V or 3.3V. It is externally selectable by means of the ADJ pin: - leaving the ADJ pin open, the output voltage is 5V; - connecting the ADJ pin to the Vstby pin the output voltage becomes 3.3V. This regulator is supplied by STCAP pin and provide the reset information. It has a current protection which limits the maximum allowable output current.
2.2
Reset
The RES pin (Figure 8.) is an open collector that is activated (that is forced to zero) when the stand-by regulator is not in regulation (including thermal shutdown and faults). The indication that REG1 is in regulation is delayed by a time set up by the external capacitor CT. When the RES is switched on, HSD1, HSD2, REG2, PWM are turned off and until the RES is forced to zero only the REG1 and low Voltage Warnings are active.
2.3
Low voltage warning
This circuit is able to sense two different voltages through external resistors to increase the overall flexibility. (Figure 9.) If S1 pin voltage is higher than Vst, the output of mos M1 is off: W1 is floating and can be pulled up by an external resistor. If S1 pin voltage goes down and becomes lower than Vst, the mos M1 is turned on and forces W1 to zero. The same thing happens for S2 - W2. The outputs W1 and W2 can be connected together to get a single output.
2.4
REG2 linear voltage regulator
REG2 is a linear voltage regulator (Figure 7.) with a dedicated supply pin VIN. The output voltage (between 1.5V and 3.3V) is fixed by an external divider. It can be turned on/off by SPI. It has a current protection which limits the maximum allowable output current.
2.5
High side drivers
Two high-side driver (Figure 10.) with charge pump controlled by SPI are available inside L5953. They are protected against short to ground: the short circuit protection limits the maximum output current. A diagnostic procedure is available to detect open load, short to battery and overcurrent. Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal operation of the device. (see 4.2 on page 18)
14/31
L5953
Functional description
2.6
PWM step down voltage regulator
The switching regulator (Figure 11.) inside the L5953 is a voltage control mode (also known as a direct duty cycle) Buck regulator: the error signal coming from the error amplifier is compared with a sawtooth to set on and off times of the power switch. The feedforward control is introduced to get a quickly response to input voltage changes: the sawtooth has a fixed frequency and an amplitude variable with the battery voltage. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode.
2.6.1
Error amplifier and compensation network
The error amplifier (EA) is a voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V bandgap voltage) and whose inverting input and output are externally available for feedback and frequency compensation.
15/31
Internal pin connections
L5953
3
Internal pin connections
Figure 7. Linear regulators
STCAP VREF 1.275V VSTBY CONTROLLER POWER MOS VSTBY VSTBY
ADJ
FGND FBLR VLR
LINEAR REGULATOR CONTROLLER VREF 1.275V POWER MOS
VIN
D03AU1493
Figure 8.
Reset
7.5A
Vref 2.5V/1.65V
RES
CT
FROM VST-BY Vref 1.275V
D03AU1480
Figure 9.
Low voltage warning block diagram.
V1 Vref =1.275V S1 W1 + M1
V2 Vref =1.275V S2 W2 + M2
D03AU1478
16/31
L5953 Figure 10. HSD
HSD1 HSD1 CONTROLLER POWER MOS HSD1
Internal pin connections
VDD-LIN HSD2 CONTROLLER POWER MOS HSD2 HSD2
D01AU1333
Figure 11. PWM
STRAP ERROR AMPLIFIER COMP FB VDD-SW
RS2 CURRENT SENSING DRAINOUT RS1
VREF 1.275V PWM CONTROLLER FROM THE OSCILLATOR POWER MOS
VSW
GATEIN GATEOUT
D03AU1482
Figure 12. SPI & IRQ
IRQ S Q SPI INTERFACE D C DGND
D03AU1481
17/31
SPI interface
L5953
4
4.1
SPI interface
Signals description
The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3. Serial output (Q). The output pin is used to transfer data serially out of the L5953. Data is shifted out on the falling edge of the serial clock. Serial input (D). The input pin is used to transfer data serially into the device. It receives instructions, addresses, and data to be written. Input is latched on the rising edge of the serial clock. Serial clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is deselected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After power up, the chip is at the deselect state. SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by regulator VSTBY. The SPI is reset by an internal signal whose buffered version is RES. (See Figure 12.)
4.2
Operations
All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid instruction (one not contained in table 1) leaves the chip as previously selected.
4.3
Write enable (WREN and write disable (WRDI))
The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is reset under all the following conditions: - - - Power on - WRDI instruction executed
As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and enters a wait mode until it is deselected.
18/31
L5953 Table 8.
.
SPI interface Instruction set
Instruction WREN WRDI WSTA RDIA RSTA Description Set write enable latch Reset write enable latch Write status register Read diagnostic register Read status register Instruction Format 00000110 00000100 00000010 00000101 00000011
Table 9.
s15 REG 2 s14 HSD 1
Status register
s13 HSD 2 s12 TBD s11 TBD s10 s9 s8 s7 TBD s6 TBD s5 TBD s4 TBD s3 TBD s2 TBD s1 s0
.
PWM PWM TBD freq.
Test START mode DIAG
Table 10.
Status register description
0 1 Regulator on HSD1 on HSD2 on
s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1
REG2 linear voltage regulator 1.5 to 3.3V High side driver 1 High side driver 2 TBD TBD PWM switching frequency PWM voltage regulator TBD TBD TBD TBD TBD TBD TBD Test mode
Regulator off HSD1 off HSD2 off
260kHz PWM1 off
400kHz PWM1 on
Test mode off
Test mode on (1) Starts the diagnostic procedure: - in test mode if s1=1; - during normal operation if s1=0 If s1=0 and s0=1, must be s14 = 1 (HSD1 ON) and s13=1 (HSD2 ON)
s0
Diagnostic
Diagnostic off
1. In this case the bits s15 - s2 are internally set to 0 (regulators and high side drivers are in off condition)
19/31
SPI interface Table 11.
d7 Test mode
.
L5953 Diagnostic register
d6 HSD1W1 d5 HSD1W2 d4 HSD1W3 d3 HSD2W1 d2 HSD2W2 d1 HSD2W3 d0 THW
Table 12.
.
Diagnostic register description
0 The diagnostic register is referred to a test performed during the normal working of the L5953 If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: bit value meaningless; If d7=1: HSD1 in normal condition If d7=0: HSD1 in normal condition; If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: HSD2 in normal condition If d7=0: bit value meaningless If d7=1: HSD2 in normal condition; 1 The diagnostic register is referred to a test performed in Test mode If d7=0: HSD1 is in overcurrent If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: an open load is present on HSD1 If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD If d7=0: HSD2 is in overcurrent; If d7=1: bit value meaningless If d7=0: bit value meaningless If d7=1: an open load is present on HSD2 If d7=0: bit value meaningless If d7=1: HSD1 is shorted to the supply voltage VDD Over temperature protection activated(Tj>150C)
d7
Test mode
d6
HSD1W1
d5
HSD1W2
d4
HSD1W3
d3
HSD2W1
d2
HSD2W2
d1
HSD1W3
d0
Thermal warning
Normal condition
20/31
L5953
Summary of the main operations
5
5.1
Summary of the main operations
Operation A

Test mode diagnostic procedure start 1) WREN instruction (Figure 13.) 2) WSTA instruction (Figure 14.)
5.2
Operation B
Read the diagnostic register Case1: after a test mode diagnostic procedure start 1) RDIA instruction (Figure 15.) 2) Diagnostic register output (Figure 15.)
Note:
An operation B must follow an operation A. The delay between the end of the operations A to the start of the operations B must be longer than 100S
5.3
Operation C
Write the status register 1) WREN instruction (Figure 13.) 2) WSTA instruction (Figure 18.)
5.4
Operation D
Read the status register 1) RSTA instruction (Figure 19.) 2) Status Register output (Figure 19.)
5.5
Operation E
Diagnostic procedure start 1) WREN instruction (Figure 13.) 2) WSTA instruction (Figure 16.)
5.6
Operation F
Read the diagnostic register Case 2: after a diagnostic procedure start 1) RDIA instruction (Figure 17.) 2) Diagnostic register output (Figure 17.) An operation F must follow an operation E, if the IRQ pin is not activated. The delay between Operation E and Operation F must be longer than 100s. To be recognized, the fault must be present without interruptions, during all the delays mentioned. After an Operation F, the bit s0 of the status register is reset (0)
21/31
Summary of the main operations
L5953
5.7
Operation G
Write operation disabled 1) WRDI instruction (Table 8.)
5.8
Operation H
Read the diagnostic register case 3: after an IRQ pin activation 1) RDIA instruction (Figure 17.) 2) Diagnostic register output (Figure 17.) The delay between the IRQ activation and operation F must be longer than 100s
Figure 13. Write enable latch sequence
S
00 01 02 03 04 05 06 07
C CPOL=0 CPHA=0 D
HIGH IMPEDANCE
D03AU1483
Q
Figure 14. Test mode diagnostic procedure start (after a write enable latch sequence)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1484
Figure 15. Read the diagnostic registerCase1: (after a test mode diagnostic procedure start)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
C
INSTRUCTION
D
DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE
Q
d7
d6
d5
d4
d3
d2
d1
d0
D03AU1485
22/31
L5953
Summary of the main operations Figure 16. Diagnostic procedure start (after write enable latch sequence operation A)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1486
Figure 17. Read the diagnostic RegisterCase2: during the normal working of the L5953 (after a diagnostic procedure start, see Figure 16)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
C
INSTRUCTION
D
DIAGNOSTIC REGISTER OUT HIGH IMPEDANCE
Q
d7
d6
d5
d4
d3
d2
d1
d0
D03AU1487
Figure 18. Write the status register (after a write enable latch sequence operation A)
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION STATUS REGISTER s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
D
Q
HIGH IMPEDANCE
D03AU1488
Figure 19. Read the status register
CPOL=0, CPHA=0 S
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
D
STATUS REGISTER OUT HIGH IMPEDANCE
Q
s15
s14
s13
s12
s11
s10
s9
s8
s7
s6
s5
s4
s3
s2
s1
s0
D03AU1489
23/31
Summary of the main operations
L5953
5.9
IRQ - Interrupt request pin

It is an open drain pin activated (low) every time a variation occurs in the diagnostic register. Purpose: to alert the P that one or more warning bit of the diagnostic register has changed from 0 to 1 or from 1 to 0. An activation of this pin puts the bit s0 of the status register to 1 (start diagnostic) like an operation e (diagnostic procedure start). Then an operation F has to be executed without an operation E before. After an operation F, the IRQ pin is deactivated, and goes to 1 if connected to a pull-up resistor.
24/31
L5953
Application note
6
Application note
Figure 20. Block and application diagram
C2 C5 D1 C3 C11
VDD S1 W1 S2 W2
C1
VDD-LIN
VDD-SW
STCAP
CT
RES FGND VSTBY C4 ADJ
VOLTAGE WARNING
REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP C6 DRAINOUT VSW GATEIN D2 L1 Vo R1 C7
HSD2 HSD2
GATEOUT FB VSPI IRQ REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP OSCILLATOR & SYNC SWGND GND R4 C9
R2 R3
SPI INTERFACE
C8
Q
D
S
C
VLR C10
FBLR R5 R6
VIN
SYNC
DGND
D01AU1331B
Figure 21. Block diagram and application with external power MOS
C2 C5 D1 C3
VDD S1 W1 S2 W2
C1 VDD-LIN
VDD-SW
STCAP
CT
RES FGND VSTBY C4 ADJ
VOLTAGE WARNING
REG1 ST-BY LINEAR VOLTAGE REGULATOR 3.3-5V/250mA
HSD1 HSD1 PWM STEP DOWN REGULATOR 2.5-10V/1A STRAP C6 DRAINOUT VSW D2 L1 Vo R1 C7
HSD2 HSD2
GATEIN GATEOUT FB VSPI IRQ REG2 LINEAR VOLTAGE REGULATOR 1.5-3.3V/300mA COMP R4 OSCILLATOR & SYNC SWGND GND
M1
R2
SPI INTERFACE
C9
R3
C8 Q D S C VLR C10 FBLR R5 R6 VIN SYNC DGND
D01AU1332B
25/31
Application note Part list on evaluation board
C1 = 470 F C7 = 470 F ESR=65 m R1 = 2.2 k L1 = 180 H C2 = 220 nF C8 = 56nF R2 = 2 x 1.5 k in parallel C3 = 470 F C9 = 2.7 nF R3 = 10 k D1 = 1N4007 or MBR160 C4 = 10 F C10 = 10 F R4 = 220 k D2 = MBR360 C5 = 1 F C11 = 4.7 nF R5 = 3.3 k
L5953
C6 = 100 nF
R6 = 1 k
6.1
REG1 output voltage
VSTBY = 5V if pin ADJ left floating VSTBY = 3.3V if pin ADJ is connected to the pin VSTBY Timing capacitor The value for this capacitor has to be chosen according the wanted power-on delay Td: I CT1 T d C11 = --------------------------------------------------------------( 0.5 V STBY ) + V CTLHy where ICT1 is the source current used to charge the timing capacitor and VSTBY is the REG1 output voltage.
6.2
Feedback resistors for REG2
V LR R5 = R6 --------------------------- - 1 V ref, REG2 where VLR is the required output voltage for REG2.
6.3
6.3.1
External components for PWM regulator
Bootstrap capacitor
The suggested value for the bootstrap capacitor is C6 = 100nF Here following you find the criteria for the selection of the inductor L1, the free-wheeling diode D2, the output filter capacitor C7, the feedback resistor R1, R2 and the compensation network R3, C8, R4, C9 to have a Buck regulator working in continuous mode. Continuous mode operation is recommended in order to reduce the stress of the output capacitor and of the free-wheeling diode.
6.3.2
Inductor selection
The minimum value of the inductor L7 has to be so that the maximum inductor current ripple IL,max is 20% to 30% of the maximum load current load Io,max.The maximum ripple is present when the switching frequency is minimum (fsw,min) and the input voltage is maximum (Vin,max) so the minimum value for the inductor Lmin is:
26/31
L5953
Application note
VO VO 1 L min = -------------------- 1 - ----------------- ------------------I L, max V i, max f sw, min
6.3.3
Output capacitor selection
The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to I L, max V c = --------------------------------------8 C7 f sw, min and a resistive contribute given by the ESR of the capacitor and which is equal to V ESR = ESR I L, max VC fixes the value for C7 while VESR limits the ESR of the capacitor.Usually the capacitor is chosen so that the total ripple on the output regulated voltage Vo is equal to 1% of the value of Vo. If Vripple is the maximum allowed voltage ripple on Vo then it should result: V ripple V c + V ESR
2 2
More often the minimum value of C7 is imposed by other considerations such as to get a good dynamic behavior of the output voltage in case of large load variations.
6.4
Free-wheeling diode
The diode must withstand an average current Id equal to Id = Ilim (1- Dmin) where Ilim is the current of intervention of the short circuit protection and Dmin is the minimum duty cycle. As Dmin is very low, the current Id can be assumed equal to Ilim.
6.5
Compensation network
In continuous mode, the voltage controlled buck converter shows two poles due to the output LC filter and one zero due to the ESR of the output capacitor. The suggested compensation network introduces two zeros and two poles: - - the zeros compensate the double poles of the LC filter one pole compensates the zero due to ESR of the output capacitor
the second pole is nominally located in the origin which means an infinite gain at frequency null. In the reality the DC value of the closed loop gain can not be greater than the DC value of the EA open loop gain and the pole is located at very low frequency. The values for the components of the compensation network can be fixed when the inductor L1 and the output capacitor C7 are chosen. The necessary steps are:
27/31
Application note 1. Fix the cross-over frequency fC of the overall loop gain. Usually: f c = 0.1 f sw,min where fsw,min is the minimum switching frequency 2. Calculate the high frequency error amplifier gain L1 G c = 0.25 f c 2 -----------ESR 3. Chose R3 and calculate
L5953
L1 C7 C8 = 2 ---------------------R3 The value for R3 has not to be very high (for example 10K) so to limit the error due to an error amplifier input offset current. 4. Calculate R3 R p = -------------------------------------------2 L1 ------------ ------- - 1 ESR C7 VO R1 = R p -------------------------V ref, PWM Rp R2 = ---------------------------------V ref,PWM 1 - -----------------------VO 5. Finally calculate R4 = G C R1 and L1 C7 C9 = 2 ---------------------R4
28/31
L5953
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 22. PowerSO36 mechanical data and package dimensions
DIM. A a1 a2 a3 b c D D1 E E1 E2 E3 e e3 G H h L N s 0.8 0 15.50 5.80 0.65 11.05 0.10 15.90 0.6102 1.10 1.10 0.0315 10 (max) 8 (max) 0 0.22 0.23 15.80 9.40 13.90 10.90 0.10 mm MIN. TYP. MAX. 3.60 0.30 3.30 0.10 0.38 0.32 9.80 14.5 2.90 6.20 0.2283 0.0256 0.4350 0.0039 0.6260 0.0433 0.0433 0.0087 0.0091 0.3701 0.5472 0.0039 MIN. inch TYP. MAX. 0.1417 0.0118 0.1299 0.0039 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441
OUTLINE AND MECHANICAL DATA
16.00 0.6220
11.10 0.4291
PowerSO-36
Note: "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions are "a3", "E" and "G".
0096119 C
29/31
Revision history
L5953
8
Revision history
Table 13.
Date 25-Mar-2003 04-Sep-2007
Document revision history
Revision 1 2 Initial release. Layout changes and text mofifications. Changes
30/31
L5953
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