View PT6311-LQ_4853296.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PT6311 VFD Driver/Controller IC
DESCRIPTION
PT6311 is a Vacuum Fluorescent Display (VFD) Controller driven on a 1/8 to 1/16 duty factor housed in 52-pin plastic QFP Package. Twelve segment output lines, 8 grid output lines, 8 segment/grid output drive lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro computer. Serial data is fed to PT6311 via a three-line serial interface.
FEATURES
CMOS Technology Low Power Consumption Key Scanning (12 x 4 matrix) Multiple Display Modes: (12 segments, 16 digits to 20 segments, 8 digits) * 8-Step Dimming Circuitry * LED Ports Provide (5 channels, 20mA max.) * 4- Bits General Purpose Input Ports Provided * Serial Interface for Clock, Data Input, Data Output, Strobe Pins * No External Resistors Needed for Driver Outputs * Available in 52pins QFP and LQFP * * * *
APPLICATIONS
* Microcomputer Peripheral Devices
BLOCK DIAGRAM
Con tro l DIN DOUT CLK STB VDD Ser ial Data Inter face SG 1/KS 1 SG 2/KS 2 SG 3/KS 3 SG 4/KS 4 SG 5/KS 5 SG 6/KS 6 SG 7/KS 7 SG 8/KS 8 SG 9/KS 9 SG 10/KS 10 SG 11 /K S11 SG 12/KS 12 SG 13/G R1 6 SG 14/G R1 5 SG 15/G R1 4 SG 16/G R1 3 SG 17/G R1 2 SG 18/G R11 SG 19/G R1 0 SG 20/G R9 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8
Displa y Memo ry
OS C
OS C
Ti ming Ge ner ato r
S egmen t Driver / G rid Driver / Ke y Scan O utput
SW1 SW2 SW3 SW4
Ge ner al Inp ut Reg iste r
Ke y Matrix Memory
LE D1 LE D2 LE D3 LE D4 LE D5
LED Drive r Gr id Drive r Dimming Cir cu it
K1 K2 K3 K4
VDD
GND
VE E
Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6311
12-GRID X 16-SEGMENT VFD APPLICATION CIRCUIT
VDD
0.1uF
220
220
220
56K VDD 10K
49 48 46 45 47 44 41 52 51 50 43 42
220
220
1 2 3 4 5 6
40
39 38 37 36 35 34 33 VEE VDD
G12 G11 G10
MCU
7 8 9 10 11 12
17
PT6311
32 30 29 28
18 19 15 16 21 22 20 23 24 25 26
S16 S15 S14 S13
12-GRID x 16-SEGMENT VFD
S12 S11 S10 S2 S1 S9 S8 S7 S6 S5 S4 S3
10K x 4
VDD
14
13
27
1N4148 x 12
10K x 4
V3.2
2
November 2009
G2 G1
G9
G8
G7
G6
G5
G4
G3
31
PT6311
ORDER INFORMATION
Valid Part Number PT6311 PT6311-LQ Package Type 52 Pins, QFP 52 Pins, LQFP Top Code PT6311 PT6311-LQ
PIN CONFIGURATION
V3.2
3
November 2009
PT6311
PIN DESCRIPTION
Pin Name SW1 to SW4 DOUT I/O I O Description General Purpose Input Pins Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit). Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit). No Connection Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this in is "HIGH", CLK is ignored. Key Data Input Pins The data inputted to these pins is latched at the end of the display cycle. Logic Power Supply High-Voltage Segment Output Pins Also acts as the Key Source. High-Voltage Segment/Grid Output Pins Pull-Down Level High-Voltage Grid Output Pins LED Output Pin Ground Pin Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency. Pin No. 1 to 4 5
DIN NC CLK
I I
6 7 8
STB
I
9
K1 to K4 VDD SG1/KS1 to SG12/KS12 SG20/GR9 to SG19/GR10 SG18/GR11 to SG13/GR16 VEE GR1 to GR8 LED1 to LED5 GND OSC
I O O O O I
10 to 13 14, 33, 45 15 to 26 36 to 35 32 to 27 34 44 to 37 50 to 46 51 52
V3.2
4
November 2009
PT6311
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
OUTPUT PINS: SGn/GRn
INPUT PINS: DIN, CLK, STB
INPUT PINS: SW1 TO SW4, K1 TO K4
V3.2
5
November 2009
PT6311 OUTPUT PIN: DOUT
OUTPUT PINS: LED1 TO LED5
V3.2
6
November 2009
PT6311
FUNCTION DESCRIPTION
COMMANDS
Commands determine the display mode and status of PT6311. A command is the first byte (b0 to b7) inputted to PT6311 via the DIN Pin after STB Pin has changed from "HIGH" to "LOW" State. If for some reason the STB Pin is set to "HIGH" while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid.
COMMAND 1: DISPLAY MODE SETTING COMMANDS
PT6311 provides 9 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6311 via the DIN Pin when STB is "LOW". However, for these commands, the bits 5 to 6 (b4 to b5) are ignored, bits 7 & 8 (b6 to b7) are given a value of "0". The Display Mode Setting Commands determine the number of segments and grids to be used (1/8 to 1/16 duty, 20 to 12 segments). When these commands are executed, the display is forcibly turned off, the key scanning stops. A display command "ON" must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned "ON", the 16-digit, 12-segment modes is selected. MSB 0 LSB b0
0
-
-
b3
b2
b1
Not Relevant
Display Mode Settings: 0XXX: 8 digits, 20 segments 1000: 9 digits, 19 segments 1001: 10 digits, 18 segments 1010: 11 digits, 17 segments 1011: 12 digits, 16 segments 1100: 13 digits, 15 segments 1101: 14 digits, 14 segments 1110: 15 digits, 13 segments 1111: 16 digits, 12 segments
V3.2
7
November 2009
PT6311
DISPLAY MODE AND RAM ADDRESS
Data transmitted from an external device to PT6311 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6311 are given below in 8 bits unit. SG1 SG4 00HL 03HL 06HL 09HL 0CHL 0FHL 12HL 15HL 18HL 1BHL 1EHL 21HL 24HL 27HL 2AHL 2DHL SG5 00HU 03HU 06HU 09HU 0CHU 0FHU 12HU 15HU 18HU 1BHU 1EHU 21HU 24HU 27HU 2AHU 2DHU SG8 SG9 SG12 01HL 04HL 07HL 0AHL 0DHL 10HL 13HL 16HL 19HL 1CHL 1FHL 22HL 25HL 28HL 2BHL 2EHL SG13 01HU 04HU 07HU 0AHU 0DHU 10HU 13HU 16HU 19HU 1CHU 1FHU 22HU 25HU 28HU 2BHU 2EHU SG16 SG17 02HL 05HL 08HL 0BHL 0EHL 11HL 14HL 17HL 1AHL 1DHL 20HL 23HL 26HL 29HL 2CHL 2FHL SG20 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 DIG16
b0 xxHL Lower 4 bits
b3
b4 xxHU Higher 4 bits
b7
V3.2
8
November 2009
PT6311 COMMAND 2: DATA SETTING COMMANDS
The Data Setting Commands executes the Data Write or Data Read Modes for PT6311. The data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of "1" while bit 8 (b7) is given the value of "0". Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of "0". MSB 0 1 b3 b2 b1 LSB b0
Not Relevant
Data Write & Read Mode Settings: 00: Write Data to Display Mode 01: Write Data to LED Port 10: Read Key Data 11: Read SW Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode
V3.2
9
November 2009
PT6311
PT6311 KEY MATRIX & KEY INPUT DATA STORAGE RAM
PT6311 Key Matrix consists of 12 x 4 arrays as shown below:
K1 K2 K3 K4 SG1/KS1 SG11/KS11 SG2/KS2 SG10/KS10 SG12/KS12
November 2009
SG4/KS4
SG8/KS8
Each data inputted by each key are stored as follows. They are read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG12, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1.....................K4 SG1/KS1 SG3/KS3 SG5/KS5 SG7/KS7 SG9/KS9 SG11/KS11 b0......................b3 K1.....................K4 SG2/KS2 SG4/KS4 SG6/KS6 SG8/KS8 SG10/KS10 SG12/KS12 b4......................b7
SG5/KS5
SG9/KS9
SG3/KS3
SG6/KS6
SG7/KS7
Reading Sequence
V3.2
10
PT6311
LED DISPLAY
PT6311 provides 5 LED Display Terminals, namely LED1 to LED5. Data is written to the LED Port starting from the least significant bit (b0) of the port using a WRITE Command. Each bit starting from the least significant (b0) activates a specific LED Display Terminal -- b0 corresponds LED1 Display, b1 activates LED2 and so forth. Since there are only 5 LED display terminals, bits 6 to 8 (b5 ~ b7) are not used and therefore ignored. This means that b5 to b7 does NOT in anyway activate any LED Display, they are totally ignored. When a bit (b0 ~ b4) in the LED Port is "0", the corresponding LED is ON. Conversely, when the bit is "1", the LED Display is turned OFF. For example, Bit 1 (as designated by b0) has the value of "0", then this means that LED1 is ON. It must be noted that when power is turned ON, bit 5 to bit 1 (b4 to b0) are given the value of "1". Please refer to the diagrams below: MSB Not Used b3 b2 b1 LSB b0 LED1 LED2 LED3 LED4 LED5
SWITCH DATA
PT6311 provides 4 Switch Inputs, namely: SW1 to SW4. SW Data is read starting from the least significant bit (b0) using a READ Command. Each bit starting from the least significant (b0) corresponds to a specific Switch Input -- b0 corresponds SW1, b1 to SW2 and so forth. Since there are only 4 Switch Inputs, Bits 5 to 8 (b4 to 7) are given the value of "0". Please refer to the diagram below. MSB 0 0 0 0 b3 b2 b1 LSB b0 SW1 SW2 SW3 SW4
V3.2
11
November 2009
PT6311 COMMAND 3: ADDRESS SETTING COMMANDS
Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of "00H" to "2FH". If the address is set to 30H or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at "00H". Please refer to the diagram below. MSB 1 1 b5 b4 b3 b2 b1 LSB b0
Address: 00H to 2FH
COMMAND 4: DISPLAY CONTROL COMMANDS
The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is stopped). MSB 1 0 b3 b2 b1 LSB b0
Not Relevant
Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width - 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off (Key Scan Continues) 1: Display On
V3.2
12
November 2009
PT6311
SCANNING AND DISPLAY TIMING
The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the 12 x 4 matrix is stored in the RAM.
V3.2
13
November 2009
PT6311
SERIAL COMMUNICATION FORMAT
The following diagram shows the PT6311 serial communication format. The DOUT Pin is an N-channel, open-drain output pin; therefore, it is highly recommended that an external pull-up resistor (1 K to 10 K) must be connected to DOUT.
Reception (Data/Command Write)
If data continues STB
DIN
b0
b1
b2
b6
b7
CLK
1
2
3
7
8
Transmission (Data Read)
STB DIN CLK b0 1 b1 2 b2 3 b3 4 b4 5 b5 6 b6 7 b7 8
t wait
1
2
3
4
5
6
DOUT Data Read Command is set
b0
b1
b2
b3
b4
b5
Data Reading Starts
where: twait (waiting time) > 1s It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1s.
V3.2
14
November 2009
PT6311
SWITCHING CHARACTERISTIC WAVEFORM
PT6311 Switching Characteristics Waveform is given below.
fosc OSC
50%
PWSTB STB PWCLK CLK tsetup DIN tPZL DOUT tTHZ Sn/Gn
90% 10%
PWCLK
tCLK-STB
thold
tPLZ
tTZH
where: fosc = Oscillation Frequency PWSTB (Strobe Pulse Width)1s tsetup (Data Setup Time)100ns tTZH1 (Segment Rise Time)2s (VDD=5V) tTZH2 (Grid Rise Time)0.5s (VDD=5V) tTHZ (Segment & Grid Fall Time)150s tPLZ (Propagation Delay Time)400ns (VDD=5V)
PWCLK (Clock Pulse Width)400ns tCLK-STB (Clock - Strobe Time)1s thold (Data Hold Time)100ns tTZH1 (Segment Rise Time)4s (VDD=3.3V) tTZH2 (Grid Rise Time)1.2s (VDD=3.3V) tPZL (Propagation Delay Time)100ns tPLZ (Propagation Delay Time)600ns (VDD=3.3V)
V3.2
15
November 2009
PT6311
APPLICATIONS
Display memories are updated by incrementing addresses. Please refer to the following diagram.
STB
CLK DIN
Command 2 Command 3 Data 1 Data n Command 1 Command 4
where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n : Transfer Display Data (48 Bytes max.) Command 4: Display Control Command
The following diagram shows the waveforms when updating specific addresses.
STB
CLK DIN
Command 2 Command 3 Data Command 3 Data
where: Command 2: Data Setting Command Command 3: Address Setting Command Data: Display Data
V3.2
16
November 2009
PT6311
RECOMMENDED SOFTWARE FLOWCHART
START Delay 200 ms
SET COMMAND 2 (Write Data)
SET COMMAND 3 Clear Display RAM (See Note 5)
INITIAL SETTING
SET COMMAND 1
SET COMMAND 4 (88H~8FH: Display ON)
MAIN PROGRAM
SET COMMAND 2 (Read Key & Write Data Includeed) MAIN LOOP SET COMMAND 3
SET COMMAND 1
SET COMMAND 4
END
Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting.
V3.2
17
November 2009
PT6311
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise stated, Ta=25, GND=0V) Parameter Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage LED driver output current Oscillation frequency Operating temperature Storage temperature VFD driver output current Symbol VDD VEE VI VO IOLED fosc Topr Tstg IOVFD Ratings -0.3 to +7 VDD +0.3 to VDD -40 -0.3 to VDD +0.3 VEE -0.3 to VDD +0.3 +25 3M(Max.) -40 to +85 -65 to +150 -40 (Grid) -15 (Segment) Unit V V V V mA Hz mA
RECOMMENDED OPERATING RANGE
(Unless otherwise stated, Ta=25, GND=0V) Parameter Logic supply voltage High-Level input voltage Low-Level input voltage Driver supply voltage POWER SUPPLY SEQUENCE Symbol VDD VIH VIL VEE Min. 3 0.7VDD 0 VDD -35 Typ. 5 Max. 5.5 VDD 0.3VDD 0 Unit V V V V
Note: The power on/off sequence suggestion: Applications must observe the following sequence when turning the power on or off. * At power on: First turn on the logic system power (VDD), and then turn on the driver power (VEE). * At power off: First turn off the driver power (VEE), and then turn off the logic system power (VDD).
V3.2
18
November 2009
PT6311
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD=5V, GND=0V, VEE=VDD-35 V, Ta=25) Parameter Symbol Test Condition IOHLED=-1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED=+20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT=4mA VO=VDD -2V High-Level output current IOHSG SG1 to SG12 VO=VDD -2V, High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R=56K Input current Dynamic current consumption II IDDdyn VI=VDD or GND Under no load Display OFF Min. 0.9VDD -3 -15 0.7VDD 350 Typ. 500 Max. 1 0.4 0.3VDD 650 1 5 Unit V V V mA mA V V KHz A mA
(Unless otherwise stated, VDD=3.3V, GND=0V, VEE=VDD-35 V, Ta=25) Parameter Symbol Test Condition IOHLED = -1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED = +20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT = 4mA VO = VDD -2V High-Level output current IOHSG SG1 to SG12 VO = VDD -2V High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R = 56 K Input current Dynamic current consumption II IDDdyn VI = VDD or GND Under no load Display OFF
Min. 0.9VDD -1.5 -6 0.7VDD 350 -
Typ. 500 -
Max. 1 0.4 0.2VDD 650 1 3
Unit V V V mA mA V V KHz A mA
V3.2
19
November 2009
PT6311
PACKAGE INFORMATION
52 PINS, QFP (BODY SIZE: 14MM X 14MM, PITCH=1.00MM)
Symbol A A1 A2 b c D D1 E E1 e L L1
Note: Refer to JEDEC MS-022 BD
Dimensions (MM) Min. 0.00 1.90 0.29 0.11 Nom. 0.35 17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 1.00 BSC 1.60 REF 20 Max. 3.15 0.25 2.90 0.41 0.23
0 0.65
8 1.05
V3.2
November 2009
PT6311
52 PINS, LQFP
Symbol A A1 A2 b c D D1 E E1 e L L1
Note: Refer to JEDEC MS-026
Dimensions (MM) Min. 0.05 1.35 0.35 0.09 Nom. 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 1.00 BSC 3.5 0.85 1.30 REF 21 Max. 1.60 0.15 1.45 0.50 0.20
0 0.70
7 1.00
V3.2
November 2009
PT6311 IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw
V3.2
22
November 2009

▲Up To Search▲

Price & Availability of PT6311-LQ

	To Download PT6311-LQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .