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Features * Six Half-bridge Outputs Formed by Six High-side and Six Low-side Drivers * Capable of Switching all Kinds of Loads (Such as DC Motors, Bulbs, Resistors, * * * * * * * * * * * * Capacitors and Inductors) RDSon Typically 1.0 at 25C, Maximum 1.8 at 150C Up to 650-mA Output Current Very Low Quiescent Current IS < 20A in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40V Daisy Chaining Possible Serial Interface 5V Compatible, up to 2MHz Clock Frequency SO28 or QFN24 Power Package Hex Half-bridge Driver with Serial Input Control Atmel ATA6836 ATA6836C 1. Description The Atmel(R) ATA6836 is a fully protected hex half-bridge driver designed in Smart Power SOI technology, used to control up to six different loads by a microcontroller in automotive and industrial applications. Each of the six high-side and six low-side drivers is capable of driving currents up to 650mA. The drivers are internally connected to form six half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads, such as bulbs, resistors, capacitors and inductors, can be combined. The IC especially supports the application of H-bridges to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode make a wide range of applications possible. Automotive qualification referring to conducted interferences, EMC protection and ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. 4952I-AUTO-08/10 Figure 1-1. Block Diagram SO28 S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 5, 10 VS Input register Ouput register Serial interface Charge pump L S 1 T P 20 GND 21 GND 22 DI 26 P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 CLK 25 23 GND GND CS 24 INH 17 DO 18 Control logic Power on reset 6 GND Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect UV protection 19 VCC 7 GND Thermal protection 8 GND 9 15, 16 OUT1 13, 14 OUT2 11, 12 OUT3 3, 4 OUT4 1, 2 OUT5 27, 28 OUT6 GND 2 ATA6836 4952I-AUTO-08/10 ATA6836 Figure 1-2. Block Diagram QFN24 S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 3, 4 VS Input register Ouput register Serial interface Charge pump L S 1 T P DI 19 P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 CLK 18 CS 17 INH 12 DO 13 Control logic Power on reset 24 GND Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect UV protection 14 VCC 16 GND Thermal protection 15 GND 7 11 OUT1 8 OUT2 5 OUT3 2 OUT4 23 OUT5 20 OUT6 GND 3 4952I-AUTO-08/10 2. Pin Configuration 2.1 SO28 Pinning SO28 OUT5 OUT5 OUT4 OUT4 VS GND GND GND GND VS OUT3 OUT3 OUT2 OUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OUT6 OUT6 DI CLK CS GND GND GND GND VCC DO INH OUT1 OUT1 Figure 2-1. Table 2-1. Pin 1, 2 3, 4 5 6, 7, 8, 9 10 11, 12 13, 14 15, 16 17 18 19 20, 21, 22, 23 24 25 26 27, 28 Pin Description SO28 Symbol OUT5 OUT4 VS GND VS OUT3 OUT2 OUT1 INH DO VCC GND CS CLK DI OUT6 Function Half-bridge output 5; formed by internally connected power MOS high-side switch 5 and low-side switch 5 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Output 4; see pin 1 Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary Ground; reference potential; internal connection to pins 20 to 23; cooling tab Power supply output stages HS1, HS2 and HS3 Output 3; see pin 1 Output 2; see pin 1 Output 1; see pin 1 Inhibit input, 5V logic input with internal pull down, low = standby, high = normal operation Serial data output, 5V CMOS logic level tri-state output for output (status) register data, sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low; therefore, several ICs can operate on one data output line only Logic supply voltage (5V) Ground, see pins 6 to 9 Chip select input, 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial clock input, 5V CMOS logic level input with internal pull down, controls serial data input interface and internal shift register (fmax = 2MHz) Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Output 6; see pin 1 4 ATA6836 4952I-AUTO-08/10 ATA6836 2.2 QFN24 Pinning QFN 24, 5 x 5, 0.65mm pitch NC OUT5 OUT5 SENSE OUT6 SENSE OUT6 DI OUT4 SENSE OUT4 VS VS OUT3 OUT3 SENSE 1 2 3 4 5 6 24 23 22 21 20 19 18 17 16 15 14 13 7 8 9 10 11 12 CLK CS GND SENSE NC VCC DO Figure 2-2. Note: YWW ATAxyz ZZZZZ AL Date code (Y = Year above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number Table 2-2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description QFN24 Symbol Function Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and low-side switch 4 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Power supply output stages HS4, HS5 and HS6 Power supply output stages HS1, HS2 and HS3 Output 3; see pin 1 Internal bond to GND Output 2; see pin 1 OUT4 SENSE Only for testability in final test OUT4 VS VS OUT3 NC OUT2 OUT3 SENSE Only for testability in final test OUT2 SENSE Only for testability in final test OUT1 SENSE Only for testability in final test OUT1 INH DO VCC NC Output 1; see pin 1 Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only Logic supply voltage (5V) Internal bond to GND GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab NC OUT2 OUT2 SENSE OUT1 SENSE OUT1 INH 5 4952I-AUTO-08/10 Table 2-2. Pin 17 18 19 20 21 22 23 24 Pin Description QFN24 (Continued) Symbol CS CLK DI OUT6 Function Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial clock input; 5V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2MHz) Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Output 6; see pin 1 OUT6 SENSE Only for testability in final test OUT5 SENSE Only for testability in final test OUT5 NC Output 5; see pin 1 Internal bond to GND 6 ATA6836 4952I-AUTO-08/10 ATA6836 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer Input Data Protocol DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 LS4 7 HS4 8 LS5 9 HS5 10 LS6 11 HS6 12 OLD 13 SCT 14 15 SI CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Data Protocol Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 Open load detection (low = on) Programmable time delay for short circuit (shutdown delay high/low = 12ms/1.5ms) Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) 15 SI 7 4952I-AUTO-08/10 Table 3-2. Bit 0 Output Data Protocol Output (Status) Register TP Function Temperature prewarning: high = warning (overtemperature shutdown see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin INH). High = standby, low = normal operation Power supply fail: undervoltage at pin VS detected 1 Status LS1 2 Status HS1 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Status LS2 Status HS2 Status LS3 Status HS3 Status LS4 Status HS4 Status LS5 Status HS5 Status LS6 Status HS6 SCD INH PSF Bit 0 to 15 = high: overtemperature shutdown Table 3-3. Bit 15 Bit 14 (SI) (SCT) H H Status of the Input Register After Power on Reset Bit 13 (OLD) H Bit 12 (HS6) L Bit 11 (LS6) L Bit 10 (HS5) L Bit 9 (LS5) L Bit 8 (HS4) L Bit 7 (LS4) L Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 Bit 1 (HS1) (LS1) L L Bit 0 (SRR) L 8 ATA6836 4952I-AUTO-08/10 ATA6836 3.2 Power-supply Fail In case of undervoltage at pin VS, an internal timer is started. When during a permanent undervoltage the delay time (tdUV) is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS - VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open load function for this output. 3.4 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit There are two ways to inhibit the Atmel(R) ATA6836: * Set bit SI in the input register to 0 * Switch pin INH to 0V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 (when INH = VCC) or by pin INH switched back to VCC (when SI = 1). 9 4952I-AUTO-08/10 4. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Supply voltage Supply voltage t < 0.5s; IS > -2A Supply voltage difference VS_pin5(3) - VS_pin10(4) Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Pin SO28 Pin QFN24 5, 10 5, 10 5, 10 19 24-26 18 18 3, 4 3, 4 3, 4 14 17-19 13 13 Symbol VVS VVS VVS VVCC VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO IOUT1 to IOUT6 Value -0.3 to +40 -1 150 -0.3 to +7 -0.3 to VVCC +0.3 -0.3 to VVCC +0.3 -10 to +10 -10 to +10 Internally limited, see "Output Specification" in Section 7. on page 11 Unit V V mV V V V mA mA 17, 24-26 12, 17-19 1-4, 11-16, 2, 5, 8, 11, 27, 28 20, 23 Output voltage 2, 3, 12, 2, 5, 8, 11, OUT1 to OUT6 13, 15, 28 20, 23 1, 4, 11, 14, 16, 27 Tj TSTG -0.3 to +40 V Junction temperature range Storage temperature range -40 to +150 -55 to +150 C C 5. Thermal Resistance Table 5-1. Parameter Junction pin Junction ambient SO28 Test Conditions Measured to GND Pin 6 to 9, 20 to 23 Symbol RthJP RthJA Min. Typ. Max. 25 65 Unit K/W K/W Table 5-2. Parameter Junction pin QFN24: Depends on the PCB-board Test Conditions Pin 16 Symbol RthJP RthJA Min. Typ. Max. <5 35 Unit K/W K/W Junction ambient 10 ATA6836 4952I-AUTO-08/10 ATA6836 6. Operating Range Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Test Conditions Pin SO28 Pin QFN24 5, 10 19 17, 24-26 3, 4 14 12, 17-19 Symbol VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj -40 Min. VUV(1) 4.75 -0.3 Typ. Max. 40 5.25 VVCC 2 +150 Unit V V V MHz C 7. Electrical Characteristics 7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Min. Typ. Max. Unit Pin SO28 Pin QFN24 Symbol 1 Current Consumption VS = 33V VCC = 0V or Total quiescent current VCC = 5V, bit SI = low or 1.1 (VS and all outputs to VCC = 5V, pin INH = low VS) Output pins to VS and GND 4.75V < VVCC < 5.25V, INH or bit SI = low 4.75V < VVCC < 5.25V, INH or bit SI = low, TJ = -40C VVS < 28V normal operation, all output stages off VVS < 28V normal operation, all output low stages on, no load VVS < 28V normal operation, all output high stages on, no load 4.75V < VVCC < 5.25V, normal operation Type* 5, 10 3, 4 IVS 2 A A 19 19 14 14 IVCC IVCC 20 30 A A A A Quiescent current 1.2 (VCC) 1.3 Supply current (VS) 5, 10 3, 4 IVS 0.8 1.2 mA A 1.4 Supply current (VS) 5, 10 3, 4 IVS 10 mA A 1.5 Supply current (VS) 1.6 Supply current (VCC) 5, 10 19 5, 10 3, 4 14 3, 4 IVS IVCC IVS 16 150 5 mA A mA A A A 1.7 Discharge current (VS) VVS = 40V, INH = low 2 Internal Oscillator Frequency Frequency (time base 2.1 for delay timers) 3 Undervoltage Detection, Power-on Reset Power-on reset 3.1 threshold Notes: fOSC 19 45 kHz A 19 14 VVCC 2.3 2.7 3.0 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 11 4952I-AUTO-08/10 7. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Min. Typ. Max. Unit Pin SO28 Pin QFN24 Symbol Power-on reset delay 3.2 time 3.3 3.4 3.5 4 Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay Thermal Prewarning and Shutdown TjPWset TjPWreset TjPW Tj switch off Tj switch on Tj switch off Tj switch off/ TjPW set Type* A A A A After switching on VVCC 19 19 14 14 tdPor VUV VUV tdUV 30 5.5 95 160 7.0 s V V 0.4 7 21 ms 4.1 Thermal prewarning 4.2 Thermal prewarning 4.3 Thermal prewarning hysteresis 120 105 145 130 15 170 155 C C K B B C B B C C 4.4 Thermal shutdown 4.5 Thermal shutdown 4.6 Thermal shutdown hysteresis 150 135 175 160 15 200 185 C C K Ratio thermal 4.7 shutdown/thermal prewarning Ratio thermal 4.8 shutdown/thermal prewarning 5 Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40V IOut = 600mA 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1.05 1.2 Tj switch on/ TjPW reset 1.05 1.2 C 5.1 On resistance RDS OnL 1.8 A 5.2 On resistance IOut = -600mA RDS OnH 1.8 A High-side output leakage current VOut1-6 = 0V 5.3 (total quiescent current all output stages off see 1.1) Low-side output leakage current VOut1-6 = VS 5.4 (total quiescent current all output stages off see 1.1) 5.5 Inductive shutdown energy Overcurrent limitation V = 13V and shutdown threshold VS IOut1-6 -15 A A IOut1-6 120 A A Woutx 15 mJ D 5.6 ILS1-6 650 950 1400 mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 12 ATA6836 4952I-AUTO-08/10 ATA6836 7. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Min. Typ. Max. Unit Pin SO28 Pin QFN24 Symbol 5.7 Overcurrent limitation V = 13V and shutdown threshold VS Overcurrent limitation 20V < VVS < 40V and shutdown threshold Overcurrent limitation 20V < VVS < 40V and shutdown threshold Overcurrent shutdown delay time Overcurrent shutdown delay time High-side open load detection current Low-side open load detection current Open load detection current ratio High-side open load detection voltage Low-side open load detection voltage Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off Input register bit 14 (SCT) = low VVS = 13V Input register bit 14 (SCT) = High VVS = 13V Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16 11, 20, 23 1-4, 2, 5, 8, 11-16 11, 20, 23 1-4, 2, 5, 8, 11-16 11, 20, 23 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 1-4, 2, 5, 8, 11-16, 11, 20, 23 27, 28 IHS1-6 -1400 -950 -650 mA Type* A 5.8 ILS1-6 650 950 1600 mA C 5.9 IHS1-6 -1600 -950 -650 mA C 5.10 tdSd 0.9 1.5 2.1 ms A 5.11 tdSd 7 12 17 ms A 5.12 IOut1-6H -1.5 -0.4 mA A 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 IOut1-6L IOLoutLX/ IOLoutHX VOut1-6H VOut1-6L tdon tdon tdoff tdoff tdon - tdoff 0.4 1.05 0.6 0.6 1.2 1.5 2 2.5 2 20 20 20 3 mA A V V s s s s s A A A A A A A High-side output switch VVS = 13V RLoad = 30 on delay(1) Low-side output switch VVS = 13V RLoad = 30 on delay(1) High-side output switch VVS =13V off delay(1) RLoad = 30 Low-side output switch VVS =13V RLoad = 30 off delay(1) Dead time between V =13V 5.21 corresponding high- and VS RLoad = 30 low-side switches 6 Inhibit Input 17 17 17 VINH = VVCC 12 12 12 Input voltage low-level 6.1 threshold 6.2 6.3 Input voltage high-level threshold Hysteresis of input voltage 1 VIL VIH VI IPD 0.3 x VVCC 0.7 x VVCC 100 10 700 80 V V mV A A A A A 6.4 Pull-down current Notes: *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 13 4952I-AUTO-08/10 7. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Min. Typ. Max. Unit Pin SO28 Pin QFN24 Symbol 7 7.1 7.2 7.3 7.4 Serial Interface: Logic Inputs DI, CLK, CS Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pin DI, CLK VDI, VCLK = VVCC VCS= 0V 24-26 24-26 24-26 25, 26 24 18 18 18 17-19 17-19 17-19 18, 19 17 13 13 13 VIL VIH VI IPDSI IPUSI VDOL VDOH IDO VVCC - 0.7V -10 10 50 2 -50 0.3 x VVCC 0.7 x VVCC 500 50 -2 0.5 V V mV A A V V A A A A A A A A A Type* 7.5 Pull-up current pin CS 8 Serial Interface: Logic Output DO 8.1 Output voltage low level IOL = 3mA Output voltage high 8.2 level 8.3 Leakage current (tri-state) IOL = -1mA VCS = VVCC, 0V < VDO < VVCC *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 8. Serial Interface: Timing Number in Timing Diagram (Figure 8-1 on page 15) 1 2 10 4 8 9 9 5 6 7 3 11 12 Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Test Conditions CDO = 100pF CDO = 100pF CDO = 100pF CDO = 100pF CDO = 100pF Pin SO28 18 18 18 18 18 24 24 QFN24 13 13 13 13 13 17 17 17 17 18 18 18 18 18 19 19 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold Min. Typ. Max. Unit 200 200 100 100 200 225 225 17 2.1 225 225 500 225 225 40 40 ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns Input register bit 14 (SCT) = high Input register bit 14 (SCT) = low 24 24 25 25 25 25 25 26 26 14 ATA6836 4952I-AUTO-08/10 ATA6836 Figure 8-1. Serial Interface Timing Diagram with Item Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.2 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC 15 4952I-AUTO-08/10 9. Noise and Surge Immunity Parameters Conducted interferences Interference suppression ESD (Human Body Model) CDM (Charge Device Model) MM (Machine Model) Note: 1. Test pulse 5: Vvbmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 ESD S 5.1 ESD STM5.3 ESD STM5.2 Value Level 4(1) Level 5 4kV 750V for corner pins (SO package only) 500V all other pins 200V 10. Application Circuit Figure 10-1. Application Circuit VS BYT41D VS Input register Ouput register Serial interface + VCC U5021M Enable Watchdog Trigger Reset S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R Vbatt 24V Charge pump GND L S 1 T P GND DI P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 GND CLK Microcontroller GND CS Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect UV protection VCC Power on reset VCC INH Control logic DO VCC 5V + GND VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect GND Thermal protection GND GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 M M M M M 16 ATA6836 4952I-AUTO-08/10 ATA6836 10.1 Application Notes * Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. * Recommended value for capacitors at VS: Electrolytic capacitor C > 22F in parallel with a ceramic capacitor C = 100nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse-conducting current IHSX (see Section 4. "Absolute Maximum Ratings" on page 10). * Recommended value for capacitors at VCC: Electrolytic capacitor C > 10F in parallel with a ceramic capacitor C = 100nF. * To reduce thermal resistance, place cooling areas on the PCB as close as possible to GND pins and to the die paddle in QFN24. 17 4952I-AUTO-08/10 11. Ordering Information Extended Type Number ATA6836-TIQY ATA6836C-TIQY ATA6836-PXQW ATA6836C-PXQW Package SO28 SO28 QFN24 QFN24 Remarks Taped and reeled, Pb-free Taped and reeled, Pb-free Taped and reeled, Pb-free Taped and reeled, Pb-free 12. Package Information 12.1 SO28 Package SO28 Dimensions in mm 18.05 17.80 9.15 8.65 7.5 7.3 2.35 0.4 1.27 28 16.51 15 0.25 0.10 0.25 10.50 10.20 technical drawings according to DIN specifications 1 14 18 ATA6836 4952I-AUTO-08/10 ATA6836 12.2 QFN24 Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 24 1 0.4 18 19 +0 5 3.6 24 1 technical drawings according to DIN specifications 6 0.3 13 12 7 6 0.65 nom. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 3.25 19 4952I-AUTO-08/10 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4952I-AUTO-08/10 4952H-AUTO-02/10 4952G-AUTO-12/09 4952F-AUTO-07/09 History * Table 2-1 "Pin Description SO28" on page 4 changed * Ordering Information page 19 changed * Section 7 "Electrical Characteristics" numbers 5.10 and 5.11 on page 13 changed * Section 7 "Electrical Characteristics" number 1.2 on page 11 changed * Put datasheet in a new template * Section 4 "Absolute Maximum Ratings" on pag 10 changed * Section 7 "Electrical Charcteristics" number 1.7 on page 11 added * Features on page 1 changed * Table 2-1 "Pin Description SO28" on page 4 changed * Table 2-2 "Pin Description QFN24" on pages 5 to 6 changed * Section 4 "Absolute Maximum Ratings" on page 10 changed * Section 6 "Operating Range" on page 10 changed * Section 7 "Electrical Characteristics" on pages 11 to 13 changed * Section 8 "Serial Interface: Timing" on page 14 changed * Section 9 "Noise and Surge Immunity" on page 16 changed * Section 11 "Ordering Information" on page 18 changed * Section 7 "Electrical Characteristics" numbers 5.15 and 5.16 on page 12 changed * Section 9 "Noise and Surge Immunity" on page 16 changed * Put datasheet in a new template * Section 7 "Electrical Characteristics" numbers 1.5, 3.1, 5.15 and 8.2 on pages 11 to 13 changed 4952E-AUTO-10/08 4952D-AUTO-10/07 4952C-AUTO-09/07 4952B-AUTO-07/07 20 ATA6836 4952I-AUTO-08/10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2010 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4952I-AUTO-08/10 |
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