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IT7001M/IT7001N
Programmable 8-Bit Binary Counter with Synchronous Preset Enable
Preliminary Specification V0.2
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives.
Copyright (c) 2000 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE' s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT7001M/IT7001N is a trademark of ITE, Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE (USA) Inc. Marketing Department 1235 Midas Way Sunnyvale, CA 94086 U.S.A. ITE (USA) Inc. Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A. ITE, Inc. Marketing Department 7F, No. 435, Nei Hu District, Jui Kuang Rd., Taipei 114, Taiwan, R.O.C. Phone: Fax: (408) 530-8860 (408) 530-8861
Phone: Fax:
(512) 388-7880 (512) 388-3108
Phone: Fax:
(02) 2657-9896 (02) 2657-8561, 2657-8576
If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: lawrence.liu@ite.com.tw, Tel: 886-2-26579896 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: david.lin@iteusa.com, Tel: (408) 530-8860 X238, Fax: (408) 530-8861 Don Gardenhire, at ITE Eastern USA Office: E-mail: don.gardenhire@iteusa.com Tel: (512) 388-7880, Fax: (512) 388-3108 To find out more about ITE, visit our World Wide Web at: http://www.ite.com.tw http://www.iteusa.com Or email itesupport@ite.com.tw for more product information/services.
Revision History
Revision History
Section
l
Revision To avoid the custom misunderstanding of CLR and PR signal in the IT7001 specification, CLR and PR signals were replaced by CLR_N and PR_N respectively. Sections 6, 7, 8 in the previous version were removed. The section arrangement was adjusted as follows: Section 9 was changed to section 6. Section 10 was changed to section 7. Section 11 was changed to section 9. Section 12 was changed to section 10.
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Section 1 Features was revised. Figure 7-1. Timing Diagram When Jn is fixed was revised. Section 8 Electrical Characteristics was revised.
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IT7001M/IT7001N V0.2
Contents
CONTENTS
1. Features ...................................................................................................................................................1 2. General Description..................................................................................................................................3 3. Block Diagram ..........................................................................................................................................5 4. Pin Configuration ......................................................................................................................................7 5. IT7001M/IT7001N Pin Description ............................................................................................................9 6. Example of Application Circuit ................................................................................................................ 11 7. Timing Chart: Example of AC Signal Generator ...................................................................................... 13 8. DC Characteristics.................................................................................................................................. 15 9. Package Information............................................................................................................................... 17 10. Ordering Information............................................................................................................................... 19
Tables
Table 5-1. Function Table of CLR_N, PR_N and SPE_N Pins ........................................................................9
Figures
Figure 6-1. Example of Application Circuit .................................................................................................... 11 Figure 7-1. Timing Diagram When Jn is fixed ............................................................................................... 13 Figure 7-2. Timing Diagram When Jn is changed ......................................................................................... 14
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IT7001M/IT7001N V0.2
Features
1. Features
n Wide Operation Voltage - Vcc = 2.5 to 5.5 V n Low Static Current (Ta = 25C) - Icc (Static) = 10 A (max) n Package: - IT7001M: 16-SOP - IT7001N: 16-TSSOP
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IT7001M/IT7001N V0.2 By Felix Sun, 12/18/2000 ITPM-PN-200045
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IT7001M/IT7001N V0.2
General Description
2. General Description
The IT7001M/IT7001N consists of 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE_N) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rising edge. It is applied to generate AC signal for STN-type liquid crystal and divider for general usage.
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IT7001M/IT7001N V0.2
Logic Diagram
3. Block Diagram
J0 J1 J2 J3 J4 J5 J6 J7
J0 CLK J1 J2 J3 J4 J5 J6 J7 SPE_N
CLK_N CLK
8-bit binary counter
PR_N
PR D CO_N CK CLR Q_N Q Q
SPE_N CLR_N
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IT7001M/IT7001N V0.2
Pin Configuration
4. Pin Configuration
J0 1 J1 2 J2 3 J3 4 J4 5 J5 6 J6 7 GND 8 IT7001M/N
16 Vcc 15 CLK_N 14 13 12
CLK Q PR_N
11 SPE_N 10 CLR_N 9
J7
Top View
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IT7001M/IT7001N V0.2
IT7001M/IT7001N Pin Description
5. IT7001M/IT7001N Pin Description
Signal VCC GND J0 to J7 CLK, CLK_N SPE_N PR_N CLR_N Q Pin(s) No. 16 8 1-7,9 14,15 11 12 10 13 Attribute I I I I I O Power Ground Count data input for option Clock inputs CLK: Rising edge trigger CLK_N: Falling edge trigger Preset input for Jn data Please refer to the table below Preset input for D-type Flip Flop (Initialize "L" at Q output) Please refer to the table below Clear input for D-type Flip Flop (Initialize "H" at Q output) Please refer to the table below Output for D-type Flip Flop Description
Table 5-1. Function Table of CLR_N, PR_N and SPE_N Pins Control Inputs CLR_N PR_N SPE_N H X L H H X H L H L Mode Generally count Synchronous preset Initialize of Q output Initialize of Q output Operation Description Down count at the rising edge of clock (CLK) Down count at the falling edge of clock (CLK_N) Jn data is preset at the rise of clock (CLK) , the fall of clock (CLK_N) Initialize of Q = "L" Initialize of Q = "H"
H: High level X: Immaterial L: Low level : Irrespective of condition 1) Synchronous preset (SPE_N) input can set max 256 down counts. 2) When the count value is 0, the next clock pulse presets the data to invert the output. 3) CLR_N and PR_N inputs initialize the output data.
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Example of Application Circuit
6. Example of Application Circuit * AC Signal Generator for STN-Type Liquid Crystal Panel Initialize counter: 50
J0 J1 J2 J3 J4 J5 J6 GND
Vcc CLK_N CLK Q PR_N SPE_N CLR_N J7 * *
*When initializing output D-F/F, apply "L".
Figure 6-1. Example of Application Circuit
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Timing Chart: Example of AC Signal Generator
7. Timing Chart: Example of AC Signal Generator
1 CLK SPE_N J0 J1 J2 J3 50 J4 J5 J6 J7 (CO_N) 2 3 49 50 51 52 53
101 102 103 104
.....
.....
.....
CLR_N (initialize of CLR_N) Q PR_N (initialize of PR_N) Q Count 50 49 48..... 2 1 0 50 49..... 1 0 50 49.....
Figure 7-1. Timing Diagram When Jn is fixed
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IT7001M/IT7001N V0.2
IT7001M/IT7001N
CLK SPE_N J0 J1 J2 J3 J4 J5 J6 J7 (CO_N) CLR_N (Initialize of CLR_N) Q PR_N (Initialize of PR_N) Q Count 5 4 3 2 1 0 3 2 1 0 35 34
Figure 7-2. Timing Diagram When Jn is changed
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IT7001M/IT7001N V0.2
DC Characteristics
8. DC Characteristics
Absolute Maximum Ratings Power Supply (VCC) input Voltage (VIN ) Output Voltage (VOUT) Output current / pin (IOUT) Storage Temperature (TSTG) -0.3V to 6.0V -0.3V to VCC + 0.3V -0.3V to VCC + 0.3V 24mA -40C to 125C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (Operation Condition Vcc=2.5V~5.5V, VIN / VOUT=0~Vcc, Tj=-30C~85C) (Note : This item guarantees maximum limit when one input switches.) Item High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Static Current Maximum clock frequency Symbol VIH VIL VOH VOL IIL ICC fmax Conditions CMOS CMOS IOH =-2mA IOL =2mA VIN = Vcc or GND VIN = Vcc or GND Vcc = 3.3V Min 0.7*Vcc 0.7*Vcc Typ 20 Max 0.3*Vcc 0.3*Vcc 1.0 10 Unit V V V V A A MHz
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IT7001M/IT7001N V0.2
Package Information
9. Package Information
SOP 16L Outline Dimensions
16 9
Unit: inches/mm
E
HE
1
b
8
L
Detail F
D
A2
y
Seating Plane
D
A1
e
A
See Detail F
Dimension in inches Symbol Min A A1 A2 b C D E e HE L L1 y 0 0.228 0.016 0.053 0.004 0.051 0.013 0.007 0.386 0.150 Nom 0.064 0.006 0.055 0.016 0.390 0.154 0.050 0.236 0.025 0.042 0.004 8 0.244 0.050 Max 0.069 0.010 0.059 0.020 0.010 0.394 0.157
Dimension in mm Min 1.35 0.10 1.30 0.33 0.19 9.80 3.80 Nom 1.63 0.15 1.40 0.41 9.91 3.90 1.27 5.80 0.40 6.00 0.64 1.07 0 0.10 8 6.20 1.27 Max 1.75 0.25 1.50 0.51 0.25 10.01 4.00
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IT7001M/IT7001N V0.2
C L1
IT7001M/IT7001N
TSSOP 16L Outline Dimensions
16 9
Unit: inches/mm
E
HE
1
b
8
L
Detail F
D C A2 A1
e
y Seating Plane D
A
L1 See Detail F
Dimension in inches Symbol Min A A1 A2 b C D E e HE L L1 y 0 0.020 0.002 0.031 0.007 0.004 0.193 0.169 Nom 0.035 0.197 0.173 0.026BSC. 0.252BSC. 0.024 0.039REF. 0.004 8 0.030 Max 0.047 0.006 0.041 0.012 0.008 0.201 0.177
Dimension in mm Min 0.05 0.80 0.19 0.09 4.90 4.30 Nom 0.90 5.00 4.40 0.65BSC. 6.40BSC. 0.50 0.60 1.0REF. 0 0.10 8 0.75 Max 1.20 0.15 1.05 0.30 0.20 5.10 4.50
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IT7001M/IT7001N V0.2
Ordering Information
10. Ordering Information
Part No.
IT7001M IT7001N
Package
16-SOP 16-TSSOP
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IT7001M/IT7001N V0.2

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