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HI-1579, HI-1581
October 2009
MIL-STD-1553 / 1760 3.3V Monolithic Dual Transceivers
PIN CONFIGURATIONS
44 43 BUSA 42 BUSA 41 BUSA 40 BUSA 39 VDDA 38 VDDA 37 TXA 36 TXA 35 34 -1 RXENA 2 GNDA 3 GNDA 4 GNDA 5 VDDB 6 VDDB 7 BUSB 8 BUSB 9 BUSB 10 BUSB 11
DESCRIPTION
The HI-1579 and HI-1581 are low power CMOS dual transceivers designed to meet the requirements of the MIL-STD-1553 specification. The transmitter section of each bus takes complementary CMOS / TTL Manchester II bi-phase data and converts it to differential voltages suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. The receiver section of the each bus converts the 1553 bus bi-phase differential data to complementary CMOS / TTL data suitable for inputting to a Manchester decoder. Each receiver has a separate enable input which can be used to force the output of the receiver to a logic "0" (HI-1579) or logic 1 (HI-1581). To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer.
1579PCI 1579PCT 1579PCM 1581PCI 1581PCT 1581PCM
12 13 14 15 16 17 18 19 20 21 22
33 32 31 TXINHA 30 RXA 29 RXA 28 27 26 TXB 25 TXB 24 TXINHB 23 -
44 Pin Plastic 7mm x 7mm Chip-scale package
VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 20 19 18 17 16 15 14 13 12 11 TXA TXA TXINHA RXA RXA TXB TXB TXINHB RXB RXB
FEATURES
* Compliant
to MIL-STD-1553A and B, MIL-STD-1760 and ARINC 708A
* 3.3V single supply operation * Smallest footprint available in 7mm x 7mm
44 pin plastic chip-scale package (QFN)
20 Pin Plastic ESOIC - WB package
VDDA 1 BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 20 TXA 19 TXA
* Less
than 0.5W maximum power dissipation and extended temperature ranges
* Industrial *
Industry standard pin configurations
BUSB 8 RXENB 9 GNDB 10
20 Pin Ceramic DIP package
(DS1579 Rev. G)
HOLT INTEGRATED CIRCUITS www.holtic.com
RXENB GNDB GNDB GNDB RXB RXB -
1579PSI 1579PST 1579PSM 1581PSI 1581PST 1581PSM
1579CDI 1579CDT 1579CDM 1581CDI 1581CDT 1581CDM
18 TXINHA 17 RXA 16 RXA 15 TXB 14 TXB 13 TXINHB 12 RXB 11 RXB
10/09
HI-1579, HI-1581
PIN DESCRIPTIONS
PIN (DIP & SOIC)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SYMBOL
VDDA BUSA BUSA RXENA GNDA VDDB BUSB BUSB RXENB GNDB RXB RXB TXINHB TXB TXB RXA RXA TXINHA TXA TXA
FUNCTION
power supply analog output analog output digital input power supply power supply analog output analog output digital input power supply digital output digital output digital input digital input digital input digital output digital output digital input digital input digital input
DESCRIPTION
+3.3 volt power for transceiver A MIL-STD-1533 bus driver A, positive signal MIL-STD-1553 bus driver A, negative signal Receiver A enable. If low, forces RXA and RXA low Ground for transceiver A +3.3 volt power for transceiver B MIL-STD-1533 bus driver B, positive signal MIL-STD-1553 bus driver B, negative signal Receiver B enable. If low, forces RXB and RXB low Ground for transceiver B Receiver B output, inverted Receiver B output, non-inverted Transmit inhibit, bus B. If high BUSB, BUSB disabled Transmitter B digital data input, non-inverted Transmitter B digital data input, inverted Receiver A output, inverted Receiver A output, non-inverted Transmit inhibit, bus A. If high BUSA, BUSA disabled Transmitter A digital data input, non-inverted Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1579 family of dual data bus transceivers contains differential voltage source drivers and differential receivers. It is intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. TRANSMITTER Data input to the device's transmitter section is from the complementary CMOS inputs TXA/B and TXA/B. The transmitter accepts Manchester II bi-phase data and converts it to differential voltages on BUSA/B and BUSA/B. The transceiver outputs are either direct or transformer coupled to the MIL-STD-1553 data bus. Both coupling methods produce a nominal voltage on the bus of 7.5 volts peak to peak. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are either at a logic "1" or logic "0" simultaneously. A logic "1" applied to the TXINHA/B input will force the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B.
RECEIVER The receiver accepts bi-phase differential data from the MIL-STD-1553 bus through the same direct or transformer coupled interface as the transmitter. The receiver's differential input stage drives a filter and threshold comparator that produces CMOS data at the RXA/B and RXA/B output pins. When the MIL-STD-1553 bus is idle and RXENA or RXENB are high, RXA/B will be logic "0" on HI-1579 and logic "1" on HI-1581. Each set of receiver outputs can also be independently forced to the bus idle state (logic "0" on HI-1579 or logic "1" on HI-1581) by setting RXENA or RXENB low. MIL-STD-1553 BUS INTERFACE A direct coupled interface (see Figure 2) uses a 1:2.5 ratio isolation transformer and two 55 ohm isolation resistors between the transformer and the bus. In a transformer coupled interface (see Figure 3), the transceiver is also connected to a 1:2.5 isolation transformer which in turn is connected to a 1:1.4 coupling transformer. The transformer coupled method also requires two coupling resistors equal to 75% of the bus characteristic impedance (Zo) between the coupling transformer and the bus.
HOLT INTEGRATED CIRCUITS 2
HI-1579, HI-1581
Each Bus
TRANSMITTER
Data Bus Isolation Transformer Coupler Network Direct or Transformer
BUSA/B
TXA/B Transmit Logic TXA/B TXINHA/B RECEIVER RXA/B Receive Logic RXA/B RXENA/B
BUSA/B Slope Control
Input Filter
Comparator
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
Vin (Line to Line)
tDR tDR tDR tDR
RXA/B (HI-1579)
tRG tRG
RXA/B (HI-1579) RXA/B (HI-1581)
tRG tRG
RXA/B (HI-1581)
HOLT INTEGRATED CIRCUITS 3
HI-1579, HI-1581 ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD) Logic input voltage range Receiver differential voltage Driver peak output current Power dissipation at 25C ceramic DIL, derate Solder Temperature Junction Temperature Storage Temperature -0.3 V to +5 V -0.3 V dc to +3.6 V 10 Vp-p +1.0 A 1.0 W 7mW/C 275C for 10 sec. 175C -65C to +150C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage VDD....................................... 3.3V... 5% Temperature Range Industrial ........................ -40C to +85C Hi-Temp ....................... -55C to +125C
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage Total Supply Current
SYMBOL
VDD ICC1 ICC2 ICC3
CONDITION
Not Transmitting Transmit one bus @ 50% duty cycle Transmit one bus @ 100% duty cycle Not Transmitting Transmit one bus @ 100% duty cycle Digital inputs Digital inputs Digital inputs Digital inputs IOUT = -1.0mA, Digital outputs IOUT = 1.0mA, Digital outputs
MIN
3.15
TYP
3.30 4 225 425
MAX
3.45 10 300 600 0.06
UNITS
V mA mA mA W W VDD
Power Dissipation
PD1 PD2
0.3 70%
0.5
Min. Input Voltage Max. Input Voltage Min. Input Current Max. Input Current Min. Output Voltage Max. Output Voltage RECEIVER Input resistance Input capacitance
(HI) (LO) (HI) (LO) (HI) (LO)
VIH VIL IIH IIL VOH VIH
30% 20 -20 90% 10%
VDD A A VDD VDD
(Measured at Point "AD" in Figure 2 unless otherwise specified) RIN CIN CMRR VIN VICM Detect No Detect VTHD VTHND 1 MHz Sine Wave (Measured at Point "AD" in Figure 2) (RX pulse width 70 ns) Differential -5.0 0.65 Differential (at chip BUS pins) Differential 40 9 5.0 20.0 0.45 20 5 Kohm pF dB Vp-p V-pk Vp-p Vp-p
Common mode rejection ratio Input Level Input common mode voltage Threshold Voltage - Direct-coupled
Theshold Voltage - Transformer-coupled
Detect
VTHD VTHND
No Detect
1 MHz Sine Wave (Measured at Point "AT" in Figure 3) (RX pulse width 70 ns)
0.65
14.0 0.45
Vp-p Vp-p
HOLT INTEGRATED CIRCUITS 4
HI-1579, HI-1581
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
TRANSMITTER Output Voltage
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
(Measured at Point "AD" in Figure 2 unless otherwise specified) Direct coupled Transformer coupled VOUT VOUT VON Direct coupled VDYN VDYN ROUT COUT 35 ohm load (Measured at Point "AD" in Figure 2) 70 ohm load (Measured at Point "AT" in Figure 3) Differential, inhibited 35 ohm load (Measured at Point "AD" in Figure 2) 70 ohm load (Measured at Point "AT" in Figure 3) Differential, not transmitting 1 MHz sine wave -90 -250 10 15 6.1 20.0 9.0 27.0 10.0 90 250 Vp-p Vp-p mVp-p mV mV Kohm pF
Output Noise Output Dynamic Offset Voltage
Transformer coupled Output resistance Output Capacitance
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
RECEIVER Receiver Delay Receiver gap time Receiver Enable Delay TRANSMITTER Driver Delay Rise time Fall Time Inhibit Delay
SYMBOL
tDR tRG tREN
TEST CONDITIONS
From input zero crossing to RXA/B or RXA/B Spacing between RXA/B and RXA/B pulses From RXENA/B rising or falling edge to RXA/B or RXA/B
MIN
TYP
MAX
450
UNITS
ns ns ns
(Measured at Point "AD" in Figure 2) 90 365 40
(Measured at Point "AD" in Figure 2) tDT tr tf tDI-H tDI-L TXA/B, TXA/B to BUSA/B, BUSA/B 35 ohm load 35 ohm load Inhibited output Active output 100 100 150 300 300 100 150 ns ns ns ns ns
TRANSMITTER TXA/B TXA/B TXINHA/B BUSA/B
1:2.5
55 W 35 W Point "AD"
BUSA/B
Isolation Transformer
55 W
55 W Point "AD" 35 W 55 W
2.5:1
RECEIVER RXA/B RXA/B
Isolation Transformer RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS 5
HI-1579, HI-1581
TRANSMITTER TXA/B TXA/B TXINHA/B 52.5 W (.75 Zo) 35 W (.5 Zo) 52.5 W (.75 Zo) BUSA/B
1:2.5
Point "AT"
1:1.4
52.5 W (.75 Zo) 35 W (.5 Zo)
BUSA/B
Isolation Transformer Point "AT" 2.5:1
Coupling Transformer
52.5 W (.75 Zo)
1.4:1
RECEIVER RXA/B RXA/B
Coupling Transformer
Isolation Transformer RXENA/B
Figure 3. Transformer Coupled Test Circuits
HEAT SINK - ESOIC & CHIP-SCALE PACKAGE
The HI-1579PSI/T/M and HI-1581PSI/T/M use a 20-pin thermally enhanced SOIC package. The HI-1579PCI/T/M and HI-1581PCI/T/M use a plastic chip-scale package (QFN). These packages include a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated and may be soldered to any convenient power or ground plane.
APPLICATIONS NOTE
Holt Applications Note AN-500 provides circuit design notes regarding the use of Holt's family of MIL-STD-1553 transceivers. Layout considerations, as well as recommended interface and protection components are included.
THERMAL CHARACTERISTICS
PART NUMBER HI-1579PSI / T / M HI-1581PSI / T / M HI-1579CDI / T / M HI-1581CDI / T / M HI-1579PCI / T / M HI-1581PCI / T / M PACKAGE STYLE CONDITION Heat sink unsoldered Heat sink soldered Socketed Heat sink unsoldered OJA 54C/W 47C/W 62C/W 49C/W JUNCTION TEMPERATURE TA=25C 52C 49C 56C 50C TA=85C TA=125C 112C 109C 116C 110C 152C 149C 156C 150C
20-pin Thermally enhanced plastic SOIC (ESOIC) 20-pin Ceramic side-brazed DIP 44-pin Plastic chipscale package (QFN)
Data taken at VDD=3.3V, continuous transmission at 1Mbit/s, single transmitter enabled.
HOLT INTEGRATED CIRCUITS 6
HI-1579, HI-1581 ORDERING INFORMATION HI - 15xx xx x x (Plastic)
PART NUMBER Blank F PART NUMBER I T M PART NUMBER PC PS PART NUMBER 1579 1581 LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE -40C TO +85C -55C TO +125C -55C TO +125C PACKAGE DESCRIPTION 44 PIN PLASTIC CHIP-SCALE PACKAGE QFN (44PCS) 20 PIN PLASTIC ESOIC, Thermally Enhanced Wide SOIC w/Heat Sink (20HWE) RXENA = 0 RXA RXA 0 1 0 1 RXENB = 0 RXB RXB 0 1 0 1 FLOW I T M BURN IN No No Yes
HI - 15xxCD x (Ceramic)
PART NUMBER I T M PART NUMBER 1579 1581 TEMPERATURE RANGE -40C TO +85C -55C TO +125C -55C TO +125C RXENA = 0 RXA RXA 0 1 0 1 FLOW I T M BURN IN No No Yes LEAD FINISH Gold (Pb-free, RoHS compliant) Gold (Pb-free, RoHS compliant) Tin / Lead (Sn / Pb) Solder
RXENB = 0 RXB RXB 0 1 0 1
PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAZED DIP (20C) 20 PIN CERAMIC SIDE BRAZED DIP (20C)
RECOMMENDED TRANSFORMERS
The HI-1579 and HI-1581 transceivers have been characterized for compliance with the electrical requirements of MIL-STD-1553 when used with the following
MANUFACTURER Premier Magnetics Technotrol Premier Magnetics Technotrol PART NUMBER PM-DB2725EX TL1553-45 PM-DB2702 TQ-1553-2
transformers. Holt recommends the Premier Magnetics parts as offering the best combination of electrical performance, low cost and small footprint.
TURNS RATIO(S) Dual tapped 1:1.79, 1:2.5 Dual tapped 1:1.79, 1:2.5 1:1.4 1:1.4 DIMENSIONS .500 x .500 x .375 inches .630 x 630 x .155 inches .625 x .500 x .250 inches .625 x .625 x .250 inches
APPLICATION Isolation Isolation Stub coupling Stub coupling
HOLT INTEGRATED CIRCUITS 7
HI-1579, HI-1581
REVISION HISTORY
Document Rev. Date DS1579 F 07/24/09 Description of Change Correct typographical errors in package dimensions. Clarified available temperature ranges. Clarified status of RXA/B and RXA/B pins in bus idle state when RXENA or RXENB are high (logic "1"). Clarified nomenclature of chip-scale package as QFN. Added 'M' flow option for QFN package ('PCM' package option). Updated datasheet to include HI-1581 variant.
G
10/5/09
HOLT INTEGRATED CIRCUITS 8
PACKAGE DIMENSIONS
20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced)
.0105 .0015 (.267 .038)
inches (millimeters)
Package Type: 20HWE
.504 .008 (12.79 .19)
.290 typ (7.37)
.407 .013 (10.325 .32)
Top View
.295 .002 (7.493 .05)
.205 typ (5.21)
Bottom View
See Detail A .0165 .0035 (.419 .089) .090 .01 (2.29 .25)
Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation.
.050 BSC (1.27) BSC = "Basic Spacing between Centers" is theoretical true position dimension and has no tolerance. (JEDEC Standard 95)
0 to 8 .033 .017 (.838 .432)
.0075 .004 (.191 .089)
Detail A
20-PIN CERAMIC SIDE-BRAZED DIP
1.000 .010 (25.400 .254) .310 .010 (7.874 .254) .050 TYP. (1.270 TYP.) .200 max (5.080) .085 .009 (2.159 .229)
inches (millimeters)
Package Type: 20C
.300 .010 (7.620 .254)
.125 min (3.175) .017 .002 (.432 .051)
.100 BSC (2.54)
.010 + 002/-.001 . (.254 .051/.025)
BSC = "Basic Spacing between Centers" is theoretical true position dimension and has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS 9
PACKAGE DIMENSIONS
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
.276 BSC (7.00)
inches (millimeters)
Package Type: 44PCS
.203 .006 (5.15 .15)
.020 BSC (0.50) .276 BSC (7.00)
Top View
.203 .006 (5.15 .15)
Bottom View
.010 (0.25) typ
.039 max (1.00)
.008 typ (0.2)
Electrically isolated heat sink pad on bottom of package. Connect to any ground or power plane for optimum thermal dissipation.
.016 .002 (0.40 .05)
BSC = "Basic Spacing between Centers" is theoretical true position dimension and has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS 10

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