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8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface AD5424/AD5433/AD5445
FEATURES
2.5 V to 5.5 V supply operation Fast parallel interface (17 ns write cycle) Update rate of 20.4 MSPS INL of 1 LSB for 12-bit DAC 10 MHz multiplying bandwidth 10 V reference input Extended temperature range: -40C to +125C 20-lead TSSOP and chip scale (4 mm x 4 mm) packages 8-, 10-, and 12-bit current output DACs Upgrades to AD7524/AD7533/AD7545 Pin-compatible 8-, 10-, and 12-bit DACs in chip scale Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Readback function 0.4 A typical power consumption
GENERAL DESCRIPTION
The AD5424/AD5433/AD5445 1 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs utilize data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing with a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of the AD7524/AD7533/ AD7545 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. The AD5424 is available in small, 20-lead LFCSP and 16-lead TSSOP packages, while the AD5433/AD5445 DACs are available in small, 20-lead LFCSP and TSSOP packages.
1
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming
U.S Patent No. 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
VDD VREF R 8-/10-/12-BIT R-2R DAC RFB IOUT1 IOUT2
AD5424/ AD5433/ AD5445
POWER-ON RESET
DAC REGISTER
CS R/W
INPUT LATCH
DATA INPUTS
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005-2009 Analog Devices, Inc. All rights reserved.
03160-001
GND
DB0
DB7/DB9/DB11
AD5424/AD5433/AD5445 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Terminology ................................................................................ 16 Theory of Operation ...................................................................... 17 Circuit Operation ....................................................................... 17 Bipolar Operation....................................................................... 18 Single-Supply Applications ....................................................... 19 Positive Output Voltage ............................................................. 19 Adding Gain ................................................................................ 20 DACs Used as a Divider or Programmable Gain Element ... 20 Reference Selection .................................................................... 21 Amplifier Selection .................................................................... 21 Parallel Interface ......................................................................... 22 Microprocessor Interfacing ....................................................... 22 PCB Layout and Power Supply Decoupling ................................ 23 Evaluation Board for the AD5424/AD5433/AD5445 ........... 23 Power Supplies for Evaluation Board ...................................... 23 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 29
REVISION HISTORY
8/09--Rev. A to Rev. B Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 3/05--Rev. 0 to Rev. A Updated Format ................................................................ Universal Changes to Specifications ............................................................... 4 Changes to Figure 49 .....................................................................17 Changes to Figure 50 .....................................................................18 Changes to Figure 51, Figure 52, and Figure 54 ........................19 Added Microprocessor Interfacing Section ...............................22 Added Figure 59.............................................................................24 Added Figure 60.............................................................................25 10/03--Initial Version: Revision 0
Rev. B | Page 2 of 32
AD5424/AD5433/AD5445 SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: -40C to +125C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177and ac performance measured with AD8038, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient1 Output Leakage Current1 REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUTS/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to 16 mV of full scale Measured to 4 mV of full scale Measured to 1 mV of full scale Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error Min Typ Max Unit Conditions
8 0.25 0.5 10 0.5 1 12 1 -1/+2 10 5 10 20 10 10 10 3 5 1.7 0.6 VDD - 1 VDD - 0.5 0.4 0.4 1 10
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV ppm FSR/C nA nA V k k pF pF V V V V V V A pF MHz
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0x0000, TA = 25C, IOUT1 Data = 0x0000, T = -40C to +125C, IOUT1
8 8
12 12 6 8
Input resistance TC = -50 ppm/C Input resistance TC = -50 ppm/C
VDD = 4.5 V to 5 V, ISOURCE = 200 A VDD = 2.5 V to 3.6 V, ISOURCE = 200 A VDD = 4.5 V to 5 V, ISINK = 200 A VDD = 2.5 V to 3.6 V, ISINK = 200 A
4 10
VREF = 3.5 V; DAC loaded all 1s VREF = 3.5 V, RLOAD = 100 , DAC latch alternately loaded with 0s and 1s
30 35 80 20 15 2 70 48
60 70 120 40 30
ns ns ns ns ns nV-s dB dB
Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, VREF = 3.5 V Reference = 1 MHz Reference = 10 MHz
Rev. B | Page 3 of 32
AD5424/AD5433/AD5445
Parameter Output Capacitance IOUT1 IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity
1
Min
Typ 12 25 22 10 1 81 65 25
Max 17 30 25 12
Unit pF pF pF pF nV-s dB dB nVHz
Conditions All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Clock = 10 MHz, VREF = 3.5 V @ 1 kHz AD5445, VREF = 3.5 V
55 63 65 50 60 62
dB dB dB dB dB dB AD5445, VREF = 3.5 V
73 80 82 70 75 80
dB dB dB dB dB dB AD5445, VREF = 3.5 V
65 72 51 65 2.5 0.4 5.5 0.6 5 0.001
dB dB dB dB V A A %/%
TA = 25C, logic inputs = 0 V or VDD Logic inputs = 0 V or VDD, T= -40C to +125C VDD = 5%
Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 32
AD5424/AD5433/AD5445 TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: -40C to +125C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 VDD = 2.5 V to 5.5 V 0 0 10 6 0 5 9 20 40 5 10 VDD = 4.5 V to 5.5 V 0 0 10 6 0 5 7 10 20 5 10 Unit ns min ns min ns min ns min ns min ns min ns min ns typ ns max ns typ ns max Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time (write cycle) Data setup time Data hold time R/W high to CS low CS min high time Data access time Bus relinquish time
1
Guaranteed by design, not subject to production test.
t1 t2 t6 t2
R/W
t7
CS
t3 t4 t5 t8
DATA VALID
t9
03160-002
DATA
DATA VALID
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
AD5424/AD5433/AD5445 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP JA Thermal Impedance 20-Lead TSSOP JA Thermal Impedance 20-Lead LFCSP JA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating -0.3 V to +7 V -12 V to +12 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +150C 150C 150C/W 143C/W 135C/W 300C 235C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Overvoltages at DBx, CS, and R/W, are clamped by internal diodes.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 32
AD5424/AD5433/AD5445 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1 1 IOUT2 2 GND 3 DB7 4 DB6 5 DB5 6 DB4 7 DB3 8
16 15 14
RFB VREF VDD R/W CS DB0 (LSB) DB1
03160-004
20 19 18 17 16
AD5424
(Not to Scale)
13 12 11 10 9
GND DB7 DB6 DB5 DB4
IOUT2 IOUT1 RFB VREF VDD
1 2 3 4 5
PIN 1 INDICATOR
AD5424
TOP VIEW
15 14 13 12 11
R/W CS NC NC NC
DB3 DB2 DB1 DB0 NC
DB2
6 7 8 9 10
03160-005
Figure 3. AD5424 Pin Configuration (TSSOP)
NC = NO CONNECT
Figure 4. AD5424 Pin Configuration (LFCSP)
Table 4. AD5424 Pin Function Descriptions
Pin No. TSSOP LFCSP 1 19 2 20 3 1 4-11 2-9 10-13 12 14 13 14 15 16 15 16 17 18 Mnemonic IOUT1 IOUT2 GND DB7-DB0 NC CS R/W VDD VREF RFB Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. Parallel Data Bits 7 to 0. No Internal Connection. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
Rev. B | Page 7 of 32
AD5424/AD5433/AD5445
IOUT1 1 IOUT2 2 GND 3 DB9
4 20 19 18 17
RFB
IOUT2 IOUT1 RFB VREF VDD
VREF VDD R/W CS NC NC DB0 (LSB) DB1 DB2
03160-006
20 19 18 17 16
DB8 5 DB7 6 DB6 7 DB5 8 DB4 9 DB3 10
AD5433
(Not to Scale)
16 15 14 13 12 11
GND DB9 DB8 DB7 DB6
1 2 3 4 5
PIN 1 INDICATOR
AD5433
TOP VIEW
15 14 13 12 11
R/W CS NC NC DB0
6 7 8 9 10
DB5 DB4 DB3 DB2 DB1
03160-007
NC = NO CONNECT
NC = NO CONNECT
Figure 5. AD5433 Pin Configuration (TSSOP)
Figure 6 AD5433 Pin Configuration (LFCSP).
Table 5. AD5433 Pin Function Descriptions
Pin No. TSSOP LFCSP 1 19 2 20 3 1 4-13 2-11 14, 15 12, 13 16 14 17 18 19 20 15 16 17 18 Mnemonic IOUT1 IOUT2 GND DB9-DB0 NC Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. Parallel Data Bits 9 to 0. Not Internally Connected. Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
20 19 18 17
CS
R/W VDD VREF RFB
IOUT1 1 IOUT2 2 GND 3 DB11 4 DB10 5 DB9 6 DB8 7 DB7 8 DB6 9 DB5 10
RFB VREF VDD R/W CS DB0 (LSB) DB1 DB2
03160-008
20 19 18 17 16
IOUT2 IOUT1 RFB VREF VDD
AD5445
(Not to Scale)
16 15 14 13 12 11
GND DB11 DB10 DB9 DB8
1 2 3 4 5
PIN 1 INDICATOR
AD5445
TOP VIEW
15 14 13 12 11
R/W CS DB0 DB1 DB2
6 7 8 9 10
DB7 DB6 DB5 DB4 DB3
DB3 DB4
Figure 8. AD5445 Pin Configuration (LFCSP)
Figure 7. AD5445 Pin Configuration (TSSOP)
Table 6. AD5445 Pin Function Descriptions
Pin No. TSSOP LFCSP 1 19 2 20 3 1 4-15 2-13 16 14 17 18 19 20 15 16 17 18 Mnemonic IOUT1 IOUT2 GND DB11-DB0 CS R/W VDD VREF RFB Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 11 to 0. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
Rev. B | Page 8 of 32
03160-009
AD5424/AD5433/AD5445 TYPICAL PERFORMANCE CHARACTERISTICS
0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 50 100 CODE 150 200 250 TA = 25C VREF = 10V VDD = 5V 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 50 100 CODE 150 200 250 TA = 25C VREF = 10V VDD = 5V
03160-010
DNL (LSB)
INL (LSB)
Figure 9. INL vs. Code (8-Bit DAC)
0.5
TA = 25C VREF = 10V VDD = 5V
Figure 12. DNL vs. Code (8-Bit DAC)
0.5 0.4 0.3 0.2
0.4 0.3 0.2
DNL (LSB)
TA = 25C VREF = 10V VDD = 5V
INL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4
03160-011
0.1 0 -0.1 -0.2 -0.3 -0.4
03160-014 03160-015
-0.5 0 200 400 CODE 600 800 1000
-0.5 0 200 400 CODE 600 800 1000
Figure 10. INL vs. Code (10-Bit DAC)
Figure 13. DNL vs. Code (10-Bit DAC)
1.0 0.8 0.6 0.4 TA = 25C VREF = 10V VDD = 5V
1.0 0.8 0.6 0.4
DNL (LSB)
TA = 25C VREF = 10V VDD = 5V
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8
03160-012
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
-1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
Figure 11. INL vs. Code (12-Bit DAC)
Rev. B | Page 9 of 32
Figure 14. DNL vs. Code (12-Bit DAC)
03160-013
AD5424/AD5433/AD5445
0.6 0.5 0.4 0.3 MAX INL
2.0 1.5 1.0 0.5 MAX DNL 0 -0.5 MAX INL TA = 25C VREF = 0V VDD = 3V
INL (LSB)
0.2 0.1 0 MIN INL -0.1 -0.2
TA = 25C VDD = 5V
LSB
-1.0 MIN INL -1.5 -2.0 0.5
MIN DNL
03160-016
2
3
4
5
6
7
8
9
10
0.6
0.7
0.8
0.9
1.0 VBIAS (V)
1.1
1.2
1.3
1.4
1.5
REFERENCE VOLTAGE
Figure 15. INL vs. Reference Voltage, AD5445
Figure 18. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
-0.40 TA = 25C VDD = 5V
4 3 2 MAX INL TA = 25C VREF = 2.5V VDD = 3V
-0.45
MAX DNL
-0.50
1
LSB
DNL (LSB)
0 -1 -2
-0.55
-0.60 MIN DNL
MIN DNL -3
MIN INL
-0.65
-4
03160-017
2
3
4
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1.0 VBIAS (V)
1.2
1.4
1.6
1.8
2.0
REFERENCE VOLTAGE
Figure 16. DNL vs. Reference Voltage, AD5445
Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
5 4 3 2 1 0 VDD = 2.5V -1 -2 -3 VREF = 10V -4
03160-018
0.5 0.4
VDD = 5V
0.3 0.2 VOLTAGE (mV) 0.1 0 -0.1 -0.2 -0.3 -0.4
TA = 25C VREF = 0V VDD = 3V AND 5V GAIN ERROR
ERROR (mV)
OFFSET ERROR
-40
-20
0
20
40
60
80
100
120
140
0.6
0.7
0.8
0.9
1.0 VBIAS (V)
1.1
1.2
1.3
1.4
1.5
TEMPERATURE (C)
Figure 17. Gain Error vs. Temperature
Figure 20. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
Rev. B | Page 10 of 32
03160-021
-5 -60
-0.5 0.5
03160-020
-0.70
-5
03160-019
-0.3
AD5424/AD5433/AD5445
0.5 0.4 0.3
6 8 7
0.2 VOLTAGE (mV) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.2 0.4 0.6 0.8
GAIN ERROR
CURRENT (mA)
5 VDD = 5V 4 3 2
OFFSET ERROR
TA = 25C VREF = 2.5V VDD = 3V AND 5V
03160-022
1 0 0 0.5 1.0
VDD = 3V VDD = 2.5V
1.0 VBIAS (V)
1.2
1.4
1.6
1.8
2.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE (V)
Figure 21. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
Figure 24. Supply Current vs. Logic Input Voltage (Driving DB0 to DB11, All Other Digital Inputs @ Supplies)
3 TA = 25C VREF = 0V VDD = 5V MAX INL
1.6 1.4 1.2
2
1
IOUT1 VDD 5V
MAX DNL
IOUT LEAKAGE (nA)
1.0 IOUT1 VDD 3V 0.8 0.6 0.4 0.2
LSB
0
-1
-2 MIN INL -3 0.5 1.0 1.5 VBIAS (V) MIN DNL 2.0 2.5
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 22. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
Figure 25. IOUT1 Leakage Current vs. Temperature
4 3 2 1 TA = 25C VREF = 2.5V VDD = 5V MAX DNL
0.50 0.45 0.40 0.35 VDD = 5V ALL 0s 0.30 0.25 0.20 0.15 0.10 0.05
03160-027
LSB
0 MAX INL -1 -2 -3 -4
03160-024
CURRENT (A)
ALL 1s VDD = 2.5V ALL 1s ALL 0s
MIN DNL MIN INL
-5 0.5
1.0 VBIAS (V)
1.5
2.0
0 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
Figure 23. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
Rev. B | Page 11 of 32
Figure 26. Supply Current vs. Temperature
03160-026
03160-023
0 -40
03160-025
AD5424/AD5433/AD5445
14 TA = 25C LOADING ZS TO FS 12 VDD = 5V 10 8 0 3 TA = 25C VDD = 5V AD5445
GAIN (dB)
VDD = 3V
IDD (mA)
-3
6
4 2
-6 VDD = 2.5V
03160-028
1
10
100
1k
10k
100k
1M
10M
100M
100k
1M FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
Figure 27. Supply Current vs. Update Rate
Figure 30. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor
03160-029
1
10
100
1k
10k
100k
1M
10M
100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (Hz)
TIME (ns)
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 31. Midscale Transition, VREF = 0 V
0.2
-1.68 0x7FF TO 0x800 -1.69 TA = 25C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF
0
OUTPUT VOLTAGE (V)
VDD = 5V -1.70 -1.71 -1.72 -1.73 -1.74 -1.75 -1.76 0x800 TO 0x7FF VDD = 3V VDD = 5V
GAIN (dB)
-0.2
-0.4 TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC 1 10 100 1k 10k 100k 1M 10M 100M
03160-030
VDD = 3V
-0.6
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (Hz)
TIME (ns)
Figure 29. Reference Multiplying Bandwidth--All 1s Loaded
Figure 32. Midscale Transition, VREF = 3.5 V
Rev. B | Page 12 of 32
03160-033
-0.8
-1.77
03160-032
6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102
TA = 25C LOADING ZS TO FS
OUTPUT VOLTAGE (V)
ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0.045 0.040 0.035 0.030 0.025 0.020 0.015
0x7FF TO 0x800 VDD = 5V
TA = 25C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF
GAIN (dB)
VDD = 3V
0x800 TO 0x7FF 0.010 0.005 0 -0.005 -0.010 VDD = 5V VDD = 3V
ALL OFF
TA = 25C VDD = 5V VREF = 3.5V INPUT CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC
03160-031
0
-9 10k
VREF = 2V, AD8038 CC 1.47pF VREF = 2V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1.47pF VREF = 3.51V, AD8038 CC 1.8pF
AD5424/AD5433/AD5445
1.8 1.6 1.4 80 VIH 1.2 1.0 VIL 0.8 0.6 0.4 0.2
03160-062
TA = 25C
100 MCLK = 1MHz
THRESHOLD VOLTAGE (V)
SFDR (dB)
60
MCLK = 200kHz MCLK = 0.5MHz
40
20
TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5445 0 20 40 60 80 100 120 140 160 180 200
03160-036 03160-038 03160-037
0 2.5
0
3.0
3.5
4.0 VOLTAGE (V)
4.5
5.0
5.5
fOUT (kHz)
Figure 33. Threshold Voltages vs. Supply Voltage
Figure 36. Wideband SFDR vs. fOUT Frequency
20 0 TA = 25C VDD = 3V AMP = AD8038
90 80 MCLK = 5MHz 70 MCLK = 10MHz
-20 60
PSRR (dB)
SFDR (dB)
-40
50 40 30 MCLK = 25MHz
-60 FULL SCALE -80 ZERO SCALE -100
20 10
1
10
100
1k
10k
100k
1M
10M
03160-034
-120 FREQUENCY (Hz)
TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5445 0 100 200 300 400 500 600 700 800 900 1000
0
fOUT (kHz)
Figure 34. Power Supply Rejection vs. Frequency
Figure 37. Wideband SFDR vs. fOUT Frequency
-60 TA = 25C VDD = 3V VREF = 3.5V p-p
0 -10 -20 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES
-65
-70
THD + N (dB)
-30
SFDR (dB)
03160-035
-75
-40 -50 -60 -70 -80
-80
-85
-90 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)
-90 0 2 4 6 FREQUENCY (MHz) 8 10 12
Figure 35. THD and Noise vs. Frequency
Figure 38. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. B | Page 13 of 32
AD5424/AD5433/AD5445
0 -10 -20 -30 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES 20 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES 0
-20
SFDR (dB)
SFDR (dB)
03160-039
-40 -50 -60 -70 -80
-40
-60
-80 -100
-90
03160-042 03160-044 03160-043
-100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
-120 50
60
70
80
90
100
110
120
130
140
150
FREQUENCY (kHz)
Figure 39. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Figure 42. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz
0 -10 -20 -30 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES
0 -10 -20 -30 -40 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES
SFDR (dB)
(dB)
03160-040
-40 -50 -60 -70 -80 -90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
-50 -60 -70 -80 -90 -100 200
250
300
350
400
450
500
550
600
650
700
FREQUENCY (kHz)
Figure 40. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Figure 43. Narrow-Band IMD, fOUT = 400 kHz, 500 kHz, Clock = 10 MHz
0 -10 -20 -30 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES
0 -10 -20 -30 -40 TA = 25C VDD = 3V AMP = AD8038 AD5445 65k CODES
SFDR (dB)
-40 -50 -60 -70 -80 -90
03160-041
(dB)
300 350 400 450 500 550 600 650 700 750
-50 -60 -70 -80 -90 -100 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (kHz)
-100 250
FREQUENCY (kHz)
Figure 41. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
Figure 44. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Rev. B | Page 14 of 32
AD5424/AD5433/AD5445
0 -10 -20 -30 -40 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES 0 -10 -20 -30 -40 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES
(dB)
-50 -60 -70 -80 -90
03160-045
(dB)
MCLK 10MHz VDD 5V
-50 -60 -70 -80 -90
03160-047
-100 20 25 30 35 40 45 50 55 60 65 70 FREQUENCY (kHz)
-100 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
Figure 45. Narrow-Band IMD, fOUT = 40 kHz, 50 kHz, Clock = 10 MHz
Figure 47. Wideband IMD, fOUT = 60 kHz, 50 kHz, Clock = 10 MHz
0 -10 -20 -30 -40 TA = 25C VDD = 5V AMP = AD8038 AD5445 65k CODES
(dB)
-50 -60 -70 -80 -90 0 50 100 150 200 250 300 350 400
03160-046
-100 FREQUENCY (kHz)
Figure 46. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
Rev. B | Page 15 of 32
AD5424/AD5433/AD5445
TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1, or IOUT2, to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 resistor to ground. The settling time specification includes the digital delay from the CS rising edge to the full-scale output change. Digital to Analog Glitch lmpulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA seconds or nV seconds, depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled through the device to show up as noise on the IOUT pins and subsequently in the following circuitry. This noise is called digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth.
THD = 20 log
(V2 2 + V3 2 +V4 2 + V5 2 )
V1
Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa - fb and 2fb - fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is measured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case, 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.
Rev. B | Page 16 of 32
AD5424/AD5433/AD5445 THEORY OF OPERATION
The AD5424, AD5433, and AD5445 are 8-, 10-, and 12-bit current output DACs consisting of a standard inverting R-2R ladder configuration. A simplified diagram for the 8-bit AD5424 is shown in Figure 48. The matching feedback resistor RFB has a value of R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of resistance value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node.
R VREF 2R S1 2R S2 2R S3 2R S8 2R R RFBA IOUT1
03160-048
where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-bit AD5424) = 0 to 1023 (10-bit AD5433) = 0 to 4095 (12-bit AD5445) Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the DAC switches' on and off states. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. With a fixed 10 V reference, the circuit shown in Figure 49 gives a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table 7 shows the relationship between digital code and expected output voltage for unipolar operation (AD5424, 8-bit device).
Table 7. Unipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000
VDD
R
R
IOUT2 DAC DATA LATCHES AND DRIVERS
Figure 48. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, 4-quadrant multiplication in bipolar mode or in single-supply modes of operation. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity.
Analog Output (V) -VREF (255/256) -VREF (128/256) = -VREF/2 VREF (1/256) VREF (0/256) = 0
R2
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 49. When an output amplifier is connected in unipolar mode, the output voltage is given by
VOUT = -VREF x D 2n
VREF R1 VREF VDD RFB
C1
AD5424/ AD5433/ AD5445
R/W CS
IOUT1 IOUT2 GND
A1 VOUT = 0 TO -VREF
AGND DATA INPUTS NOTES: 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
03160-049
Figure 49. Unipolar Operation
Rev. B | Page 17 of 32
AD5424/AD5433/AD5445
R3 20k VDD VDD VREF 10V R1 VREF RFB IOUT1 IOUT2 GND R2 C1 A1 R5 20k R4 10k A2 VOUT = -VREF TO +VREF
AD5424/ AD5433/ AD5445
R/W CS
DATA INPUTS
AGND
NOTES: 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 50. Bipolar Operation (4-Quadrant Multiplication)
BIPOLAR OPERATION
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 50. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage, results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF).
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as closely as possible and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closedloop applications. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 49 and Figure 50. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for compensation.
VOUT = (V REF x D / 2 n -1 ) - V REF where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-bit AD5424) = 0 to 1023 (10-bit AD5433) = 0 to 4095 (12-bit AD5445) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 8 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5424, 8-bit device).
Table 8. Bipolar Code Table
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 -VREF (127/128) -VREF (128/128)
Rev. B | Page 18 of 32
03160-050
AD5424/AD5433/AD5445
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
The current mode circuit in Figure 51 shows a typical circuit for operation with a single 2.5 V to 5 V supply. IOUT2 and therefore IOUT1 is biased positive by the amount applied to VBIAS. In this configuration, the output voltage is given by VOUT = [D x (RFB/RDAC) x (VBIAS - VIN)] + VBIAS As D varies from 0 to 255 (AD5424), 0 to 1023 (AD5433), or 0 to 4095 (AD5445), the output voltage varies from VOUT = VBIAS to VOUT = 2VBIAS - VIN. VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal.
VDD C1
RFB VIN IOUT1 IOUT2 GND NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. VDD DAC VREF A1 VOUT VDD R1 R2
Figure 52. Single-Supply Voltage-Switching Mode Operation
VDD VIN VREF DAC GND
RFB IOUT1 IOUT2
A1 VOUT
It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. See Figure 18 to Figure 23. Also, VIN must not go negative by more than 0.3 V,;otherwise, an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost.
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V respectively, as shown in Figure 53.
VDD = 5V ADR03 VOUT VIN GND +5V VDD -2.5V VREF GND -5V NOTES: 1ADDITIONAL PINS OMITTED FOR CLARITY. 2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED, IF A1 IS A HIGH SPEED AMPLIFIER. RFB IOUT1 IOUT2 VOUT = 0V TO +2.5V C1
VBIAS NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 51. Single-Supply Current Mode Operation
It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, their on resistance differs and the linearity of the DAC degrades.
Voltage Switching Mode of Operation
Figure 52 shows these DACs operating in the voltage-switching mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source.
03160-051
Figure 53. Positive Voltage Output with Minimum of Components
Rev. B | Page 19 of 32
03160-053
03160-052
AD5424/AD5433/AD5445
ADDING GAIN
In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can be achieved in a single stage. It is important to consider the effect of the temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients and results in larger gain temperature coefficient errors. Instead, the circuit shown in Figure 54 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains greater than 1 are required.
VDD
As D is reduced, the output voltage increases. For small values of D, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. For example, in the circuit shown in Figure 55, an 8-bit DAC driven with the binary code 0x10 (00010000), that is, 16 decimal, should cause the output voltage to be 16 x VIN. However, if the DAC has a linearity specification of 0.5 LSB, then D can in fact have a weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage falls in the range 15.5 VIN to 16.5 VIN--an error of 3% even though the DAC itself has a maximum error of 0.2%.
VIN RFB IOUT1 IOUT2 VDD
VDD VREF GND
VDD R1 VIN VREF
RFB IOUT1 IOUT2
C1
8-/10-/12-BIT DAC
GND
VOUT R3 R2 GAIN = R2 + R3 R2
03160-054
VOUT
03160-055
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
NOTES: 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
R2R3 R1 = R2 + R3
Figure 55. Current-Steering DAC Used as a Divider or Programmable Gain Element
Figure 54. Increasing the Gain of the Current Output DAC
DACS USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor, as shown in Figure 55, then the output voltage is inversely proportional to the digital input fraction, D. For D = 1 - 2-n the output voltage is VOUT = -VIN/D = -VIN/(1 - 2-n)
DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Since only a fraction, D, of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: Output Error Voltage due to DAC Leakage = (Leakage x R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV.
Rev. B | Page 20 of 32
AD5424/AD5433/AD5445
Table 9. Suitable ADI Precision References
Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temp Drift (ppm/C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12 Output Noise (V p-p) 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23
Table 10. Suitable ADI Precision Op Amps
Part No. OP97 OP1177 AD8551 AD8603 AD8628 Supply Voltage (V) 2 to 20 2.5 to 15 2.7 to 5 1.8 to 6 2.7 to 6 VOS (Max) (V) 25 60 5 50 5 IB (Max) (nA) 0.1 2 0.05 0.001 0.1 0.1 Hz to 10 Hz Noise (V p-p) 0.5 0.4 1 2.3 0.5 Supply Current (A) 600 500 975 50 850 Package SOIC-8 MSOP, SOIC-8 MSOP, SOIC-8 TSOT TSOT, SOIC-8
Table 11. Suitable ADI High Speed Op Amps
Part No. AD8065 AD8021 AD8038 AD9631 Supply Voltage (V) 5 to 24 2.5 to 12 3 to 12 3 to 6 BW @ ACL (MHz) 145 490 350 320 Slew Rate (V/s) 180 120 425 1300 VOS (Max) (V) 1500 1000 3000 10000 IB (Max) (nA) 6000 10500 750 7000 Package SOIC-8, SOT-23,MSOP SOIC-8, MSOP SOIC-8, SC70-5 SOIC-8
REFERENCE SELECTION
When selecting a reference for use with the AD5424/AD5433/ AD5445 family of current output DACs, pay attention to the reference's output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0C to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/C. By choosing a precision reference with low output temperature coefficient this error source can be minimized. Table 9 suggests some references available from Analog Devices that are suitable for use with this range of current output DACs. of the DAC) of the circuit. A change in the noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. In general, the input offset voltage should be <1/4 LSB to ensure monotonic behavior when stepping through codes. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing into the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. Common-mode rejection of the op amp is important in voltage-switching circuits, since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common mode rejection for use at 8-, 10-, and 12-bit resolution.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance
Rev. B | Page 21 of 32
AD5424/AD5433/AD5445
Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices.
8xC51-to-AD5424/AD5433/AD5445 Interface
Figure 57 shows the interface between the AD5424/AD5433/ AD5445 and the 8xC51 family of DSPs. To facilitate external data memory access, the address latch enable (ALE) mode is enabled. The low byte of the address is latched with this output pulse during access to external memory. AD0 to AD7 are the multiplexed low order addresses and data bus and require strong internal pull-ups when emitting 1s. During access to external memory, A8 to A15 are the high order address bytes. Since these ports are open drained, they also require strong internal pull-ups when emitting 1s.
A8 TO A15 ADDRESS BUS
PARALLEL INTERFACE
Data is loaded to the AD5424/AD5433/AD5445 in the format of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W allow data to be written to or read from the DAC register. A write event takes place when CS and R/W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word to the DAC register. The DAC latches are not transparent, thus a write sequence must consist of a falling and rising edge on CS to ensure that data is loaded to the DAC register and its analog equivalent is reflected on the DAC output. A read event takes place when R/W is held high and CS is brought low. New data is loaded from the DAC register back to the input register and out onto the data line where it can be read back to the controller for verification or diagnostic purposes.
8051* ADDRESS DECODER CS AD5424/ AD5433/ AD5445*
WR 8-BIT LATCH
R/W DB0 TO DB11
ALE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 57. 8xC51-to-AD5424/AD5433/AD5445 Interface
ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface
Figure 58 shows a typical interface between the AD5424/ AD5433/AD5445 and the ADSP-BF5xx family of DSPs. The asynchronous memory write cycle of the processor drives the digital inputs of the DAC. The AMSx line is actually four memory select lines. Internal ADDR lines are decoded into AMS3-0 , these lines are then inserted as chip selects. The rest of the interface is a standard handshaking operation.
ADDR1 TO ADRR19 ADDRESS BUS
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5424/AD5433/AD5445 Interface
Figure 56 shows the AD5424/AD5433/AD5445 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD5424/ AD5433/AD5445 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family user's manual for details).
ADDR0 TO ADRR13 ADDRESS BUS
ADSP-BF5xx AMSx ADDRESS DECODER CS
AD5424/ AD5433/ AD5445*
ADSP-21xx* DMS ADDRESS DECODER CS
AD5424/ AD5433/ AD5445*
AWE
R/W DB0 TO DB11
WR
R/W DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 58. ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface
03160-056
DATA 0 TO DATA 23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 56. ADSP21xx-to-AD5424/AD5433/AD5445 Interface
Rev. B | Page 22 of 32
03160-057
DATA 0 TO DATA 23
DATA BUS
03160-063
AD0 TO AD7
DATA BUS
AD5424/AD5433/AD5445 PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5424/AD5433/AD5445 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply, located as close to the package as possible and ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A micro-strip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible.
EVALUATION BOARD FOR THE AD5424/AD5433/AD5445
The board consists of a 12-bit AD5445 and a current-to-voltage amplifier, the AD8065. Included on the evaluation board is a 10 V reference, the ADR01. An external reference may also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software allows the user to simply write a code to the device.
POWER SUPPLIES FOR EVALUATION BOARD
The board requires 12 V and 5 V supplies. The 12 V VDD and VSS are used to power the output amplifier, while the +5 V VDD and VSS are used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10 F tantalum and 0.1 F ceramic capacitors. Link1 (LK1) is provided to allow selection between the onboard reference (ADR01) and an external reference applied through J2.
Rev. B | Page 23 of 32
VCC C1 0.1F
VCC
R2 10k
VDD1
B-A (LSB)
U4 VCC 23 LEBA
C6
18
P1-36 P1-7 P1-6
+ C5 10F R1
P1-5
0.1F
P1-4 P1-3
P1-2
C7
20
C9
VCC
4.7pF VSS 2 3 4
V- V+
10F + C10 0.1F TP1
AD5424/AD5433/AD5445
1 2 3 4 5 6 7 8 9 10 11 12 OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND 1 2 CEBA B7 B6 B5 B4 B3 B2 B1 B0 LEAB OEAB 23 15 16 17 18 19 20 21 22 14 13
R3 10k
P1-9
A-B (LSB)
74ABT543 U3
TP2
6 7
J1
OUTPUT
VCC VCC C2 0.1F
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 15 14 13 12 11 10 9 8 7 6 5 4
DB0 U1 V DD DB1 DB2 DB3 DB4 DB5 RFB DB6 DB7 IOUT1 DB8 DB9 IOUT2 DB10 DB11
VDD
C11 10F + C12 0.1F
R4 10k
CS RW 16 CS 17 R/W
3 GND
P1-31
B-A (MSB)
U5 VCC 24
VREF
19
AD5424/AD5433/ AD5445 V
DD
2 +V IN
VOUT 6
J2
Figure 59. Evaluation Board Schematic
J3
Rev. B | Page 24 of 32
C3 10F
J4
VCC 14 13
23 15 16 17 18 19 20 21 22
C4 0.1F
U2 ADR01AR 5 TRIM
GND
BA LK1
EXTERNAL REFERENCE
C8 0.1F
R5 10k
1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND CEBA B7 B6 B5 B4 B3 B2 B1 B0 LEAB OEAB
4
P1-8
A-B (MSB)
74ABT543
P1-1
P1-14
P2-3 C13 0.1F P2-2 C15 AGND VDD1 0.1F P2-1 VSS P2-4 C17 0.1F P2-6 C19 0.1F P2-5 + C20 10F 10F + C18
VCC
VDD + C14 10F + C16 10F
P1-19 P1-20 P1-21 P1-22 P1-23 P1-24 P1-25 P1-26 P1-27 P1-28 P1-29 P1-30
03160-058
AD5424/AD5433/AD5445
P1
R2 R4
C1 C12
U5 R5 C2
TP2
DB10 DB8 DB6 DB4 DB2 DB0 CS J3
DB11 DB9 U1 DB7 DB5 R1 DB3 DB1 C6 C5 RW J2 C18
U3
C10
TP1 C7 C8 LK1 U2 EXT VREF
J1 OUTPUT C4
C3
U4 J4 R3 CS
C14 C13
C16
R/W C19 C20
C17
C15 P2
DGND
AGND
VDD1
VCC
VDD
Figure 60. Silkscreen--Component-Side View
Figure 61. Component-Side Artwork
Rev. B | Page 25 of 32
03160-060
03160-059
EVAL-AD5424/ AD5433/AD5445EB
VSS
AD5424/AD5433/AD5445
Figure 62. Solder-Side Artwork
Table 12. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board
Name C1, C2, C4, C6, C8 C10, C12, C13 C15 C3, C5, C9, C11, C14 C17, C19 C16, C18, C20 C7 CS DB0-DB11 J1-J4 LK1 P1 P2 R1 R2, R3, R4, R5 RW, TP1, TP2 U1 U2 U3 U4 U5 Each Corner Part Description X7R Ceramic Capacitor X7R Ceramic Capacitor Tantalum Capacitor, Taj Series X7R Ceramic Capacitor Tantalum Capacitor, Taj Series X7R Ceramic Capacitor Test Point Red Test Point SMB Socket 3-Pin Header (3 x 1) 36-Pin Centronics Connector 6-Pin Terminal Block 0.063 W Resistor 0.063 W Resistor Red Test Point AD5445 ADR425/ADR01/ADR02/ADR03 AD8065 74ABT543 74ABT543 Rubber Stick-On Feet Value 0.1 F 0.1 F 10 F 20 V 0.1 F 10 F 10 V 4.7 pF Tolerance 10% 10% 10% 10% 10% 10% PCB Decal 0603 0603 CAP\TAJ_B 0603 CAP\TAJ_A 0603 TESTPOINT TESTPOINT SMB LINK-3P- 36WAY CON\POWER6 0603 0603 TESTPOINT TSSOP20 SO8NB SO8NB TSSOP24 TSSOP24 Stock Code FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-130 FEC 240-345 (Pack) FEC 240-345 (Pack) FEC 310-682 FEC 511-717 and 150-411 FEC 147-753 FEC 151-792 Not Inserted FEC 911-355 FEC 240-345 (Pack) AD5445YRU ADR01AR AD8065AR Fairchild 74ABT543CMTC Fairchild 74ABT543CMTC FEC 148-922
10 k
1%
Rev. B | Page 26 of 32
03160-061
AD5424/AD5433/AD5445
Table 13. Overview of AD54xx and AD55xx Devices
Part No. AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5405 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL(LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Package RU-16, CP-20 RM-10 RU-20 RU-10 RJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 RJ-8 RM-10 RM-8 RU-24 CP-40 RU-20, CP-20 RU-24 RU-16 RJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Features 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 50 MHz serial interface 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width
Rev. B | Page 27 of 32
AD5424/AD5433/AD5445 OUTLINE DIMENSIONS
5.10 5.00 4.90
20
6.60 6.50 6.40
11
16
9
4.50 4.40 4.30
1 8
6.40 BSC
1 10
4.50 4.40 4.30 6.40 BSC
PIN 1 0.65 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05 COPLANARITY 0.10
1.20 MAX
0.15 0.05
0.20 0.09 8 0
0.30 0.19
SEATING PLANE
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
Figure 64. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX
0.60 MAX
15
16
20 1
PIN 1 INDICATOR
2.25 2.10 SQ 1.95
5
PIN 1 INDICATOR
3.75 BCS SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
10
6
TOP VIEW 0.80 MAX 0.65 TYP
0.75 0.60 0.50
11
0.25 MIN
1.00 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
Rev. B | Page 28 of 32
012508-B
0.30 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD5424/AD5433/AD5445
ORDERING GUIDE
Model AD5424YRU AD5424YRU-REEL AD5424YRU-REEL7 AD5424YRUZ 1 AD5424YRUZ-REEL1 AD5424YRUZ-REEL71 AD5424YCP AD5424YCP-REEL AD5424YCP-REEL7 AD5424YCPZ-REEL1 AD5424YCPZ-REEL71 AD5433YRU AD5433YRU-REEL AD5433YRU-REEL7 AD5433YRUZ1 AD5433YRUZ-REEL1 AD5433YRUZ-REEL71 AD5433YCP AD5433YCP-REEL AD5433YCP-REEL7 AD5433YCPZ1 AD5445YRU AD5445YRU-REEL AD5445YRU-REEL7 AD5445YRUZ1 AD5445YRUZ-REEL1 AD5445YRUZ-REEL71 AD5445YCP AD5445YCP-REEL AD5445YCP-REEL7 AD5445YCPZ1 EVAL-AD5424EBZ1 EVAL-AD5433EBZ1 EVAL-AD5445EBZ1
1
Resolution (Bits) 8 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 10 10 10 12 12 12 12 12 12 12 12 12 12
INL (LSB) 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 1 1 1 1 1 1 1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Kit Evaluation Kit Evaluation Kit
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 CP-20-1 CP-20-1 CP-20-1 CP-20-1 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 CP-20-1 CP-20-1 CP-20-1 CP-20-1
Z = RoHS Compliant Part.
Rev. B | Page 29 of 32
AD5424/AD5433/AD5445 NOTES
Rev. B | Page 30 of 32
AD5424/AD5433/AD5445 NOTES
Rev. B | Page 31 of 32
AD5424/AD5433/AD5445 NOTES
(c)2005-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03160-0-8/09(B)
Rev. B | Page 32 of 32

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