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| PCF8576C Universal LCD driver for low multiplex rates Rev. 09 -- 9 July 2009 Product data sheet 1. General description The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCF8576C is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing. 2. Features I Single-chip LCD controller and driver I 40 segment drives: N Up to twenty 7-segment numeric characters N Up to ten 14-segment alphanumeric characters N Any graphics of up to 160 elements I Versatile blinking modes I No external components required (even in multiple device applications) I Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing I Selectable display bias configuration: static, 12 or 13 I Internal LCD bias generation with voltage-follower buffers I 40 x 4-bit RAM for display data storage I Auto-incremented display data loading across device subaddress boundaries I Display memory bank switching in static and duplex drive modes I Wide logic LCD supply range: N From 2 V for low-threshold LCDs N Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs I Low power consumption I May be cascaded for large LCD applications (up to 2560 segments possible) I Cascadable with 24-segment LCD driver PCF8566 I No external components I Compatible with chip-on-glass technology I Separate or combined LCD and logic supplies I Optimized pinning for plane wiring in both and multiple PCF8576C applications I Power-saving mode for extremely low power consumption in battery-operated and telephone applications 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19. NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Package Name PCF8576CH PCF8576CT PCF8576CTT LQFP64 VSO56 HTSSOP56 Description plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic very small outline package, 56 leads Version SOT314-2 SOT190-1 Type number plastic thermal enhanced thin shrink small outline package, 56 leads; SOT793-1 body width 6.1 mm; exposed die pad PCF8576CU/10 PCF8576CU PCF8576CU/2 wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm[2] bare die; 56 bumps; 3.0 x 2.82 x 0.40 mm[2] PCF8576CU/10 PCF8576CU/10 wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm[1] PCF8576CU PCF8576CU/2 [1] [2] PCF8576CU PCF8576CU/2 Delivery form: chip on FFC. Delivery form: chip in tray. 4. Marking Table 2. Marking codes Marking code PCF8576CH PCF8576CT PCF8576CTT PC8576C-1 PC8576C-1 PC8576C-2 Type number PCF8576CH PCF8576CT PCF8576CTT PCF8576CU/10 PCF8576CU PCF8576CU/2 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 2 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 5. Block diagram BP0 BP2 BP1 BP3 S0 to S39 40 VDD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY LATCH VLCD LCD BIAS GENERATOR SHIFT REGISTER PCF8576C CLK TIMING SYNC DISPLAY CONTROLLER OSC OSCILLATOR POWERON RESET COMMAND DECODER INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER DATA POINTER BLINKER INPUT BANK SELECTOR DISPLAY RAM 40 x 4 BITS OUTPUT BANK SELECTOR VSS SCL SDA SA0 A0 A1 A2 013aaa094 Fig 1. Block diagram of PCF8576C PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 3 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning 64 S33 63 S32 62 S31 61 S30 60 S29 59 S28 58 S27 57 S26 56 S25 55 S24 54 S23 53 S22 52 S21 51 S20 50 S19 49 S18 n.c. S34 S35 S36 S37 S38 S39 n.c. n.c. 1 2 3 4 5 6 7 8 9 48 n.c. 47 S17 46 S16 45 S15 44 S14 43 S13 42 S12 41 S11 40 S10 39 S9 38 S8 37 S7 36 S6 35 S5 34 S4 33 n.c. PCF8576CH SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16 A1 17 A2 18 SA0 19 VSS 20 VLCD 21 n.c. 22 n.c. 23 n.c. 24 BP0 25 BP2 26 BP1 27 BP3 28 S0 29 S1 30 S2 31 S3 32 001aag241 Top view. For mechanical details, see Figure 32. Fig 2. Pin configuration of PCF8576CH (LQFP64) PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 4 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates SDA SCL SYNC CLK VDD OSC A0 A1 A2 1 2 3 4 5 6 7 8 9 56 S39 55 S38 54 S37 53 S36 52 S35 51 S34 50 S33 49 S32 48 S31 47 S30 46 S29 45 S28 44 S27 43 S26 42 S25 41 S24 40 S23 39 S22 38 S21 37 S20 36 S19 35 S18 34 S17 33 S16 32 S15 31 S14 30 S13 29 S12 001aag240 SA0 10 VSS 11 VLCD 12 BP0 13 BP2 14 BP1 15 BP3 16 S0 17 S1 18 S2 19 S3 20 S4 21 S5 22 S6 23 S7 24 S8 25 S9 26 S10 27 S11 28 PCF8576CT Top view. For mechanical details, see Figure 33. Fig 3. Pin configuration of PCF8576CT (VSO56) PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 5 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates SDA SCL SYNC CLK VDD OSC A0 A1 A2 1 2 3 4 5 6 7 8 9 56 S39 55 S38 54 S37 53 S36 52 S35 51 S34 50 S33 49 S32 48 S31 47 S30 46 S29 45 S28 44 S27 43 S26 42 S25 41 S24 40 S23 39 S22 38 S21 37 S20 36 S19 35 S18 34 S17 33 S16 32 S15 31 S14 30 S13 29 S12 013aaa095 SA0 10 VSS 11 VLCD 12 BP0 13 BP2 14 BP1 15 BP3 16 S0 17 S1 18 S2 19 S3 20 S4 21 S5 22 S6 23 S7 24 S8 25 S9 26 S10 27 S11 28 PCF8576CTT Top view. For mechanical details, see Figure 34. Fig 4. Pin configuration of PCF8576CTT (HTSSOP56) PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 6 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 22 34 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 S34 33 32 31 30 29 28 27 26 25 24 23 21 20 S3 19 S2 18 S1 17 S0 16 BP3 15 BP1 14 BP2 PCF8576CU S4 13 BP0 12 VLCD 11 VSS 10 SA0 9 8 A2 A1 7 A0 013aaa096 (c) NXP B.V. 2009. All rights reserved. 52 S35 53 S36 54 S37 55 S38 56 S39 1 SDA 2 SCL 3 SYNC 4 CLK 5 VDD 6 OSC Top view. For mechanical details, see Figure 35, Figure 36 and Figure 37. Fig 5. Pin locations of PCF8576CU PCF8576C_9 Product data sheet Rev. 09 -- 9 July 2009 7 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol Pin description Pin PCF8576CH SDA SCL SYNC CLK VDD OSC A0 to A2 SA0 VSS VLCD BP0, BP2, BP1, BP3 S0 to S39 n.c. [1] Description PCF8576CT PCF8576CTT 1 2 3 4 5 6 7 to 9 10 11 12 13 to 16 17 to 56 PCF8576CU 1 2 3 4 5[1] 6 7 to 9 10 11 12 13 to 16 17 to 56 I2C-bus serial data input and output I2C-bus serial clock input cascade synchronization input and output external clock input/output supply voltage internal oscillator enable input subaddress inputs I2C-bus address input; bit 0 logic ground LCD supply voltage LCD backplane outputs LCD segment outputs not connected 10 11 12 13 14 15 16 to 18 19 20 21 25 to 28 2 to 7, 29 to 32, 34 to 47, 49 to 64 1, 8, 9, 22 to 24, 33, 48 - The substrate (rear side of the die) is wired to VDD but should not be electrically connected. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 8 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7. Functional description The PCF8576C is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 4 backplanes and up to 40 segments. The display configurations possible with the PCF8576C depend on the number of active backplane outputs required. Display configuration selection is shown in Table 4. All of the display configurations given in Table 4 can be implemented in the typical system shown in Figure 6. Table 4. Display configurations 7 segment numeric Digits 20 15 10 5 Indicator symbols 20 15 10 5 14-segment numeric Characters 10 8 5 2 Indicator symbols 20 8 10 12 160 (4 x 40) 120 (3 x 40) 80 (2 x 40) 40 (1 x 40) Dot matrix Number of: Backplanes Elements 4 3 2 1 160 120 80 40 VDD R tr 2CB SDA SCL OSC V DD V LCD 40 segment drives LCD PANEL (up to 160 elements) HOST MICROPROCESSOR/ MICROCONTROLLER PCF8576C 4 backplanes A0 A1 A2 SA0 V SS 013aaa098 VSS Fig 6. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576C. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application. 7.1 Power-on-reset At power-on the PCF8576C resets to the following starting conditions: * * * * PCF8576C_9 All backplane and segment outputs are set to VDD The selected drive mode is 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset (as defined in Table 8) (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 9 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates * The I2C-bus interface is initialized * The data pointer and the subaddress counter are cleared Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator The full-scale LCD voltage (Voper) is obtained from VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin VLCD. Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three series resistors connected between VDD and VLCD. The center resistor can be switched out of the circuit to provide a 12 bias voltage level for the 1:2 multiplex configuration. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5. Table 5. LCD drive mode static Preferred LCD drive modes: summary of characteristics LCD bias V on ( RMS ) V off ( RMS ) V on ( RMS ) -------------------------- ------------------------ D = -------------------------V LCD V off ( RMS ) Backplanes Bias levels configuration V LCD 1 2 3 4 4 4 static 1 2 1 3 1 3 1 3 Number of: 0 0.354 0.333 0.333 0.333 1 0.791 0.745 0.638 0.577 2.236 2.236 1.915 1.732 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD < 3 x Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1 V on ( RMS ) = V LCD 1 (n - 1) 1 2 -- + ---------------- x ------------ n n 1 + a (1) where VLCD is the resultant voltage at the LCD segment and where the values for n are PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 10 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2) V LCD Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ----------------------- = V off ( RMS ) (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1) 2 (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1 1 2 bias 2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with 21 is ---------- = 1.528 . 3 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: * 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS ) ) * 1:4 multiplex (12 bias): V LCD = ( 4 x 3 - = 2.309V off ( RMS ) --------------------- 3 These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 11 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 7. Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V -VLCD VLCD state 2 0V -VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = VSn+1(t) - VBP0(t). Voff(RMS) = 0 V. Fig 7. Static drive mode waveforms PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 12 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8576C allows the use of 12 bias or 13 bias (see Figure 8 and Figure 9). Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD Fig 8. Waveforms for the 1:2 multiplex drive mode with 12 bias PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 13 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl747 LCD segments state 1 state 2 Sn+1 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD Vstate2(t) = VSn(t) - VBP1(t) Voff(RMS) = 0.333VLCD. Fig 9. Waveforms for the 1:2 multiplex drive mode with 13 bias PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 14 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure 10. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments BP2 Sn+2 (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 10. Waveforms for the 1:3 multiplex drive mode with 13 bias PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 15 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 11. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments Sn Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 Sn+3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. Fig 11. Waveforms for the 1:4 multiplex mode with 13 bias PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 16 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8576C are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data rate of 100 kHz, fclk should be chosen to be above 125 kHz. 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCF8576s or PCF8566s in the system. Remark: The PCF8576C is backwards compatible with the PCF8576 (Voper up to 9 V). Where resistor Rext (on pin OSC) to VSS is present, the internal oscillator is selected. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. Remark: A clock signal must always be supplied to the device. Removing the clock, freezes the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The timing of the PCF8576C sequences the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCF8576Cs in the system. The timing also generates the LCD frame frequency which is derived as an integer division of the clock frequency (see Table 6). The frame frequency is set by the mode set commands when an internal clock is used or by the frequency applied to the pin CLK when an external clock is used. Table 6. LCD frame frequencies [1] Frame frequency Nominal frame frequency (Hz) 69 [2] 65 [3] PCF8576C mode Normal mode f clk f fr = -----------2880 f clk f fr = --------480 Power saving mode [1] [2] [3] The possible values for fclk see Table 20. For fclk = 200 kHz. For fclk = 31 kHz. The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power consumption. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 17 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. When a device is unable to process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and one column of the display RAM. 7.8 Shift register The shift register transfers display information from the display RAM to the display register while previous data is displayed. 7.9 Segment outputs The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data residing in the display register. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.10 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. * In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left as an open-circuit. * In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. * In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. * In static drive mode: the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.11 Display RAM The display RAM is a static 40 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a direct relationship between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 12 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 18 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates display RAM addresses (columns)/segment outputs (S) 0 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 mbe525 1 2 3 4 35 36 37 38 39 Display RAM bit map showing direct relationship between RAM addresses and segment outputs; also between bits in a RAM word and the backplane outputs. Fig 12. Display RAM bit map When display data is transmitted to the PCF8576C, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 13; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 13: * In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. * In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. * In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. * In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2 and 3 of two successive 4-bit RAM words. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 19 of 56 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 09 -- 9 July 2009 (c) NXP B.V. 2009. All rights reserved. PCF8576C_9 NXP Semiconductors drive mode LCD segments LCD backplanes display RAM filling order display RAM addresses (columns)/segment outputs (S) byte1 transmitted display byte Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6 e d f a b g c Sn+1 Sn Sn+7 DP BP0 display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3 n c x x x n+1 b x x x n+2 a x x x n+3 f x x x n+4 g x x x n+5 e x x x n+6 d x x x n+7 DP x x x MSB cba f LSB g e d DP BP0 Sn 1:2 Sn+1 f g a b display RAM addresses (columns)/segment outputs (S) byte1 byte2 n display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3 a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP multiplex Sn+2 Sn+3 e d c BP1 DP Sn+1 1:3 Sn+2 f a b g BP0 Sn display RAM bits (rows)/ backplane outputs (BP) display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 n 0b 1 DP 2c 3x n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB multiplex e d c Universal LCD driver for low multiplex rates BP1 DP BP2 e display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 byte4 byte5 Sn 1:4 f g a b BP0 BP2 display RAM bits (rows)/ backplane outputs (BP) n 0a 1c 2b 3 DP n+1 f e g d MSB a c b DP f LSB egd multiplex e c d BP1 DP PCF8576C BP3 Sn+1 001aaj646 x = data bit unchanged. Fig 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus 20 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 7.12 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load data pointer command (see Table 13). After this, the data byte is stored starting at the display RAM address indicated by the data pointer (see Figure 13). Once each byte is stored, the data pointer is automatically incremented based on the selected LCD configuration. The contents of the data pointer are incremented as follows: * * * * In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two. If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. 7.13 Sub-address counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device select command (see Table 14). If the contents of the subaddress counter and the hardware subaddress do not match then data storage is blocked but the data pointer will be incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576C occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1:3 multiplex mode). 7.14 Bank selector 7.14.1 Output bank selector The output bank selector (see Table 15), selects one of the four bits per display RAM address for transfer to the display register. The actual bit selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. * In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially by the contents of bit 1, bit 2 and then bit 3. * In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially. * In 1:2 multiplex mode: bits 0 and 1 are selected. * In the static mode: bit 0 is selected. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 21 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14.2 Input bank selector The input bank selector (see Table 15) loads display data into the display RAM based on the selected LCD drive configuration. Using the bank select command, display data can be loaded in bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. The input bank selector functions independently of the output bank selector. 7.15 Blinker The display blinking capabilities of the PCF8576C are very versatile. The whole display can be blinked at frequencies selected by the blink command. The blinking frequencies are integer fractions of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7). Table 7. Blink frequencies Normal operating mode ratio Power saving mode ratio Blink frequency blinking off 2 Hz Blinking mode off 1 f clk f blink = --------------92160 f clk f blink = ------------------184320 f clk f blink = ------------------368640 f clk f blink = --------------15360 f clk f blink = --------------30720 f clk f blink = --------------61440 2 1 Hz 3 0.5 Hz An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the blink command (see Table 16). In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blink frequency, this can be done using the mode set command to set and reset the display enable bit E at the required rate (see Table 9). PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 22 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 8. Basic architecture 8.1 Characteristics of the I2C-bus The I2C-bus provides bidirectional, two-line communication between different IC or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When connected to the output stages of a device, both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 8.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 14. SDA SCL data line stable; data valid change of data allowed mba607 Fig 14. Bit transfer 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 15. SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 15. Definition of START and STOP conditions 8.1.2 System configuration A device generating a message is a transmitter and a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is illustrated in Figure 16. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 23 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 16. System configuration 8.1.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. Acknowledgement on the I2C-bus is illustrated in Figure 17. * A slave receiver which is addressed must generate an acknowledge after the reception of each byte. * A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). * A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will now generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 17. Acknowledgement on the I2C-bus PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 24 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 8.1.4 PCF8576C I2C-bus controller The PCF8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576C are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two devices with a common I2C-bus slave address have the same hardware subaddress. In the power-saving mode it is possible that the PCF8576C is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are completed. This is known as the clock synchronization feature of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. 8.1.5 Input filter To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.2 I2C-bus protocol Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C. The least significant bit of the slave address that a PCF8576C responds to is defined by the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on the same I2C-bus which allows: * Up to 16 PCF8576Cs on the same I2C-bus for very large LCD applications. * The use of two types of LCD multiplex on the same I2C-bus. The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8576C slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8576Cs. The last command byte is tagged with a cleared most significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8576Cs on the bus. After the last command byte, a series of display data bytes (n) may follow. These display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8576C device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8576C. After the last display byte, the I2C-bus master issues a STOP condition (P). PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 25 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates R/W slave address S 0 1 1 1 0 0A 0AC 0 1 byte acknowledge by all addressed PCF8576Cs acknowledge by A0, A1 and A2 selected PCF8576C only S COMMAND A DISPLAY DATA A P n 1 byte(s) n 0 byte(s) update data pointers and if necessary, subaddress counter mbe538 Fig 18. I2C-bus protocol 8.3 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Figure 19. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. The five commands available to the PCF8576C are defined in Table 8. MSB C REST OF OPCODE LSB msa833 (1) C = 0; last command (2) C = 1; commands continue Fig 19. General format of byte command Table 8. Command mode set Definition of PCF8576C commands OPCODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 1 0 LP E B M1 M0 Section 8.3.1 defines LCD drive mode, LCD bias configuration, display status and power dissipation mode Section 8.3.2 data pointer to define one of 40 display RAM addresses Section 8.3.3 define one of eight hardware subaddresses Section 8.3.4 bit I: defines input bank selection (storage of arriving display data); bit O: defines output bank selection (retrieval of LCD display data) Section 8.3.5 defines the blink frequency and blink mode (c) NXP B.V. 2009. All rights reserved. Reference Description load data pointer C 0 1 1 P5 1 1 P4 0 1 P3 0 1 P2 A2 0 P1 A1 I P0 A0 O device select C bank select C blink C 1 1 1 0 A BF1 BF0 PCF8576C_9 Product data sheet Rev. 09 -- 9 July 2009 26 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 8.3.1 Mode set command Table 9. LCD drive mode command bit description Bit Backplane BP0 BP0, BP1 BP0, BP1, BP2 BP0, BP1, BP2, BP3 M1 0 1 1 0 M0 1 0 1 0 LCD drive mode Drive mode static 1:2 1:3 1:4 Table 10. LCD bias 1 3 1 2 LCD bias configuration command bit description Bit B 0 1 Display status command bit description[1] Bit E 0 1 bias bias Table 11. Display status disabled (blank) enabled [1] The possibility to disable the display allows implementation of blinking under external control. Table 12. Power dissipation mode command bit description Bit LP 0 1 Display status normal mode power saving mode 8.3.2 Load data pointer command Table 13. Load data pointer command bit description Bits P5 P4 P3 P2 P1 P0 Description 6 bit binary value, 0 to 39 8.3.3 Device select command Table 14. Device select command bit description Bits A2 A1 A0 Description 3 bit binary value, 0 to 7 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 27 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 8.3.4 Bank select command Table 15. Bank Input bank RAM bit 0 RAM bit 2 Output bank RAM bit 0 RAM bit 2 [1] Bank select command[1] Mode Static 1:2 multiplex drive mode RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 O I 0 1 0 1 Bit Value The bank select command has no effect in 1:3 or 1:4 multiplex drive modes. 8.3.5 Blink command Table 16. Blink frequency command bit description Bit BF1 off 1 2 3 Table 17. 0 0 1 1 Blink mode command bit description Bit A 0 1 BF0 0 1 0 1 Blink frequency Blink mode normal blinking alternate RAM bank blinking 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8576C and coordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. 9. Internal circuitry VLCD VSS SDA, SCL CLK, OSC, A0 to A2, SA0, SYNC VDD BP0 to BP3, S0 to S39 013aaa109 Fig 20. Device protection diagram PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 28 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VLCD VI supply voltage LCD supply voltage input voltage [1] Conditions Min -0.5 Max 8.0 8.0 Unit V V V VDD - 8.0 VDD -0.5 on each of the pins SCL, SDA, CLK, SYNC, SA0, OSC and A0 to A2 on each of the pins S0 to S39 and BP0 to BP3 [1] VO II IO IDD ISS IDD(LCD) Ptot Po Tstg VESD Ilu [1] [2] [3] [4] [5] output voltage input current output current supply current ground supply current LCD supply current total power dissipation output power storage temperature electrostatic discharge voltage latch-up current Values with respect to VDD. -0.5 -20 -25 -50 -50 -50 - 8.0 +20 +25 +50 +50 +50 400 100 +150 4000 200 100 V mA mA mA mA mA mW mW C V V mA [2] -65 - HBM MM [3] [4] [5] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %. Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115. Pass level; latch-up testing, according to JESD78. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 29 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 11. Static characteristics Table 19. Static characteristics VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD - 6.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD IDD IDD(lp) Logic VIL VIH VOL VOH IOL IL IL(OSC) Ipd RSYNC_N VPOR CI VIL VIH IOH(CLK) IOL(SDA) LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current leakage current leakage current on pin OSC pull-down current SYNC resistance power-on reset voltage input capacitance LOW-level input voltage HIGH-level input voltage HIGH-level output current on pin CLK LOW-level output current on pin SDA voltage on pin BP voltage on pin S resistance on pin BP resistance on pin S VLCD VDD - 3 V for 13 bias. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. Resets all logic when VDD < VPOR. Periodically sampled, not 100 % tested. Outputs measured one at a time. (c) NXP B.V. 2009. All rights reserved. Parameter supply voltage LCD supply voltage supply current: low-power mode supply current Conditions Min 2.0 [1] Typ - Max 6.0 120 60 Unit V A A VDD - 6.0 - VDD - 2.0 V fclk = 200 kHz VDD = 3.5 V; VLCD = 0 V; fclk = 35 kHz; A0, A1 and A2 connected to VSS on pins CLK, SYNC, OSC, A0 to A2 and SA0 on pins CLK, SYNC, OSC, A0 to A2 and SA0 IOL = 0 mA IOH = 0 mA VOL = 1.0 V; VDD = 5.0 V; on pins CLK and SYNC VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 VI = VDD VI = 1.0 V; VDD = 5.0 V; on pins A0 to A2 and OSC [2] VSS 0.7VDD 1 -1 -1 15 20 [3] [4] 50 50 1.0 - 0.3VDD VDD 0.05 +1 +1 150 150 1.6 7 0.3VDD 6.0 - V V V V mA A A A k V pF V V mA mA VDD - 0.05 - VSS 0.7VDD I2C-bus; pins SDA and SCL VOH = 4.0 V; VDD = 5.0 V VOL = 0.4 V; VDD = 5.0 V -1 3 LCD outputs VBP VS RBP RS [1] [2] [3] [4] [5] Cbpl = 35 nF; on pins BP0 to BP3 Csgm = 5 nF; on pins S0 to S39 VLCD = VDD - 5 V; on pins BP0 to BP3 VLCD = VDD - 5 V; on pins S0 to S39 [5] [5] -20 -20 - - +20 +20 5 7.5 mV mV k k PCF8576C_9 Product data sheet Rev. 09 -- 9 July 2009 30 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 11.1 Typical supply current characteristics mbe530 mbe529 50 ISS (A) 40 normal mode 50 -IDD(LCD) (A) 40 30 30 20 power-saving mode 10 20 10 0 0 100 ffr (Hz) 200 0 0 100 ffr (Hz) 200 VDD = 5 V; VLCD = 0 V; Tamb = 25 C VDD = 5 V; VLCD = 0 V; Tamb = 25 C Fig 21. ISS as a function of ffr Fig 22. -IDD(LCD) as a function of ffr 50 ISS (A) 40 normal mode fclk = 200 kHz mbe528 50 -IDD(LCD) (A) 40 85 C 30 25 C mbe527 30 20 20 10 power-saving mode fclk = 35 kHz -40 C 10 0 0 5 VDD (V) 10 0 0 5 VDD (V) 10 VLCD = 0 V; external clock; Tamb = 25 C VLCD = 0 V; external clock; Tamb = 25 C Fig 23. ISS as a function of VDD Fig 24. -IDD(LCD) as a function of VDD PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 31 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 11.2 Typical LCD output characteristics mbe532 mbe526 10 RO(max) (k) 2.5 RO(max) (k) 2.0 RS RS RBP 1 1.5 RBP 1.0 0.5 10-1 0 3 VDD (V) 6 0 -40 0 40 80 120 Tamb (C) VLCD = 0 V; Tamb = 25 C VDD = 5 V; VLCD = 0 V Fig 25. RO(max) as a function of VDD Fig 26. RO(max) as a function of Tamb PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 32 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 20. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol fclk Parameter clock frequency power saving mode; VDD = 3 V tclk(H) tclk(L) tSYNC_NL tPD(drv) tBUF tHD;STA tSU;STA tLOW tHIGH tr tf Cb tSU;DAT tHD;DAT tSU;STO [1] [2] Conditions [1] Min Typ Max Unit Timing characteristics: driver timing waveforms (see Figure 27) normal mode; VDD = 5 V 125 21 1 1 1 VLCD = VDD - 5 V [2] 200 31 - 315 48 400 30 1 0.3 400 - kHz kHz s s ns s s s s s s s s s pF ns ns s clock HIGH time clock LOW time SYNC LOW time driver propagation delay bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line data set-up time data hold time set-up time for STOP condition tPD(SYNC_N) SYNC propagation delay 4.7 4.0 4.7 4.7 4.0 250 0 4.0 Timing characteristics: I2C-bus (see Figure 28) fclk < 125 kHz, I2C-bus maximum transmission speed is derated. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 33 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 1/fCLK tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S39 (VDD = 5 V) 0.5 V tPD(drv) mce424 tPD(SYNC_N) Fig 27. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 28. I2C-bus timing waveforms PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 34 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation In large display configurations, up to 16 PCF8576Cs can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 21. Cluster 1 Addressing cascaded PCF8576C Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Cascaded PCF8576Cs are synchronized. They can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8576Cs of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 29). The PCF8576C can also be cascaded with the PCF8566. The connections are identical to the PCF8576C cascade. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 35 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates VDD SDA 1 SCL 2 SYNC CLK 3 5 VLCD 12 17 to 56 40 segment drives LCD PANEL PCF8576CT 13,15, 14,16 A0 A1 A2 SAO VSS BP0 to BP3 (open-circuit) (up to 2560 elements) 4 OSC 6 VLCD VDD R tr 2CB 5 HOST MICROPROCESSOR/ MICROCONTROLLER SDA SCL SYNC CLK OSC 1 2 3 4 6 mbe533 VDD VLCD 12 17 to 56 40 segment drives PCF8576CT 13,15, 14,16 4 backplanes BP0 to BP3 7 VSS A0 8 A1 9 A2 10 11 SA0 VSS Fig 29. Cascaded PCF8576C configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8576C asserts the SYNC line and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF8576C to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8576C are shown in Figure 30. For single plane wiring of packaged PCF8576Cs and chip-on-glass cascading, see Figure 31. . PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 36 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse can be countered by an external pull-up resistor. Fig 30. Synchronization of the cascade for the various PCF8576C drive modes PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 37 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates SDA SCL SYNC CLK VDD VSS VLCD SDA SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 open 42 41 40 39 38 S25 S24 S23 S22 S21 BP1 BP3 S40 S41 S42 S43 34 S7 S8 S9 S10 S11 S0 backplanes S10 S11 24 25 26 27 28 33 32 31 30 29 S17 S16 S15 S14 S13 S12 S12 S13 S39 segments S40 S50 S47 S48 S49 S50 S51 S51 24 25 26 27 28 15 16 17 18 19 20 34 33 32 31 30 29 S57 S56 S55 S54 S53 S52 S52 S53 S79 mbe537 1 2 3 4 5 6 7 8 9 10 11 12 BP0 BP2 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 PCF8576CT 15 16 17 18 19 20 PCF8576CT 42 41 40 39 38 Fig 31. Single plane wiring of packaged PCF8576CTs PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 38 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 14. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 32. Package outline SOT314-2 (LQFP64) of PCF8576CH PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 39 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates VSO56: plastic very small outline package; 56 leads SOT190-1 D E A X c y HE vM A Z 56 29 Q A2 A1 pin 1 index Lp L 1 e bp 28 wM detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 3.3 0.13 A1 0.3 0.1 0.012 0.004 A2 3.0 2.8 0.12 0.11 A3 0.25 0.01 bp 0.42 0.30 c 0.22 0.14 D (1) 21.65 21.35 E (2) 11.1 11.0 e 0.75 HE 15.8 15.2 L 2.25 0.089 Lp 1.6 1.4 0.063 0.055 Q 1.45 1.30 v 0.2 w 0.1 y 0.1 Z (1) 0.90 0.55 0.017 0.0087 0.85 0.012 0.0055 0.84 0.44 0.62 0.0295 0.43 0.60 0.057 0.035 0.008 0.004 0.004 0.051 0.022 7o o 0 Notes 1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT190-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-08-11 03-02-19 Fig 33. Package outline SOT190-1 (VSO56) of PCF8576CT PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 40 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates HTSSOP56: plastic thermal enhanced thin shrink small outline package; 56 leads; body width 6.1 mm; exposed die pad SOT793-1 D E A X c y exposed die pad HE vM A Z Dh 56 29 A A2 Eh pin 1 index A1 L detail X Lp (A 3) 1 bp 28 wM e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.80 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 Dh 4.3 4.1 E (2) 6.2 6.0 Eh 4.3 4.1 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 v 0.2 w 0.08 y 0.1 Z (1) 0.4 0.1 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT793-1 REFERENCES IEC 143E36T JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 03-03-04 Fig 34. Package outline SOT793-1 (HTSSOP56) of PCF8576CTT PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 41 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 15. Bare die outline Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm PCF8576CU/10 D 34 C1 35 20 e 21 A X x 0 E 0 y (4) 50 C2 51 56 1 7 F 8 P4 P3 P2 P1 detail X 0 Dimensions Unit mm A D E e(3) P1(1) P2(2) P3(1) P4(2) 0.5 scale 1 mm max 0.610 nom 0.38 2.82 3.00 0.110 0.097 0.110 0.097 min 0.096 Note 1. Pad size 2. Passivation opening 3. Dimension not drawn to scale 4. Marking code: PC8576C-1 Outline version PCF8576CU/10 References IEC JEDEC JEITA European projection PCF8576CU_10_do Issue date 09-06-02 Fig 35. Bare die outline of PCF8576CU/10 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 42 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm PCF8576CU D 34 C1 35 20 e 21 A X x 0 E 0 y (4) 50 C2 51 56 1 7 F 8 P4 P3 P2 P1 detail X 0 Dimensions Unit mm A D E e(3) P1(1) P2(2) P3(1) P4(2) 0.5 scale 1 mm max 0.610 nom 0.38 2.82 3.00 0.110 0.097 0.110 0.097 min 0.096 Note 1. Pad size 2. Passivation opening 3. Dimension not drawn to scale 4. Marking code: PC8576C-1 Outline version PCF8576CU References IEC JEDEC JEITA European projection PCF8576CU_do Issue date 29-06-02 Fig 36. Bare die outline of PCF8576CU PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 43 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Bare die; 56 bumps; 3.0 x 2.82 x 0.40 mm PCF8576CU/2 D 34 C1 35 20 e 21 X x 0 E 0 y (2) 50 C2 51 56 1 7 F 8 Y L A b detail X detail Y 0 Dimensions Unit mm A A1 A2 b D 2.82 E 3.00 0.096 e(1) 0.610 0.094 L 0.5 scale 1 mm A2 A1 max nom 0.398 0.0175 0.380 0.094 min Note 1. Dimension not drawn to scale 2. Marking code: PC8576C-2 Outline version PCF8576CU/2 References IEC JEDEC JEITA European projection PCF8576CU_2_do Issue date 09-06-02 Fig 37. Bare die outline of PCF8576CU/2 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 44 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Table 22. Pad and bump description for PCF8576CU All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip. Symbol SDA SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 PCF8576C_9 Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 X (m) -74 148 355 534 742 913 1087 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1290 1074 914 741 581 408 248 75 -85 -258 -418 -591 -751 -924 -1084 -1290 -1290 -1290 -1290 -1290 Y (m) -1380 -1380 -1380 -1380 -1380 -1380 -1380 -1284 -1116 -945 -751 -485 125 285 458 618 791 951 1124 1284 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1380 1243 1083 910 750 577 Description I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization input/output external clock input/output supply voltage internal oscillator enable input subaddress input subaddress input subaddress input subaddress input logic ground LCD supply voltage LCD backplane output LCD backplane output LCD backplane output LCD backplane output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 45 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Table 22. Pad and bump description for PCF8576CU All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip. Symbol S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 Table 23. Symbol C1 C2 F Pad 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 X (m) -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1290 -1083 -923 -750 -590 -417 -257 Y (m) 417 244 84 -89 -249 -422 -582 -755 -915 -1088 -1248 -1380 -1380 -1380 -1380 -1380 -1380 Description LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output Alignment marks X (m) -1290 -1295 1305 Y (m) 1385 -1385 -1405 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Packing information 17.1 Tray information Tray information for the PCF8576CU and PCF8576CU/2 is shown in Figure 38, Figure 39 and Table 24. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 46 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates G A C H D B F E 001aai237 Fig 38. Tray details marking code 001aaj619 Fig 39. Tray alignment Table 24. Symbol A B C D PCF8576C_9 Tray dimensions Description pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction Value 5.59 mm 6.35 mm 3.22 mm 3.50 mm (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 47 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Tray dimensions Description tray width; x direction tray width; y direction cut corner to pocket 1,1 center cut corner to pocket 1,1 center tray thickness tray cross section tray cross section pocket depth number of pockets; x direction number of pockets; y direction Value 50.67 mm 50.67 mm 5.78 mm 6.29 mm 3.94 mm 1.76 mm 2.46 mm 0.89 mm 8 7 Table 24. Symbol E F G H J K L M x y PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 48 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 17.2 Film frame carrier information 100 m S aw lane 200 m detail X Marking code X Straight edge of the wafer 013aaa112 Fig 40. Layout of wafer on film frame carrier of PCF8576CU/10 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 49 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 50 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 18.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 41) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 25 and 26 Table 25. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 26. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 41. PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 51 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 52 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 19. Abbreviations Table 27. Acronym DC FFC HBM I2C IC LCD LSB MM MOS MSB MSL PCB POR RC RAM RMS SCL SDA SMD Abbreviations Description Direct Current Film Frame Carrier Human Body Model Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display Least Significant Bit Machine Model Metal Oxide Semiconductor Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Resistance-Capacitance Random Access Memory Root Mean Square Serial Clock Line Serial Data Line Surface Mount Device PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 53 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 20. Revision history Table 28. Revision history Release date 20090709 Data sheet status Product data sheet Change notice Supersedes PCF8576C_8 Document ID PCF8576C_9 Modifications: * * * * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Symbols updated and checked with NXP Symbols Library Changed values in limiting values table (see Table 18) from relative to absolute values Added TT type Added bare die outline drawings Added FFC information Rewritten chapter 7.3 (see Section 7.3) Product specification Product specification Product specification Product specification Product specification Product specification Product specification Product specification PCF8576C_7 PCF8576C_6 PCF8576C_5 PCF8576C_4 PCF8576C_3 PCF8576C_2 PCF8576C_1 - PCF8576C_8 PCF8576C_7 PCF8576C_6 PCF8576C_5 PCF8576C_4 PCF8576C_3 PCF8576C_2 PCF8576C_1 20041122 20011002 19980730 19971114 19970402 19970203 19961209 19950630 PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 54 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 21. Legal information 21.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 21.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8576C_9 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 -- 9 July 2009 55 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.14.1 7.14.2 7.15 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . . 9 Power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 LCD bias generator. . . . . . . . . . . . . . . . . . . . . 10 LCD voltage selector . . . . . . . . . . . . . . . . . . . 10 LCD drive mode waveforms . . . . . . . . . . . . . . 12 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 13 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 15 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 16 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 17 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Display register . . . . . . . . . . . . . . . . . . . . . . . . 18 Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 18 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sub-address counter . . . . . . . . . . . . . . . . . . . 21 Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output bank selector. . . . . . . . . . . . . . . . . . . . 21 Input bank selector . . . . . . . . . . . . . . . . . . . . . 22 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 23 Characteristics of the I2C-bus . . . . . . . . . . . . . 23 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 START and STOP conditions . . . . . . . . . . . . . 23 System configuration . . . . . . . . . . . . . . . . . . . 23 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24 PCF8576C I2C-bus controller . . . . . . . . . . . . . 25 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25 Command decoder . . . . . . . . . . . . . . . . . . . . . 26 Mode set command . . . . . . . . . . . . . . . . . . . . 27 Load data pointer command . . . . . . . . . . . . . . 27 Device select command . . . . . . . . . . . . . . . . . 27 Bank select command . . . . . . . . . . . . . . . . . . 28 8.3.5 8.4 9 10 11 11.1 11.2 12 13 13.1 14 15 16 17 17.1 17.2 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 Blink command. . . . . . . . . . . . . . . . . . . . . . . . Display controller . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Typical supply current characteristics. . . . . . . Typical LCD output characteristics . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Cascaded operation . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tray information . . . . . . . . . . . . . . . . . . . . . . . Film frame carrier information . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 29 30 31 32 33 35 35 39 42 46 46 46 49 50 50 50 50 51 53 54 55 55 55 55 55 55 56 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 July 2009 Document identifier: PCF8576C_9 |
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