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IP113A LF
Preliminary Data Sheet
10 /100Base-Tx/Fx Media Converter
Features
A 10/100BASE-TX/ 100BASE-FX converter Built in a 10/100BASE-TX transceiver Built in a PHY for 100BASE-FX Built in a 2-port switch - Pass all packets without address and CRC check (optional) - Supports modified cut-through frame forwarding for low latency - Supports pure converter mode data forwarding for extreme low latency - Supports flow control for full and half duplex operation - Bandwidth control - Forward 1600 bytes packet for management - Optional forward fragments Built in 128Kb RAM for data buffer Supports auto MDI-MDIX function Supports link fault pass through function Supports far end fault function LED display for link/activity, full/half, 10/100 Built in a watchdog timer to monitor internal switch error Supports EEPROM Configuration 0.25u CMOS technology Single 2.5V power supply 48-pin LQFP package Support Lead Free package (Please refer to the Order Information)
General Description
IP113A LF can be a 10/100BASE-TX to 100BASE-FX converter. It consists of a 2-port switch controller, a fast Ethernet transceiver and a PHY for 100BASE-FX. The transceivers in IP113A LF are designed in DSP approach with advance 0.25-um technology; this results in high noise immunity and robust performance. IP113A LF not only supports store and forward mode, it also supports modified cut through mode and pure converter mode for low latency data forwarding. IP113A LF can transmit packet(s) up to 1600 bytes to meet requirement of extra long packets. IP113A LF supports IEEE802.3x, collision base backpressure, and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins.
1/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
Block Diagram
SSRAM
PLL/ Clock Generator
RXIP RXIM TXOP TXOM
10/100M TX PHY
MII Two port switch
MII
100M FX
FXSD FXRDP FXRDM FXTDP FXTDM
SCL SDA
EEPROM I/F
Forward Mode Control
LED I/F
LED
Revision History
Revision # IP113A LF-DS-R01 IP113A LF-DS-R02 IP113A LF-DS-R03 IP113A LF-DS-R04 IP113A LF-DS-R05 IP113A LF-DS-R06 Change Description Initial release. Remove Operation Junction Temperature. TP port should be linked at 100M full duplex when working at this mode. Add the order information for lead free package. Revise the diagram. TP_FORCE (Pin24) &X_EN(Pin29) It is an input pin during reset period. The default value is latched at the end of reset. IP113A LF-DS-R07 Remove internal pull-high resistance & pull-low resistance on page 5. Modify the IPL : pull-low and IPH : pull-high IP113A LF-DS-R08 Add Power Pin description on Page10
2/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
Application Diagram
FX
Fiber Module
IP113A LF
TX
Applications
Un-managed converter
1 0 B A S E _ T /1 0 0 B A S E -T X
PHY1
S W IT C H
1 0 0 B A S E -F X
PHY2
RAM
IP 1 1 3 A L F
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
PIN Diagram
OSCI X2 VCC LED_FX_SD/ SPEED_MODE
48 47 46 45 44 43 42 41 40 39 38 37 AVCC BGRES NC GND RXIP RXIM AVCC TXOP TXOM GND AVCC A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 LED_FX_LINK/ FX_FULL GND_IO VCC_IO LED_TP_SPD LED_TP_FDX LED_TP_LINK LED_FX_FEF_DET/ DUPLEX_MODE X_EN RESETB TSE TSM NC
IP113A LF
LED_FX_FDX / A2 31 30 29 28 27 26 25
FXRDP FXRDM NC
VCC NC SCL / A0 SDA VCC GND GND
4/22 Copyright (c) 2004, IC Plus Corp.
DIRECT_WIRE FAST_FWD TP_FORCE
FXTDP FXTDM FXSD VCC GND LFP
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
1. PIN Description
Type I O IPL IPH Description Input pin Output pin Input pin with internal pull-low resistor. Input pin with internal pull-high resistor.
Pin no. Transceiver 5, 6 8, 9 2
Label
Type
Description
RXIP, RXIM TXOP, TXOM BGRES
I O O
TP receive TP transmit Band gap resistor It is connected to GND through a 6.19k (1%) resistor in application circuit. 100Base-FX signal detect Fiber signal detect. It is an input signal from fiber MAU. Fiber signal detect is active if the voltage on FXSD is higher than the threshold voltage, which is 1.35v 5% when VCC is equal to 2.5v. Fiber receiver data pair Common-mode voltage of FXRDP and FXRDM are suggested to near 0.5x AVCC. When voltage peak-to-peak>0.1V,FXRX could be workable. Fiber transmitter data pair FXTX with the external 100 resistor. Common-mode voltage of FXTDP and FXTDM are suggested to near 0.5x AVCC. Swing of Voltage 0.8V.
18
FXSD
I
13, 14
FXRDP, FXRDM
I
16, 17
FXTDP, FXTDM
O
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IP113A LF
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. LED pins 31 LED_TP_LINK O TP port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) TP port speed LED On: 100M, Off: 10M TP port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) Fiber port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port signal detect On: fiber signal detected, Off: fiber unplugged O Far end fault pattern received For End Fault Patterns Receive LED On: 80ms, LED Off: 20ms For End Fault Pattern not Receive LED always Off Label Type Description
33 32
LED_TP_SPD LED_TP_FDX
O O
36
LED_FX_LINK
O
37
LED_FX_FDX
O
38 30
LED_FX_SD LED_FX_FEF_DET
Note: The output of LED pin is logic low when the LED is on.
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IP113A LF
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type O/IPH Description
MC operation mode 29 X_EN IEEE 802.3X enable on TP port and fiber port 1: enable (default), 0: disable It is an input pin during reset period. The default value is latched at the end of reset. After reset, it becomes an output pin for testing. It should be connected to GND through a 1k ohm resister to set 0. Local TP port auto negotiation enable 1: TP port supports auto-negotiation with limited capability defined in SPEED_MODE and DUPLEX_MODE. 0: TP port supports auto-negotiation with 10M/100M, full/ half capability (default) The default value may be updated by either programming EEPROM register 3.5 or MII register 20.13. It is an input pin during reset period. The default value is latched at the end of reset. After reset, it becomes an output pin for testing. It should be connected to VCC through a 1k ohm resister to set 1. Local TP port speed 1: TP port has the 100Mb speed ability 0: TP port has the 10Mb speed ability only It is valid only if TP_FORCE is enabled. 30 DUPLEX_MODE IPH Local TP port duplex 1: TP port has the Full duplex ability 0: TP port has the Half duplex ability only It is valid only if TP_FORCE is enabled. 36 FX_FULL IPH Set the duplex of fiber port 1: full duplex (default) 0: half duplex
24
TP_FORCE
O/IPL
38
SPEED_MODE
IPH
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type Description
MC operation mode
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. Label Type Description
MC operation mode 21 LFP IPL Link fault pass through (LFP) 1: enable Link status of one port is forwarded to the other port. 0: disable (default) DIRECT_ FAST_FWD Function WIRE 0 0 Store and forward switch mode (default) 0 1 Modified cut-through switch mode 1 0 Converter mode 1 1 Converter mode with auto-change-forward function Store and forward switch mode: IP113A LF will begin to transmit a frame right after the completion of receiving a frame. Modified cut-through switch mode: IP113A LF will begin to forward a frame after the first 64 bytes data received. TP port should be forced at 100M at this mode. Converter mode: Incoming frames are not buffered in IP113A LF to achieve the min latency. Both TP port and fiber port of IP113A LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802.3. Converter mode with auto-change-forward function: IP113A LF will change to forward mode if it detects the speed is different in TP port and FX port. In converter mode, IP113A LF forwards IEEE802.3x pause frame directly. In the other modes, IP113A LF doesn't forward IEEE802.3x pause frame directly, it sends out pause frame when its internal buffer is full.
22, 23
DIRECT_WIRE, FAST_FWD
IPL
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
1. PIN Description (continued)
Pin no. EEPROM interface 45, 46 37, 12, 46 SDA, SCL A[2:0] IPH, O EEPROM interface IPL PHY address IP113A LF uses A[2:0] as EEPROM address to read EPROM. Label Type Description
Pin no. Misc. 28 41, 40
Label
Type
Description
RESETB OSCI, X2
I I, O
Reset It is low active. Crystal pins OSCI and X2 are connected to a 25Mhz crystal. If a 25MHz oscillator is used, OSCI is connected to the oscillator's output and X2 should be left open.
26, 27
TSM, TSE
IPL
Scan pins These two pins should be left open or connected to ground for normal operation.
Pin no. Power 1,7,11 19,39,44 34 35 4,10,20, 42,43 AVCC VCC
Label
Type 2.5V Analog Power 2.5V Digital Power
Description
VCC_IO GND_IO GND
3.3V or 2.5V Digital Power I/O Ground Ground
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
2. Functional Description
Data forwarding IP113A LF supports three types of data forwarding mode, store & forward mode, modified cut-through mode and pure converter mode. It can forward a frame despite of its address and CRC error. IP113A LF begins to forward the received data only after it receives the frame completely. The latency depends on the packet length. Modified cut-through mode IP113A LF begins to forward the received data when it receives the first 64 bytes of the frame. The latency is about 512 bits time width. The maximum packet length can be up to1600 bytes in this mode. Please refer to the pin description of FAST_FWD for configuration information. Pure converter mode IP113A LF operates with the minimum latency in this mode. The transmission flow does not wait until entire frame is ready, but instead it forwards the received data immediately after the data being received. Both transceivers are interconnected via internal MII signals, therefore the internal switch engine and data buffer are not used. Both TP port and fiber port of IP113A LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802.3.The packet length is not limited at this mode. Please see pin description of DIRECT_WIRE for configuration information. Fragment forwarding IP113A LF forwards CRC error packets but it will filter fragments when it works in modified cut-through mode. IP113A LF forwards fragments if user turns on bit 3 of EEPROM register 2.
11/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
TP port force mode The TP port of IP113A LF can work at auto mode or force mode. The following table shows all of the combination of its TP port. Link partner's capability AN on {TP_FORCE, SPEED_MODE, DUPLEX_MODE} 011 010 001 000 111 110 101 100 IP113A LF's link result 100F 100H IP113A LF's capability 100/10M, Full/Half, AN on 100/10M, Half, AN on 10M, Full/Half, AN on 10M, Half, AN on 100M, Full, AN on 100M, Half, AN on 10M, Full, AN on 10M, Half, AN on 100F 100H X 100H X X X X 100F X X 100H X X X X 10F X 10F X X X 10F X 10H 10H 10H 10H X X X 10H 100H 100H 100H 100H 100F 100H X X 100H 100H 100H 100H 100F 100H X X 10H 10H 10H 10H X X 10F 10H 10H 10H 10H 10H X X 10F 10H 10F 10H 100F 100H 10F 10H AN off
Note: AN on: with auto-negotiation capability AN off: without auto-negotiation capability 100F: 100M full duplex 100H: 100M half duplex 10F: 10M full duplex 10H: 10M half duplex
12/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
Link fault pass through When link fault pass through function is enabled, link status on TX port will inform the FX port of the same device and vice versa. From the link fault pass through procedure illustrates in the figure below, if link fail happens on IP113A LF's TX port (1), the local FX port sends non-idle pattern to notice the remote FX port (2). The remote FX port then forces its TX port to link failed after receiving the non-idle pattern (4). In other words, this mechanism will alert the link fault status of local TX port to the remote converter's TX port, and the link status of the remote TX port will become off. Link status LED will also be off for both IP113A LF and its link partner.
(3) fiber port gets remote link fault information remote IP113A LF (5) remote TP link is off
(1) TP port link failed local IP113A LF
Switch1 or NIC 1
UTP
Fiber
UTP
Switch2 or NIC 2 link off
(2) fiber port sends non-idle pattern
(4) TP link fail
The procedure of link fault pass through
Normal case
remote Switch1 LED SW1 UTP IP113A LF Fiber IP113A LF UTP local Switch2 LED SW2
LED_TP_LINK1 LED_FX_LINK1
LED_FX_LINK2 LED_TP_LINK2
Link LED on SW1 ON
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 ON ON ON ON
Link LED on SW2 ON
Remote TP port disconnected
remote Switch1 LED SW1 UTP disconnect UTP LED SW2 local Switch2
IP113A LF
Fiber
IP113A LF
LED_TP_LINK1 LED_FX_LINK1
LED_FX_LINK2 LED_TP_LINK2
Link LED on SW1 Off
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Off Off Off Off
Link LED on SW2 Off
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
FX port disconnected
remote Switch1 LED SW1 UTP IP113A LF Fiber IP113A LF UTP local Switch2 LED SW2
LED_TP_LINK1 LED_FX_LINK1
LED_FX_LINK2 LED_TP_LINK2
Link LED on SW1 Off
LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Off Off Off Off
Link LED on SW2 Off
LED diagnostic functions for fault indication LED_TP_LINK LED_FX_LINK On Flash Off Off Off On Flash Off Off Off LED_FX_SD On On On Off On LED_FX_FEF_DET Off Off Off Off Flash Status Link ok Link ok & activity Remote TP link off Fiber RX off, Fiber TX/ RX off Fiber TX off
Note Flash: flash, period 100 ms Link fault pass through is enabled.
14/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
EEPROM - store the initial value IP113A LF supports two ways to load initial value of MII registers. The procedure is illustrated as below.
1. IP113A LF reads the default setting of MII register from pins
IP113A LF pins
2. IP113A LF updates the default setting of MII by reading EEPROM . If there exists an EEPROM
EEPROM
IP113A LF
3. After reading EEPROM, IP113A LF is virtually isolated from the EEPROM. Micro-controller can program both MII register and EEPROM.
EEPROM uC
IP113A LF SCL, SDA MDC, MDIO
4. IP113A LF reloads the content of EEPROM to recover the value in MII registers programmed by Micro-controller after power on reset.
EEPROM
IP113A LF
15/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
Auto MDI_MDIX IP113A LF supports auto MDI-MDIX. It is always enabled. The following is its application circuit for auto MDI-MDIX.
RXIP RXIM RD + RD AVCC TXOP TXOM TD + TD AVCC
IP113A LF 50 50
CT
IP113A LF 50 50
CT
MDI-MDIX 0.1u transformer 0.1u
MDI-MDIX transformer
GND
GND
IP113A LF's application circuit (auto MDI-MDIX on)
16/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
EEPROM registers Type R/W SC RO Pin(1) Description Read/Write Self-Clearing Read Only The default value is "1" and it depends on the setting of its corresponding pin. Type RC LL LH Pin(0) Description Read and Clear Latching Low Latching High The default value is "0" and it depends on the setting of its corresponding pin.
ROM
NAME
R/W
DESCRIPTION
DEFAULT
EEPROM enable register 0 0[7:0] -EEPROM enable register 0 This register should be filled with 55. IP113A LF will examine the specified pattern to confirm if there is a valid EEPROM. 55h
ROM
NAME
R/W
DESCRIPTION
DEFAULT
EEPROM enable register 1 1[7:0] -EEPROM enable register 1 This register should be filled with AA. IP113A LF will examine the specified pattern to confirm if there is a valid EEPROM. The initial setting is updated with the content of EEPROM only if the specified pattern 55AA is found. AAh
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
EEPROM registers (continued) ROM NAME R/W DESCRIPTION DEFAULT
Switch configuration register 1 2.0 2.1 2.2 2.3 reserved direct_wire fast_fwd mg_pass_fragment
_en
-----
The default value must be adopted for normal operation. Please see pin description of DIRECT_WIRE for more detail information. Please see pin description of FAST_FWD for more detail information. Pass fragment packet (>7B and <64B) 1: pass fragment 0: not pass fragment Collision 16 times drop enable 1: drop 0: not drop Collision back-off enable 1: back after collision 0: not back off after collision The default value must be adopted for normal operation. TP port backpressure control enable for half duplex 1: backpressure enable 0: backpressure disable The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. The default value must be adopted for normal operation. SSRAM BIST enable (R/W by EEPROM only) 1: BIST enable 0: bypass BIST This pin overwrites the setting on pin 26 TP_FORCE. TP receive enable 1: TP port can receive packet 0: TP port drop all received packet The default value must be adopted for normal operation.
0 Pin (0) Pin (0) 0
2.4
mg_col16_drop_en
--
0
2.5
mg_col_backoff _en reserved p01_mg_backpress_en
--
1
2.6 2.7
---
0 1
3.0 3.1 3.2 3.3 3.4
reserved reserved reserved reserved mg_em_bist_en
------
0 0 1 1 1
3.5 3.6
tp_force mg_receive_en
---
Pin (0) 1
3.7
reserved
--
0
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April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
ROM NAME R/W DESCRIPTION DEFAULT
Switch configuration register 2 4[7:0] p01_mg_port_page_no 5[7:0] p02_mg_port_page_no --TP port allocated memory pages The default is 120 pages with 64 bytes per page. FX port allocated memory pages The default is 120 pages with 64 bytes per page. 120d 120d
Note: p01_mg_port_page_no adds p02_mg_port_page_no must be equal to 240.
19/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
EEPROM registers (continued) ROM NAME R/W DESCRIPTION DEFAULT
Local MC extended register 6.0 6.1 6.2 reserved reserved p01_mg_auto_neg_en ---The default value must be adopted for normal operation. The default value must be adopted for normal operation. TP port auto-negotiation enable 1: TP auto-negotiation enable 0: TP auto-negotiation disable TP port speed selection 1: 100M, 0:10M TP port duplex mode selection 1: full duplex, 0:half duplex TP port flow control selection 1: on, 0:off The default value must be adopted for normal operation. Fiber port flow control/backpressure enable 1: enable, 0: disable Fiber port duplex mode (FX_FULL) 1: full duplex, 0:half duplex The default value must be adopted for normal operation. The default value must be adopted for normal operation. TP port input Rate Control 2'b00: full speed 2'b01: 1/4 speed 2'b10: 2/4 speed 2'b11: 3/4 speed TP port output Rate Control 2'b00: full speed 2'b01: 1/4 speed 2'b10: 2/4 speed 2'b11: 3/4 speed Link Fault Pass through enable (LFP) 1: enable, 0: disable 0 0 1
6.3 6.4 6.5 6.6 6.7 7.0 7.1 7.2
p01_mg_speed_mode p01_mg_duplex_mode p01_mg_flow_ctrl_en reserved p02_mg_flow_ctrl_en p02_mg_duplex_mode reserved reserved
----------
1 1 1 0 Pin (1) 1 1 0 00
7[4:3] p01_mg_throttle_confg
7[6:5] p01_mg_throttle_confg
--
00
7.7
mg_link_pass_en
--
1
20/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
3. Signal Requirements
Absolute Maximum Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage -0.3V to Vcc+0.3V Input Voltage -0.3V to Vcc+0.3V Output Voltage -0.3V to Vcc+0.3V Storage Temperature -55C to 125C Ambient Operating Temperature (Ta) 0C to 70C DC Characteristic Operating Conditions Parameter Supply Voltage Power Consumption Input Clock Parameter Frequency Frequency Tolerance I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Sym. VIL VIH VOL VOH VCC_I O-0.4 Min. 2.0 0.4 Typ. Max. 0.8 Unit V V V V IOH=4mA IOL=4mA Conditions -100 Sym. Min. Typ. 25 Max. +100 Unit MHz PPM Conditions Sym. VCC Min. 2.375 Typ. 2.5 0.475 Max. 2.625 Unit V W Conditions VCC=2.5v
4. Order Information
Part No. IP113A IP113A LF Package 48-PIN LQFP 48-PIN LQFP Notice Lead free
21/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
IP113A LF
Preliminary Data Sheet
5. Package Detail
48 37
1
36
PH
12
25
13
HE
24
"E"
12" A2 GAUGE PLANE L L1 DETAIL "E" 13 24 Symbol A 12
2
D
E
unit
mm 1.600MAX. 0.050~0.150 1.400 + 0.05
A1 inch 0.0630MAX. 0.0020~0.0059 0.0551 + 0.0020
F SEATING PLANE
0.254
Fy
e
b 12"
D
c
25
A1 A2 b c D E e Hd
-
-
0.200TYP 0.127TYP 7.000 + 0.100 7.000 + 0.100
0.0078TYP 0.0050TYP 0.2756 + 0.0039 0.2756 + 0.0039
2
-
-
1
36
He L L1 y
0.500TYP 9.000 + 0.250 9.000 + 0.250 0.600 + 0.150
-
0.0196TYP 0.3543 + 0.0098 0.3543 + 0.0098
0.0236 + 0.006 0.0393REF 0.0039MAX. 0"~7"
48
37
1.000REF 0.100MAX. 0"~7"
Notes: 1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSION. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION / INTRUSION. 3. MAX. END FLASH IS 0.15MM. 4. MAX. DAMBAR PROTRUSION IS 0.13MM. GENERAL APPEARANCE SPEC SHOULD BE BASED ON FINAL VISUAL INSPECTION SPEC.
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website : www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
22/22 Copyright (c) 2004, IC Plus Corp.
April 9, 2007 IP113A LF-DS-R08
A

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