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D a t a S h e e t , R e v . 1 . 0 , D e c . 2 00 8
TLE7184F
S y s t em I C f or B 6 m o to r d r i v e s
A u to m o t i v e P o w e r
TLE7184F
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 3 3.1 3.2 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 6 6.1 7 7.1 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.2.11 9.2.12 9.2.13 9.2.14 9.2.15 9.3 9.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Assignment TLE7184F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Default State of Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs and Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13
Shunt Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 V Low Drop Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interface, VDH Switch and INH Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Interface (IFMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDHS Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Output INHD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Modes, Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Diagnosis Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Shut Down (OTSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Prewarning (OTPW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Under Voltage Lockout (VS_UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Under Voltage Diagnosis (VDD_UVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Under Voltage Shut Down (VDD_UVSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREG Under Voltage Diagnosis (VREG_UVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREG Under Voltage Shut Down (VREG_UVSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOV and VDH Over Voltage Shut Down (IOV_OVSD, VDH_OVSD) . . . . . . . . . . . . . . . . . . . . . . . . Dead Time and Shoot Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCDL Pin Open Detection (SCDL_open) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Current Shut Down (OCSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passive Gxx Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 19 19 19 19 20 21 21 24 24 24 24 24 25 25 25 26 26 26 26 27 27 27 27 27 29
Data Sheet
Rev. 1.0, 2008-12-04
TLE7184F
Table of Contents 10 11 12 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
3
Rev. 1.0, 2008-12-04
System IC for B6 motor drives
TLE7184F
1
Features * * * * * * * * * * * * * * * * * *
Overview
Drives 6 N-Channel Power MOSFETs Integrated 5V Vreg-Controller to power C Integrated switch for VDH voltage Separate control input for each MOSFET Adjustable dead time Shoot through protection Analog adjustable Short Circuit Protection levels Low quiescent current mode 1 bit diagnosis ERR Over Temperature shut down and analog temperature output Over Temperature pre-warning Under Voltage shut down Adjustable Over Voltage shut down Current sense OpAmp Over current shut down based on Current sense OpAmp, fixed shut down level 0 ...94% at 25 kHz Duty cycle of phase voltage Green Product (RoHS compliant) AEC Qualified
PG-VQFN-48
Description The TLE7184F is a system IC for Brushless Motor Control. It incorporates a voltage supply for a C, a bridge driver for a B6 configuration, an application typical PWM interface and some other smaller features. Target is to reduce the number of discrete components in typical BLDC automotive applications and give enough flexibility for custom specific adaptations. It works with 3-phase motors and brush DC motors. Its exposed pad package allows the usage even at high ambient temperatures.
Type TLE7184F Data Sheet
Package PG-VQFN-48 4
Marking TLE7184F Rev. 1.0, 2008-12-04
TLE7184F
Block Diagram
2
Block Diagram
VDD VS GND ___ ____ INH INHD VREG VDHS
5V voltage regulator
switch VREG
VDH
BH1 Floating HS driver Short circuit detection GH1 SH1 IOV ____ ERR ____ RGS SCDL TEMP IFuC IFMA Diagnostic logic Under voltage Over voltage Overtemperature Short circuit Reset Over current
Floating LS driver Short circuit detection
GL1
Interface
L E V E L S H I F T E R
BH2 Floating HS driver Short circuit detection GH2 SH2
DT IL1 ___ IH1 IL2 ___ IH2 IL3 ___ IH3
Floating LS driver Short circuit detection
GL2
Input control Shoot through protection dead time
BH3 Floating HS driver Short circuit detection GH3 SH3
Floating LS driver Short circuit detection AGND
GL3 SL
ISP ISN
OCTH
GND
ISO
Figure 1
Block Diagram
Data Sheet
5
Rev. 1.0, 2008-12-04
TLE7184F
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment TLE7184F
____ RGS GND
____ ERR TEMP
GND VDD
N.C N.C
IOV N.C
GND VDH
36 ___ IH1 37
35
34
33
32
31
30
29
28
27
26
25 24 BH1
IL1 ___ IH2
38
23
GH1
39
22
SH1
IL2 ___ IH3
40
21
GL1
41
20
BH2
IL3
42
TLE 7184 F
19
GH2
AGND
43
Topview
18
SH2
ISN
44
17
GL2
ISP
45
16
BH3
ISO ____ INHD
46
15
GH3
47
14
SH3
IFuC
48
13
GL3
1 GND
2
3 IFMA
4
5 VS
6
7 VREG
8
9 SCDL
10
11 DT
12
___ INH
VDHS
NC
NC
SL
GND
Figure 2
Pin Configuration
Data Sheet
6
Rev. 1.0, 2008-12-04
TLE7184F
Pin Configuration
3.2
Pin 5 7 31 2 47 4 33 36 38 37 40 39 42 41 11 9 28 34 25 24 23 22 21 20 19 18 17 16 15 14 13 10 44 45 46 43 3 48
Pin Definitions and Functions
Symbol VS VREG VDD INH INHD VDHS TEMP RGS IL1 IH1 IL2 IH2 IL3 IH3 DT SCDL IOV ERR VDH BH1 GH1 SH1 GL1 BH2 GH2 SH2 GL2 BH3 GH3 SH3 GL3 SL ISN ISP ISO AGND IFMA IFuC Function Supply Pin Output of supply for driver output stages - connect to capacitor Output of 5V supply for C - connect to capacitor Input pin wake up the complete system IC Digital output 5V for INH state (high when INH is high) Switched output of VDH voltage; switch open in sleep mode Output pin for analog temperature signal Reset and Go-to-Sleep input pin for reset of error registers, set HIGH to avoid to goto-sleep Input for low side switch 1 (active high) Input for high side switch 1 (active low) Input for low side switch 2 (active high) Input for high side switch 2 (active low) Input for low side switch 3(active high) Input for high side switch 3(active low) Input pin for adjustable dead time function, connect to GND via resistor Analog input pin for adjustable Short Circuit Detection function, connect to voltage divider Input pin for Over Voltage detection. Open drain error output Voltage input common drain high side for short circuit detection Pin for + terminal of the bootstrap capacitor of phase 1 Output pin for gate of high side MOSFET 1 Pin for source connection of high side MOSFET 1 Output pin for gate of low side MOSFET 1 Pin for + terminal of the bootstrap capacitor of phase 2 Output pin for gate of high side MOSFET 2 Pin for source connection of high side MOSFET 2 Output pin for gate of low side MOSFET 2 Pin for + terminal of the bootstrap capacitor of phase 3 Output pin for gate of high side MOSFET 3 Pin for source connection of high side MOSFET 3 Output pin for gate of low side MOSFET 3 Pin for common source connection of low side MOSFETs Input for OpAmp - terminal Input for OpAmp + terminal Output of OpAmp Analog GND for Opamp and analog temperature output Interface to master ECU (used for wake up) Interface to C 7 Rev. 1.0, 2008-12-04
Data Sheet
TLE7184F
Pin Configuration Pin 1 12 26 32 35 6 8 27 29 30 Symbol GND GND GND GND GND NC NC NC NC NC Function Ground pin Ground pin Ground pin Ground pin Ground pin connect to GND connect to GND connect to GND connect to GND connect to GND
Exposed pad to be connected to GND
Data Sheet
8
Rev. 1.0, 2008-12-04
TLE7184F
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 Voltage range at VS, IFMA, INH, IOV Voltage range at IFMA, INH Voltage range at VS Voltage range at VS Voltage range at VREG output Voltage range at VDH, VDHS Voltage range at VDH Parameter Symbol Limit Values Min. Max. 45 45 45 45 15 55 55 V V V V V V V - With RVDH >=10; 60s, 5x; Tj<=150C - - Unit Conditions
VVS1 VIFMA VVS2 VVS3 VVREG VVDHx VVDH1
-0.3 -6.0 -3.0 -3.0 -0.3 -0.3 -3.0
R >= 10k RVS >= 4.7;
60s, 5x;
RVS >= 2.0;;
200ms, 5x;
4.1.8
Voltage range at IHx, ILx, RGS, ERR, IFuC, TEMP, DT, VDD, ISO, INHD, SCDL, Voltage range at ISP, ISN Voltage range at BHx Voltage range at GHx Voltage range at GHx Voltage range at SHx Voltage range at SHx Voltage range at GLx Voltage range at GLx Voltage range at SL Voltage range at SL Voltage difference Gxx-Sxx Voltage difference BHx-SHx Minimum bootstrap capacitor CBS Junction temperature Storage temperature Case temperature
2)
VDP
-0.3
6
V
4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16 4.1.17 4.1.18 4.1.19 4.1.20 4.1.21 4.1.22 4.1.23 4.1.24
VOPI VBH VGH VGHP VSH VSHP VGL VGLP VSL VSLP VGS VBS CBS Tj Tstg TCase
-5.0 -0.3 -0.3 -7.0 -2.0 -7.0 -0.3 -7.0 -0.3 -7.0 -0.3 -0.3 330 -40 -55 -
5.0 55 55 55 45 45 18 18 5.0 5.0 15 15 - 150 150 145
V V V V V V V V V V V V nF C C C
- - -
tP < 1s; f=50kHz
-
tP < 1s; f=50kHz
-
tP < 0.5s; f=50kHz
-
tP < 0.5s; f=50kHz
- - - - - -
Temperatures
Data Sheet
9
Rev. 1.0, 2008-12-04
TLE7184F
General Product Characteristics Absolute Maximum Ratings (cont'd)1)
Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Min. ESD Susceptibility 4.1.25 4.1.26 ESD Resistivity3) CDM Max. +2 500 kV V - - Unit Conditions
VESD VCDM
-2 -
1) Not subject to production test, specified by design. 2) Calculation based on Tjmax, RthJC and the assumption of 1W power dissipation 3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
4.2
Pos. 4.2.1 4.2.2
Functional Range
Parameter Supply voltage at VS Quiescent current (IVS + IVDH + IIFMA) Supply current at VS (device enabled) Symbol Min. Limit Values Max. 45 50 V A below 7V reduced functionality1) 2) 6.0 - Unit Conditions
VVS IQ
VS<16V; sleep mode VVS=VVDH=VIFMA Vs=8...18V;
no load3); fPWM=25kHz;
4.2.3
IVS(0)
-
19
mA
4.2.4 4.2.5 4.2.6
Duty cycle HS Duty cycle LS Junction temperature
DHS DLS TJ
0 0 -40
94 100 150
% % C
fPWM=25kHz;
continuous operation -
1) MOS driver output deactivated and ERROR pin set to low if VREG is lower UVVR 2) MOS driver output stage will operate at Vs=6.7V with 5mA load current at VREG 3) no load at VDD, ERR, ISO, IFC, VDHS, GXX, TEMP, DT
The limitations in the PWM frequency are given by thermal constraints and limitations in the duty cycle (charging time of bootstrap capacitor). All maximum ratings have to be considered All basic functions will work between TJ=150C and Over Temperature shut down. In this temperature range, the parameters might leave the specified range. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
10
Rev. 1.0, 2008-12-04
TLE7184F
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.3.1 4.3.2 Parameter Junction to Case
1) 1)
Symbol Min.
Limit Values Typ. - 29 Max. 5 - - -
Unit K/W K/W
Conditions -
2)
Junction to Ambient
RthJC RthJA
1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.4
Table 1
Default State of Inputs
Default State of Inputs State Low High Low Low High High Low max. dead time Remark Low side MOSFETs off High side MOSFETs off Errors is reset and system IC goes to sleep no wake up by INH Error is set; all MOSFETs switched off no wake up by IFMA no Over Voltage detection by IOV max. dead time
Characteristic Default state of ILx (if ILx left open -pull down) Default state of IHx (if IHx left open - pull up) Default state of RGS (if RGS left open - pull down) Default state of INH (if INH left open - pull down) Default state of SCDL (if SCDL left open - pull up) Default state of IFMA (if IFMA left open - pull up)1) Default state of IOV (if IOV left open - pull down) Default state of DT (if DT left open)
1) external capacitance < 25pF
Data Sheet
11
Rev. 1.0, 2008-12-04
TLE7184F
MOSFET Driver
5
5.1
MOSFET Driver
Inputs and Dead Time
There are 6 independent control inputs to control the 6 MOSFETs individually. However, the control inputs for the Highs Side MOSFETs IHx are inverted. Hence, the control inputs for High Side IHx and Low Side MOSFETs ILx of the same half bridge can be tight together to control one half bridge by one control signal. To avoid shoot through currents within the half bridges, a dead time is provided by the TLE7184F. For more details about the dead time please see Chapter 9.2.10
5.2
Output Stages
The 3 low side and 3 high side powerful push-pull output stages of the TLE7184F are all floating blocks. All 6 output stages have the same output power and thanks to the used bootstrap principle they can be switched all up to high frequencies. Each output stage has its own short circuit detection block. For more details about short circuit detection see Chapter 9.2.11.1)
VS
___ INH
VREG
VDH
Voltage regulator
BHx
____ ERR ____ RGS
Error logic Reset Power On Reset
VREG
+ -
GHx
VSCP
VDH
blanking
SCD SCD
Level shifter
SHx
Floating HS driver 3x
SCD lock / unlock
VREG
___ IH1 IL1 ___ IH2 IL2 ___ IH3 IL3 DT
short circuit filter Input Logic Shoot Through Protection Dead Time
ON / OFF
Short Circuit Detection Level +
ON / OFF
VSCP Level shifter Floating LS driver 3x
GLx
SL
GND
SCDL
Figure 3
Block Diagram of Driver Stages including Short Circuit Detection
1) The high side outputs are not designed to be used for low side MOSFETs; the low side outputs are not designed to be used for high side MOSFETs
Data Sheet
12
Rev. 1.0, 2008-12-04
TLE7184F
MOSFET Driver
5.3
Bootstrap Principle
The TLE7184F provides a bootstrap based supply for its high side output stages. The benefit of this principle is a fast switching of the high side switches - supporting active freewheeling in high side. The bootstrap capacitors are charged by switching on the external low side MOSFETs connecting the bootstrap capacitor to GND. Under this condition the bootstrap capacitor will be charged from the VREG capacitor. If the low side MOSFET is switched off and the high side MOSFET is switched on, the bootstrap capacitor will float together with the SHx voltage to the supply voltage of the bridge. Under this condition the supply current of the high side output stage will discharge the bootstrap capacitor. This current is specified. The size of the capacitor together with this current will determine how long the high side MOSFET can be kept on without recharging the bootstrap capacitor. When all external MOSFETs are switched off, the SHx voltage can be undefined. Under this condition, the bootstrap capacitors can be discharged, dependent on the SHx voltage.
5.4
Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 33 V, Tj = -40 C to +150 C all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Inputs 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 Parameter Symbol Min. Limit Values Typ. - - - - - - - 11 Max. 1.6 - - 66.5 490 13.5 9 14 V V mV k k V - - - - - Iload=20mA Iload=20mA 13,5V Unit Conditions
VI_LL High level input voltage of ILx; IHx VI_HL Input hysteresis of IHx; ILx1) dVI IHx pull-up resistors to VDD RIH RIL ILx pull-down resistors to GND
Low level input voltage of ILx; IHx Output source resistance Output sink resistance High level output voltage Gxx vs. Sxx
- 2.8 100 33.5 210 2 2 -
MOSFET driver output
RSou RSink VGxx1
5.4.9
High level output voltage GHx vs. SHx1)
VGxx2
6
-
-
V
<=VVS<=45V2), VIOV<=VOVIOV, VVDH<=VOVVDH Iload=37,5mA VVs=8V, Cload=20nF,
dc=94%; fPWM=20kHz
5.4.10
High level output voltage GHx vs. SHx1)3)
VGxx3
6 +Vdiode
-
-
V
VVs=8V, Cload=20nF,
dc=94%; fPWM=20kHz; passive freewheeling
Data Sheet
13
Rev. 1.0, 2008-12-04
TLE7184F
MOSFET Driver Electrical Characteristics MOSFET Drivers
VS = 7.0 to 33 V, Tj = -40 C to +150 C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) Pos. 5.4.11 Parameter High level output voltage GLx vs. GND Symbol Min. Limit Values Typ. - Max. - V 6.7 Unit Conditions
VGxx4
VVS=8V, Cload=20nF,
dc=94%; fPWM=20kHz;
5.4.12 5.4.13
Rise time Fall time
trise tfall VGUV
- -
200 200
- -
ns ns
CLoad=11nF; RLoad=1 VVS=7V
20-80% sleep mode or VS_UVLO1) 4)
5.4.14 5.4.15 5.4.16 5.4.17 5.4.18 5.4.19 5.4.20
High level output voltage (in passive clamping) Pull-down resistor at BHx to GND
- - - - 15 48 -
- - - - 35 80 -
1.2 80 30 150 60 112 2
V k k A A k mA
RBHUV Pull-down resistor at VREG to GND RVRUV Bias current into BHx IBH
Current between BHx and SHx
VBHx-VSHx=5...13V;
no switching
Resistor between SHx and GND Bias current out of SL
IBSH RSHGN ISL
VBHx-VSHx=5...13V
0V<=VSH<=VS+1 V; no switching; VCBS>5V
5.4.21 5.4.22 5.4.23 5.4.24 5.4.25
Input propagation time (low on) Input propagation time (low off) Input propagation time (high on) Input propagation time (high off) Absolute input propagation time difference between above propagation times VREG output voltage VREG over current limitation Voltage drop between Vs and VREG
tP(ILN) tP(ILF) tP(IHN) tP(IHF) tP(diff)
0 0 0 0 -
- - - - -
200 200 200 200 100
ns ns ns ns ns
C=11nF; RLoad=1
VREG 5.4.26 5.4.27 5.4.28
VVREG IVREGOCL VVsVREG
11 100 -
12.5 - -
14 500 0.5
V mA V
VVS >= 13,5V; Iload=37,5mA
no activation of error; VVREG>VVRSD
VVS>= 7V; Iload=37,5mA;
Ron operation
1) Not subject to production test; specified by design 2) Values above 33V not subjected to production test; specified by design 3) Vdiode is the bulk diode of the external low side MOSFET 4) see Chapter 9.2.15
Data Sheet
14
Rev. 1.0, 2008-12-04
TLE7184F
Shunt Signal Conditioning
6
Shunt Signal Conditioning
The TLE7184F incorporates a fast and precise operational amplifier for conditioning and amplification of the current sense shunt signal. The gain of the OpAmp is adjustable by external resistors within a range higher than 5. The usage of higher gains in the application might be limited by required settling time and band width. It is recommended to apply a small offset to the OpAmp, to avoid operation in the lower rail at low currents. The output of the OpAmp ISO is not short-circuit proof. In addition to the integrated operational amplifier, the TLE7184F incorporates a comparator to detect over current situations. The output voltage VISO is compared to a reference voltage VOCTH close to the upper rail of the 5V OpAmp supply (VDD). If VISO reaches this level an error is set.
V DD VDD
ISP ISN
Rfb2 RS1 Rshunt RS2 external + Rfb3
ASIC internal
ISO
+ ERR V OCTH
Rfb1
Figure 4
Shunt Signal Conditioning Block Diagram and Over Current Limitation
Over current shut down see Chapter 9.2.13.
6.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 6.0 to 33 V, Tj = -40 C to +150 C, gain = 5 to 75, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)1) Parameter Series resistors Feedback resistor Limited by the output voltage dynamic range Resistor ratio (gain ratio) Steady state differential input voltage range across VIN Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) Pos. 6.1.1 6.1.2 Symbol Min. Limit Values Typ. 500 7500 Max. 1000 - - - 100 2000 Unit Conditions
RS Rfb
6.1.3 6.1.4 6.1.5 6.1.6 6.1.7
Rfb/RS VIN(ss)
5 -400 -800 -800 -
- - - - -
- 400 800 2000 +/-2
- mV mV mV mV
- - - -
Input differential voltage (ISP - ISN) VIDR
VLL
Input offset voltage of the I-DC link VIO OpAmp, including temperature drift
RS=500; VCM=0V; VISO=1.65V;
Data Sheet
15
Rev. 1.0, 2008-12-04
TLE7184F
Shunt Signal Conditioning Electrical Characteristics - Current sense signal conditioning (cont'd)
VS = 6.0 to 33 V, Tj = -40 C to +150 C, gain = 5 to 75, all voltages with respect to ground, positive current flowing
into pin (unless otherwise specified)1) Parameter Input bias current (ISN,ISP to GND) High level output voltage of ISO Low level output voltage of ISO Output short circuit current Differential input resistance
2) 2)
Pos. 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14
Symbol Min.
Limit Values Typ. - - - - - - 100 Max. - -300
Unit A V V mA k pF dB
Conditions
IIB VOH VOL ISC RI CCM CMRR
VCM=0V; VISO=open IOH=-3mA IOH=3mA
- - 10kHz -
VVDD0.2 -0.1 5 100 - 80
VVDD
0.2 - - 10 -
Common mode input capacitance Common mode rejection ratio at DC CMRR = 20*Log((Vout_diff/Vin_diff) * (Vin_CM/Vout_CM))
6.1.15
Common mode suppression3) with CMS CMS = 20*Log(Vout_CM/Vin_CM) Freq =100kHz Freq = 1MHz Freq = 10MHz Slew rate Large signal open loop voltage gain (DC) Unity gain bandwidth Phase margin Gain margin 2) Bandwidth
2)
- 62 43 33 - 80 10 - - 1.6 10 100 20 50 12 -
-
dB
VIN=360mV*
sin(2**freq*t); Rs=500; Rfb=7500
6.1.16 6.1.17 6.1.18 6.1.19 6.1.20 6.1.21
dV/dt AOL GBW FM AM BWG
- - - - - -
V/s dB MHz dB MHz
Gain>= 5;
RL=1.0k; CL=500pF
-
RL=1k; CL=100pF
Gain>= 5; RL=1k; CL=100pF
RL=1k; CL=100pF
Gain=15; RL=1k; CL=500pF; Rs=500
6.1.22
Output settle time to 98% Rfb/RS=15 Rfb/RS=75
tset1
- - 1 4.6 1.8 8
s
RL=1k; CL=500pF;
0.31) A minimum capacitance of 100pF is needed at the output of the OpAmp (parasitic or real capacitor) 2) Not subject to production test; specified by design 3) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in external resistors.
Data Sheet
16
Rev. 1.0, 2008-12-04
TLE7184F
5 V Low Drop Voltage Regulator
7
5 V Low Drop Voltage Regulator
The TLE7184F incorporates a 5V LDO for C supply. The voltage regulator is protected against Over Temperature by the central temperature sensor (see Chapter 9.2.1 and Chapter 9.2.2). It has an integrated current limitation and Under Voltage detection. Parameters for Under Voltage detection see Chapter 9.2.5.
VDD
VS 5V LDO temperature sensor
Error logic and wake up
Figure 5
Block diagram of 5V LDO
7.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 6.0 to 45 V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Parameter Output voltage Output voltage LDO over current limitation Load regulation Power supply ripple rejection2) Symbol Min. Limit Values Typ. - - - 50 - Max. 5.25 5.20 270 100 - V V mA mV dB 4.85 4.90 130 - 50 Unit Conditions
VDD1 VDD2 IOCL DVDD PSRR
Iload<=70mA; Cload= 1...22uF1) 5mA <=Iload<=25mA; Cload= 1...22uF1)
no activation of error
load step 0...20mA; CVDD=1uF
100Hz sine wave; 0.5Vpp VVS>=7V 100Hz sine wave; 0.5Vpp 6V<=VVS<7V
7.1.6
Power supply ripple rejection2)
PSRR
-
31
-
dB
1) ceramic C with 100nF with ESR<0.1 in parallel 2) Not subject to production test; specified by design
Data Sheet
17
Rev. 1.0, 2008-12-04
TLE7184F
5 V Low Drop Voltage Regulator
5,150
5,100
U_VDD [V]
5,050
25C -40C +150C
5,000
4,950 0,000
0,010
0,020
0,030
0,040
0,050
0,060
0,070
0,080
I_VDD [A]
Figure 6
Typ. VDD output voltage vs. load current
5,07 5,065 5,06 5,055
U_VDD [V]
5,05 5,045 5,04 5,035 5,03 0 5 10 15 20 25 30 35 40 45 50
25C
U_VS [V]
Figure 7
Typ. VDD output voltage vs. load current
Data Sheet
18
Rev. 1.0, 2008-12-04
TLE7184F
Interface, VDH Switch and INH Digital Output
8
8.1
Interface, VDH Switch and INH Digital Output
PWM Interface (IFMA)
The TLE7184F has an integrated interface supporting the typical PWM interface between a remote master ECU and the C. The link to the external master ECU is a single wire communication based on the battery voltage and running typ. with about 10 to 400 Hz. The information is encoded in the duty cycle of the signal. This communication line requires a signal conditioning to connect to the on board C. The integrated circuit supports the incoming data path. The outgoing data path is formed by external components
uC
VDD
TLE 7184 F
interface
ECU
Wake up
IFuC
Interface_uC
KL 30 Pull up IFMA T3 10k T2
T1 control
T1 GND GND
VCC
Figure 8
Structure PWM Interface
The integrated circuitry is described in Figure 8. The main task of this interface is level shifting and protection of the C. The IFuC signal is following the IFMA signal, passing the duty cycle information from IFMA to the IFuC. The C port is used as input and is listening to the IFuC signal. The voltage at IFMA is monitored. If IFMA is low the IFuC open drain output is switched on - forcing the IFuC signal to low. If IFMA is high, the IFuC open drain output is deactivated and the IFuC signal is pulled to high by the internal pullup resistor. The IFMA input is used as well for wake-up. See Chapter 9.1
8.2
VDHS Switch
The System IC has an integrated switch connecting the VDH pin to the VDHS pin. This allows to place an external voltage divider for VDH voltage monitoring at the VDHS pin and to disconnect this voltage divider from VDH during sleep mode to assure low current consumption. The VDHS switch is only deactivated when the VDD regulator is switched off.
8.3
Digital Output INHD
The System IC provides a digital output INHD showing the logic state of INH (e.g. KL15) after complete wake-up of the driver (approx. 1ms). The input levels of INH for the INHD output are defined separately from the levels for wake up. Voltage levels for INH wake up function please see Chapter 9.4 section Wake-up and go-to-sleep. The output stage consists of an integrated low side switch with a pull-up resistor to VDD. Data Sheet 19 Rev. 1.0, 2008-12-04
TLE7184F
Interface, VDH Switch and INH Digital Output
8.4
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 6.0 to 20V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Min. Interface - static parameters 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 IFMA input voltage high level (for IFC high) IFMA input voltage low level (for IFC low) IFMA input hysteresis (for IFC) IFMA wake up voltage high level = VS-VIFMA Limit Values Typ. - - - - 340 700 - - - - - Max. - 46 9 4 495 980 +5 0.5 20 100 6 % % % V k k % V k % s of VVS; IC not in Sleep Mode of VVS; IC not in Sleep Mode; of VVS; IC not in Sleep Mode valid in Sleep Mode - not active in Sleep Mode - no external load - - Including rising time to 80% of VVDD; Cload=100pF Including falling time to 20% of VVDD; Cload=100pF Unit Conditions
VIMHL VIMLL VIMhy VIMWH
59 - 0.5 2 210 420
IFMA internal pull-up resistor to VS RIMu IFMA internal pull-down resistor to RIMd GND Matching of internal pull-up / pulldown resistor1) IFC output low voltage IFC internal pull-up resistor to VDD IFC duty cycle
RIMu/RIMd -5 VIuLL RIu
- 10 0 -
Interface - dynamic parameters
dIu Propagation time rising edge IFC tPRE
8.4.12
Propagation time falling edge IFC tPFE
-
-
5
s
8.4.13
Deviation between rising and falling tPD IFC Ron VDH switch Low level input voltage INH (for INHD=low) High level input voltage INH (for INHD=high) Input hysteresis of INH for INHD1) INHD low level output voltage INHD Internal pull-up resistor to
-
-
4
s
Cload=100pF
VDH switch 8.4.14 8.4.15 8.4.16 8.4.17 8.4.18 8.4.19
RVDH VINHDL VINHDH dVINHD VINHD RINHD
- - 2.1 100 - 50
- - - - - -
150 1.5 - - 0.5 100
V V mV V k
Load current = 1mA - - - no external load -
INHD digital output
VDD
1) Not subject to production test; specified by design
Data Sheet
20
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions
9
9.1
Description of Modes, Protection and Diagnostic Functions
Description of modes
The operation of TLE7184F can be described by different operation modes
Error conditions TLE7184F and used abbreviations: VREG Under Voltage Diagnosis ( VREG_UVD) VDD Under Voltage Diagnosis (VDD_UVD) Over Current Shut Down ( OCSD) VDH Over Voltage Shut Down ( VDH_OVSD) IOV Over Voltage Shut Down ( IOV_OVSD)) Short Circuit Detection ( SCD) SCDL Pin Open Detection ( SCDLPOD) Over Temperature Pre-Warning (OTPW) Over Temperature Shut Down OTSD) ( VDD Under Voltage Shut Down ( VDD_UVSD) VREG Under Voltage Shut Down VREG_UVSD) ( VS Under Voltage Lockout ( VS_UVLO)
Sleep Mode
- low quiescent current - all supplies switched off /INH = High "OR" IFMA= Low
VS Under Voltage Lockout (VS_UVLO) leads from every mode into the Sleep Mode Over Temperature Shut Down ( OTSD) leads from every mode except Dead Lock Mode into the Sleep Mode
Wake-up Mode
- ramp-up of int5V, VREG and VDD
VREG_UVSD (no OTPW) Wake-up time expired
VDD_UVSD "OR" (VREG_UVSD "AND" OTPW) Reset by /RGS "AND" OTPW OTPW "OR" VDD_UVSD
Error Mode
- latched error is reported - MOSFets switched-off - VREG and VDD on
Normal Mode with OT-Prewarning
- latched error is reported - driver stages are active -
Deadlock Mode
*2) VREG and VDD off latched error is reported MOSFets switched-off only 5Vint supply is on
VREG Shut-down
Mode
- latched error is reported - MOSFets switched-off - VREG off
Error condition occures*1)
Error condition occures*1) Reset of error Reset of OTPW error
Normal Mode without Error Conditions
- no error is reported - driver stages are active OTPW
VDD_UVSD "OR" VREG_UVSD
VDD_UVSD "OR" (VREG_UVSD "AND" OTPW) /RGS = Low for t > tsleep VREG_UVSD (no OTPW)
/RGS = Low for t > sleep t
Go-to-Sleep Mode
- VDD andVREG are switched off - latched error is reported *1) Error conditions: VREG_UVD, VDD_UVD, OCSD, VDH_OVSD, IOV_OVSD, SCD, SCDLPOD *2) only way to leave this mode is VS_UVLO VDD <= V DDsleep
Figure 9 Data Sheet
State diagram TLE7184F 21 Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions Sleep Mode: The sleep mode is entered if the device is in the Go-to-sleep Mode and the VDD voltage is lower than VDDsleep. The complete chip is deactivated beside the wake-up function (see Wake-up Mode). This mode is designed for lowest current consumption from the power net of the car. The passive clamping is active. For details see the description of passive clamping, see Chapter 9.2.15. The only way to leave the Sleep Mode is to go to the Wake-up Mode. Wake-up Mode: The TLE7184F wakes up if INH (=KL15) is high or if IFMA is low and VVS is higher than VVSLO. In this mode all supplies are ramping up. As soon as the internal 5V is available, a so called wake-up timer starts to run. If the IC reaches this state, the wake up will continue even if the wake up signals at INH or IFMA disappear. The PWM interface (IFMA) is active as soon as the VDD voltage is sufficient high. During this time it is expected that the supplies are powered up and the C sets the RGS to high. All external MOSFETs are switched off actively or passively. When the wake up timer is expired the IC goes into the Error mode. In this mode all errors will be ignored beside Over Temperature Shut Down or VS Under Voltage Lockout. Error Mode The Error Mode can be reached in 3 different ways: 1. The device is in Wake-up Mode and the wake up timer expires 2. The device is in Normal Mode and one or more of the following errors occur: VREG Under Voltage Shut Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage Shut Down, Short Circuit Detection or SCDL Open Detection. 3. The device is in Normal Mode with OT-Prewarning and one or more of the following errors occur: VREG Under Voltage Shut Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage Shut Down, Short Circuit Detection or SCDL Open Detection. In this mode an Error is set at the ERROR Pin and all external MOSFETs are actively switched off as long as the bootstrap voltages allows it. The interface is active. VDHS switch is on and the current sense functions are working. VDD and VREG are active. Passive clamping is not active. The Error mode can be left in the following ways: 1. If no error is present, the IC can be sent to Normal Mode by a reset with the RGS pin. 2. If a VREG Under Voltage Shut Down occurs and no Over Temperature Prewarning is present, the device will go to VREG Shut-down Mode. 3. If VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over Temperature Prewarning occurs, the device will go into Deadlock Mode. 4. If Over Temperature Prewarning is present, the IC can be sent to Normal Mode with OT-Prewarning by a reset with the RGS pin. Normal Mode The Normal Mode can be reached in two different ways: 1. The device is in Error Mode, no error is present and a reset is performed by the RGS pin. 2. The device is in Normal Mode with OT-Prewarning, the chip temperature is below the OT-Prewarning level and a reset is performed by the RGS pin. In the Normal Mode all functions are active and available with the regular limitations of the bootstrap principle. The gate drive output stages can be controlled with the input pins. The Normal Mode can be left in 5 ways: 1. The devices goes to the Go-To-Sleep Mode by setting RGS to low for a time longer than tsleep. 2. If a Over Temperature Prewarning occurs the device goes into the Normal Mode with OT-Prewarning.
Data Sheet
22
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions 3. If a VREG Under Voltage Shut Down occurs and no Over Temperature Prewarning is present, the device will go to VREG Shut-down Mode. 4. If VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over Temperature Prewarning occurs, the device will go into Deadlock Mode. 5. If one or more of the following errors occur, the device goes to the Error Mode: VREG Under Voltage Shut Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage Shut Down, Short Circuit Detection or SCDL Open Detection. Go-To-Sleep Mode The Go-To-Sleep Mode can be reached in 2 different ways: 1. The device is in Normal Mode and RGS is set to low for a time longer than tsleep. 2. The device is in VREG Shut-down Mode and RGS is set to low for a time longer than tsleep. In this mode all external MOSFETs are actively or passively switched off. An Error is set and is shown as long as VDD is sufficient high. In this mode VDD and VREG is switched off. As soon as VDD voltage reaches the VVDDsleep level the IC goes into the Sleep Mode. Normal Mode with Over Temperature Prewarning This mode can be reached in 2 different ways: 1. The device is in Error Mode, the chip temperature is above the prewarning level while a reset is performed by the RGS pin. 2. The device is in Normal Mode and the chip temperature increases above the prewarning level. In this mode all functions are active and available. The gate drive output stages can be controlled with the input pins with the regular limitations of the bootstrap principle. The ERR pin is set to low and is latched. There are 3 possibilities to leave this mode: 1. This mode can be left into the Normal Mode by applying a reset at RGS if the temperature has dropped below the Over Temperature pre-warning level. 2. The device goes into Error Mode if one of the following errors occurs: VREG Under Voltage Shut Down, VDD Under Voltage Shut Down, Over Current Shut Down, VDH Over Voltage Shut Down, IOV Over Voltage Shut Down, Short Circuit Detection or SCDL Open Detection. 3. The device goes into Deadlock Mode if either a VREG Under Voltage Shut Down or a VDD Under Voltage Shut Down occurs. If the temperature is still in the pre-warning range and RGS is low, the ERR pin gets high only during the time were RGS is low and the IC stays in the "Normal Mode with Over Temperature Prewarning". Deadlock Mode This mode is intended to prevent the IC for long time toggling in Over Temperature if a short is present at the VDD pin. There are 4 ways to enter this mode: 1. The IC is in Error Mode and a VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over Temperature Prewarning occurs 2. The IC is in Normal Mode with Over Temperature Prewarning and a VDD Under Voltage Shut Down or a VREG Under Voltage Shut Down occurs. 3. The IC is in Normal Mode and a VDD Under Voltage Shut Down occurs or a VREG Under Voltage Shut Down together with a Over Temperature Prewarning occurs. 4. The IC is in VREG Shut Down Mode and a VDD Under Voltage Shut Down or a Over Temperature Prewarning occurs. In this mode VDD and VREG are switched off. The gates of the external MOSFETs are passively clamped. Data Sheet 23 Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions The VDHS switch is deactivated. The IC will not react to IFMA or INH signals. Even a Over Temperature Shut Down detection will have no influence. The internal logic is supplied and prevents the IC from going into "Go to sleep mode". The only way to leave this state is that VS is lower than VVSLO., means a VS Under Voltage Lockout occurs. In this case the IC goes to Sleep Mode. VREG Shut Down Mode This mode is intended to prevent the IC for long time toggling in Over Temperature if a short is present at the VREG pin. There are 2 ways to enter this mode: 1. The IC is in the Error Mode and a VREG Under Voltage Shut-down occurs without a Over Temperature Prewarning. 2. The IC is in the Normal Mode and a VREG Under Voltage Shut-down occurs without a Over Temperature Prewarning. In this mode VREG is switched off, but VDD is still present. VDHS switch is still active. The PWM interface (IFMA) is working. The IC will not react to IFMA or INH signals. In this situation the C is still able to provide diagnostic information by the interface. It can prevent the IC from Goto-Sleep Mode and to avoid unintended toggling as long there is no Over Temperature Shut Down. This state can be left by 2 ways: 1. The C has to set RGS to low for a time longer than tsleep. In this case the IC goes to Sleep Mode. 2. If a VDD Under Voltage Shut Down or a Over Temperature Prewarning occurs the IC will go into the Deadlock Mode.
9.2 9.2.1
Protection and Diagnosis Functions Over Temperature Shut Down (OTSD)
If the junction temperature is exceeding the Over Temperature shut down level an error signal is set. The driver IC will pull- down the gate-source voltage of all external MOSFETs, deactivate the VDD and VREG supply and go directly into the Sleep Mode. In the Sleep Mode the regular wake-up conditions will be used. Over Temperature cycling is possible and will lead to accelerated aging of the IC. In Deadlock Mode an Over Temperature Shut Down is ignored.
9.2.2
Over Temperature Prewarning (OTPW)
The IC provides a digital Over Temperature Pre-Warning. If no other errors are present, the IC goes into "Normal Mode with Over Temperature Prewarning". This function is not available in Deadlock Mode.
9.2.3
Analog Temperature Monitoring
The TEMP output of the TLE7184F provides an analog voltage signal proportional to the chip temperature. This function is not available in Deadlock Mode.
9.2.4
VS Under Voltage Lockout (VS_UVLO)
The TLE7184F has an integrated VS Under Voltage Lockout, to assure that the behavior of the complete IC is predictable in all supply voltage ranges.
Data Sheet
24
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions If the supply voltage at VS reaches the Under Voltage shut down level VVSLO for a minimum specified filter time the IC goes into Go-to-Sleep Mode and finally into Sleep Mode.
9.2.5
VDD Under Voltage Diagnosis (VDD_UVD)
The TLE7184F has an integrated VDD Under Voltage Diagnosis, to assure that the behavior of the bridge driver output stages is predictable in all supply voltage ranges. If the voltage at VDD reaches the Under Voltage diagnosis level VUVVDD for a minimum specified filter time an error is set the IC goes into Error Mode.
VS
VVDD < TRR VRT
ERR
TRR
____ RGS
Figure 10
Timing of VDD Under Voltage Diagnosis
9.2.6
VDD Under Voltage Shut Down (VDD_UVSD)
The TLE7184F has an integrated VDD Under Voltage Shut Down, to avoid operation with VDD shorted to GND. If the supply voltage at VDD reaches the Under Voltage shut down level VVDDsleep, and the wake-up time is expired, VREG and VDD will be switched off and the IC will go to the Deadlock Mode.
9.2.7
VREG Under Voltage Diagnosis (VREG_UVD)
The TLE7184F has an integrated VREG Under Voltage Diagnosis, to assure that the behavior of the bridge driver output stages is predictable in all supply voltage ranges. If the voltage at VREG reaches the Under Voltage diagnosis level VUVVR for a minimum specified filter time an error is set the IC goes into Error Mode.
Data Sheet
25
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions As long as the VS Under Voltage Lock Out is not reached, the low side MOSFETs will stay actively switched off. The status of the high side MOSFET drivers is dependent on the bootstrap voltage - which depends on the SHx voltage. It is expected that the SHx will be pulled to VDH level by the high side MOSFETs and this will switch off the high side MOSFETs passively. In this situation the short circuit detection of this output stage is deactivated to avoid wrong error reporting.
9.2.8
VREG Under Voltage Shut Down (VREG_UVSD)
The TLE7184F has an integrated VREG Under Voltage Shut Down, to avoid operation with VREG shorted to GND. If the supply voltage at VREG reaches the Under Voltage shut down level VVRSD, "AND" no Over Temperature Prewarning is set "AND" the wake up time is expired, VREG will be switched off and the IC will go to the VREG Shut Down Mode. In this condition the C is still supplied and can communicate via the PWM interface (IFMA), the MOSFETs are switched off and an error is set. The only way to leave this mode is to go to Sleep Mode. If the supply voltage at VREG reaches the Under Voltage shut down level VVRSD, "AND" Over Temperature Prewarning is set and the wake-up time is expired, VREG and VDD will be switched off and the IC will go to the "Dead Lock Mode". The only way to leave this Deadlock Mode is to provoke a VS Under Voltage Shut Down, for example by removing battery voltage.
9.2.9
IOV and VDH Over Voltage Shut Down (IOV_OVSD, VDH_OVSD)
The TLE7184F has an integrated Over Voltage shut down to minimize risk of destruction of the IC at high supply voltages caused by violation of the maximum ratings. The voltage is observed at the Over Voltage input pin IOV and at the VDH pin. If the voltage at the IOV pin or at the VDH exceeds the Over Voltage shut down level for more than the specified filter time the IC goes into Error Mode. The effective Over Voltage level can be adjusted by a voltage divider at IOV connected to VDHS. The Over Voltage level at VDH is fix.
9.2.10
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs are not "on" at the same time, connecting directly the battery voltage to GND. The dead time generated in the TLE7184F is fixed to a minimum value if the DT pin is connected to GND. This function assures a minimum dead time if a common input signal for ILx and IHx is used. The dead time can be increased beyond the internal fixed dead time by connecting the DT pin via a dead time resistor RDT to GND - the larger the dead time resistor the larger the dead time. If an exact dead time of the bridge is needed the use of the C PWM generation unit is recommended. In case of an open DT pin, the dead time is set to the internal maximum value. In addition to this dead time, the TLE7184F provides a locking mechanism, avoiding that both external MOSFETs of one half bridge can be switched on at the same time. This functionality is called shoot through protection. If the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored. The outputs will stay in the situation like before the conflicting input.
9.2.11
Short Circuit Protection (SCP)
The TLE7184F provides a short circuit protection for the external MOSFETs. It is a monitoring of the drain-source voltage of the external MOSFETs. (see Figure 3 ) The drain-source voltage monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding driver output stage is set to "on", the dead time and the blanking time is expired. Data Sheet 26 Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions The blanking time starts when the dead time is expired and assures that the switch on process of the MOSFET is not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time. The short circuit detection level is adjustable in an analogue way by the voltage setting at the SCDL pin. There is a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V as well. The drain-source voltage limit can be chosen between 0.3 ... 2 V. If after the expiration of the blanking time the drain source voltage of the observed MOSFET is still higher then the SCDL level, the SCD filter time tSCP starts to run. A capacitor is charged with a current. If the capacitor voltage reaches a specific level (filter time tSCP), the error signal is set and the IC goes into Error Mode. If the SCD condition is removed before the SC is detected, the capacitor is discharged with the same current. The discharging of the capacitor happens as well when the MOSFET is switched off. It has to be considered that the high side and the low side output of one phase are working with the same capacitor.
9.2.12
SCDL Pin Open Detection (SCDL_open)
For safety reasons an pull-up resistor at the SCDL pin assures that in case of an open pin the SCDL voltage is pulled to high levels. In this case an error is set and the IC goes into Error Mode.
9.2.13
Over Current Shut Down (OCSD)
The TLE7184F is monitoring the output signal of the operational amplifier. If the output signal reaches a specified level close to the upper rail (VDD) for a specified time, the System IC detects over current and sets an error signal. The driver output pulls down the gate-source voltage of all external MOSFETs actively and stays in the Error Mode.
9.2.14
VDD Current Limitation
The TLE7184F has an integrated voltage supply for an external C. The output current of the supply is limited to a specified value. This limitation does not cause any error reporting. If the current is limited for a longer time, the Over Temperature protection will react.
9.2.15
Passive Gxx Clamping
If VS Under Voltage Lock Out is detected or the device is in Sleep Mode, a passive clamping is active as long as the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not switch on the MOSFET actively. The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors. Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx respectively VREG, this assures that the gate of the external MOSFETs are not floating undefined.
9.3
ERR Pin
The TLE7184F has a status pin to provide diagnostic feedback to the C. The logical output of this pin is an open drain output with integrated pull-down resistor to GND (see Figure 11). Reset of error registers and Disable The TLE7184F can be reset by the enable pin RGS. If the RGS pin is pulled to low for a specified minimum time, the error registers are cleared. If the error is still existing when the RGS pin is pulled to low, no reset will be performed and the ERR pin stays low. The only exemption of this behavior is the Over Temperature Prewarning. Even if the junction temperature is exceeding the over temperature prewarning level, the ERR signal goes to high when RGS is pulled low. Figure 12 describes the timing behavior during error reset:
Data Sheet
27
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions For more details see description of Error Mode and Normal Mode with Over Temperature Pre-Warning in Chapter 9.1.
Internal 5V
internal
uC
Error Logic
ERR
Interface_uC
GND
GND
Figure 11
Structure of ERR output
TLE 7184 F releases signal Error occurs
5V
Err reset;
Normal operation
Sleep mode
ERR
0V
No driver reset
undefined
tnres-min
5V ____ RGS 0V
t res-min
Short glitches are ignored
t sleep
Figure 12
Enable / Disable timing
Data Sheet
28
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions
9.4
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 7.0 to 33V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Min. Dead time 9.4.1 Programmable internal dead time Limit Values Typ. 0.14 0.41 1.05 1.85 3.82 - - - - - - - - - - - - 300 - - 0.3 Max. 0.20 0.57 1.45 2.7 5.6 6.4 20 15 14 12 14 12 2 +30 +10 4.3 8 420 2.5 3.4 - s Unit Conditions
tDT
0.08 0.25 0.62 1.0 2.0 2.3 -20 -15 -14 -12 -14 -12
RDT=0 RDT=10 k RDT=47 k RDT=100 k RDT=1000 k
DT pin open -
9.4.2 9.4.3 9.4.4 9.4.5
Max. internal dead time Dead time deviation between channels Dead time deviation between channels LSoff -> HS on Dead time deviation between channels HSoff -> LS on Short circuit protection detection level Short circuit protection detection Accuracy Short circuit protection detection Accuracy Blanking time plus filter time of short circuit detection Internal pull-up resistor SCDL to VDD SCDL open pin detection level Filter time of SCDL open pin SCDL open pin detection level hysteresis Over Voltage shut down at IOV Pull down resistor at IOV to GND Over Voltage shut down at VDH Over Voltage shut down filter time for IOV or VDH Under Voltage diagnosis at VREG
tDT_MAX dtDT dtDTH dtDTL
s % % % % % % V % % s s k V s V
RDT<=47 k
-
RDT<=47 k
-
RDT<=47 k
programmed by SCDL pin 0.3V<= VSCDL<1.2V 1.2V<=
Short circuit protection 9.4.6 9.4.7 9.4.8 9.4.9 9.4.10 9.4.11 9.4.12 9.4.13 9.4.14
VSCPDL ASCP ASCP
0.3 -30 -10 2.3 4 180 2.0 1 -
VSCDL<=2.0V
Ixx static on Ixx switching "off" to "on" - - - -
Filter time of short circuit protection tSCP(off)
tSCPTT RSCDL VSCPOP tSCPOP VSCOPH
Over- and Under Voltage monitoring 9.4.15 9.4.16 9.4.17 9.4.18 9.4.19
VOVIOV RIOV VOVVDH tOV VUVVR
4.15 300 33 13 5.5
- - - - -
4.4 700 37 23 6.5
V k V s V
IOV voltage increasing - VDH increasing - VREG decreasing
Data Sheet
29
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions
Electrical Characteristics - Protection and diagnostic functions (cont'd)
VS = 7.0 to 33V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified) Pos. 9.4.20 9.4.21 9.4.22 9.4.23 Parameter Symbol Min. Under Voltage diagnosis filter time tUVVR for VREG Under Voltage shut down at VREG VVRSD 10 1.5 4.4 1 Limit Values Typ. - - 5.0 - Max. 30 2.3 5.5 3 s V V s - VREG decreasing Unit Conditions
VVSLO Under Voltage lockout filter time for tUVLO
Under Voltage lockout at VS VS
VVS decreasing
-
ERR pin1) 9.4.24 9.4.25 9.4.26 ERR output voltage 5V) Internal pull-down resistor ERR to GND
VERR Rise time ERR (20 - 80% of internal tf(ERR) Rf(ERR)
4.4 - 25
- - -
- 3 52
V s k
No external load
CLOAD=1nF;
-
Reset and Enable 9.4.27 9.4.28 Low time of uC RGS signal without tnres reset Low time of uC RGS pin necessary tres to trigger reset and to clear error registers - 3 - - 0.5 - s s - -
Wake-up and go-to-sleep 9.4.29 9.4.30 9.4.31 9.4.32 9.4.33 9.4.34 9.4.35 9.4.36 9.4.37 9.4.38
VRGSLL High level input voltage of RGS VRGSHL Input hysteresis of RGS2) dRGS RGS pull-down resistors to GND RRGS 3) Low level input voltage of INH for VINHL
Low level input voltage of RGS wake up High level input voltage of INH3) for VINHH wake up INH pull-down resistors to GND Wake up delay time RGS low time for go-to-sleep
- 2.8 100 100 - 2.1 100 9 20 1.5
- - - - - - - - - -
1.6 - - 210 0.75 - 210 17 50 2.3
V V mV k V V k ms s V
- - - - - - -
VDD voltage for changing from Go-to-Sleep Mode to Sleep Mode VDD Under Voltage Shut Down
RINH twake tsleep VDDsleep
-
9.4.39
VUVSDVDD 1.5 - 2.3 V - 1) ERR pin and Reset & Enable functional between VVS=6 ... 7V, but characteristics might be out of specified range
2) Not subject to production test; specified by design 3) These levels are valid for wake up of the IC. The input levels for INH deciding the output state of INHD are shown in Chapter 8.4
Data Sheet
30
Rev. 1.0, 2008-12-04
TLE7184F
Description of Modes, Protection and Diagnostic Functions
Electrical Characteristics - Protection and diagnostic functions
VS = 6.0 to 33V, Tj = -40 C to +150 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Min. Temperature monitoring 9.4.40 9.4.41 9.4.42 Over Temperature shut down Over Temperature pre-warning Difference between Over Temperature shut down level and Over Temperature pre-Warning level Limit Values Typ. 170 140 30 Max. 180 150 40 C C C
1) 1) 1)
Unit
Conditions
Tj(SD) Tj(PW) dTj(SDPW)
160 130 20
-
-
-
9.4.43 9.4.44 9.4.45 9.4.46 9.4.47 9.4.48 9.4.49 9.4.50
Analog temperature output at 25C VATRT Analog temperature output coefficient Analog temperature output drift over lifetime1) Analog temperature range1)
1.15 4.57 0 -40 92 1.8 3.7 15
- - - - - - - -
1.8 5.20 +6 175 96.5 4.2 4.2 45
V mV/K mV C % s V s
KATRT VATRTd TAT
Cload<=1.5nF; Tj=25C Cload<=1.5nF 1) Cload<=1.5nF
- - -
Over current detection Over current detection level in% of VOCTH
VVDD
Filter time for over current detection tOC
Under Voltage monitoring VDD
VUVVDD Under Voltage shut down filter time tUVVDD
Under Voltage shut down at VDD2)
VVDD decreasing
-
1) Not subject to production test; specified by design 2) For Under Voltage detection level during go-to-sleep see VDDsleep
Data Sheet
31
Rev. 1.0, 2008-12-04
TLE7184F
Application Description
10
Application Description
In the automotive sector there are more and more applications requiring high performance motor drives, such as HVAC fans, engine cooling fans, pumps etc.. In these applications 3 phase motors, synchronous and asynchronous, are used, combining high output performance, low space requirements and high reliability.
R 2,2k R 33 R 1,2k R 1,6k RVS 10 L 2,2H L 2,2H
KL 15
interface VBAT
CBR 4,7mF CVS 2F PGND
CBR 1F PGND
C VS 100 nF R 10k R 10k ___ INH IFMA
CREG 2F R VDH C BS1 470nF RGH1 C BS2 470nF RGH2 T HS2 T HS1
VDHS
VS VREG VDH BH1 GH1
RVDH1
ROV1 IOV
SH1 BH2 GH2 SH2 BH3 CBS3 470nF RGH3 T HS3
RVDH2
ROV2
IFuC ____ RGS ____ INHD
____ ERR TEMP
TLE 7184
GH3 SH3
C
IL1 ___ IH1 IL2 ___ IH2 IL3 ___ IH3 R SC1 SCDL R SC2
+
GL1
RGL1
TLS1
GL2
RGL2
TLS2
GL3
RGL3 Rfb2
TLS3
CVDD1 100nF
CVDD2 2.2nF
VDD DT SL ISP
RDT ISN GND CTP AGND ISO GND AGND
Rfb3 AGND
RS Shunt RS
Rfb1
GND
GND
AGND
PGND
Figure 13
Application Circuit TLE7184F
Note: This is a simplified example of an application circuit. The function must be verified in the real application
Data Sheet
32
Rev. 1.0, 2008-12-04
TLE7184F
Package Outlines
11
Package Outlines
A
9 0.1 8.75 0.1 B 48x 0.08
0.9 MAX. (0.65) 0.55 0.05
11 x 0.65 = 7.15 0.65
25 24 36 37
11 x 0.65 = 7.15
8.75 0.1
0.65
SEATING PLANE
12MAX.
13 48 12 1
Index Marking C
0.35 0.05 (0.2) 0.05 MAX. STANDOFF 6.8 0.15
Index Marking 48x 0.1 M A B C
6.8 0.15
GVQ01049
Figure 14
PG-VQFN-48
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. Data Sheet 33
9 0.1
Dimensions in mm Rev. 1.0, 2008-12-04
TLE7184F
Revision History
12
Revision Rev.1.0
Revision History
Date 2008-12-04 Changes - Test conditions of bias current into BHx modified - Current between BHx and SHx adapted - IFMA internal pull-up resistor to VS modified - Matching of internal pull-up / pulldown resistor expanded - Filter time of short circuit protection test conditions improved - Blanking time plus filter time of short circuit detection test conditions added - Filter time for over current detection expanded
Data Sheet
34
Rev. 1.0, 2008-12-04
Edition 2008-12-04 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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