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PD - 97378A
IRFS3004-7PPBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G D
HEXFET(R) Power MOSFET
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
40V 0.90m 1.25m 400Ac 240A
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
S
S G S S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case)
Max.
400 280 240 1610 380 2.5 20 2.0 -55 to + 175 300 290 See Fig. 14, 15, 22a, 22b
Units
A
d
W W/C V V/ns C
f
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentAd Repetitive Avalanche Energy
e
Thermal Resistance
Symbol
RJC RJA
d j
mJ A mJ
Junction-to-Case Junction-to-Ambient (PCB Mount)
kl
Parameter
Typ.
--- ---
Max.
0.40 40
Units
C/W
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1
04/22/2010
IRFS3004-7PPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
40 --- --- 2.0 --- --- --- --- --- --- --- 0.038 --- 0.90 1.25 --- 4.0 --- 20 --- 250 --- 100 --- -100 2.0 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 195A V VDS = VGS, ID = 250A A VDS = 40V, VGS = 0V VDS = 40V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
g
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related)h
Min. Typ. Max. Units
1300 --- --- --- --- --- --- --- --- --- --- --- --- --- --- 160 42 65 95 23 240 91 160 9130 2020 990 2590 2650 --- 240 --- --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 10V, ID = 195A ID = 180A VDS =20V VGS = 10V ID = 180A, VDS =0V, VGS = 10V VDD = 26V ID = 240A RG = 2.7 VGS = 10V VGS = 0V VDS = 25V = 1.0 MHz, See Fig. 5 See Fig. 11 VGS = 0V, VDS = 0V to 32V VGS = 0V, VDS = 0V to 32V
g
ns
pF
g
iA
i, h
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ad Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 400 --- 1610 A A
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 49 --- ns --- 51 --- --- 37 --- nC TJ = 125C --- 41 --- --- 3.2 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 195A, VGS = 0V VR = 34V, TJ = 25C IF = 240A TJ = 125C di/dt = 100A/s TJ = 25C
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140) Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.01mH RG = 25, IAS = 240A, VGS =10V. Part not recommended for use above this value .
ISD 240A, di/dt 740A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C. RJC value shown is at time zero.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFS3004-7PPBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
10
100
1 4.5V 0.1 0.1 1
60s PULSE WIDTH
Tj = 25C 10 10 100 1000 0.1
4.5V 1
60s PULSE WIDTH
Tj = 175C 10 100 1000
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 195A
ID, Drain-to-Source Current (A)
VGS = 10V
100 T J = 175C 10 T J = 25C
1.5
1.0
1 VDS = 25V 60s PULSE WIDTH 3 4 5 6 7 8
0.1
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
14.0 ID= 180A
VGS, Gate-to-Source Voltage (V)
12.0 10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance (pF)
10000
Ciss Coss Crss
VDS= 32V VDS= 20V
1000
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
50
100
150
200
250
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS3004-7PPBF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000
100sec
100
10
T J = 25C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
T J = 175C
100
1msec 10msec
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
10 Tc = 25C Tj = 175C Single Pulse 1 0 1 10 100 VDS, Drain-to-Source Voltage (V)
DC
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
420 360
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
50 Id = 5mA 48
Limited By Package
300 240 180 120 60 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
46
44
42
40 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
3.5 3.0 2.5
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
1200 1000 800 600 400 200 0 ID 44A 80A BOTTOM 240A TOP
Energy (J)
2.0 1.5 1.0 0.5 0.0 -5 0 5 10 15 20 25 30 35 40 45
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS3004-7PPBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 0.001
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 1 2 3 4 4
Ri (C/W)
0.00757 0.06508 0.18313 0.14378
0.000006 0.000064 0.001511 0.009800
i (sec)
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1
0.001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01 0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
320 280
EAR , Avalanche Energy (mJ)
240 200 160 120 80 40 0 25 50
TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 240A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
75
100
125
150
Starting T J , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRFS3004-7PPBF
4.5
VGS(th), Gate threshold Voltage (V)
10 9 8 7 6 5 4 3 2 IF = 96A V R = 34V TJ = 25C TJ = 125C
4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) ID = 250A ID = 1.0mA ID = 1.0A
IRRM (A)
100
200
300 diF /dt (A/s)
400
500
Fig 16. Threshold Voltage vs. Temperature
12 11 10 9
IRRM (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
140 IF = 96A V R = 34V TJ = 25C TJ = 125C
IF = 144A V R = 34V TJ = 25C TJ = 125C
QRR (nC)
120 100 80 60 40 20
8 7 6 5 4 3 2 100 200 300 diF /dt (A/s) 400 500
100
200
300 diF /dt (A/s)
400
500
Fig. 18 - Typical Recovery Current vs. dif/dt
180 160 140
QRR (nC)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 144A V R = 34V TJ = 25C TJ = 125C
120 100 80 60 40 20
100
200
300 diF /dt (A/s)
400
500
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS3004-7PPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFS3004-7PPBF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFS3004-7PPBF
D2Pak - 7 Pin Part Marking Information
AIR
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 04/2010
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