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1/4 STRUCTURE Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE FUNCTION
36V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Circuit protection with quick Shutdown Mode-selectable the operating or stand-by mode by stand-by pin BURST mode controlled by PWM and DC input VQFN024V4040 small package
Absolute Maximum Ratings
Parameter Supply Voltage BST PIN SW PIN BST-SW voltage difference Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation
*
Symbol VCC BST SW BST-SW Topr Tstg Tjmax Pd
Limits 36 40 36 15 -40+85 -55+150 +150 700*
Unit V V V V mW
Pd derate at 5.6mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition
Parameter Supply voltage BST voltage BST-SW voltage difference oscillation frequency BCT oscillation frequency Symbol VCC BST BST-SW FOUT fBCT Limits 8.030.0 5.037.5 5.014.0 30110 0.051.00 Unit V V V kHz kHz
REV. A
2/4
Electric CharacteristicsTa=25VCC=24VSTB=3.0V
Parameter WHOLE DEVICE Operating current Stand-by current STAND BY CONTROL Stand-by voltage H Stand-by voltage L VCC UVLO BLOCK Operating voltage (VCC) Hesteresis width (VCC UVLO) REG BLOCK REG output voltage REG source current OSC BLOCK RT Output Voltage SRT ON Resistor value SOFT START BLOCK Soft start Charge Current SS term start voltage SS term end voltage BOSC BLOCK BOSC Max voltage BOSC Min voltage BOSC frequency FEED BACK BLOCK IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage OUTPUT BLOCK LN output sink resistance LN output source resistance HN output sink resistance HN output source resistance MAX DUTY OFF period Drive output frequency TIMER LATCH BLOCK VCP ICP VIS VVS IIS1 IIS2 IVS VBCTH VBCTL FBCT TSS VRT RSRT VREG IREG VstH VstL Icc1 Icc2
Symbol MIN.
Limits TYP. MAX.
Unit
Conditions

2.2 0
5.0 10
mA A
FOUT=60kHz, FB=SW=GND, BST=OPEN
2.0 -0.3

VCC 0.8
V V
System System
V_VCCUVP V_VCCUVP
6.17 0.37
6.50 0.50
6.83 0.63
V V
7.35 20
7.50
7.65
V mA
VCC>8.5V, Io=10mA
1.05
1.50 100
1.95 200
V
1.5 0 2.8
2.0 50 3.0
2.5 150 3.2
uA mV V
VSS_ST VSS_END
1.94 0.4 291
2.00 0.5 300
2.06 0.6 309
V V Hz
fBCT=0.3kHz fBCT=0.3kHz BCT=10000pF
1.225 1.215 40 0.606
1.250 1.250 50 0.625
1.275 1.285 0.9 60 0.9 0.644
V V A A A V DUTY=2.2V DUTY=0V IS=1.0V
VISCOMP
RsinkLN RsourceLN RsinkHN RsourceHN MAX DUTY TOFF FOUT
1.5 5 1.5 5 46.0 100 57.9
3 10 3 10 48.5 200 60.0
6 20 6 20 49.5 400 62.1
% ns kHz VBST-VSW=7.0V VBST-VSW=7.0V FOUT=60kHz, SW=GND, BST=OPEN SW=GND, BST=OPEN RT=82k
CP timer latch detect voltage CP timer latch charge current COMP BLOCK COMP1 over voltage detect voltage Hysteresis width COMP1 COMP2 over voltage detect voltage
1.9 0.85
2.0 1.0
2.1 1.15
V A
VCOMP1 VCOMP1 VCOMP2
3.88 0.15 3.88
4.00 0.20 4.00
4.12 0.25 4.12
V V V
(This product is not designed to be radiation-resistant.)
REV. A
3/4
Package Dimensions
Device Mark
Block Diagram
VCC REG RT BCT DUTY
D9243
STB
REG BLOCK
OSC
BOSC
DUTY BLOCK
STB BLOCK
SYSTEMON/OFF
Lot No.
SS FB IS VS F/B BLOCK PWM BLOCK LOGIC BLOCK HN BLOCK
BST1 BST2 HN1 HN2 SW1 SW2 REG PROTECT BLOCK
SS CT
GND UVLO BLOCK
LN BLOCK
LN1 LN2
VCC
PGND
COMP1
COMP2
CP
SRT
VQFN024V4040 (UNIT:mm)
Pin Description
PIN PIN NAME No. 1 GND Ground External capacitor between BCT and GND for adjusting the 2 BCT BURST triangle oscillator 3 DUTY Control Burst-dimming by PWM signal or DC External capacitor between SS and GND for Soft Start Control 4 SS and detect the time of Soft Start 5 6 7 8 9 10 CP FB IS VS COMP2 COMP1 External capacitor between CP and GND for timer latch Error amplifier output Error amplifier input 2 Error amplifier input 1 Input of over voltage detector2 Input of over voltage detector1 17 18 19 20 21 22 LN2 BST2 HN2 SW2 VCC STB NMOS FET driver (Ch. 2) Boot-strap input for HN2 output NMOS FET driver (Ch. 2) Lower rail voltage for HN2 output Power supply input with UVLO Protection Stand-by switch External resister from SRT to RT for adjusting the start-up Triangle 11 SW1 Lower rail voltage for HN1 output 23 SRT oscilator External resistor between RT and GND for adjustment frequency of saw 12 HN1 NMOS FET driver (Ch. 1) 24 RT tooth wave 16 PGND Power Ground for FET drivers 15 LN1 NMOS FET driver (Ch. 1) 14 REG Regulator output FUNCTION No. 13 BST1 Boot-strap input for HN1 output PIN PIN NAME FUNCTION
REV. A
4/4
NOTE FOR USE
. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. . The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . Mounting failures, such as misdirection or miscounts, may harm the device. . A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin. . If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual current flow into pins may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection diodes for prevention against backward current flow. . BD9243MUV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. . Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. . About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. . By STB voltage, BD9243MUV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.82.0V). . The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig.4)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin
Resistance (PinA) (PinB) Transistor (NPN)

P substrate

P substrate Parasitic diode (PinB)
Parasitic diode
(PinA) Parasitic

Parasitic diode
Other adjacent components
Fig.4. Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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R1010A

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