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PD - 96214
IRFB4110GPBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
HEXFET(R) Power MOSFET
Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
100V 3.7m: 4.5m: 180A 120A
D
c
G S
G TO-220AB IRFB4110GPBF
D
S
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
180 130 120 670 370 2.5 20 5.3 -55 to + 175 300 10lbfxin (1.1Nxm) 190 See Fig. 14, 15, 22a, 22b
Units
A
d
W W/C V V/ns
f
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentAd Repetitive Avalanche Energy
e
d
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat Greased Surface Junction-to-Ambient
j
Parameter
Typ.
--- 0.50 ---
Max.
0.402 --- 62
Units
C/W
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1
01/06/09
IRFB4110GPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
100 --- --- 2.0 --- --- --- --- --- --- 0.108 --- 3.7 4.5 --- 4.0 --- 20 --- 250 --- 100 --- -100
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A V VDS = VGS, ID = 250A VDS = 100V, VGS = 0V A VDS = 100V, VGS = 0V, TJ = 125C VGS = 20V nA VGS = -20V
g
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd RG td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
160 --- --- ---
---
Conditions
VDS = 50V, ID = 75A ID = 75A VDS = 50V VGS = 10V
--- 150 35 43 1.3 25 67 78 88 9620 670 250 820 950
--- 210 --- --- --- --- --- --- --- --- --- --- --- ---
S nC
g
--- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h
ns
pF
VDD = 65V ID = 75A RG = 2.6 VGS = 10V VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V VGS = 0V, VDS = 0V to 80V
g
i h
D
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ad Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 170 --- 670 A
Conditions
MOSFET symbol showing the integral reverse
G
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 75A, VGS = 0V TJ = 25C VR = 85V, --- 50 75 ns TJ = 125C IF = 75A --- 60 90 di/dt = 100A/s TJ = 25C --- 94 140 nC TJ = 125C --- 140 210 --- 3.5 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.033mH RG = 25, IAS = 108A, VGS =10V. Part not recommended for use above this value.
ISD 75A, di/dt 630A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as R is measured at TJ approximately 90C.
Coss while VDS is rising from 0 to 80% VDSS.
2
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IRFB4110GPBF
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
1000
TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
BOTTOM
4.5V
100
4.5V
100
60s PULSE WIDTH
Tj = 25C 10 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
60s PULSE WIDTH
Tj = 175C 10 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (A)
100
2.5
ID = 75A VGS = 10V
2.0
10 T J = 175C 1
T J = 25C
1.5
VDS = 25V 60s PULSE WIDTH 0.1 1 2 3 4 5 6 7
1.0
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
12.0 ID= 75A
VGS, Gate-to-Source Voltage (V)
10.0 8.0 6.0 4.0 2.0 0.0
C, Capacitance (pF)
10000
Ciss
VDS= 80V VDS= 50V
Coss 1000 Crss
100 1 10 VDS, Drain-to-Source Voltage (V) 100
0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4110GPBF
1000 10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000
100
T J = 175C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
10
T J = 25C
100sec
100
10msec
1 VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-to-Drain Voltage (V)
10 Tc = 25C Tj = 175C Single Pulse 1 0 1
DC
1msec
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
180 160 140
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
125 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Limited By Package
120 100 80 60 40 20 0 25 50 75 100 125 150 175 TC , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
5.0 4.5 4.0 3.5
Fig 10. Drain-to-Source Breakdown Voltage
800
EAS , Single Pulse Avalanche Energy (mJ)
700 600 500 400 300 200 100 0
ID 17A 27A BOTTOM 108A TOP
Energy (J)
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ , Junction Temperature (C)
4
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB4110GPBF
1 D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01
J R1 R1 J 1 2 R2 R2 R3 R3 C 1 2 3 3 C
Thermal Response ( Z thJC )
0.01
0.001
Ci= i/R i Ci= i/Ri
Ri (C/W) 0.09876251 0.2066697 0.09510464
i (sec) 0.000111 0.001743 0.012269
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
0.0001 1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01 0.05
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
10
0.10
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
250 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 108A
EAR , Avalanche Energy (mJ)
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150 Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4110GPBF
4.0
VGS(th), Gate threshold Voltage (V)
25 IF = 30A V R = 85V TJ = 25C TJ = 125C
3.5 3.0
IRR (A)
20
2.5 2.0 1.5 1.0 0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) ID = 250A ID = 1.0mA ID = 1.0A
15
10
5
0 0 200 400 600 800 1000 diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
25 IF = 45A V R = 85V TJ = 25C TJ = 125C
QRR (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
560 480 400 320 240 IF = 30A V R = 85V TJ = 25C TJ = 125C
20
IRR (A)
15
10
5
160 80
0 0 200 400 600 800 1000 diF /dt (A/s)
0
200
400
600
800
1000
diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
560 480 400
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 45A V R = 85V TJ = 25C TJ = 125C
320 240 160 80 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4110GPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD VDS
Fig 21b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
7
IRFB4110GPBF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
@Y6HQG@) UCDTADTA6IADSA7#" BQ7A Ir)AABAAssvAvAhAirA vqvphrAAChytrAAArrA Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqAAArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@) 2G6TUA9DBDUAPA 86G@I96SA@6S XX2XPSFAX@@F Y2A68UPSA8P9@
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.01/2009
8
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