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ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Rev. 02 -- 7 August 2008 Product data sheet
1. General description
The ADC1207S080 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct Input Frequency (IF) sampling and supporting the most demanding use conditions in ultra high IF radio transceivers for cellular infrastructure and other applications such as wireless infrastructure, optical networking and fixed telecommunication. Due to its broadband input capabilities, the ADC1207S080 is ideal for single and multiple carriers data conversion. Operating at a maximum sampling rate of 80 MHz, analog input signals are converted into 12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output signals are Low-Voltage Complementary Metal-Oxide Semiconductor (LVCMOS) compatible. The ADC1207S080 offers the most flexible acquisition control system because of its programmable Complete Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock. The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy because of its internal front-end buffer.
2. Features
I I I I I I I I I I I I I I I 12-bit resolution Differential input with 375 MHz bandwidth 90 dB SFDR; 71 dB S/N (fi = 225 MHz; fclk = 80 MHz; B = 5 MHz) 74 dB SFDR; 66.5 dB S/N (fi = 175 MHz; fclk = 80 MHz; B = Nyquist) High speed sampling rate up to 80 MHz Internal front-end buffer (input capacitance < 1 pF) Programmable acquisition output clock (complete conversion signal) Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale Single 5 V power supply 3.3 V LVCMOS compatible digital outputs Binary or two's-complement LVCMOS outputs CMOS compatible static digital inputs Only 2 clock cycles latency Industrial temperature range from -40 C to +85 C HTQFP48 package
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
3. Applications
High speed analog to digital conversion for: I Radio transceivers I Wireless infrastructure I Cable modem I Digital storage scope I Fixed telecommunication, I Optical networking I Wireless Local Area Network (WLAN) infrastructure. I General purpose applications
4. Ordering information
Table 1. Ordering information Package Name ADC1207S080HW HTQFP48 Description plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad Version Sampling frequency (MHz) Type number
SOT545-2 80
5. Block diagram
CLK CLKN
ADC1207S080
CLOCK DRIVER
2
DEL0 to DEL1 CCS
12
LATCH
12
D0 to D11 OTC
front-end buffer IN INN TRACK AND HOLD RESISTOR LADDERS ADC CORE
U/I FSIN
VCCO LATCH IR
FSOUT
VREF REFERENCE
CMADC REFERENCE
OUTPUTS ENABLE
014aaa430
CMADC
DEC
CE_N
Fig 1. Block diagram
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
2 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
6. Pinning information
6.1 Pinning
42 DGND1 38 DGND1 48 AGND1 46 AGND1 43 AGND2 41 VCCD1 47 VCCA1 45 VCCA1 44 VCCA2
39 CLKN
n.c. AGND1 IN CMADC INN AGND1 DEC n.c. FSOUT
37 CCS 36 D0 35 D1 34 D2 33 D3 32 D4 31 D5 30 D6 29 D7 28 D8 27 D9 26 D10 25 D11 IR 24
014aaa431
1 2 3 4 5 6 7 8 9 DGND
ADC1207S080HW
FSIN 10 n.c. 11 n.c. 12 n.c. 13 DEL1 14
DEL0 15
VCCD2 16
DGND2 17
CE_N 18
OTC 19
OGND 20
VCCO 21
40 CLK
OGND 22
Fig 2. Pin configuration
6.2 Pin description
Table 2. Symbol n.c. AGND1 IN CMADC INN AGND1 DEC n.c. FSOUT FSIN n.c. n.c. n.c. DEL1 DEL0 VCCD2
ADC1207S080_2
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type [1] G I O I G I/O O I I I P Description not connected analog ground 1 analog input voltage regulator common mode ADC output complementary analog input voltage analog ground 1 decoupling node not connected full-scale reference voltage output full-scale reference voltage input not connected not connected not connected complete conversion signal delay input 1 complete conversion signal delay input 0 digital supply voltage 2 (5.0 V)
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
VCCO 23
3 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Pin description ...continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type [1] G I I G P G P O O O O O O O O O O O O O O G I I P G G P P G P G Description digital ground 2 chip enable input (CMOS level; active LOW) control input for two's complement output (active HIGH) data output ground data output supply voltage (3.3 V) data output ground data output supply voltage (3.3 V) in-range output data output bit 11 (Most Significant Bit (MSB)) data output bit 10 data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (Least Significant Bit (LSB)) complete conversion signal output digital ground 1 complementary clock input clock input digital supply voltage 1 (5.0 V) digital ground 1 analog ground 2 analog supply voltage 2 (5.0 V) analog supply voltage 1 (5.0 V) analog ground 1 analog supply voltage 1 (5.0 V) analog ground 1 digital ground
Table 2. Symbol DGND2 CE_N OTC OGND VCCO OGND VCCO IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CCS DGND1 CLKN CLK VCCD1 DGND1 AGND2 VCCA2 VCCA1 AGND1 VCCA1 AGND1 DGND
exposed G die pad
[1]
P: power supply; G: ground; I: input; O: output.
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
4 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO VCC Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA - VCCD VCCD - VCCO VCCA - VCCO Vi(IN) Vi(INN) Vi(CLK) Vi(CLKN) IO Tstg Tamb Tj
[1] [2]
Conditions
[1] [1] [2]
Min -0.5 -0.5 -0.5 -1.0 -1.0 -1.0 0 0 0 0 -55 -40 -
Max +7.0 +7.0 +5.0 +1.0 +4.0 +4.0 VCCA + 1 VCCA + 1 VCCD + 1 VCCD + 1 10 +150 +85 150
Unit V V V V V V V V V V mA C C C
input voltage on pin IN input voltage on pin INN input voltage on pin CLK input voltage on pin CLKN output current storage temperature ambient temperature junction temperature
referenced to AGND referenced to AGND referenced to DGND referenced to DGND
The supply voltages VCCA and VCCD may have any value between -0.5 V and +7.0 V provided that the supply voltage differences VCC are respected. The supply voltage VCCO may have any value between -0.5 V and +5.0 V provided that the supply voltage differences VCC are respected.
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 36.2 14.3
Unit K/W K/W
In compliance with JEDEC test board, in free air.
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
5 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
9. Characteristics
Table 5. Characteristics VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; Vi(IN) - Vi(INN) = -0.5 dBFS; Vref(fs) = VCCA - 1.87 V; VI(cm) = VCCA - 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO Ptot VIL analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current total power dissipation CLKN[1] referenced to DGND; VCCD = 5 V Positive Emitter-Coupled Logic (PECL) mode Transistor-Transistor Logic (TTL) mode VIH PECL mode TTL mode IIL IIH Vi(clk)dif LOW-level input current VCLK or VCLKN = 3.52 V VCLK or VCLKN = 0.80 V HIGH-level input current VCLK or VCLKN = 3.83 V VCLK or VCLKN = 2.00 V differential clock input voltage input resistance input capacitance LOW-level input current input resistance input capacitance common-mode input voltage LOW-level input voltage HIGH-level input voltage Vi(IN) = Vi(INN); output code = 2047 VCLK - VCLKN; AC mode; DC voltage level is 2.5 V fclk = 80 MHz fclk = 80 MHz Vref(fs) = VCCA - 1.75 V
[2] [2] [2] [2] [2]
Parameter
Conditions
Min 4.75 4.75 2.7 -
Typ 5.0 5.0 3.3 120 50 10 840
Max 5.25 5.25 3.6 135 65 15 990
Unit V V V mA mA mA mW
fclk = 80 MHz; fi = 93 MHz fclk = 80 MHz; DC input
-
Clock inputs: pins CLK and
LOW-level input voltage
3.19
-
3.52
V
DGND
-
0.8
V
HIGH-level input voltage referenced to DGND; VCCD = 5 V 3.83 2.0 1 2 1.3 1.5 4.12 VCCD 28 30 1.7 V V A nA A nA V
Ri Ci IIL IIH Ri Ci VI(cm)
6.3 VCCA - 2
6.3 1.1 5 5 VCCA - 1.8
700 VCCA - 1.6
k fF A A M fF V
Analog inputs: pins IN and INN HIGH-level input current Vref(fs) = VCCA - 1.75 V
Digital inputs: pins OTC and CE_N VIL VIH
ADC1207S080_2
DGND 0.7 x VCCD
-
0.3 x VCCD VCCD
V V
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
6 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Table 5. Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; Vi(IN) - Vi(INN) = -0.5 dBFS; Vref(fs) = VCCA - 1.87 V; VI(cm) = VCCA - 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol IIL IIH VIL VIH IIL IIH VO(cm) Parameter LOW-level input current Conditions VIL = 0.8 V Min DGND 0.7 x VCCD VIL = 0.8 V see Figure 5; Vi = Vi(IN) - Vi(INN); VI(cm) = VCCA - 1.95 V Typ 1 1 8 20 VCCA - 1.88 VCCA - 1.95 VCCA - 1.80 0.1 1.85 Max 0.3 x VCCD VCCD Unit A A V V A A V V V A V
HIGH-level input current VIH = 2.0 V LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current VIH = 2.0 V common-mode output voltage FSIN[3] IL = 0 mA IL = 2 mA
Digital inputs: pins DEL0 and DEL1
Voltage controlled regulator output: pin CMADC
Reference voltage input: pin Vref(fs) Iref(fs) Vi(a)(p-p)
full-scale reference voltage full-scale reference current peak-to-peak analog input voltage
Full-scale voltage controlled regulator output: pin FSOUT VO(ref) reference output voltage IL = Iref(fs) IL = 2 mA Digital outputs: pins D11 to D0, IR and CCS Output levels VOL VOH IOZ Timing[4] td(s) th(o) td(o) tdZH tdZL tdHZ tdLZ
ADC1207S080_2
-
VCCA - 1.80 VCCA - 1.82
-
V V
LOW-level output voltage HIGH-level output voltage OFF-state output current sampling delay time output hold time output delay time float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time
IOL = 2 mA IOH = -0.4 mA output level between 0.5 V and VCCO CL = 10 pF CL = 10 pF CL = 10 pF
DGND VCCO - 0.5 -0.1
0
DGND + 0.5 VCCO +0.1
V V A
2.6 -
0.1 3.8 4.7 3.6 3.9 9.2 7.2
0.24 7.8 -
ns ns ns ns ns ns ns
(c) NXP B.V. 2008. All rights reserved.
3-state output delay
Product data sheet
Rev. 02 -- 7 August 2008
7 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Table 5. Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; Vi(IN) - Vi(INN) = -0.5 dBFS; Vref(fs) = VCCA - 1.87 V; VI(cm) = VCCA - 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol fclk(min) fclk(max) Parameter duty cycle minimum clock frequency maximum clock frequency CCS delay time = 45 % to 55 % Conditions fclk = 80 MHz; fi = 175 MHz Min 45 80 Typ Max 55 9.5 Unit % MHz MHz Clock timing inputs: pins CLK and CLKN
Timing complete conversion signal: pin CCS; see Figure 6 td(CCS) CL = 10 pF; DEL0 = HIGH; DEL1 = LOW CL = 10 pF; DEL0 = LOW; DEL1 = HIGH CL = 10 pF; DEL0 = HIGH; DEL1 = HIGH Analog signal processing (clock duty cycle 50 %) INL DNL integral non-linearity differential non-linearity fclk = 20 MHz; fi = 21.4 MHz fclk = 20 MHz; fi = 21.4 MHz; no missing code guaranteed VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 2047 VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C fclk = 80 MHz; -3 dB; full-scale input fi = 21.4 MHz fi = 93 MHz fi = 175 MHz 3H third harmonic level fi = 21.4 MHz fi = 93 MHz fi = 175 MHz THD total harmonic distortion fi = 21.4 MHz fi = 93 MHz fi = 175 MHz Nth(RMS) RMS thermal noise Vi(IN) = Vi(INN); fclk = 80 MHz
[6] [5]
-
0.3
-
ns
-
1.3
-
ns
-
2.3
-
ns
-
2.0 0.6
-
LSB LSB
Eoffset
offset error
-4
+8
+24
mV
EG
gain error
-
2.5
-
%FS
B 2H
bandwidth second harmonic level
320 -
375 -79 -78 -74 -84 -80 -76 -75 -73 -68 0.45
-
MHz dBc dBc dBc dBc dBc dBc dBc dBc dBc LSB
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
8 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Table 5. Characteristics ...continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = -40 C to +85 C; Vi(IN) - Vi(INN) = -0.5 dBFS; Vref(fs) = VCCA - 1.87 V; VI(cm) = VCCA - 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol S/N Parameter signal-to-noise ratio Conditions fi = 21.4 MHz fi = 93 MHz fi = 175 MHz SFDR spurious free dynamic range fi = 21.4 MHz fi = 93 MHz fi = 175 MHz ACPR adjacent channel power ratio second-order intermodulation distortion fi = 93 MHz; 5 MHz channel spacing; B = 3.84 MHz fi 1 = 21 MHz; fi 2 = 22 MHz fi 1 = 91.5 MHz; fi 2 = 94.5 MHz fi 1 = 174 MHz; fi 2 = 176 MHz IMD3 third-order intermodulation distortion fi 1 = 21 MHz; fi 2 = 22 MHz fi 1 = 91.5 MHz; fi 2 = 93.5 MHz fi 1 = 174 MHz; fi 2 = 176 MHz
[1]
[8] [8] [7]
Min 63 68 -
Typ 67.4 67.2 66.5 76 78 74 70
Max -
Unit dBc dBc dBc dBc dBc dBc dB
IMD2
-
-89 -86 -83 -88 -82 -83
-
dBFS dBFS dBFS dBFS dBFS dBFS
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. Guaranteed by design. The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to VCCA. Output data acquisition: the output data is available after the maximum delay of td(o). The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. The total harmonic distortion is obtained with the addition of the first five harmonics. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. Intermodulation measured relative to either tone with analog input frequencies fi 1 and fi 2. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full-scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
[2] [3] [4] [5] [6] [7] [8]
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
9 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
10. Additional information relating to Table 5
Table 6. Output coding with differential inputs Vi(IN) - Vi(INN) = 1.9 V; Vref(fs) = VCCA1 - 1.87 V; typical values to AGND. Code Underflow 0 1 2047 4094 4095 Overflow Table 7. 0 1 X [1]
[1] X = don't care.
Vi(IN) (V) Vi(INN) (V) IR < 2.675 2.675 3.15 3.625 > 3.625 > 3.625 3.625 3.15 2.675 < 2.675 0 1 1 1 1 1 0
Binary outputs (D11 to D0) 0000 0000 0000 0000 0000 0000 0000 0000 0001 0111 1111 1111 1111 1111 1110 1111 1111 1111 1111 1111 1111
Two's complement outputs (D11 to D0) 1000 0000 0000 1000 0000 0000 1000 0000 0001 1111 1111 1111 0111 1111 1110 0111 1111 1111 0111 1111 1111
Mode selection 0 0 1 binary; active two's complement; active high-impedance
Two's complement output (OTC) Chip enable input (CE_N) Data output (D0 to D11; IR)
CLK
n
50 %
td(o) D0 to D11 data n-1 data n th(o) td(s) IN sample n sample n+1 sample n+2 sample n+3 sample n+4
014aaa432
data n+1
VCCO - 0.5 V 0.5 V
Fig 3. Output timing diagram
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
10 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
0 power spectrum (dBc) -40
014aaa435
(1)
-80
(2)
(3)
(4)
(5)
(6)
-120
-160 0 10 20 30 fi (MHz) 40
(1) fi 1H = 15 MHz; 0 dBc (2) fi 2H = 5.1 MHz; -79.6 dBc (3) fi 3H = 9.88 MHz; -82.1 dBc (4) fi 4H = 20.1 MHz; -80.6 dBc (5) fi 5H = 30 MHz; -74.7 dBc (6) fi 6H = 35.1 MHz; -93.9 dBc THD (5H): -72.2 dBc SFDR: 74.7 dBc
Fig 4.
Single tone; fi = 175 MHz; fCLK = 80 MHz
2.2 Vi(a)(p-p) (V) 2.0
014aaa436
1.8
1.6
1.4 1.4
1.6
1.8
2.0 Vref(fs) (V)
2.2
Fig 5.
ADC full-scale; Vi(a)(p-p) as a function of Vref(fs)
The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN (full-scale input) according to Figure 5.
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
11 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
The ADC1207S080 generates an adjustable clock output called Complete Conversion Signal (CCS), which can be used to control the acquisition of converted output data by the digital circuit connected to the ADC1207S080 output data bus. Two logic inputs, DEL0 and DEL1 pins, allow adjusting the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data.
Table 8. DEL1 0 0 1 1 0 1 0 1 Complete conversion signal selection DEL0 CCS output high-impedance active, typical delay 0.3 ns active, typical delay 1.3 ns active, typical delay 2.3 ns
(1)
D0 to D11 td(CCS) CCS
014aaa433
(1) td(CSS) is referenced to the middle of the active data.
Fig 6. Complete conversion signal timing diagram
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
12 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
11. Definitions
11.1 Static parameters
11.1.1 Integral Non-Linearity (INL)
It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V i ( i ) - V i ( ideal ) INL ( i ) = ----------------------------------------S where: S corresponds to the slope of the ideal straight line (code width); i corresponds to the code value; Vi is the input voltage.
11.1.2 Differential Non-Linearity (DNL)
It is the deviation in code width from the value of 1 LSB. V i(i + 1) - V i(i) DNL ( i ) = --------------------------------------S where: Vi is the input voltage; i from 0 to (2n - 2).
11.2 Dynamic parameters
Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency f, conforming to coherent sampling (f/fs = M/N, with M number of cycles and N number of samples, M and N being relatively prime), and digitized by the ADC under test.
magnitude
a1
SFDR
s a2 a3 ak
frequency
014aaa437
Fig 7.
Single tone spectrum of full-scale input sine wave with frequency ft
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
13 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and `quantization noise'.
11.2.1 SIgnal-to-Noise And Distortion (SINAD)
The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ dB ] = 10log 10 --------------------------------------- P noise + distortion
11.2.2 Effective Number Of Bits (ENOB)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: SINAD - 1.76 ENOB = ---------------------------------6.02
11.2.3 Total Harmonic Distortion (THD)
The ratio of the power of the harmonics to the power of the fundamental. For k - 1 harmonics the THD is: P harmonics THD [ dB ] = 10log 10 ------------------------ P signal - where: P harmonics = 2 + 3 + ... + k P signal = 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
2 2 2 2
11.2.4 Signal-to-Noise ratio (S/N)
The ratio of the output signal power to the noise power, excluding the harmonics and the DC component is: P signal S N [ dB ] = 10log 10 --------------- P noise-
11.2.5 Spurious Free Dynamic Range (SFDR)
The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious harmonic and non-harmonic, excluding DC component: 1 SFDR [ dB ] = 20log 10 ------------------ max ( S )
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
14 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
11.2.6 IMD2 (IMD3)
magnitude
f2
f1
2f2 - f1 f1 - f2
2f1 - f2 f1 + f2 2f2 2f1
f1 + 2f2 2f1 + f2 3f2 3f1
frequency
014aaa439
Fig 8. Spectral of dual tone input sine wave with frequency
From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows. The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total InterModulation Distortion (IMD) is given by: P intermod IMD [ dB ] = 10log 10 --------------------- P signal - where: P intermod = im ( f
2 - f t2 )
t1
- im ( f
2
2
t1
+ f t2 ) - f t2 )
+ im ( f
2
2
t1
- 2 f t2 ) + f t2 )
+ im ( f
2
t1
+ 2 f t2 )
+...
... + im ( 2 f with im ( f
2
t1 )
t1
+ im ( 2 f
t1
corresponding to the power in the intermodulation component at frequency ft.
2
t2
P signal = f + f
t1
2
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
15 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
12. Application information
12.1 ADC1207S080 in 3G radio receivers
The ADC1207S080 has been proven in many 3G radio receivers with various operating conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency. The ADC1207S080 is provided with a maximum analog input signal frequency of 400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only one, even in multi-carriers architecture. Table 9 describes some possible applications with the ADC1207S080 in high IF sampling mode.
Table 9. fi (MHz) 350 243.95 96 96 96 80 78.4 70
[1]
Examples of possible fi, fclk, IF BW combinations supported fclk (MHz) 80 9.60 76.80 76.80 76.80 61.44 44.80 40.00 IF BW (MHz) [1] 5.00 0.25 1.60 4.80 20.00 10.00 3.50 1.25 SNR (dB) 65 71 72 71 68 70 71 72 SFDR (dBc) 71 80 76 77 76 85 76 79
IF bandwidth corresponds to the observed area on the ADC output spectrum.
For a dual carrier Wideband-Code-Division-Multiple-Access (W-CDMA) receiver, the most important parameters are sensitivity and Adjacent Channel Selectivity (ACS). The sensitivity is defined as the lowest detectable signal level. In W-CDMA, it can be far below the noise floor. This difference, between the sensitivity and the noise floor, is defined by the Sensitivity-to-Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the full-scale -3 dB peak and the noise floor. It represents the ratio of the adjacent-channel power and the average power level of the channel. The ACS is defined by the sum of SENR and ACPR.
interfering channel
wanted channel
ACS
ACPR
noise floor NF SENR sensibility thermal noise
014aaa434
Fig 9. Adjacent channel sensitivity and ADC sensibility
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
16 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
12.2 Application diagram
ADT1_1WT 100 nF 6 2 4 VCCA VCCD
2.2 k
CLK
3 5 1 n.c.
50
VCCD1 DGND1 AGND1 VCCA1 DGND1 AGND1 AGND2 TL431CPK CCS 37 36 35 34 33 32 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 31 30 29 DGND 28 27 26 25 13 n.c. 14 DEL1 15 DEL0 16 VCCD2 17 DGND2 18 CE_N 19 OTC 20 OGND 21 VCCO 22 OGND 23 VCCO 24 IR G1
10 nF 10 nF 100 nF
VCCD1
VCCA1
VCCA2
48
330 nF
47
46
45
44
43
42
41
40
CLKN 39
10 nF
CLK
38
ADT1_1WT 3 n.c. IN
100 nF
n.c. AGND1
100
1 2
6 2 4
5 1
IN CMADC INN AGND1
3 4 5 6 7 8 9 10 11 12
100
10 nF 100 nF
DEC n.c. FSOUT FSIN n.c. n.c.
ADC1207S080
10 nF
VCCD VCCD 4700_000_S analog ground digital ground
330 nF 100 nF
VCCO (16) (41)
VCCA 4700_000_S (44)
100 nF 10 nF
(45)
(47)
10 nF
330 nF
VCCO 5V XX
10 V 4.7 F
HF70ACB (21) (23)
IN
470 nF
3
LM317MDT
1 ADJ
2
OUT
240 100 nF
10 nF 10 nF
GND
XX
300
014aaa438
Fig 10. Application diagram
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
17 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
13. Package outline
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad
SOT545-2
c y exposed die pad side X
Dh 36 37 25 24 ZE A
e Eh wM bp pin 1 index 48 1 wM 12 ZD vM A 13 detail X Lp L E HE A A2 A1 (A 3)
bp e D HD
B vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 7.1 6.9 Dh 4.6 4.4 E(1) 7.1 6.9 Eh 4.6 4.4 e 0.5 HD 9.1 8.9 HE 9.1 8.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.9 0.6 0.9 0.6 7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 04-01-29
Fig 11. Package outline SOT545-2 (HTQFP48)
ADC1207S080_2 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
18 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
14. Revision history
Table 10. Revision history Release date 20080807 Data sheet status Product data sheet Change notice Supersedes ADC1207S080_1 Document ID ADC1207S080_2 Modifications:
* * * *
Corrections made to version number in Table 1. Corrections made to several entries in Table 5. Corrections made to alignment in Figure 10. Corrections made to Figure 11. Product data sheet -
ADC1207S080_1
20080611
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
19 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1207S080_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 7 August 2008
20 of 21
NXP Semiconductors
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
17. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 5 . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Static parameters . . . . . . . . . . . . . . . . . . . . . . 13 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 13 Differential Non-Linearity (DNL) . . . . . . . . . . . 13 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13 SIgnal-to-Noise And Distortion (SINAD). . . . . 14 Effective Number Of Bits (ENOB) . . . . . . . . . . 14 Total Harmonic Distortion (THD). . . . . . . . . . . 14 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 14 Spurious Free Dynamic Range (SFDR) . . . . . 14 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 16 ADC1207S080 in 3G radio receivers . . . . . . . 16 Application diagram . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 August 2008 Document identifier: ADC1207S080_2

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