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iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 1/12 FEATURES E E E E E E E E E E E E 2 x 4 bidirectional input/output stages at 24 V Input/output mode programmable for each 4 bits Guaranteed low-side driving capability of 100 mAdc and 500 mApeak for pulse load Short-circuit-proof driver with high electric strength up to 48 V Low saturation voltage of 0.4 V at 10 mA and 1.5 V at 500 mA Programmable pull-down current sources Built-in free-wheeling diodes with externally accessible common cathode Flashing function for the outputs Programmable digital input filters with externally adjusted filtering times Bus capability via high-speed microprocessor interface Programmable interrupt output Shutdown at overtemperature and low voltage APPLICATIONS E Dual quad low-side driver as bidirectional P interface with digital filtering in 24 V industrial applications
PACKAGES
PLCC44
BLOCK DIAGRAM
Input/Output Stage 0 D 30 34 VCCA VCCD Test D NQ R 4 6 7 41 44 39 2 3 40 42 43 1 35 36 37 38 8 CSN WRN R RDN ENERR I/O Logic CERR Input/Output Stage 1 Input Filter Q up/dwn 3 Bit Counter
DISABLE
IO0
24
Output Latch Q R GND01 25
VCC-1.3V
IO1
26
IO2 CTEST A0 I/O Logic A1 D0 D1 D2 D3 D4 D5 D6 D7 RESN DIV Chn DIV Cln DIV Bhn DIV Bln Low Voltage Thermal Shutdown GNDD 12 GNDS 13 I/O Logic Input/Output Stage 7 higher nibble COM I/O Logic Input/Output Stage 6 I/O Logic Input/Output Stage 5 IO6 GND67 IO7 Input/Output Stage 3 lower nibble IO4 Input/Output Stage 4 GND45 IO5 I/O Logic Input/Output Stage 2 GND23 IO3
27 28 29
iC-VRV
I/O Logic
17 18 19
20 21 22
23
Control Register
Interrupt
Bias
Frequency Divider INTN 11 CLK 10 BLFQ 9 GNDA 16
PLCC44
Copyright (c) 2003, 2009 iC-Haus
www.ichaus.com
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 2/12 DESCRIPTION iC-VRV is an 8-fold low-side driver with integrated control logic which is divided internally into two mutually independent blocks (nibbles). In the input mode, ports IO0 to IO7 can be used to record logical levels. In this process, a programmable pull-down current (200 A or 2 mA) sets a defined level and functions as the biasing current for switching contacts. The stages programmed as outputs can drive any desired loads (e. g. lamps, long cables, relays) at a continuous current of 100 mA or 500 mA in pulse operation. The free-wheeling currents created upon each stage turn-off are discharged through the integrated free-wheeling diodes to a voltage applied externally to the COM pin; a circuit with a Zener diode is also possible. In the event of a short circuit, a protective circuit breaker ensures that the output stage affected does not just simply switch off but is instead clocked as a function of the load. As a result, the current assumes a low average value. The output stage is ready for operation immediately just as soon as the cause of the short circuit has been eliminated. The shutdown at overtemperature protects the IC against thermal destruction by causing the output stages to turn off and the pull-down currents to be reduced from 2 mA to 200 A. This shutdown is also triggered in case of undervoltage at VCC. Due to the microprocessor interface the iC-VRV can be operated directly on a bus system. The interface consists of the data bits D0 to D7 and the associated control signals A0, A1, CSN, WRN and RDN. The signal CLK clocks the implemented digital input filter and BLFQ clocks the programmed flashing function. In the event of a signal change of the I/O pins programmed as inputs, an interrupt signal can be generated at output INTN. Activating the input RESN resets the initial condition. Chip programming is conducted via four addresses at A0 and A1. During this programming, presettings for flashing frequencies, filtering times, interrupt control, pull-down currents and input/output mode, etc. are stored in two registers (CONTROL WORD1+2). All inputs and outputs are protected with diodes against destruction due to ESD.
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 3/12 PACKAGES PLCC44 to JEDEC Standard PIN CONFIGURATION PLCC44 (top view)
PIN FUNCTIONS PLCC44 No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Name
D3 A0 A1 CSN n.c. WRN RDN RESN BLFQ CLK INTN GNDD n.c. n.c. n.c. GNDA IO4 GND45 IO5 IO6 GND67 IO7
Function
B I I I I I I I I O
Description
Bus Data Bit 3 Address Address Chip Select Write Enable Read Enable Reset Clock, flashing function Clock, filter function Interrupt Report Digital Ground
No.
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39(*) 40 41(*) 42 43 44(x)
Name
COM IO0 GND01 IO1 IO2 GND23 IO3 VCCA n.c. n.c. n.c. VCCD D4 D5 D6 D7 CTEST D0 ENERR D1 D2 CERR
Function
B B B B
Description
Diodes, common cathode I/O Stage 0 Ground Stage 0+1 I/O Stage 1 I/O Stage 2 Ground Stage 2+3 I/O Stage 3 +5 V Supply (analog section)
B B B B
Analog Ground I/O Stage 4 Ground Stage 4+5 I/O Stage 5 I/O Stage 6 Ground Stage 6+7 I/O Stage 7
B B B B B B B
+5 V Supply (digital section) Bus Data Bit 4 Bus Data Bit 5 Bus Data Bit 6 Bus Data Bit 7 Bus Data Bit 0 Bus Data Bit 1 Bus Data Bit 2
*: pin needs external wiring to Ground x: pin should left open Function: I = Input, O = Output, B = bidirectional
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 4/12 PROGRAMMING
Selection of functions Data Word D7..D0 higher nibble Selected I/O Stage function: Address A1 0 0 1 1 A0 0 1 0 1 Write
Test Pattern IR Enable Control Word 2 Control Word 1
lower nibble
Input Read
IR Inputs IR Enable
Output Write
Outputs
Input Write
Test Pattern
Output Write
Outputs
Read
Outputs
Read
IR Inputs IR Enable
Read
Outputs
Pulse Enable Pulse Enable IR Enable Control Word 2 Control Word 1 Feedback I/O Stages Control Word 1 Control Word 2 Control Word 1
Pulse Enable Pulse Enable Control Word 2 Control Word 1 Feedback I/O Stages Control Word 1
Inputs Control Word 1
Inputs Control Word 1
Reading the inputs or the output feedback (IO7..0 to D7..0) I/O stage with input function: A high level at IOx generates a high signal at Dx (selection of functions: read inputs) during the course of the digital hysteresis. I/O stage with output function: A high level at IOx generates a low signal at Dx (selection of functions: read feedback of the outputs). The inversion while reading back the outputs (I/O stage with output function) occurs so that the same signal is applied to Dx as was programmed for switching the output stage on or off, for example: switching on the final stage with Dx = high results in low level at IOx. After the digital hysteresis ends, Q becomes low, the microprocessor interface inverts this message and a high signal can be read back via Dx. The microprocessor can check the output state in this manner. Test The test circuit consists of registers which can be set via the microprocessor interface (test pattern). Its content is applied via constantly active OR gates to the counting direction inputs UP/DOWN (D7..0 to UP/DOWN7..0). In response to a reset (low signal at RESN) the registers are set to low; as a result, there is no effect on the UP/DOWN inputs. In the test mode (control word 2, bit 2 and 6 at high) the comparators of the I/O stages are switched off and only the test registers continue to operate the UP/DOWN inputs. Any desired input signals can be entered to test all digital functions; the microprocessor can also conduct a system test in this manner. Interrupt enable The interrupt generation can be activated separately for every I/O stage with input function. The interrupt enable is programmed via the data word DO..7 (function selection IR enable: 1 = stage relevant, 0 = stage not relevant). If a signal change is recognized for an I/O stage with input function - after the digital hysteresis due to change at Qx - and if this stage is enabled for interrupt generation, this is indicated with INTN = low. The interrupt message as well as the interrupt register which shows the stages with signal changes are reset via control word 2 (writing bit 0 = 1 is sufficient; bit 0 = 0 is set by the chip automatically).
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 5/12 Signal changes which would be relevant for an interrupt generation could occur in the read-out phase following an interrupt message. These signal changes are lost when the interrupt register is deleted. As an alternative, the read-out of the interrupt register is possible (functional selection: read IR inputs). The registers can then be reset separately by blocking the IR enable for each reporting stage singly and then releasing it (functional selection: IR enable).
Filter periods The input comparator of each I/O stage switches the counting direction of a 3 bit counter. The counter output Q does not change until the final status is reached (to high for high level at IOx, to low for low level at IOx if constantly applied during the filter period). The counter is clocked externally (pin CLK); the divisor for the clock frequency can be programmed separately for both nibbles. A low signal at reset input RESN resets the counters to the value 3. Due to the digital hysteresis, the change of an input signal is therefore not recognized until the selected filter period has elapsed.
Pulse enable and pulse times The flashing or pulsing function can be switched on separately for each I/O stage with output function. The programming of the divisors for the flashing frequency input BLFQ (control word 1, bits 0,1 and 4,5) is conducted for each nibble. The clock signal at BLFQ is transfered with the slope of CLK (synchronized). For this reason the clock frequency for CLK must be higher than the clock frequency for BLFQ, e. g. 2 MHz for CLK and 50 Hz for BLFQ.
Control Word 1 higher nibble Bit Name 7 FH0 6 FH1 5 PH0 4 PH1 lower nibble 3 FL0 2 FL1 1 PL0 0 PL1
Control Word 1 (lower nibble) Filtering Time Bit 3 FLO 0 1 0 1 Bit 2 FL1 0 0 1 1 14.5 * CLK 896.5 * CLK 3584.5 * CLK 7168.5 * CLK 1 * CLK 64 * CLK 256 * CLK 512 * CLK Flashing Pulse Duration Bit 1 PLO 0 1 0 1 Bit 0 PL1 0 0 1 1 BLFQ BLFQ * 2 BLFQ * 4 BLFQ * 16
Control Word 1 (higher nibble) Filtering Time Bit 7 FHO 0 1 0 1 Bit 6 FH1 0 0 1 1 14.5 * CLK 896.5 * CLK 3584.5 * CLK 7168.5 * CLK 1 * CLK 64 * CLK 256 * CLK 512 * CLK Flashing Pulse Duration Bit 5 PHO 0 1 0 1 Bit 4 PH1 0 0 1 1 BLFQ BLFQ * 2 BLFQ * 4 BLFQ * 16
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 6/12 Control Word 2 higher nibble Bit Name 7 NIOH 6 TSTH 5 IBH 4 not used lower nibble 3 NIOL 2 TSTL 1 IBL 0 EOI
Control Word 2 (lower nibble) Interrupt Bit 0 (EOI) 0 1 Interrupt is not cancelled Clearing Interrupt
Current Sources at I/O Pins Bit 1 (IBL) Test Bit 2 (TSTL) 0 1 Feedback of I/O stages active (OR gated with test pattern) Test pattern activated, feedback of I/O stages switched off 0 1 Pull-Down Current 200 A Pull-Down Current 2 mA
Input/Output Mode Bit 3 (NIOL) 0 1 Input Mode Output Mode
Control Word 2 (higher nibble) Bit 4 not used
Current Source at I/O Pins Bit 5 (IBH) Test Bit 6 (TSTH) 0 1 Feedback of I/O stages active (OR gated with test pattern) Test pattern activated, feedback of I/O stages switched off 0 1 Pull-Down Current 200 A Pull-Down Current 2 mA
Input/Output Mode Bit 7 (NIOH) 0 1 Input Mode Output Mode
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 7/12 ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed. Absolute Maximum Ratings are no Operating Conditions. Integrated circuits with system interfaces, e.g. via cable accessible pins (I/O pins, line drivers) are per principle endangered by injected interferences, which may compromise the function or durability. The robustness of the devices has to be verified by the user during system development with regards to applying standards and ensured where necessary by additional protective circuitry. By the manufacturer suggested protective circuitry is for information only and given without responsibility and has to be verified within the actual system with respect to actual interferences. Item Symbol Parameter Supply Voltage Voltage at COM Voltage at IOx IOx= lo (* see below)
Conditions
Fig. Min. Max. 6 49 49 0 -0.3 -0.3 -0.3 -500 2 -1000 -1.3 -1
Unit V V V mA mA A mA 600 mA A 49 26 49 50 20 V V V mA mA
G001 VCCA VCCD G201 V(COM) G202 Vact(IO)
G203 Idc(COM) Current in COM G204 Ipk(COM) Peakcurrent in COM G205 Isc(COM) Free-Wheeling Current in COM G206 Idc(COM) Current in IOx G207 Ipk(IOx) G208 Ipsc (Iox) G301 V(IOx) G302 V(IOx) Peakcurrent in IOx Peakcurrent in IOx Voltage at IO0..3, IO4..7 Voltage at IO0..3, IO4..7 IOx= lo, = 2ms, T$ 2s IOx= lo, Overload current protection IBL= 0, IBH= 0 (current source 200A) IBL= 1, IBH= 1 (current source 2mA)
= 2ms, T$ 2s
2
-1 -1.3 -0.3 -0.3
G401 Imx (VCCD) G402 Ic()
Current in VCCD, GNDD Current in Clamping Diodes at CSN, WRN, RDN, A0, A1, D0..7, RESN, CLK, BLFQ Current in D0..7,INTN Peakcurrent in CSN, WRN, RDN, A0, A1, D0..7, RESN, CLK, BLFQ, INTN (Latch-Up Strength) ESD Susceptibility, all Inputs and Outputs Junction Temperature Storage Temperature D0..7 set to inputs
G402 I() G404 Ilu()
D0..7 set to outputs pulse duration # 10s -100
EG1 Vd() TG1 Tj TG2 Ts
HBM 100pF discharged through 1.5k
(*) IOx= lo : pin set to output, active low, x 0 0..7
THERMAL DATA
Operating Conditions: VCC= VCCA= VCCD= 5V 10% Item T1 T2 Symbol Ta Rthja Parameter Operating Ambient Temperature Range Thermal Resistance Chip to Ambient PLCC44 surface mounted on PCB Conditions Fig. Min. 0 55 Typ. Max. 70 EC K/W Unit
All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative.
= 2ms, T$ 2s
-0.3 -50 -20
25 100
mA mA
2 -40 -40 150 150
kV EC EC
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 8/12 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC= VCCA= VCCD= 5V 10%, Tj= 0..125 unless otherwise noted C, Item Symbol Parameter Conditions Tj C Total Device 001 VCCA VCCD 002 I(VCCA) Permissible Supply Voltage Range Supply Current in VCCA, power section IO0..7= lo, unloaded 0 27 70 125 4.5 5 5 5 5 0 80 100 5.5 65 60 55 55 10 V mA mA mA mA mA mA mA Fig. Min. Typ. Max. Unit
003 I(VCCD) Supply Current in VCCD, digital section 004 I(VCCD) Supply Current in VCCD, digital section 005 I(VCCD) Supply Current in VCCD, digital section 101 VCCon 102 VCCoff 103 VCChys 104 Toff 105 Thys Turn-on Threshold VCC Undervoltage Threshold at VCC Hysteresis Thermal Shutdown Threshold Thermal Shutdown Hysteresis
all logic inputs lo= 0V or hi= VCC all logic inputs lo= 0.8V all logic inputs lo= 2.0V
Bias, Thermal Shutdown and Low Voltage Detection 3.6 decreasing Supply VCC VCChys= VCCon-VCCoff Thys= Toff - Ton V(COM)= 25V, V(IOx)= 0V Vf()= V(IOx)-V(COM); I(IOx6COM)= 100mA, IOx= hi or set to Inputs I(IOx)= 10mA, IO0..7= lo I(IOx)= 100mA, IO0..7= lo I(IOx)= 500mA, IO0..7= lo, = 2ms, T$ 2s IOx= lo, V(IOx)= 0..25V IOx= lo, V(IOx)= 0..25V depends on Load IOx= lo, V(IOx)= 0..25V
4 3.9 100 135 8
4.4 4.3 250 150 12 100
V V mV EC EC
3.5 40 120 4
I/O Stages: Low-side Driver 201 Ilk(COM) Leakage Current in COM 202 Vf(COM) Forward Voltage of the FreeWheeling Diodes 203 Vs(IO) 204 Vs(IO) 205 Vs(IO) 206 Ioff(IO) 207 Ion(IO) 208 f(IO) 209 Iav(IO) Saturation Voltage lo at IOx Saturation Voltage lo at IOx Saturation Voltage lo at IOx for pulse load Threshold Current in IOx for Overcurrent Cut-off Free-Wheeling Current I(IOx6COM) for Cut-off release Cut-off Oscillation Frequency Mean Current in IOx during Cut-off A V 0.5 1.5
1 1 1 0.5 0.1 0.1 50
0.4 0.6 1.5 1.3 20 20 700
V V V A mA MHz mA
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 9/12 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC= VCCA= VCCD= 5V 10%, Tj= 0..125 unless otherwise noted C, Item Symbol Parameter Conditions Tj C I/O Stages: Comparator 301 Idwn(IO) Pull-down Current in IOx 302 Idwn(IO) Pull-down Current in IOx 303 V0(IO) 304 Vt()hi 305 Vt()lo 401 Ilk(Dx) 402 Ilk(Dx) Open-Circuit Voltage at IOx Threshold Voltage hi at IOx Threshold Voltage lo at IOx Leakage Current in Dx Leakage Current in Schmitt Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ Threshold Voltage hi at Schmitt D0..7 set to Inputs Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7 Threshold Voltage lo at Schmitt D0..7 set to Inputs Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7 Hysteresis at Schmitt Trigger Vt()hys= Vt()hi-Vt()lo; Inputs CSN, WRN, RDN, A0, A1, D0..7 set to Inputs RESN, CLK, BLFQ, D0..7 Saturation Voltage hi at INTN Saturation Voltage hi at INTN Saturation Voltage lo at INTN Saturation Voltage lo at INTN Vs()hi= VCCD-V(INTN); INTN=hi, I(INTN)= -100A Vs()hi= VCCD-V(INTN); INTN=hi, I(INTN)= -2mA INTN= lo, I(INTN)= 100A INTN= lo, I(INTN)= 2mA Vs(Dx)hi= VCCD-V(Dx); Dx= hi, I(Dx)= -100A Vs(Dx)hi= VCCD-V(Dx); Dx= hi, I(Dx)= -4mA Dx= lo, I(Dx)= 100A Dx= lo, I(Dx)= 4mA 0.4 0.7 D0..7 set to Inputs 3 -5 -1 5 1 V(IOx)= 3..48V, IBL= 0, IBH= 0, IO0..7= hi or set to Inputs V(IOx)= 3..25V, IBL= 1, IBH= 1, IO0..7= hi or set to Inputs IOx open, IO0..7= hi or set to Inputs 120 1.4 200 2 280 2.6 1 4.6 A mA V V V A A Fig. Min. Typ. Max. Unit
P-Interface, I/O-Logic, Frequency Divider, Interrupt
403 Vt()hi
2.3
V
404 Vt()lo
V
405 Vt()hys
0.3
V
406 Vs()hi 407 Vs()hi 408 Vs()lo 409 Vs()lo
0.2 0.8 0.2 0.49 0.2 0.8 0.2 0.49 2.5
V V V V V V V V V
410 Vs(Dx)hi Saturation Voltage hi at Dx 411 Vs(Dx)hi Saturation Voltage hi at Dx 412 Vs(Dx)lo Saturation Voltage lo at Dx 413 Vs(Dx)lo Saturation Voltage lo at Dx 414 Vc()hi
Clamp Voltage hi at Vc()hi= V()-VCC, CSN, WRN, RDN, A0, A1, RESN, I()= 20mA CLK,BLFQ, D0..7, INTN, CERR Clamp Voltage lo at I()= -20mA CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7, INTN, CERR
415 Vc()lo
-1.8
-0.4
V
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 10/12 ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC= VCCA= VCCD= 5V 10%, Tj= 0..125 unless otherwise noted C, Item Symbol Parameter Conditions Tj C Switching Characteristics 501 tc(CLK) 502 tw(CLK) Permissible Cycle Duration CLK Permissible Pulse Width lo at CLK 400 200 100 50 Write Cycle, WRN: hi6lo Write Cycle, WRN: hi6lo Write Cycle, WRN: hi6lo Write Cycle, WRN: hi6lo 2 3 5 5 5 ns ns ms ms s s s s s Fig. Min. Typ. Max. Unit
503 tc(BLFQ) Permissible Cycle Duration BLFQ 504 tw(BLFQ) Permissible Pulse Width lo at BLFQ 505 tphl() 506 tplh() 507 tp()Ion 508 tp()Ioff 509 tp(IOx6 up/dwn) Propagation Delay until IOx= lo Propagation Delay until IOx= off Current Source Enable Time at IOx Current Source Disable Time at IOx Propagation Delay Input IOx to Up/Dwn Filter Input
ELECTRICAL CHARACTERISTICS: WAVEFORMS
I
IOxpeak
IOxdc
T
t
Figure 1: DC load
Figure 2: Pulse load, Pulse duration 2 ms
iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 11/12 OPERATING REQUIREMENTS: P INTERFACE
Operating Conditions: VCC= VCCA= VCCD= 5V 10%, Ta= 0..70EC, CL()= 150pF, input levels lo= 0..0.45V, hi= 2.4V..VCC, see Fig. 3 for reference levels and waveforms Item Symbol Parameter Conditions Fig. Min. Data Word Read Timing I1 I2 I3 I4 I5 tAR tRA tRD tDF tRW Setup Time: CSN, A0, A1 set before RDN hi6lo Hold Time: CSN, A0, A1 stable after RDN lo6hi Read Data Access Time: Data valid after RDN hi6lo Read Data Hold Time: Ports high impedance after RDN lo6hi Recovery Time between Read/Write Cycles Setup Time: CSN, A0, A1 set before WRN hi6lo Write Data Setup Time: Data valid before WRN lo6hi Hold Time: CSN, A0, A1 stable after WRN lo6hi Write Data Hold Time: Data valid after WRN lo6hi 4 4 4 4 4 165 30 10 120 65 ns ns ns ns ns Max. Unit
Data Word Write Timing I6 I7 I8 I9 tAW tDW tWA tWD 4 4 4 4 30 100 10 10 ns ns ns ns
Figure 3: Reference levels
Figure 4: Data word read/write timing
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iC-VRV
BIDIRECTIONAL P INTERFACE TO 24V
Rev A2, Page 12/12 ORDERING INFORMATION
Type iC-VRV
Package PLCC44
Order designation iC-VRV PLCC44
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