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ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Data Sheet August 7, 2008 FN9124.10
Improved Industry Standard Single-Ended Current Mode PWM Controller
The ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 family of adjustable frequency, low power, pulse width modulating (PWM) current mode controllers is designed for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Peak current mode control effectively handles power transients and provides inherent overcurrent protection. This advanced BiCMOS design is pin compatible with the industry standard 384x family of controllers and offers significantly improved performance. Features include low operating current, 60A start-up current, adjustable operating frequency to 2MHz, and high peak current drive capability with 20ns rise and fall times.
PART NUMBER ISL6840 ISL6841 ISL6842 ISL6843 ISL6844 ISL6845 RISING UVLO (V) MAX. DUTY CYCLE (%) 7.0 7.0 14.4 8.4 14.4 8.4 100 50 100 100 50 50
Features
* 1A MOSFET Gate Driver * 60A Start-up Current, 100A Maximum * 25ns Propagation Delay Current Sense to Output * Fast Transient Response with Peak Current Mode Control * Adjustable Switching Frequency to 2MHz * 20ns Rise and Fall Times with 1nF Output Load * Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control * High Bandwidth Error Amplifier * Tight Tolerance Voltage Reference Over Line, Load, and Temperature * Tight Tolerance Current Limit Threshold * Pb-Free Available (RoHS Compliant)
Applications
* Telecom and Datacom Power * Wireless Base Station Power * File Server Power * Industrial Power Systems
Pinouts
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 (8 LD SOIC, MSOP) TOP VIEW
COMP 1 FB 2 CS 3 RTCT 4 8 VREF 7 VDD 6 OUT 5 GND
* PC Power Supplies * Isolated Buck and Flyback Regulators * Boost Regulators
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 (8 LD DFN) TOP VIEW
COMP FB CS RTCT VREF VDD OUT GND
1 2 3 4
8 7 6 5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Ordering Information
PART NUMBER ISL6840IB* ISL6840IBZ* (Note) ISL6840IRZ-T (Note) ISL6840IU* ISL6840IUZ* (Note) ISL6841IB* ISL6841IBZ* (Note) ISL6841IRZ-T (Note) ISL6841IU* ISL6841IUZ* (Note) ISL6842IB* ISL6842IBZ* (Note) ISL6842IRZ-T (Note) ISL6842IU* ISL6842IUZ* (Note) ISL6843IB* ISL6843IBZ* (Note) ISL6843IRZ-T (Note) ISL6843IU* ISL6843IUZ* (Note) ISL6844IB* ISL6844IBZ* (Note) ISL6844IRZ-T (Note) ISL6844IU* ISL6844IUZ* (Note) ISL6845IB* ISL6845IBZ* (Note) ISL6845IRZ-T (Note) ISL6845IU* ISL6845IUZ* (Note) PART MARKING ISL 6840IB 6840 IBZ 40Z 6840 6840Z ISL 6841IB 6841 IBZ 41Z 6841 6841Z ISL 6842IB 6842 IBZ 42Z 6842 6842Z ISL 6843IB 6843 IBZ 43Z 6843 6843Z ISL 6844IB 6844 IBZ 44Z 6844 6844Z ISL 6845IB 6845 IBZ 45Z 6845 6845Z TEMP RANGE (C) -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 -40 to +105 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld 2x3 DFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) PKG. DWG. # M8.15 M8.15 L8.2x3 M8.118 M8.118 M8.15 M8.15 L8.2x3 M8.118 M8.118 M8.15 M8.15 L8.2x3 M8.118 M8.118 M8.15 M8.15 L8.2x3 M8.118 M8.118 M8.15 M8.15 L8.2x3 M8.118 M8.118 M8.15 M8.15 L8.2x3 M8.118 M8.118
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. Contact Factory for Availability NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN9124.10 August 7, 2008
Functional Block Diagram
VDD UVLO COMPARATOR ENABLE + BG + VDD OK
VREF 5.00V
VREF
VREF FAULT
-
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
+ VREF UV COMPARATOR 4.65V 4.80V
A 2.5V A = 0.5
BG
PWM COMPARATOR CS + + -
100mV
ERROR AMPLIFIER FB + -
2R
1.1V CLAMP R
ISL6841/ISL6844/ISL6845 ONLY Q T Q
COMP OUT VREF 2.6V 0.7V ON OSCILLATOR COMPARATOR + 8.4mA
FN9124.10 August 7, 2008
SQ RQ RESET DOMINANT
RTCT
CLOCK P/N -40, -41 -42, -44 -43, -45 UVLO ON/OFF 7.0/6.6V 14.3/8.8V 8.4/7.2V
ON
+ -
3
GND
Typical Application - 48V Input Dual Output Flyback
CR5 +3.3V T1 VIN+ C4 R3 C2 C5 CR6 36V TO 75V C1 R1 C6 C3 Q1 R16 U2 R17 R19 C14 R18 C17 CR4 + C22 + C21 R21 +1.8V + C15 + C16
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
CR2
C19
C20 RETURN
4
VINR6 Q3 VR1
FN9124.10 August 7, 2008
R4
R22 U3 R27
C13
R15
R20 U4 R26 COMP CS FB VREF V DD OUT
RTCT GND ISL684x
R10 CR1
C12 C8 R13 C11
Typical Application - Boost Converter
R8 C10
CR1 VIN+ L1 +VOUT
+ C2 C3
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
5
Q1 R4 RETURN R5 C9 C1 R1 R2 U1 COMP ISL684x FB C4 CS RTCT VREF VDD OUT GND R7 C8 VIN+ R6 R3 C5 C7 C6 VINFN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) DFN Package (Notes 1, 2) . . . . . . . . . . 77 6 SOIC Package (Note 1) . . . . . . . . . . . . 100 N/A MSOP Package (Note 1) . . . . . . . . . . . 130 N/A Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL684xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C Supply Voltage Range (Typical, Note 3) ISL6840, ISL6841. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V to 14V ISL6843, ISL6845. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 16V ISL6842, ISL6844. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" and "Typical
Application" schematic on pages 3 and 4. VDD = 15V (Note 6), Rt = 10k, Ct = 3.3nF, TA = -40 to +105C Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER UNDERVOLTAGE LOCKOUT START Threshold (ISL6840, ISL6841) START Threshold (ISL6843, ISL6845) START Threshold (ISL6842, ISL6844) STOP Threshold (ISL6840, ISL6841) STOP Threshold (ISL6843, ISL6845) STOP Threshold (ISL6842, ISL6844) Hysteresis (ISL6840, ISL6841) Hysteresis (ISL6843, ISL6845) Hysteresis (ISL6842, ISL6844) Start-up Current, IDD Operating Current, IDD Operating Supply Current, ID REFERENCE VOLTAGE Overall Accuracy Long Term Stability Fault Voltage VREF Good Voltage Hysteresis Current Limit, Sourcing Current Limit, Sinking CURRENT SENSE Input Bias Current CS Offset Voltage COMP to PWM Comparator Offset Voltage Input Signal, Maximum VCS = 1V VCS = 0V (Note 5) VCS = 0V (Note 5) -1.0 95 0.80 0.91 100 1.15 0.97 1.0 105 1.30 1.03 A mV V V Over line (VDD = 12V to 18V), load, temperature TA = +125C, 1000 hours (Note 5) 4.925 4.40 4.60 50 -20 5 5.000 5 4.65 4.80 165 5.050 4.85 VREF - 0.05 250 V mV V V mV mA mA VDD < START Threshold (Note 4) Includes 1nF GATE loading 6.5 7.8 13.3 6.1 6.7 8.0 7.0 8.4 14.3 6.6 7.2 8.8 0.4 0.8 5.4 60 3.3 4.1 7.5 9.0 15.3 6.9 7.7 9.6 100 4.0 5.5 V V V V V V V V V A mA mA TEST CONDITIONS MIN TYP MAX UNITS
6
FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" and "Typical
Application" schematic on pages 3 and 4. VDD = 15V (Note 6), Rt = 10k, Ct = 3.3nF, TA = -40 to +105C Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER Gain, ACS = VCOMP/VCS CS to OUT Delay ERROR AMPLIFIER Open Loop Voltage Gain Unity Gain Bandwidth Reference Voltage FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR OSCILLATOR Frequency Accuracy Frequency Variation with VDD Temperature Stability Amplitude, Peak-to-Peak RTCT Discharge Voltage Discharge Current OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time PWM Maximum Duty Cycle ISL6840, ISL6842, ISL6843 ISL6841, ISL6844, ISL6845 Minimum Duty Cycle ISL6840, ISL6842, ISL6843 ISL6841, ISL6844, ISL6845 NOTES: 4. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 5. Limits established by characterization and are not production tested. 6. Adjust VDD above the start threshold and then lower to 15V. 94 47 96 48 0 0 % % % % VDD to OUT, IOUT = -200mA OUT to GND, IOUT = 200mA COUT = 1nF (Note 5) COUT = 1nF (Note 5) COUT = 1nF (Note 5) 1.0 1.0 1.0 20 20 2.0 2.0 40 40 V V A ns ns RTCT = 2.0V Initial, TJ = +25C T = +25C (f18V - f12V)/f12V (Note 5) 49 7.2 52 0.2 1.9 0.7 8.4 55 1.0 5 9.5 kHz % % V V mA (Note 5) (Note 5) VFB = VCOMP VFB = 0V VCOMP = 1.5V, VFB = 2.7V VCOMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz, VDD = 12V to 18V (Note 5) 60 3.5 2.475 -1.0 1.0 -0.4 4.80 0.4 60 90 5 2.514 -0.2 80 2.55 1.0 VREF 1.0 dB MHz V A mA mA V V dB TEST CONDITIONS 0 < VCS < 910mV, VFB = 0V (Note 5) (Note 5) MIN 2.5 TYP 3.0 25 MAX 3.5 40 UNITS V/V ns
7
FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Typical Performance Curves
1.02 NORMALIZED FREQUENCY 1.01 1.00 0.99 0.98 0.97 -40 1.001 1.000 NORMALIZED VREF -10 20 50 80 110 0.999 0.998 0.997 0.996 0.995 -40 -25
-10
5
20
35
50
65
80
95 110
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
1.002 NORMALIZED EA REFERENCE
103
FREQUENCY (kHz)
1.000
100pF 100 220pF 330pF 470pF 1.0nF 10 2.2nF 3.3nF 4.7nF
0.998
0.996
0.994 -40 -25 -10
5
20
35
50
65
80
95
110
1 10 20 30 40 50 60 RT (k) 70 80 90 100
TEMPERATURE (C)
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
Pin Descriptions
RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax, can be calculated from Equations 1, 2, 3 and 4:
t C 0.583 * RT * CT (EQ. 1)
COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f,
0.0083 * RT - 4.3 t D - RT * CT * ln ---------------------------------------------- 0.0083 * RT - 2.4
(EQ. 2)
f = 1 (tC + tD)
D=t C *f
(EQ. 3) (EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency.
8
FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
and the MOSFET gate charge, Qg, the average output current can be calculated in Equation 5:
I OUT = Qg x f (EQ. 5)
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. The minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. Adding excessive slope compensation, however, results in a control loop that behaves more as a voltage mode controller than as a current mode controller.
CS SIGNAL (V) DOWNSLOPE CURRENT SENSE SIGNAL
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 3.3F capacitor to filter this output as needed.
Functional Description
Features
The ISL684x current mode PWMs make an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating.
Oscillator
The ISL684x family of controllers have a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency.)
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
Slope compensation may be added to the CS signal shown in Figure 7.
Soft-Start Operation
Soft-start must be implemented externally. One method, illustrated in Figure 5, clamps the voltage on COMP.
RTCT ISL684x
VREF
CS VREF ISL684x
COMP
GND
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
FIGURE 5. SOFT-START
A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled.
Gate Drive
The ISL684x family are capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors.
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FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
4X L L1
e E L
0.026 BSC
0.65 BSC
A
A2
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 8 0.003 0.003 5o 0o 15o 6o
0.95 REF 8 0.07 0.07 5o 0o
C a C L E1
C
R1 0
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
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FN9124.10 August 7, 2008
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845 Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.80 -
NOMINAL 0.90 0.20 REF
MAX 1.00 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40 8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9124.10 August 7, 2008

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