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Integer-N Clock Translator for Wireline Communications AD9550
FEATURES
Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS) Preset pin-programmable frequency translation ratios On-chip VCO Single-ended CMOS reference input Two output clocks (independently programmable as LVDS, LVPECL, or CMOS) Single supply (3.3 V) Very low power: <450 mW (under most conditions) Small package size (5 mm x 5 mm) Exceeds Telcordia GR-253-CORE jitter generation, transfer and tolerance specifications
BASIC BLOCK DIAGRAM
REF
PLL
OUTPUT CIRCUITRY
OUT2 OUT1
PIN DECODER
09057-001
AD9550
Figure 1.
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Flexible frequency translation for wireline applications such as Ethernet, T1/E1, SONET/SDH, GPON, xDSL Wireless infrastructure Test and measurement (including handheld devices)
GENERAL DESCRIPTION
The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input. The AD9550 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The AD9550 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9550 is implemented in a strictly CMOS process. The AD9550 operates over the extended industrial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9550 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Basic Block Diagram ........................................................................ 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Output Characteristics ................................................................. 4 Jitter Characteristics ..................................................................... 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Input/Output Termination Recommendations .......................... 11 Theory of Operation ...................................................................... 12 Overview ..................................................................................... 12 Preset Frequencies ...................................................................... 12 Description of Functional Blocks............................................. 15 Jitter Tolerance ............................................................................ 16 Low Dropout (LDO) Regulators .............................................. 16 Automatic Power-On Reset ...................................................... 16 Applications Information .............................................................. 17 Thermal Performance ................................................................ 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
8/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD9550 SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD = 3.3 V; TA = 25C, unless otherwise noted. Table 1.
Parameter SUPPLY VOLTAGE POWER CONSUMPTION Total Current VDD Current By Pin Pin 18 Pin 21 LVDS Configured Output LVPECL Configured Output CMOS Configured Output Pin 28 LVDS Configured Output LVPECL Configured Output CMOS Configured Output LOGIC INPUT PINS Input Characteristics 1 Logic 1 Voltage, VIH Logic 0 Voltage, VIL Logic 1 Current, IIH Logic 0 Current, IIL LOGIC OUTPUT PINS Output Characteristics Output Voltage High, VOH Output Voltage Low, VOL RESET Pin Input Characteristics2 Input Voltage High, VIH Input Voltage Low, VIL Input Current High, IINH Input Current Low, IINL Minimum Pulse Width Low REFERENCE CLOCK INPUT CHARACTERISTICS CMOS Single-Ended Input Input Frequency Range Input High Voltage Input Low Voltage Input Threshold Voltage Input High Current Input Low Current Input Capacitance Duty Cycle Pulse Width Low Pulse Width High 2 2 Min 3.135 Typ 3.30 Max 3.465 Unit V Test Conditions/Comments Pin 18, Pin 21, and Pin 28 Tested with both output channels active at maximum output frequency; LVPECL and LVDS outputs use a 100 termination between both pins of the output driver
162 93 35 36 29 35 36 29
185 106 41 42 34 41 42 34
mA mA mA mA mA mA mA mA
1.02 0.64 3 17
V V A A
For the CMOS inputs, a static Logic 1 results from either a pull-up resistor or no connection
Tested at 1 mA load current 2.7 0.19 V V
1.96 0.3 31 150 0.85 12.5 43
V V A A s
Tested with an active source driving the RESET pin
0.008 1.62 1.0 0.04 0.03 3
200 0.52
MHz V V V A A pF
When ac coupling to the input receiver, the user must dc bias the input to 1 V
Pulse width high and pulse width low establish the bounds for duty cycle ns ns
Rev. 0 | Page 3 of 20
AD9550
Parameter x2 Frequency Multiplier Min Typ Max 125 Unit MHz Test Conditions/Comments To avoid excessive reference spurs, the x2 multiplier requires 48% to 52% duty cycle; reference clock input frequencies greater than 125 MHz require the use of the divide-by-5 prescaler
VCO CHARACTERISTICS Frequency Range VCO Gain VCO Tracking Range PLL Lock Time
3350 45 300
4050
MHz MHz/V ppm Using the pin selected frequency settings; lock time is from the rising edge of the RESET pin to the rising edge of the LOCKED pin Applies for Pin A3 to Pin A0 = 0001 to 1100, or for Pin A3 to Pin A0 = 1111
Low Bandwidth Setting (170 Hz) 13.3 kHz PFD Frequency 16 kHz PFD Frequency Medium Bandwidth Setting (20 kHz) 1.5625 MHz PFD Frequency High Bandwidth Setting (75 kHz) 2.64 MHz PFD Frequency 4.86 MHz PFD Frequency
1
214 176
ms ms Applies for Pin A3 to Pin A0 = 1110 and Pin Y5 to Pin Y0= 111111
2
ms Applies for Pin A3 to Pin A0 = 1101 to 1110
1.50 0.89
ms ms
2
The A3 to A0 and Y5 to Y0 pins have 100 k internal pull-up resistors. The OM2 to OM0 pins have 40 k pull-up resistors. The RESET pin has a 100 k internal pull-up resistor.
OUTPUT CHARACTERISTICS
Table 2.
Parameter LVPECL MODE Differential Output Voltage Swing Common-Mode Output Voltage Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) LVDS MODE Differential Output Voltage Swing Balanced, VOD Unbalanced, VOD Offset Voltage Common Mode, VOS Common-Mode Difference, V OS Short-Circuit Output Current Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) Min 690 Typ 800 Max 890 VDD - 1.01 810 60 305 Unit mV V MHz % ps Test Conditions/Comments Output driver static (for dynamic performance see Figure 15) Output driver static Up to 805 MHz output frequency 100 termination between both pins of the output driver Output driver static (for dynamic performance see Figure 15) Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static Output driver static Voltage difference between output pins; output driver static
VDD - 1.66 VDD - 1.34 0 40 255
297
398 8.3
mV mV
1.17
1.35 7.3 17 24 810 60 355
V mV mA MHz % ps
0 40 285
Up to 805 MHz output frequency 100 termination between both pins of the output driver
Rev. 0 | Page 4 of 20
AD9550
Parameter CMOS MODE Output Voltage High, VOH IOH = 10 mA IOH = 1 mA Output Voltage Low, VOL IOL = 10 mA IOL = 1 mA Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%)
1
Min
Typ
Max
Unit
Test Conditions/Comments Output driver static
2.8 2.8 0.5 0.3 200 55 745
V V Output driver static V V MHz % ps
0 45 500
3.3 V CMOS; output toggle rates in excess of the maximum are possible, but with reduced amplitude (see Figure 14) At maximum output frequency 3.3 V CMOS; 10 pF load
The listed values are for the slower edge (rise or fall).
JITTER CHARACTERISTICS
Table 3.
Parameter JITTER GENERATION Output 12 kHz to 20 MHz LVPECL Min Typ Max Unit Test Conditions/Comments
1.31 1.28 0.89 1.32 1.29 1.24 1.26
ps rms ps rms ps rms ps rms ps rms ps rms ps rms
LVDS Output CMOS Output
50 kHz to 80 MHz LVPECL
0.44 0.75 0.58 0.45 0.76 0.39 0.44
ps rms ps rms ps rms ps rms ps rms ps rms ps rms
LVDS CMOS
JITTER TRANSFER BANDWIDTH Bandwidth Setting Low Medium High JITTER TRANSFER PEAKING Bandwidth Setting Low Medium High
Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5 to Pin Y0 = 111111 (see Figure 3) Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding CMOS toggle rates above 250 MHz Input = 122.88 MHz, output = 155.52 MHz Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz Input = 25 MHz, output = 125 MHz, Pin A3 to Pin A0 = 1110, Pin Y5 to Pin Y0 = 111111 (see Figure 3) Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz Input = 122.88 MHz, output = 155.52 MHz Input = 19.44 MHz, output = 245.76 MHz, see Figure 14 regarding CMOS toggle rates above 250 MHz See the Typical Performance Characteristics section
170 20 75
Hz kHz kHz See the Typical Performance Characteristics section
1.3 0 0.08
dB dB dB
Rev. 0 | Page 5 of 20
AD9550 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 3.6 V -0.5 V to VDD + 0.5 V -65C to +150C -40C to +85C 300C 150C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 20
AD9550 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25 Y3 Y2 Y1 Y0 VDD OUT1 OUT1 GND
Y4 Y5 A0 A1 A2 A3 REF GND
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
AD9550
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
GND OUT2 OUT2 VDD LOCKED LDO VDD LDO
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 29, 30, 31, 32, 1, 2 3, 4, 5, 6 7 8, 11, 24, 25 9, 10 12, 13, 14 15 16 17, 19 18, 21, 28 20 26, 22 27, 23 N/A2
1 2
Mnemonic Y0, Y1, Y2, Y3, Y4, Y5 A0, A1, A2, A3 REF GND NC OM2, OM1, OM0 RESET FILTER LDO VDD LOCKED OUT1, OUT2 OUT1, OUT2 EP
Type1 I I I P I I I/O P/O P O O O
Description Control Pins. These pins select one of 52 preset output frequency combinations for OUT1 and OUT2. Each pin has an internal 100 k pull-up resistor. Control Pins. These pins select one of 15 preset input reference frequencies. Each pin has an internal 100 k pull-up resistor. Reference Clock Input. Connect this pin to a single-ended active clock input signal. Ground. No Connection. Make no external connection to these pins. Do not connect to GND or VDD. Control Pins. These pins select one of eight preset output configurations (see Table 10). Each pin has an internal 40 k pull-up resistor. Reset Internal Logic. This is a digital input pin. This pin is active low with a 100 k internal pull-up resistor and resets the internal logic to default states (see the Automatic Power-On Reset section). Loop Filter Node for the PLL. Connect external loop filter components (see Figure 24) from this pin to Pin 17 (LDO). LDO Decoupling Pins. Connect a 0.47 F decoupling capacitor from each of these pins to ground. Power Supply Connection: 3.3 V Supply. Pin 21 supplies the OUT2 driver and Pin 28 supplies the OUT1 driver. Locked Status Indicator for the PLL. Active high. Complementary Square Wave Clocking Outputs. Square Wave Clocking Outputs. Exposed Die Pad. The exposed die pad must be connected to GND.
I is input, I/O is input/output, O is output, P is power, and P/O is power/output. N/A means not applicable.
Rev. 0 | Page 7 of 20
09057-002
NOTES 1. NC = NO CONNECT. 2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
NC NC GND OM2 OM1 OM0 RESET FILTER
9 10 11 12 13 14 15 16
AD9550 TYPICAL PERFORMANCE CHARACTERISTICS
-30 -40 -50 -60 JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 0.89ps 50kHz TO 80MHz 0.58ps -70 -80 -90 JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 0.73ps 50kHz TO 80MHz 0.51ps
PHASE NOISE (dBc/Hz)
-70 -80 -90 -100 -110 -120 -130 -140 -150
09057-103
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150
09057-005 09057-007 09057-006
-160 10
100
1k
10k
100k
1M
10M
100M
-160 100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 3. Phase Noise (fREF = 25 MHz, fOUT1 = 125 MHz)
-30 -40 -50 -60
Figure 6. Phase Noise (fREF = 77.76 MHz, fOUT1 = 622.08 MHz)
-30 -40 -50 -60
JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 1.32ps 50kHz TO 80MHz 0.41ps
JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 1.26ps 50kHz TO 80MHz 0.49ps
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
09057-023
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 100 1k 10k 100k 1M 10M 100M
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 4. Phase Noise (fREF = 25 MHz, fOUT1 = 156.25 MHz)
-30 -40 -50 -60
Figure 7. Phase Noise (fREF = 19.44 MHz, fOUT1 = 155.52 MHz)
-30 -40 -50 -60
JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 1.25ps 0.63ps 50kHz TO 80MHz
JITTER BANDWIDTH JITTER (rms) 12kHz TO 20MHz 1.27ps 50kHz TO 80MHz 0.54ps
PHASE NOISE (dBc/Hz)
-70 -80 -90 -100 -110 -120 -130 -140 -150 100 1k 10k 100k 1M 10M 100M
09057-004
PHASE NOISE (dBc/Hz)
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 100 1k 10k 100k 1M 10M 100M
-160 10
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 5. Phase Noise (fREF = 61.44 MHz, fOUT1 = 122.88 MHz)
Figure 8. Phase Noise (fREF = 8 kHz, fOUT1 = 155.52 MHz)
Rev. 0 | Page 8 of 20
AD9550
5 JITTER TRANSFER 0
35 LVPECL 30
-5
SUPPLY CURRENT (mA)
LVDS 25 20 15 10 5
MAGNITUDE (dB)
-10
PHASE NOISE (dBc/Hz)
2 JITTER PEAKING 1
-15
0 -1 -2
-20
-25
-3
0
25
50 75 100 125 150 FREQUENCY OFFSET (Hz)
175
100 FREQUENCY OFFSET (Hz)
1k
09057-008
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
Figure 9. Jitter Transfer, Loop Bandwidth = 170 Hz
10 JITTER TRANSFER 0 -10 25 30
Figure 12. Supply Current vs. Output Frequency, LVPECL and LVDS (10 pF Load)
20pF
SUPPLY CURRENT (mA)
10pF 20 5pF 15
MAGNITUDE (dB)
-20 -30 -40 -50 -60 1k
10
5
09057-110
10k
100k
1M
0
100
200
300
400
500
600
FREQUENCY OFFSET (Hz)
FREQUENCY (MHz)
Figure 10. Jitter Transfer, Loop Bandwidth = 20 kHz
5 JITTER TRANSFER 0
Figure 13. Supply Current vs. Output Frequency, CMOS (10 pF Load)
4.0 3.5 5pF
OUTPUT VOLTAGE (V p-p)
3.0 10pF 2.5 2.0 20pF 1.5 1.0 0.5
-5
MAGNITUDE (dB)
-10
PHASE NOISE (dBc/Hz)
1
JITTER PEAKING
-15 -20
0
-1
-2
-25
-3 10 20 30 40 50 60 70 FREQUENCY OFFSET (kHz) 80
100k FREQUENCY OFFSET (Hz)
1M
09057-009
0
100
200
300
400
500
600
FREQUENCY (MHz)
Figure 11. Jitter Transfer, Loop Bandwidth = 75 kHz
Figure 14. Peak-to-Peak Output Voltage vs. Frequency, CMOS
Rev. 0 | Page 9 of 20
09057-012
-30 10k
0
09057-011
0
09057-010
-30 10
0
AD9550
1800 1600 LVPECL
OUTPUT VOLTAGE (mV p-p)
1400 1200 1000 800 600 400 200
09057-013
09057-016 09057-018 09057-017
LVDS
2
200mV/DIV
500ps/DIV
0 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz)
Figure 15. Peak-to-Peak Output Voltage vs. Frequency, LVPECL and LVDS (100 Load)
51 10pF 50 49
Figure 18. Typical Output Waveform, LVPECL (800 MHz)
DUTY CYCLE (%)
48 20pF 47 46 45 44 43
125mV/DIV 500ps/DIV
09057-014
5pF
2
42 0 100 200 300 400 500 600 FREQUENCY (MHz)
Figure 16. Duty Cycle vs. Output Frequency, CMOS
60 59 LVPECL 58 57 LVDS
Figure 19. Typical Output Waveform, LVDS (800 MHz, 3.5 mA Drive Current)
DUTY CYCLE (%)
56 55 54 53 52 51
09057-015
2
500mV/DIV
1.25ns/DIV
50 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz)
Figure 17. Duty Cycle vs. Output Frequency, LVPECL and LVDS (100 Load)
Figure 20. Typical Output Waveform, CMOS (250 MHz, 10 pF Load)
Rev. 0 | Page 10 of 20
AD9550 INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.1F
AD9550
100
3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE)
HIGH IMPEDANCE INPUT 0.1F
AD9550
3.3V DIFFERENTIAL OUTPUT (LVDS OR LVPECL MODE)
09057-024
100
DOWNSTREAM DEVICE
DOWNSTREAM DEVICE
Figure 21. AC-Coupled LVDS or LVPECL Output Driver
Figure 22. DC-Coupled LVDS or LVPECL Output Driver
Rev. 0 | Page 11 of 20
09057-025
AD9550 THEORY OF OPERATION
LOCKED FILTER LOCK DETECT x2
1 0
AD9550
PLL 3350MHz TO 4050MHz LOOP FILTER VCO 3 P0 P0 10 P2 P1 N 10 P1 OUTPUT MODE CONTROL 3 2 OUT1 P2 2 OUT2
PFD
/R
14
UP CHARGE PUMP DN
/5
1 0
x2
R
REF /5 /5, x2, R
/N 20
PRECONFIGURED DIVIDER SETTINGS
N, P0, P1, P2
OM2 TO OM0
09057-019
4 A3 TO A0
6 Y5 TO Y0
Figure 23. Detailed Block Diagram
OVERVIEW
The AD9550 accepts one input reference clock, REF. The input clock path includes an optional divide-by-5 prescaler, an optional x2 frequency multiplier, and a 14-bit programmable divider (R). The output of the R divider drives the input to the PLL. The PLL translates the R-divider output to a frequency within the operating range of the VCO (3.35 GHz to 4.05 GHz) based on the value of the feedback divider (N). The VCO prescaler (P0) reduces the VCO output frequency by an integer factor from 5 to 11, resulting in an intermediate frequency in the range of 305 MHz to 810 MHz. The 10-bit P1 and P2 dividers can further reduce the P0 output frequency to yield the final output clock frequencies at OUT1 and OUT2, respectively. Thus, the frequency translation ratio from the reference input to the output depends on the selection of the divide-by-5 prescalers, the x2 frequency multipliers, the values of the three R dividers, the N divider, and the P0, P1, and P2 dividers. These parameters are set automatically via the preconfigured divider settings per the Ax and Yx pins (see the Preset Frequencies section).
PRESET FREQUENCIES
The frequency selection pins (A3 to A0 and Y5 to Y0) allow the user to hardwire the device for preset input and output frequencies based on the pin logic states (see Figure 23). The pins decode ground or open connections as Logic 0 or Logic 1, respectively. The A3 to A0 pins allow the user to select one of 15 input reference frequencies as shown in Table 6. The device sets the appropriate divide-by-5 (/5), multiply-by-2 (x2), and input divider (R) values based on the logic levels applied to the Ax pins. The divide-by-5, x2, and R values cause the PLL input frequency to be either 16 kHz or 40/3 kHz. There are two exceptions. The first is for A3 to A0 = 1101, which yields a PLL input frequency of 155.52/59 MHz. The second is for A3 to A0 = 1110, which yields a PLL input frequency of either 1.5625 MHz or 4.86 MHz depending on the Y5 to Y0 pins. The Y5 to Y0 pins allow the user to select one of 52 output frequency combinations (fOUT1 and fOUT2) per Table 7. The device sets the appropriate P0, P1, and P2 settings based on the logic levels applied to the Yx pins. Note, however, that selecting 101101 through 110010 require A3 to A0 = 1101 and selecting 110011 requires A3 to A0 = 1110. The value (N) of the PLL feedback divider and the control setting for the charge pump current (CP) depend on a combination of both the Ax and Yx pin settings as shown in Table 8.
Rev. 0 | Page 12 of 20
AD9550
Table 6. Pin Configured Input Frequency, Ax Pins
A3 to A0 0000 0001 0010 0011 0100 0101 0110 2 0111 1000 1001 1010 1011 1100 11013 11104 1111
1 2
fREF (MHz) 0.008 1.536 2.048 16.384 19.44 25 38.88 61.44 77.76 122.88 125 1.544 155.52 25 or 77.76 200/3
Divide-by-51 Bypassed Bypassed Bypassed Bypassed Bypassed Bypassed Bypassed Bypassed Bypassed Bypassed On Bypassed Bypassed Bypassed Bypassed
x21 Not used On Bypassed Bypassed Bypassed Bypassed On Bypassed Bypassed Bypassed Bypassed On On Bypassed Bypassed Bypassed
R (Decimal) 1 96 128 1024 1215 3125 2430 3840 4860 7680 3125 193 59 16 5000
For divide-by-5 and x2 frequency scalers, on indicates active. Using A3 to A0 = 0110 to yield a 25 MHz to 125 MHz conversion provides a loop bandwidth of 170 Hz. An alternate 25 MHz to 125 MHz conversion uses A3 to A0 = 1110, which provides a loop bandwidth of 20 kHz. 3 A3 to A0 = 1101 only works with Y5 to Y0 = 101101 through 110010. 4 A3 to A0 = 1110 only works with Y5 to Y0 = 110011 or 111111.
Table 7. Pin Configured Output Frequency, Yx Pins
Y5 to Y0 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 fVCO (MHz) 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3686.4 3750 3750 3750 3750 3750 3750 3732.48 fOUT1 (MHz) 245.76 245.76 245.76 245.76 245.76 245.76 122.88 122.88 122.88 122.88 122.88 61.44 61.44 61.44 61.44 16.384 16.384 16.384 2.048 2.048 1.536 156.25 156.25 156.25 125 125 25 155.52
Rev. 0 | Page 13 of 20
fOUT2 (MHz) Not used 245.76 122.88 61.44 16.384 2.048 1.536 122.88 61.44 16.384 2.048 1.536 61.44 16.384 2.048 1.536 16.384 2.048 1.536 2.048 1.536 1.536 156.25 125 25 125 25 25 155.52
P0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6
P1 3 3 3 3 3 3 6 6 6 6 6 12 12 12 12 45 45 45 360 360 480 4 4 4 5 5 25 4
P2 3 6 12 45 360 480 6 12 45 360 480 12 45 360 480 45 360 480 360 480 480 4 5 25 5 25 25 4
AD9550
Y5 to Y0 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 to 111110 111111
1
fVCO (MHz) 3732.48 3732.48 3732.48 3732.48 3732.48 3686.4 3686.4 3686.4 3686.4 3686.4 3600 3600 3600 3600 3600 3705.6 ~3985.53 ~3985.53 ~3985.53 ~3985.53 ~3985.53 ~3985.53 3732.48 3750
fOUT1 (MHz) 155.52 155.52 77.76 77.76 19.44 153.6 153.6 153.6 153.6 153.6 100 100 100 50 50 1.544 fO1 fO 1 fO 1 fO/21 fO/21 fO/41 622.08 125
fOUT2 (MHz) 77.76 19.44 77.76 19.44 19.44 153.6 122.88 61.44 2.048 1.536 100 50 25 50 25 1.544 fO 1 fO/21 fO/41 fO/21 fO/41 fO/41 622.08 Undefined 25
P0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5
P1 4 4 8 8 32 4 4 4 4 4 6 6 6 12 12 400 1 1 1 2 2 4 1 6
P2 8 32 8 32 32 4 5 10 300 400 6 12 24 12 24 400 1 2 4 2 4 4 1 30
fO = 39,191.04/59 MHz.
Table 8. Pin Configuration vs. PLL Feedback Divider Value and Charge Pump Value
A3 to A0 0001 to 1100 Y5 to Y0 000001 to 010101 010110 to 011011 011100 to 100001 100010 to 100110 100111 to 101011 101100 101101 to 111111 000001 to 101100 101101 to 110010 110010 to 111111 000001 to 110010 110011 110100 to 111110 111111 000001 to 010101 010110 to 011011 011100 to 100001 100010 to 100110 100111 to 101011 101100 101101 to 111111 N1 230,400 234,375 233,280 230,400 225,000 231,600 Undefined Undefined 1512 Undefined Undefined 768 Undefined 2400 276,480 281,250 279,936 276,480 270,000 277,920 Undefined 121 145 145 145 145 145 145 121 255 CP2 121 121 121 121 121 121
1101
1110
1111
1 2
PLL feedback divider value (decimal). Charge pump value (decimal). Multiply by 3.5 A to yield ICP. Rev. 0 | Page 14 of 20
AD9550
DESCRIPTION OF FUNCTIONAL BLOCKS
Input Frequency Prescaler (Divide-by-5)
The divide-by-5 prescaler provides the option to reduce the input reference frequency by a factor of five. Note that the prescaler physically precedes the x2 frequency multiplier. This allows the prescaler to bring a high frequency reference clock down to a frequency that is within the range of the x2 frequency multiplier.
Loop Filter
The charge pump in the PFD delivers current to the loop filter (see Figure 24). The components primarily responsible for the bandwidth of the loop filter are external and connect between Pin 16 and Pin 17. The internal portion of the loop filter has two configurations: one is for low loop bandwidth applications (~170 Hz) and the other is for medium (~20 kHz)/high (~75 kHz) bandwidth applications. The low loop bandwidth condition applies when the feedback divider value (N) is 214 (16,384) or greater. Otherwise, the medium/high loop bandwidth configuration is in effect. The feedback divider value depends on the configuration of the Ax and Yx pins per Table 8.
FROM CHARGE PUMP 375 3k 400k CONTROL LOGIC BUFFER SWITCHES CHANGE STATE FOR N 16384
16 17
Input x2 Frequency Multiplier
The x2 frequency multiplier doubles the frequency at its input, thereby taking advantage of a higher frequency at the input to the PLL. This provides greater separation between the frequency generated by the PLL and the modulation spur associated with frequency at the PLL input.
AD9550
PLL (PFD, Charge Pump, VCO, Feedback Divider)
The PLL (see Figure 23) consists of a phase/frequency detector (PFD), a partially integrated analog loop filter (see Figure 24), an integrated voltage controlled oscillator (VCO), and a 20-bit programmable feedback divider. The PLL generates a 3.35 GHz to 4.05 GHz clock signal that is phase-locked to the input reference signal, and its frequency is the phase detector frequency (fPFD) multiplied by the feedback divider value. The PFD of the PLL drives a charge pump that increases, decreases, or holds constant the charge stored on the loop filter capacitors (both internal and external). The stored charge results in a voltage that sets the output frequency of the VCO. The feedback loop of the PLL causes the VCO control voltage to vary in such a way as to phase lock the PFD input signals. The PLL has a VCO with 128 frequency bands spanning a range of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the actual operating frequency within a particular band depends on the control voltage that appears on the loop filter capacitor. The control voltage causes the VCO output frequency to vary linearly within the selected band. This frequency variability allows the control loop of the PLL to synchronize the VCO output signal with the reference signal applied to the PFD. Selection of the VCO frequency band (as well as gain adjustment) occurs automatically as part of the automatic VCO calibration process of the device, which initiates at power-up (or reset). VCO calibration centers the dc operating point of the VCO control signal. During VCO calibration, the output drivers provide a static dc signal. The feedback divider (N-divider) sets the frequency multiplication factor of the PLL in integer steps over a 20-bit range. Note that the N-divider has a lower limit of 32.
TO VCO 53pF
170pF
FILTER
R
LDO
C2 C1
Figure 24. External Loop Filter
The bandwidth of the loop filter primarily depends on three external components (R, C1, and C2). There are two sets of recommended values for these components corresponding to the low and medium/high loop bandwidth configurations (see Table 9). Table 9. External Loop Filter Components
A3 to A0 Pins 0001 to 1100, and 1111 11101 1101 to 1110
1
R 6.8 k 12 k 12 k
C1 47 nF 51 pF 51 pF
C2 1 F 220 nF 220 nF
Loop Bandwidth 0.17 kHz 20 kHz 75 kHz
The 20 kHz loop bandwidth case only applies when the A3 pin to A0 pin = 1110 and the Y5 pin to Y0 pin = 111111.
To achieve the best jitter performance in applications requiring a loop bandwidth of less than 1 kHz, C1 and C2 must have an insulation resistance of at least 500 F.
PLL Locked Indicator
The PLL provides a status indicator that appears at Pin 20 (LOCKED). When the PLL acquires phase lock, the LOCKED pin switches to a Logic 1 state. When the PLL loses lock, however, the LOCKED pin returns to a Logic 0 state.
Rev. 0 | Page 15 of 20
09057-029
AD9550
Output Dividers
INPUT JITTER AMPLITUDE (UI p-p)
1000
The output divider section consists of three dividers: P0, P1, and P2. The P0 divider (or VCO frequency prescaler) accepts the VCO frequency and reduces it by an integer factor of 5 to 11, thereby reducing the frequency to a range between 305 MHz and 810 MHz. The output of the P0 divider independently drives the P1 divider and the P2 divider. The P1 divider establishes the frequency at OUT1 and the P2 divider establishes the frequency at OUT2. The P1 and P2 dividers are each programmable over a range of 1 to 1023, which results in a frequency at OUT1 or OUT2 that is an integer submultiple of the frequency at the output of the P0 divider.
100
AD9550
10
MASK
1
0.1
1
10
100
1M
10M
Output Driver Mode Control
Three mode control pins (OM0, OM1, and OM2) establish the logic family and pin function of the output drivers. The logic families include LVDS, LVPECL, and CMOS (see Table 10). Table 10. Logic Family Assignment via the OMx Pins
Pin OMx 000 001 010 011 100 101 110 111 OUT1 LVPECL LVPECL LVDS LVPECL LVDS LVDS CMOS CMOS Logic Family OUT2 LVPECL LVDS LVPECL CMOS LVDS CMOS LVDS CMOS
JITTER FREQUENCY (kHz)
Figure 25. Jitter Tolerance
LOW DROPOUT (LDO) REGULATORS
The AD9550 is powered from a single 3.3 V supply and contains on-chip LDO regulators for each function to eliminate the need for external LDOs. To ensure optimal performance, each LDO output should have a 0.47 F capacitor connected between its access pin and ground.
AUTOMATIC POWER-ON RESET
The AD9550 has an internal power-on reset circuit (see Figure 26). At power-up, an 800 pF capacitor momentarily holds a Logic 0 at the active low input of the reset circuitry. This ensures that the device is held in a reset state (~250 s) until the capacitor charges sufficiently via the 100 k pull-up resistor and 200 k series resistor. Note that when using a low impedance source to drive the RESET pin, be sure that the source is either tristate or Logic 0 at power-up; otherwise, the device may not calibrate properly.
VDD 100k 200k RESET 15 800pF RESET CIRCUITRY
09057-022
Because both output drivers support the LVDS and LVPECL logic families, each driver has two pins to handle the differential signals associated with these two logic families. The OUT1 driver uses the OUT1 and OUT1 pins, and the OUT2 driver uses the OUT2 and OUT2 pins. When the OMx pins select the CMOS logic family, the signal at the OUT1 pin is a phase aligned replica of the signal at the OUT1 pin and the signal at the OUT2 pin is a phase aligned replica of the signal at the OUT2 pin.
AD9550
Figure 26. Power-On Reset
JITTER TOLERANCE
Jitter tolerance is the ability of the AD9550 to maintain lock in the presence of sinusoidal jitter. The AD9550 meets the input jitter tolerance mask per Telcordia GR-253-CORE (see Figure 25). The acceptable jitter tolerance is the region above the mask.
Provided an input reference signal is present at the REF pin, the device automatically performs a VCO calibration during power-up. If the input reference signal is not present, VCO calibration fails and the PLL does not lock. As soon as an input reference signal is present, the user must reset the device to initiate the automatic VCO calibration process. Any change to the preset frequency selection pins requires the user to reset the device. This is necessary to initiate the automatic VCO calibration process.
Rev. 0 | Page 16 of 20
09057-021
0.1 0.01
AD9550 APPLICATIONS INFORMATION
THERMAL PERFORMANCE
The AD9550 is specified for case temperature (TCASE). To ensure that TCASE is not exceeded, use an airflow source. The following equation determines the junction temperature on the application printed circuit board (PCB): TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured by the customer at the top center of the package. JT is the value indicated in Table 11. PD is the power dissipation (see Table 1 for the power consumption parameters). Values of are provided for package comparison and PCB design JA considerations. JA can be used for a first-order approximation of TJ using the following equation: TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations.
1
Table 11. Thermal Parameters for the 32-Lead LFCSP
Symbol JA JMA JMA JB JB JC JT Description Junction-to-ambient thermal resistance, 0 m/sec airflow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 0 m/sec airflow per JEDEC JESD51-8 (still air) Junction-to-board characterization parameter, 0 m/sec airflow per JEDEC JESD51-6 (still air) Junction-to-case thermal resistance Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) Value1 41.6 36.4 32.6 24.2 22.9 4.8 0.5 Unit C/W C/W C/W C/W C/W C/W C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 17 of 20
AD9550 OUTLINE DIMENSIONS
PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18
25 32 1 EXPOSED PAD
PIN 1 INDICATOR
0.50 BSC
24
3.25 3.10 SQ 2.95
8 9
17
TOP VIEW 0.80 0.75 0.70
0.50 0.40 0.30
16
BOTTOM VIEW
0.25 MIN
SEATING PLANE
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 27. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm x 5 mm Body, Very, Very Thin Quad (CP-32-7) Dimensions shown in millimeters
ORDERING GUIDE
Model1 AD9550BCPZ AD9550BCPZ-REEL7 AD9550/PCBZ
1
Temperature Range -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board
112408-A
Package Option CP-32-7 CP-32-7
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
AD9550 NOTES
Rev. 0 | Page 19 of 20
AD9550 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09057-0-8/10(0)
Rev. 0 | Page 20 of 20

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