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Structure Product Type Features
Silicon monolithic integrated circuit 3ch 16bit 12MSPS CIS/CCD Analog Front End
BU6577FV
Correlated double sampling (CDS) Programmable gain amplifier (8bit resolution) 16bit 12MSPS ADC Serial control interface Offset calibration DAC (8bit resolution) Internally generated voltage references 8 or 4-bit wide multiplexed data output formats
Absolute maximum ratings (Ta=25) Parameter Symbol Supply voltage 1 VAVDD Supply voltage 2 VDVDD I/O supply voltage VVDDIO Digital input voltage *1 VID Digital output voltage *2 VOD Analog input voltage *3 VIA Analog output voltage *4 VOA Storage temperature Tstg Power dissipation *5 Pd
Ratings -0.24.0 -0.24.0 -0.24.0 -0.2VVDDIO + 0.3 -0.2VVDDIO + 0.3 -0.2VAVDD + 0.3 -0.2VAVDD + 0.3 -40125 640
Unit V V V V V V V mW
*1 : Pin No.4,5,6,7,9,11,12 *2 : Pin No.13,14,15,16,17,18,19,20 *3 : Pin No.1,27,28 *4 : Pin No.23,24,25,26 *5 : Reduced by 6.4mW for each increase in Ta of 1 over 25
Operating conditions (Ta = 0 to 70) Parameter Symbol Supply voltage 1 VAVDD Supply voltage 2 VDVDD I/O supply voltage VVDDIO
MIN 3.135 3.135 3.0
TYP 3.3 3.3 3.3
MAX 3.465 3.465 3.6
Unit V V V
This product is not designed for protection against radioactive rays
Status of this document The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority.
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Electrical characteristics (Unless otherwise noted, Ta=25VAVDD=VDVDD=VVDDIO=3.3VMCLK=24MHz)
Parameter
Input signal limits Conversion Rate
Symbol
VIN RATE VIH VIL IIH IIL VOH VOL ITOTAL IAVDD IDVDD IVDDIO IPD
MIN
0.26 0.7*VVDDIO VVDDIO-0.5 -
SPEC TYP 68 60 3 5 30
MAX
2.7 12 0.2*VVDDIO 1 1 0.5 130 100 10 20 60
Unit
V MSPS V V A A V V mA mA mA mA A
Conditions
Overall System Specification
Digital Inputs
High level input voltage Low level input voltage High level input current Low level input current
Digital Outputs
High level output voltage
Low level output voltage Supply Currents
Total supply current active Total Analog AVDD, Supply current - active Total digital DVDD, Supply current - active Total digital I/O, Supply current - active Supply current - full power down mode
IOH = 1mA IOL = 1mA
MCLK=Low
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Package outline
Include. BURR
Part number
BU6577FV
1PIN MARK
Lot No.
SSOP-B28 (Unit: mm)
Block diagram
Pin description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name VIN1 AGND DVDD OEB VSMP RLC/ACYC MCLK DGND SEN VDDIO SDI SCK B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7]/SDO AVDD AGND CN CP CM VRLC/VBIAS VIN3 VIN2
VSMP
MCLK
RLC/ACYC
AVDD
AGND
AGND
TIMING CONTROL BANDGAP REFERENCE
VIN1
CP CM CN OEB
CLAMP
PGA
8
VIN2
OFFSET DAC 16-bit ADC L A T C H
CLAMP
PGA
8
VIN3
OFFSET DAC
B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] /SDO
CLAMP
PGA
8
OFFSET DAC
8
VRLC /VBIAS
VBIAS GENERATOR
CONTROL REGISTER
DIGITAL INTERFACE
SEN
SCK
SDI
DVDD
DGND
VDDIO
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Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and GND line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and GND lines. Especially, when there are GND pattern for small signal and GND pattern for large current included the external circuits, separate each GND pattern. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (4) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (5) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (6) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals; such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (8) Rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of wiring.
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Notice
Notes
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