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| SY89852U Precision Low Power Differential 2:1 LVPECL MUX with Internal Termination General Description The SY89852U is a 2.5V/3.3V precision, highspeed, 2:1 differential MUX capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. The differential input includes Micrel's unique, patent pending 3-pin input termination architecture that allows users to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The unique, patent input isolation design minimizes crosstalk minimizing crosstalk induced jitter. The outputs are 800mV LVPECL, with extremely fast rise/fall time guaranteed to be less than 180ps. The SY89852U operates from a 2.5V 5% supply or a 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89852U is part of Micrel's high-speed, (R) product line. All support Precision Edge documentation can be found on Micrel's web site at: www.micrel.com. Precision Edge (R) Features * * * * Provides a low jitter copy of the selected input Superior alternative to the EP58 2:1 MUX Low power: 58mW (2.5V nominal, no load) Guaranteed AC performance over temperature and supply voltage: - DC- to > 2.5Gbps data rate throughput - DC- to > 2.5GHz clock fMAX - < 340ps In-to-Out tpd - < 180ps tr/tf time Ultra-low Jitter Design: - <1ps(rms) random jitter - <10ps(pp) deterministic jitter - <10ps(pp) total jitter (clock) - <0.7ps(rms) crosstalk induced jitter Unique, patent-pending input isolation design minimizes crosstalk Unique, patent pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS) Typical 800mV (100k) LVPECL output swing Power supply 2.5V +5% or 3.3V +10% o o Industrial temperature range -40 C to +85 C Available in ultra-small (3mm x 3mm) 16-pin QFN package * * * * * * * Typical Applications Applications * * * * Redundant clock distribution SONET/SDH clock/data distribution Loopback Fibre Channel distribution Markets * * * * Precision Edge is a registered trademark of Micrel, Inc. LAN/WAN Enterprise servers ATE Test and measurement October 2008 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Ordering Information(1) Part Number SY89852UMG SY89852UMGTR Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electrical Only. 2. Tape and Reel. (2) Package Type QFN-16 QFN-16 Operating Range Industrial Industrial Package Marking 852U with bar-line designator 852U with bar-line designator Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free Pin Configuration 16-Pin QFN October 2008 2 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Pin Description Pin Number 1,2, 3,4 Pin Name Pin Function Differential Input: This input pair is the signal to be buffered. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of this pair internally terminates to a VT pin through 50. Note that this input will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to this pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. Positive Power Supply. Bypass with 0.1F0.01F low ESR capacitors as close to the VCC pin as possible. Differential 100K LVPECL Output: This LVPECL output is the output of the device. Terminate through 50 to VCC -2V. PECL output requires DC path to ground. Thus, AC-coupled applications require pull-down resistors. See "Output Interface Applications" section. Ground. Ground pin and exposed pad must be connected to the same ground plane. This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25K pull-up resistor and will default to logic HIGH state if left open. No connect. IN, /IN 16,5 VT 8,13 VCC 12,9 Q, /Q GND, Exposed Pad SEL NC 10,11,14,15 6 7 Truth Table IN0 0 1 X X Note: 1. SEL is connected to a 25k pull-up resistor and will default to logic high if left open. IN1 X X 0 1 SEL 0 0 1 1 (1) Q 0 1 0 1 Functional Block Diagram October 2008 3 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Absolute Maximum Ratings(1) Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (VIN) ..................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous ................................................. 50mA Surge ........................................................ 100mA (3) Termination Current Source or sink current on VT .................... 50mA Lead Temperature (soldering, 20sec.) ........... +260C Storage Temperature (Ts) ..................-65C to 150C Operating Ratings(2) Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA) ................ -40C to +85C (4) Package Thermal Resistance QFN (JA) Still-Air ..................................................... 60C/W QFN (JB) Junction-to-Board .................................... 38C/W DC Electrical Characteristics(5) TA = -40C to +85C, unless otherwise stated. Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN VT_IN Notes: 1. Permanent device damage may occur if the "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability, use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB use a 4-layer board in still air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min) not lower than 1.2V. Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT) Input High Voltage (IN-to-/IN) Input Low Voltage (IN-to-/IN) Input Voltage Swing (IN-to-/IN) Differential Input Voltage Swing |IN-/IN| IN-to-VT (IN-to-/IN) Condition Min 2.375 3.0 Typ 2.5 3.3 23 Max 2.625 3.6 35 120 60 VCC VIH-0.1 1.7 Units V V mA V V V V No load, max. VCC 80 40 Note 6 VCC -1.6 0 See Figure 1a. See Figure 1b. 0.1 0.2 100 50 1.28 V October 2008 4 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U LVPECL Outputs DC Electrical Characteristics(7) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50 to VCC -2V, unless otherwise stated. Symbol VOH VOL VOUT VDIFF-OUT Parameter Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV LVTTL/CMOS DC Electrical Characteristics(7) Symbol VIH VIL IIH IIL Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 -125 -300 Typ Max VCC 0.8 30 Units V V A A October 2008 5 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U AC Electrical Characteristics(8) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC -2V, unless otherwise stated. Symbol fMAX Parameter Maximum Operating Frequency Propagation Delay tPD tPD Tempco IN-to-Q, /IN-to-Q SEL-to-Q Differential Propagation Delay Temperature Coefficient Data Random Jitter (RJ) Deterministic Jitter (DJ) tJitter Clock Cycle-to-Cycle Jitter Total Jitter Crosstalk-induced Jitter tr, tf Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 10. DJ is measured at 2.5Gbps, with both K28.5 and 223 - 1 PRBS pattern. 11. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 12. Total jitter definition: With an ideal clock input of frequency Min 2.5 2.5 140 100 Typ 3.2 3.5 230 250 100 Max Units Gbps GHz 340 400 ps ps fs/ C o Note 9 Note 10 Note 11 Note 12 Note 13 At full output swing. 50 100 1 10 1 10 0.7 180 psRMS psRMS psPP psRMS psRMS ps Output Rise/Fall Time (20% to 80%) October 2008 6 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Operating Characteristics VCC = 2.5V, VIN = 100mV, TA = 25C; unless otherwise stated. Amplitude vs. Frequency 900 800 700 600 500 400 300 200 100 FREQUENCY (MHz) Propagation Delay vs. Temperature 214 212 IN1 to Q 210 208 206 204 IN0 to Q 202 200 198 196 194 192 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) October 2008 7 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Operating Characteristics October 2008 8 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Singled-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagrams Figure 2. Timing Diagram October 2008 9 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Input and Output Stages Figure 3a. Simplified Differential Input Stage Figure 3b. Simplified LVPECL Output Stage October 2008 10 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Input Interface Applications Option: may connect VT to VCC Figure 4a. LVPECL Interface (DC-Coupled) Figure 4b. LVPECL Interface (AC-Coupled) Figure 4c. CML Interface (DC-Coupled) Figure 4d. CML Interface (AC-Coupled) Figure 4e. LVDS Interface October 2008 11 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Output Interface Applications Note: For +2.5V systems R1 = 250, R2 = 82.5 Figure 5a. Parallel Thevenin-Equivalent Termination Note: For +2.5V systems: Rb = 19 For 3.3V systems Rb = 50 Figure 5b. Parallel Termination (3-Resistor) Note: For +2.5V systems: Rb = 50 For 3.3V systems Rb = 100 The output pair requires a DC-current path to GND. Figure 5c. AC-Coupled Output Pull-down Resistors Related Product and Support Documentation Part Number SY89852U HBW Solutions Function Precision Low Power Differential 2:1 LVPECL MUX w/Internal Termination New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy89852u.shtml www.micrel.com/product-info/products/solutions.shtml October 2008 12 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89852U Package Information 16-Pin (3mm x 3mm) QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated. October 2008 13 M9999-100208-D hbwhelp@micrel.com or (408) 955-1690 |
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