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| Stratix III Device Handbook, Volume 2 Software Version: Document Version: Document Date: 101 Innovation Drive San Jose, CA 95134 www.altera.com 10.0 2.3 (c) July 2010 Copyright (c) 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. SIII5V2-2.3 Contents Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-v Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About-vii How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-vii Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-vii Chapter I. DC & Switching Characteristics of Stratix III Devices Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 TriMatrix Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Configuration and JTAG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 High-Speed I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 DCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 iv Contents I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Preliminary and Final Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 I/O Timing Measurement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 I/O Default Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 User I/O Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 EP3SL50 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 EP3SL70 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66 EP3SL110 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93 EP3SL150 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-119 EP3SL200 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-146 EP3SL340 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-174 EP3SE50 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-202 EP3SE80 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-229 EP3SE110 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-255 EP3SE260 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-283 Dedicated Clock Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-310 EP3SL50 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-310 EP3SL70 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-312 EP3SL110 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-313 EP3SL150 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-315 EP3SL200 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-316 EP3SL340 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-318 EP3SE50 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-319 EP3SE80 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-321 EP3SE110 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-322 EP3SE260 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-324 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-326 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-330 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter Revision Dates The chapter in this book was revised on the following date. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Stratix III Device Datasheet: DC and Switching Characteristics Revised: July 2010 Part Number: SIII52001-2.3 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 vi Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Additional Information This handbook provides comprehensive information about the Altera(R) Stratix(R) III family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Technical support Technical training Product literature Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Contact Method Website Website Email Website Email Email Address www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature nacomp@altera.com authorization@altera.com Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, file names, file name extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: Italic Type with Initial Capital Letters Italic type (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 viii Typographic Conventions Visual Cue Courier type Meaning Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or the user's work. A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. v 1 c w r f Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Section I. DC & Switching Characteristics of Stratix III Devices When Stratix(R) III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Stratix III devices, system designers must consider the operating requirements discussed in the following chapter: Chapter 1, Stratix III Device Datasheet: DC and Switching Characteristics Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 I-2 Section 1: DC & Switching Characteristics of Stratix III Devices Revision History Book Title Cross-Referenced from Title Page (c) July 2010 Altera Corporation 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-2.3 Electrical Characteristics This chapter describes the electrical characteristics, switching characteristics, and I/O timing for Stratix(R) III devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include core performance specifications and periphery performance. A glossary is also included for your reference. Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Stratix III devices, system designers must consider the operating requirements described in this chapter. Stratix III devices are offered in both commercial and industrial grades. Commercial devices are offered in -2 (fastest), -3, -4, and -4L speed grades. Industrial devices are offered only in -3, -4, and -4L speed grades. 1 In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with a "C" prefix and industrial with an "I" prefix. For example, commercial devices are indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Stratix III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions. Conditions beyond those listed in Table 1-1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device. Table 1-1. Absolute Maximum Ratings for Stratix III Devices (Note 1) (Part 1 of 2) Symbol VCCL VCC VCCD_PLL VCCA_PLL VCCPT VCCPGM VCCPD VCCIO Parameter Selectable core voltage power supply I/O registers power supply Phase-locked loop (PLL) digital power supply PLL analog power supply Programmable power technology power supply Configuration pins power supply I/O pre-driver power supply I/O power supply Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Maximum 1.65 1.65 1.65 3.75 3.75 3.9 3.9 3.9 Unit V V V V V V V V (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1-1. Absolute Maximum Ratings for Stratix III Devices (Note 1) (Part 2 of 2) Symbol VCC_CLKIN VCCBAT VI TJ IOUT TSTG Note to Table 1-1: (1) Supply voltage specifications apply to voltage readings taken at the device pins, not the power supply. Parameter Differential clock input power supply (top and bottom I/O banks only) Battery back-up power supply for design security volatile key register DC Input voltage Operating junction temperature DC output current, per pin Storage temperature (No bias) Minimum -0.5 -0.5 -0.5 -55 -25 -65 Maximum 3.75 3.75 4.0 125 40 150 Unit V V V C mA C Sinusoidal Maximum Allowed Overshoot/Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in Table 1-2 and undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Table 1-2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. The maximum allowed overshoot duration is specified as percentage of high-time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.2 V can only be at 4.2 V for 15.8% over the lifetime of the device; for a device lifetime of 10 years, this is equivalent to 15.8% of ten years which is 18.96 months. Figure 1-1 shows how to determine the overshoot duration. Figure 1-1. Overshoot Duration 4.1 V 3.15 V 3.0 V T T 1 In the example shown in Figure 1-1, the overshoot voltage is shown in red and is present at the Stratix III pin, up to 4.1 V. From Table 1-2, for an overshoot of up to 4.1 V, the percentage of high time for overshoot > 3.15 V can be as high as 46% over an 11.4-year period. The percentage of high time is calculated as (delta T/T) * 100. This 11.4-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations where the device is in an idle state, lifetimes are increased. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics 1-3 Table 1-2. Maximum Allowed Overshoot During Transitions Symbol Parameter Condition 4 4.05 4.1 4.15 4.2 4.25 4.3 4.35 Vi (AC) AC Input Voltage (1) 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 Note to Table 1-2: (1) This input voltage is regardless of the VCCIO supply which is used to power up the input buffer. Overshoot Duration as a % of High Time 100.000 79.330 46.270 27.030 15.800 9.240 5.410 3.160 1.850 1.080 0.630 0.370 0.220 0.130 0.074 0.043 0.025 0.015 Unit % % % % % % % % % % % % % % % % % % Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Stratix III devices. Table 1-3 lists the steady-state voltage and current values expected from Stratix III devices. All supplies are required to monotonically reach their full-rail values within tRAMP. Table 1-3. Recommended Operating Conditions for Stratix III Devices (Part 1 of 2) Symbol Parameter Selectable core voltage power supply for internal logic and input buffers Selectable core voltage power supply for internal logic and input buffers I/O registers power supply PLL digital power supply PLL analog power supply Power supply for the programmable power technology Conditions -- -- -- -- -- -- Minimum 1.05 0.86 1.05 1.05 2.375 2.375 Typical 1.1 0.9 1.1 1.1 2.5 2.5 Maximum 1.15 0.94 1.15 1.15 2.625 2.625 Unit V V V V V V VCCL VCC VCCD_PLL VCCA_PLL VCCPT (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-4 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1-3. Recommended Operating Conditions for Stratix III Devices (Part 2 of 2) Symbol Parameter Configuration pins power supply, 3.3 V VCCPGM Configuration pins power supply, 3.0 V Configuration pins power supply, 2.5 V Configuration pins power supply, 1.8 V I/O pre-driver power supply, 3.3 V VCCPD (1) I/O pre-driver power supply, 3.0 V I/O pre-driver power supply, 2.5 V I/O power supply, 3.3 V I/O power supply, 3.0 V VCCIO I/O power supply, 2.5 V I/O power supply, 1.8 V I/O power supply, 1.5 V I/O power supply, 1.2 V VCC_CLKIN VCCBAT (3) VI VO Differential clock input power supply (top and bottom I/O banks only) Battery back-up power supply for design security volatile key register DC Input voltage Output voltage Conditions -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- For commercial use For industrial use (2) Normal POR (PORSEL=0) Fast POR (PORSEL=1) Normal POR (PORSEL=0) Fast POR (PORSEL=1) Minimum 3.135 2.85 2.375 1.71 3.135 2.85 2.375 3.135 2.85 2.375 1.71 1.425 1.14 2.375 1.0 -0.3 0 0 -40 50 s 50 s 50 s 50 s Typical 3.3 3 2.5 1.8 3.3 3 2.5 3.3 3 2.5 1.8 1.5 1.2 2.5 -- -- -- -- -- -- -- -- -- Maximum 3.465 3.15 2.625 1.89 3.465 3.15 2.625 3.465 3.15 2.625 1.89 1.575 1.26 2.625 3.3 3.6 VCCIO 85 100 5 ms 5 ms 100 ms 12 ms Unit V V V V V V V V V V V V V V V V V C C -- -- -- -- TJ Operating junction temperature Power Supply Ramptime (For VCCPT) tRAMP Power Supply Ramptime (For all power supplies except VCCPT) Notes to Table 1-3: (1) VCCPD is 2.5, 3.0, or 3.3 V. For a 3.3-V I/O standard, VCCPD = 3.3 V. For a 3.0-V I/O standard, VCCPD = 3.0 V. For a 2.5-V or lower I/O standard, VCCPD = 2.5 V. (2) For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0 C to 100 C, regardless of supply voltage. (3) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0-V power supply. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics 1-5 DC Characteristics This section lists the input pin capacitances, on-chip termination tolerance, and hot- socketing specifications. Supply Current Standby current is the current the device draws after the device is configured with no inputs/outputs toggling and no activity in the device. Because these currents vary largely with the resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. Table 1-4 lists supply current specifications for VCC_CLKIN and VCCPGM. Use the EPE to get supply current estimates for the remaining power supplies. Table 1-4. Supply Current Specifications for VCC_CLKIN and VCCPGM Symbol ICLKIN IPGM Parameter VCC_CLKIN current specifications VCCPGM current specifications Min 0 0 Max 250 250 Unit mA mA I/O Pin Leakage Current Table 1-5 lists Stratix III I/O pin leakage current specifications. Table 1-5. I/O Pin Leakage Current for Stratix III Devices (Note 1), (2) Symbol II IOZ Parameter Input Pin Leakage Current Tri-stated I/O Pin Leakage Current Conditions VI = VCCIOMAX to 0 V VO = VCCIOMAX to 0 V Min -10 -10 Typ -- -- Max 10 10 Unit A A Notes to Table 1-5: (1) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V). (2) The 10-A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on. Bus Hold Specifications Table 1-6 lists the Stratix III device family bus hold specifications. Table 1-6. Bus Hold Parameters for Stratix III Devices (Part 1 of 2) VCCIO Parameter Symbol Conditions 1.2 V Min Max -- -- 120 1.5 V Min 25.0 -25.0 -- 1.8 V Min 30.0 -30.0 -- 2.5 V Min 50.0 -50.0 -- 3.0 V/3.3 V Min 70.0 -70.0 -- Unit Max -- -- 160 Max -- -- 200 Max -- -- 300 Max -- -- 500 A A A Low sustaining current High sustaining current Low overdrive current ISUSL ISUSH IODL VIN > VIL (maximum) VIN < VIH (minimum) 0V < VIN < VCCIO 22.5 -22.5 -- (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-6 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1-6. Bus Hold Parameters for Stratix III Devices (Part 2 of 2) VCCIO Parameter Symbol Conditions 1.2 V Min Max -120 0.95 1.5 V Min -- 0.50 1.8 V Min -- 0.68 2.5 V Min -- 0.70 3.0 V/3.3 V Min -- 0.80 Unit Max -160 1.00 Max -200 1.07 Max -300 1.70 Max -500 2.00 A V High overdrive current Bus-hold trip point IODH VTRIP 0V On-Chip Termination (OCT) Specifications If you enable OCT calibration, calibration is automatically performed at power-up for the I/Os connected to the calibration block. Table 1-7 lists the Stratix III OCT calibration block accuracy specifications. Table 1-7. On-Chip Termination Calibration Accuracy Specifications for Stratix III Devices (Note 1) Calibration Accuracy Symbol Description Conditions C2 25- RS (2) 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 50- RS 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 50- RT 2.5, 1.8, 1.5, 1.2 20-RS to 60-RS 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 Internal series termination with calibration (25- setting) Internal series termination with calibration (50- setting) Internal parallel termination with calibration (50- setting) Expanded range for internal series termination with calibration (Between 20- to 60-setting) Internal left shift series termination with calibration (25- RS _left_shift setting) Internal series termination with calibration VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V VCCIO = 2.5, 1.8, 1.5, 1.2 V VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V (3) VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V (4) 8 8 10 C3, I3 8 8 10 C4, I4 8 8 10 % % % Unit 10 10 10 % 25- R S _left_shift ROCT_CAL Notes to Table 1-7: 10 10 10 % (1) OCT calibration accuracy is valid at the time of calibration only. (2) 25- RS not supported for 1.5 V and 1.2 V in Row I/O. (3) 1.5 V and 1.2 V only supports 40- to 60- expanded range. (4) For resistance tolerance after power-up calibration, refer to Equation 1-1 and Table 1-9 on page 1-8. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics 1-7 The accuracy listed in Table 1-7 is valid at the time of calibration. If the voltage or temperature changes, the termination resistance value varies. Table 1-8 lists the resistance tolerance for Stratix III OCT. Table 1-8. On-Chip Termination Resistance Tolerance Specification for Stratix III Devices Resistance Tolerance Symbol ROCT_UNCAL 25- R S 3.3, 3.0, 2.5 25- RS 1.8, 1.5 25- RS 1.2 50- RS 3.3, 3.0, 2.5 50- RS 1.8, 1.5 50- RS 1.2 RD Description Internal series termination without calibration Internal series termination without calibration (25- setting) Internal series termination without calibration (25- setting) Internal series termination without calibration (25- setting) Internal series termination without calibration (50- setting) Internal series termination without calibration (50- setting) Internal series termination without calibration (50- setting) Internal differential termination for LVDS technology (100-setting) VCCIO = 3.3, 3.0, 2.5 V VCCIO = 1.8, 1.5 V VCCIO = 1.2 V VCCIO = 3.3, 3.0, 2.5 V VCCIO = 1.8, 1.5 V VCCIO = 1.2 V VCCIO = 2.5 V Conditions C2 -- 30 30 35 30 30 35 40 50 60 40 50 60 -15 to 35 40 50 60 40 50 60 % % % % % % % C3, I3 C4, I4 Unit Table 1-9 lists OCT variation with temperature and voltage after power-up calibration. Use Table 1-9 and Equation 1-1 to determine OCT variation without re-calibration. Equation 1-1. OCT Variation Without Re-Calibration (Note 1) dR dR R O CT = R SCAL 1 + ------ T ------ V dV dT Notes to Equation 1-1: (1) ROCT value calculated from Equation 1-1 shows the range of OCT resistance with the variation of temperature and VCCIO. (2) RSCAL is the OCT resistance value at power-up. (3) T is the variation of temperature with respect to the temperature at power-up. (4) V is the variation of voltage with respect to the VCCIO at power-up. (5) dR/dT is the percentage change of RSCAL with temperature. (6) dR/dV is the percentage change of RSCAL with voltage. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-8 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1-9. On-Chip Termination Variation after Power-up Calibration Symbol Description (Note 1) VCCIO (V) 3 2.5 Commercial Typical 0.029 0.036 0.065 0.104 0.177 0.294 0.301 0.355 0.344 0.348 Unit %/mV %/mV %/mV %/mV %/mV %/C %/C %/C %/C %/C dR/dV OCT variation with voltage without re-calibration 1.8 1.5 1.2 3 2.5 dR/dT OCT variation with temperature without re-calibration 1.8 1.5 1.2 Note to Table 1-9: (1) Valid for VCCIO range of 5% and temperature range of 0 to 85 C. Pin Capacitance Table 1-10 lists the Stratix III device family pin capacitance. s Table 1-10. Pin Capacitance for Stratix III Device Family Symbol CIOTB CIOLR CCLKTB CCLKLR COUTFB CCLK1, CCLK3, C CLK8, and CCLK10 Parameter Input capacitance on top and bottom I/O pins Input capacitance on left and right I/O pins Input capacitance on top and bottom non-dedicated clock input pins Input capacitance on left and right non-dedicated clock input pins Input capacitance on dual-purpose clock output and feedback pins Input capacitance for dedicated clock input pins Typical 4 4 4 4 5 2 Unit pF pF pF pF pF pF Hot-Socketing Table 1-11 lists the hot-socketing specifications for Stratix III devices. Table 1-11. Hot-Socketing Specifications for Stratix III Devices Symbol |IIOPIN|(DC) |IIOPIN|(AC) Note to Table 1-11: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate. Parameter DC current per I/O pin AC current per I/O pin Maximum 300 A 8 mA (1) Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics 1-9 Internal Weak Pull-Up Resistor Table 1-12 lists the weak pull-up resistor values for Stratix III devices. Table 1-12. Internal Weak Pull-Up Resistor for Stratix III Devices (Note 1), (3) Symbol Parameter Value of the I/O pin pullup resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled Conditions VCCIO = 3.3 V 5% (2) VCCIO = 3.0 V 5% (2) VCCIO = 2.5 V 5% (2) VCCIO = 1.8 V 5% (2) VCCIO = 1.5 V 5% (2) VCCIO = 1.2 V 5% (2) Min -- -- -- -- -- -- Typ 25 25 25 25 25 25 Max -- -- -- -- -- -- Unit k k k k k k RPU Notes to Table 1-12: (1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is approximately 25k . I/O Standard Specifications The following tables list input voltage sensitivities (VIH and VIL), output voltages (VOH and VOL), and current drive characteristics (IOH and IOL) for all I/O standards supported by Stratix III devices. VOL and VOH values are valid at the corresponding IOL and IOH, respectively. Table 1-13 through Table 1-18 list the Stratix III device family I/O standard specifications. Refer to "Glossary" on page 1-326 for an explanation of terms used in the Table 1-14 through Table 1-18. Table 1-13. Single-Ended I/O Standards Specifications VCCIO (V) I/O Standard Min 3.3-V LVTTL 3.0-V LVTTL 3.3-V LVCMOS 3.0-V LVCMOS 2.5-V LVTTL/ LVCMOS 1.8-V LVTTL / LVCMOS 1.5-V LVTTL/ LVCMOS 1.2-V LVTTL / LVCMOS 3.0-V PCI 3.0-V PCI-X 3.135 2.85 3.135 2.85 VIL (V) Max 3.465 3.15 3.465 3.15 2.625 2.625 2.625 1.89 1.575 1.26 3.15 3.15 VIH (V) Min 1.7 1.7 1.7 1.7 1.7 1.7 1.7 0.65 * VCCIO 0.65 * VCCIO 0.65 * VCCIO 0.5 * VCCIO 0.5 * VCCIO VOL (V) Max 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VOH (V) Min 2.4 2.4 VCCIO - 0.2 VCCIO - 0.2 2.1 2 1.7 VCCIO - 0.45 0.75 * VCCIO 0.75 * VCCIO 0.9 * VCCIO 0.9 * VCCIO Typ 3.3 3 3.3 3 2.5 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- -- Max 0.8 0.8 0.8 0.8 0.7 0.7 0.7 0.35 * VCCIO 0.35 * VCCIO 0.35 * VCCIO 0.3 * VCCIO 0.35 * VCCIO Max 0.4 0.4 0.2 0.2 0.2 0.4 0.7 0.45 0.25 * VCCIO 0.25 * VCCIO 0.1 * VCCIO 0.1 * VCCIO IOL (mA) 2 2 0.1 0.1 0.1 1 2 2 2 2 1.5 1.5 IOH (mA) -2 -2 -0.1 -0.1 -0.1 -1 -2 -2 -2 -2 -0.5 -0.5 2.375 2.5 2.5 1.71 1.425 1.14 2.85 2.85 1.8 1.5 1.2 3 3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 3.6 -- (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-10 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Refer to the figure in "Single-Ended Voltage Referenced I/O Standard" in the "Glossary" on page 1-326 for voltage referenced receiver input waveform and explanation of terms used in Table 1-14. Table 1-14. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications I/O Standard SSTL-2 CLASS I, II SSTL-18 CLASS I, II SSTL-15 CLASS I, II HSTL-18 CLASS I, II HSTL-15 CLASS I, II HSTL-12 CLASS I, II VCCIO (V) Min 2.375 1.71 1.425 1.71 1.425 1.14 VREF (V) Max 2.625 1.89 1.575 1.89 1.575 1.26 VTT (V) Max 0.51 * VCCIO Typ 2.5 1.8 1.5 1.8 1.5 1.2 Min 0.49 * VCCIO Typ 0.5 * VCCIO Min VREF - 0.04 VREF - 0.04 0.47 * VCCIO Typ VREF VREF VREF VCCIO/2 VCCIO/2 VCCIO/2 Max VREF + 0.04 VREF + 0.04 0.53 * VCCIO 0.833 0.47 * VCCIO 0.9 0.5 * VCCIO 0.969 0.53 * VCCIO 0.85 0.68 0.47 * VCCIO 0.9 0.75 0.5 * VCCIO 0.95 0.9 0.53 * VCCIO -- -- -- -- -- -- Table 1-15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications (Note 1) (Part 1 of 2) I/O Standard SSTL-2 CLASS I SSTL-2 CLASS II SSTL-18 CLASS I SSTL-18 CLASS II SSTL-15 CLASS I SSTL-15 CLASS II HSTL-18 CLASS I HSTL-18 CLASS II HSTL-15 CLASS I HSTL-15 CLASS II HSTL-12 CLASS I VIL(DC) (V) Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.15 Max VREF - 0.15 VREF - 0.15 VREF -0.125 VREF -0.125 VREF -0.1 VREF -0.1 VREF -0.1 VREF -0.1 VREF -0.1 VREF -0.1 VREF -0.08 VIH(DC) (V) Min VREF +0.15 VREF +0.15 VREF +0.125 VREF +0.125 VREF +0.1 VREF +0.1 VREF +0.1 VREF +0.1 VREF +0.1 VREF +0.1 VREF +0.08 VIL(AC) (V) Max Max VREF - 0.31 VREF - 0.31 VREF -0.25 VREF -0.25 VREF -0.175 VREF -0.175 VREF -0.2 VREF -0.2 VREF -0.2 VREF -0.2 VREF -0.15 VIH(AC) (V) Min VREF + 0.31 VREF + 0.31 VREF + 0.25 VREF + 0.25 VREF + 0.175 VREF + 0.175 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.15 VOL (V) Max VTT - 0.57 VTT - 0.76 VTT 0.475 0.28 0.2 * VCCIO 0.2 * VCCIO VOH (V) Min VTT + 0.57 VTT + 0.76 VTT + 0.475 VCCIO - 0.28 0.8 * VCCIO 0.8 * VCCIO VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 0.75 * VCCIO IOL (mA) 8.1 16.2 6.7 13.4 8 16 8 16 8 16 8 IOH (mA) -8.1 -16.2 -6.7 -13.4 -8 -16 -8 -16 -8 -16 -8 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.15 0.4 0.4 0.4 0.4 0.25* VCCIO Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics 1-11 Table 1-15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications (Note 1) (Part 2 of 2) I/O Standard HSTL-12 CLASS II VIL(DC) (V) Min -0.15 Max VREF -0.08 VIH(DC) (V) Min VREF +0.08 VIL(AC) (V) Max Max VREF -0.15 VIH(AC) (V) Min VREF + 0.15 VOL (V) Max 0.25* VCCIO VOH (V) Min 0.75 * VCCIO IOL (mA) 16 IOH (mA) -16 VCCIO + 0.15 Note to Table 1-15: (1) Use the current strength settings that are equal or larger than the IOL and IOH values listed to meet the VOL and VOH specifications for each line. OCT or lower current strengths may provide better signal integrity and lower power. Refer to the figures for "Differential I/O Standards" in "Glossary" on page 1-326 for the receiver input and transmitter output waveforms, and for all the differential I/O standards (LVDS, mini-LVDS, RSDS). V CC_CLKIN is the power supply for the differential column clock input pins. V CCPD is the power supply for the row I/Os and all other column I/Os. Table 1-16. Differential SSTL I/O Standard Specifications I/O Standard SSTL-2 CLASS I, II SSTL-18 CLASS I, II SSTL-15 CLASS I, II VCCIO (V) Min 2.375 1.71 1.425 Typ 2.5 1.8 1.5 Max 2.625 1.89 1.575 VSWING (DC) (V) Min 0.3 0.25 0.2 Max VCCIO VX (AC) (V) Min VCCIO/2 VSWING(AC) (V) Max VCCIO/2 VOX (AC) (V) Min VCCIO/2 Typ -- -- VCCIO/2 Min 0.62 0.5 0.35 Max VCCIO Typ -- -- VCCIO/2 Max VCCIO/2 + 0.15 VCCIO/2 +0.125 + 0.6 VCCIO - 0.2 VCCIO/2 + 0.2 VCCIO/2 + 0.6 VCCIO - 0.15 VCCIO/2 + 0.6 -- -0.175 -- + 0.175 -- + 0.6 -- -0.125 -- -- Table 1-17. Differential HSTL I/O Standards Specifications VCCIO (V) I/O Standard Min HSTL-18 CLASS I, II HSTL-15 CLASS I, II HSTL-12 CLASS I, II VDIF(DC) (V) Max 1.89 1.575 1.26 Min 0.2 0.2 0.16 Max -- -- VCCIO VX(AC) (V) Min 0.78 0.68 -- Typ -- -- 0.5* VCCIO VCM(DC) (V) Max 1.12 0.9 -- Min 0.78 0.68 0.4* VCCIO VDIF(AC) (V) Max 1.12 0.9 0.6* VCCIO Typ 1.8 1.5 1.2 Typ -- -- 0.5* VCCIO Min 0.4 0.4 0.3 Max -- -- VCCIO 1.71 1.425 1.14 + 0.3 + 0.48 Table 1-18. Differential I/O Standard Specifications (Part 1 of 2) I/O Standard VCCIO (V) Min 2.375 2.5 V LVDS (Row I/O) VID (V) (1) Max 2.625 2.625 Min 0.1 0.1 Condition VCM = 1.25 VCM = 1.25 VICM(DC) (V) Max -- -- Min 0.05 (6) 1.05 (6) Condition D max 700 Mbps VOD (V) (2) Max 1.8 (6) 1.55 VOCM (V) (2) Max 0.6 0.6 Min 1.125 1.125 Typ Max Typ 2.5 2.5 Min 0.247 0.247 Typ -- -- 1.25 1.375 1.25 1.375 2.375 Dmax > 700 Mbps (6) (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-12 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table 1-18. Differential I/O Standard Specifications (Part 2 of 2) I/O Standard VCCIO (V) Min 2.375 2.375 2.375 2.375 2.375 2.375 2.375 (5) 2.375 (5) Typ 2.5 2.5 2.5 2.5 2.5 2.5 2.5 (5) 2.5 (5) Max 2.625 2.625 2.625 2.625 2.625 2.625 2.625 (5) 2.625 (5) Min 0.1 0.1 0.1 0.1 0.2 0.2 0.3 0.3 VID (V) (1) Condition VCM = 1.25 VCM = 1.25 VCM = 1.25 VCM = 1.25 VICM(DC) (V) Max -- -- -- -- 0.6 0.6 -- -- Min 0.05 (6) 1.05 VOD (V) (2) Max 1.8 VOCM (V) (2) Max 0.6 0.6 0.6 0.6 0.6 0.6 -- -- Min 1.0 1.0 0.5 0.5 0.5 0.5 -- -- Typ 1.25 1.25 1.2 1.2 1.2 1.2 -- -- Max 1.5 1.5 1.4 1.5 1.4 1.5 -- -- Condition D max 700 Mbps Min 0.247 0.247 0.1 0.1 0.25 0.25 -- -- Typ -- -- 0.2 0.2 -- -- -- -- 2.5 V LVDS (Column I/O) RSDS (Row I/O) RSDS (Column I/O) Mini-LVDS (Row I/O) Mini-LVDS (Column I/0) (6) 1.55 (6) 1.4 1.4 1.325 1.325 1.8 (4) 1.6 (4) Dmax > 700 Mbps (6) 0.3 0.3 0.4 0.4 0.6 1.0 -- -- -- -- Dmax 700 Mbps -- -- -- -- LVPECL (3) Dmax > 700 Mbps Notes to Table 1-18: (1) The minimum VID value is applicable over the entire common mode range, VCM. (2) RL range: 90 RL 110 . (3) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use VCC_CLKIN that must be powered by 2.5 V. Differential clock inputs in row I/O banks are powered by VCCPD. (4) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 0.85 V VIN 1.75 V. The receiver voltage input range for the data rate when Dmax 700 Mbps is 0.45 V VIN 1.95 V. (5) Power supply for the column I/O LVPECL differential clock input buffer is VCC_CLKIN. (6) The receiver voltage input range for the data rate when Dmax > 700 Mbps is 1.0 V VIN 1.6 V. The receiver voltage input range for the data rate when Dmax 700 Mbps is zero V VIN 1.85 V. Power Consumption Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator (EPE) and the Quartus II PowerPlay Power Analyzer feature. The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides estimation based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimation. Refer to Table 1-4 on page 1-5 for supply current estimates for V CCPGM and VCC_CLKIN. Use the EPE and PowerPlay Power Analyzer for current estimates of remaining power supplies. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide For Stratix III FPGAs and the PowerPlay Power Analysis chapter in the Quartus II Handbook. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-13 Switching Characteristics This section provides performance characteristics of Stratix III core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary and Final and each designation is defined below. Preliminary--Preliminary characteristics are created using simulation results, process data, and other known parameters. Final--Final numbers are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. The upper-right hand corner of a table shows the designation as Preliminary or Final. Core Performance Specifications These sections describe the Clock Tree, PLL, digital signal processing (DSP), TriMatrix, and Configuration and JTAG specifications. Clock Tree Specifications Table 1-19 lists the clock tree performance specifications for the logic array, DSP blocks, and TriMatrix Memory blocks for Stratix III devices. Table 1-19. Clock Tree Performance for Stratix III Devices C2 Device VCCL = 1.1 V EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SE260 EP3SL340 EP3SE50 EP3SE80 EP3SE110 730 730 730 730 730 730 730 730 730 730 VCCL = 1.1 V 700 700 700 700 700 700 700 700 700 700 VCCL = 1.1 V 450 450 450 450 450 450 450 450 450 450 VCCL = 1.1 V 450 450 450 450 450 450 450 450 450 450 VCCL = 0.9 V 375 375 375 375 375 375 375 375 375 375 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz C3, I3 C4, I4 C4L, I4L Unit PLL Specifications Table 1-20 lists the Stratix III PLL specifications when operating in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (-40 to 100 C), except for EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, where the industrial junction temperature range is from 0 C to 100 C, regardless of supply voltage. Refer to the figure in "PLL Specifications" in "Glossary" on page 1-326 for the PLL block diagram. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation 1-14 Table 1-20. PLL Specifications for Stratix III Devices (Part 1 of 3) C2 Symbol Parameter VCCL = 1.1 V Min fIN fINPFD fVCO tEINDUTY fOUT fOUT_EXT tOUTDUTY tFCOMP tCONFIGPLL tCONFIGPHASE fSCANCLK tLOCK Input clock frequency Input frequency to the PFD PLL VCO operating range Input clock or external feedback clock input duty cycle Output frequency for internal global or regional clock Output frequency for dedicated external clock output Duty cycle for external clock output (when set to 50%) External feedback clock compensation time Time required to reconfigure scan chain Time required to reconfigure phase shift scanclk frequency Time required to lock from end of device configuration Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 5 5 600 40 -- -- 45 -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- 3.5 1 -- -- Max 800 (1) 325 1600 60 600 (2) 800 (2) 55 10 -- -- 100 1 C3, I3 VCCL = 1.1 V Min 5 5 600 40 -- -- 45 -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- 3.5 1 -- -- Max 717 (1) 325 1300 60 500 (2) 717 (2) 55 10 -- -- 100 1 C4, I4 VCCL = 1.1 V Min 5 5 600 40 -- -- 45 -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- 3.5 1 -- -- Max 717 (1) 325 1300 60 450 (2) 717 (2) 55 10 -- -- 100 1 VCCL = 1.1 V Min 5 5 600 40 -- -- 45 -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- 3.5 1 -- -- Max 717 (1) 325 1300 60 450 (2) 717 (2) 55 10 -- -- 100 1 C4L, I4L VCCL = 0.9 V Min 5 5 600 40 -- -- 45 -- -- -- -- -- Typ -- -- -- -- -- -- 50 -- 3.5 1 -- -- Max 717 (1) 325 1300 60 375 (2) 717 (2) 55 10 -- -- 100 1 MHz MHz MHz % MHz MHz % ns scanclk cycles scanclk cycles MHz ms Unit Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics tDLOCK -- -- 1 -- -- 1 -- -- 1 -- -- 1 -- -- 1 ms Table 1-20. PLL Specifications for Stratix III Devices (Part 2 of 3) C2 Symbol Parameter VCCL = 1.1 V Min PLL closed-loop low bandwidth fCLBW PLL closed-loop medium bandwidth PLL closed-loop high bandwidth (6) tPLL_PSERR tARESET Accuracy of PLL phase shift Minimum pulse width on areset signal Input clock cycle to cycle jitter (FREF 100 MHz) Input clock cycle to cycle jitter (FREF < 100 MHz) Period Jitter for dedicated clock output (FOUT 100 MHz) Period Jitter for dedicated clock output (FOUT < 100 MHz) Cycle to Cycle Jitter for dedicated clock output (FOUT 100 MHz) Cycle to Cycle Jitter for dedicated clock output (FOUT < 100 MHz) Period Jitter for clock output on regular IO (FOUT 100 MHz) Period Jitter for clock output on regular IO (FOUT < 100 MHz) -- -- -- -- 10 -- -- -- -- Typ 0.3 1.5 4 -- -- -- -- -- -- Max -- -- -- 50 -- 0.15 750 175 17.5 C3, I3 VCCL = 1.1 V Min -- -- -- -- 10 -- -- -- -- Typ 0.3 1.5 4 -- -- -- -- -- -- Max -- -- -- 50 -- 0.15 750 175 17.5 C4, I4 VCCL = 1.1 V Min -- -- -- -- 10 -- -- -- -- Typ 0.3 1.5 4 -- -- -- -- -- -- Max -- -- -- 50 -- 0.15 750 175 17.5 VCCL = 1.1 V Min -- -- -- -- 10 -- -- -- -- Typ 0.3 1.5 4 -- -- -- -- -- -- Max -- -- -- 50 -- 0.15 750 175 17.5 C4L, I4L VCCL = 0.9 V Min -- -- -- -- 10 -- -- -- -- Typ 0.3 1.5 4 -- -- -- -- -- -- Max -- -- -- 50 -- 0.1 MHz MHz MHz ps ns UI (p-p) Unit (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics tINCCJ (3), (4) 500 ps (p-p) 225 22.5 ps (p-p) mUI (p-p) ps (p-p) tOUTPJ_DC (5) -- -- 175 -- -- 175 -- -- 175 -- -- 175 -- -- 225 tOUTCCJ_DC (5) -- -- 17.5 -- -- 17.5 -- -- 17.5 -- -- 17.5 -- -- 22.5 mUI (p-p) ps (p-p) mUI (p-p) -- -- -- -- 600 60 -- -- -- -- 600 60 -- -- -- -- 600 60 -- -- -- -- 600 60 -- -- -- -- 750 75 tOUTPJ_IO (5), (8) 1-15 Table 1-20. PLL Specifications for Stratix III Devices (Part 3 of 3) C2 Symbol Parameter VCCL = 1.1 V Min Cycle to Cycle Jitter for clock output on regular IO (FOUT 100 MHz) Cycle to Cycle Jitter for clock output on regular IO (FOUT <100 MHz) Period Jitter for dedicated clock output in cascaded PLLs (FOUT 100 MHz) Period Jitter for dedicated clock output in cascaded PLLs (FOUT 100 MHz) fDRIFT Frequency drift after PFDENA is disabled for duration of 100 s -- Typ -- Max 600 C3, I3 VCCL = 1.1 V Min -- Typ -- Max 600 C4, I4 VCCL = 1.1 V Min -- Typ -- Max 600 VCCL = 1.1 V Min -- Typ -- Max 600 C4L, I4L VCCL = 0.9 V Min -- Typ -- Max 750 ps (p-p) Unit Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation 1-16 tOUTCCJ_IO (5), (8) -- -- 60 -- -- 60 -- -- 60 -- -- 60 -- -- 75 mUI (p-p) tCASC_OUTPJ_DC (5), (7) -- -- 250 -- -- 250 -- -- 250 -- -- 250 -- -- 325 ps (p-p) -- -- 25 -- -- 25 -- -- 25 -- -- 25 -- -- 32.5 mUI (p-p) Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics -- -- 10 -- -- 10 -- -- 10 -- -- 10 -- -- 10 % Notes to Table 1-20: (1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (2) This specification is limited by the lower of the two: I/O fmax or fout of the PLL. (3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 120 ps. (4) FREF is fIN/N when N = 1. (5) Peak-to-peak jitter with a probability level of 10-12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. (6) High bandwidth PLL settings are not supported in external feedback mode. (7) The cascaded PLL specification is only applicable with the following conditions: a) Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz b) Downstream PLL: Downstream PLL BW > 2 MHz (8) External memory interface clock output jitter specifications use a different measurement method and are available in Table 1-33 on page 1-29. Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-17 DSP Block Specifications Table 1-21 lists the Stratix III DSP block performance specifications. Table 1-21. DSP Block Performance Specifications for Stratix III Devices (Note 1) C2 (5) Mode 99-bit multiplier (a, c, e, g) (2) 99-bit multiplier (b, d, f, h) (2) 1212-bit multiplier (a, e) (3) 1212-bit multiplier (b, d, f, h) (3) 1818-bit multiplier 3636-bit multiplier Double mode 1818-bit multiply adder 1818-bit multiply adder 1818-bit multiply adder with loop back 1818-bit multiply adder with loop back (4) 1818-bit multiply accumulator 1818-bit multiply adder with chainout Input Cascade Independent output of four 1818 bit multiplier 36-bit shift (32 bit data) Notes to Table 1-21: (1) Maximum is for a fully pipelined block with Round and Saturation disabled. (2) The DSP block implements eight independent 9b9b multiplies using a, b, c, d for the top DSP half block and e, f, g, h for the bottom DSP half block multipliers. (3) The DSP block implements six independent 12b12b multiplies using a, b, d for the top DSP half block and e, f, h for the bottom DSP half block multipliers. (4) Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled. (5) The Fmax for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table. C3 VCCL = 1.1 V 365 410 365 410 495 365 365 405 405 405 320 390 390 455 390 C4 VCCL = 1.1 V 315 375 315 375 440 315 315 345 345 345 300 330 330 415 330 C4L VCCL = 1.1 V 315 375 315 375 440 315 315 345 345 345 240 330 330 415 330 I3 VCCL = 0.9 V 240 270 240 270 320 220 220 250 250 250 180 240 240 270 250 I4 VCCL= 1.1 V 315 375 315 375 440 315 315 345 345 345 300 330 330 415 330 I4L VCCL= 0.9 V 225 250 225 250 300 205 205 235 235 235 135 225 225 250 235 Number of Multipliers 1 1 1 1 1 1 1 2 4 2 2 4 4 4 1 VCCL = 1.1 V 440 500 440 500 600 440 440 490 490 490 390 475 475 550 475 VCCL= 1.1 V 345 385 345 385 470 345 345 380 380 380 300 370 370 430 370 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-18 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics TriMatrix Memory Block Specifications Table 1-22 lists the Stratix III TriMatrix Memory Block specifications. Table 1-22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 1 of 3) Memory Block Type C2 (6) Mode Single port 16 x 10 MLAB Simple dual-port 16 20 ROM 64 x 10 ROM 32 x 20 Single-port 8K x 1 Single-port 4K x 2 or 2K x 4 Single-port 1K x 9, 512 x 18, or 256 x 36 Simple dual-port, 8K x 1 Simple dual-port, 4K x 2 or 2K x 4 Simple dual-port, 1K x 9, 512 x 18, or 256 x 36 Simple dual-port, 8K x 1, 4K x 2 or 2K x 4 with read-during-write option set to Old Data Simple dual-port, 1K x 9, 512 x 18, 256 x 36 with read-during-write option set to Old Data True dual-port, 8K x 1 M9K (2) True dual-port, 4K x 2 or 2K x 4 True dual-port, 1K x 9 or 512 x 18 True dual-port, 8K x 1, 4K x 2, or 2K x 4 with read-during-write option set to Old Data True dual-port, 1K x 9 or 512 x 18 with read-during-write option set to Old Data ROM 1P, 8K x 1, 4K x 2, or 2K x 4 ROM 1P, 1K x 9, 512 x 18, or 256 x 36 ROM 2P, 8K x 1, 4K x 2, or 2K x 4 ROM 2P, 1K x 9, or 512 x 18 Min Pulse Width (Clock High Time) Min Pulse Width (Clock Low Time) C3 C4 C4L I3 I4 I4L TriMatrix ALUTs Memory 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VCCL = 1.1 V 600 600 600 600 550 575 565 545 570 565 VCCL = VCCL = VCCL = VCCL = VCCL= VCCL= VCCL= Unit 1.1 V 1.1 V 1.1 V 0.9 V 1.1 V 1.1 V 0.9 V 500 500 500 500 465 485 475 460 480 475 450 450 450 450 390 405 395 385 400 395 450 450 450 450 390 405 395 385 400 395 340 340 370 340 245 255 245 240 250 245 475 475 475 475 440 460 450 435 455 450 450 450 450 450 390 405 395 385 400 395 320 320 350 320 230 230 220 225 225 220 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 0 1 375 312 265 265 205 295 265 185 MHz 0 0 0 0 1 1 1 1 375 530 550 545 312 440 460 460 265 370 385 380 265 370 385 380 200 230 240 235 295 420 435 435 265 370 385 380 180 215 215 210 MHz MHz MHz MHz 0 1 350 295 245 245 175 280 245 160 MHz 0 1 340 285 240 240 165 270 240 150 MHz 0 0 0 0 -- -- 1 1 1 1 -- -- 580 575 580 575 800 500 485 485 485 485 1000 625 405 405 405 405 1100 690 405 405 405 405 1100 690 260 255 265 260 1800 1100 460 460 460 460 1000 625 405 405 405 405 1100 690 235 230 240 235 1800 1100 MHz MHz MHz MHz ps ps Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-19 Table 1-22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 2 of 3) Memory Block Type C2 (6) Mode True dual-port 16K x 9 or 8K x 18 True dual-port 4K x 36 Simple dual-port 16K x 9 or 8K x 18 Simple dual-port 4K x 36 or 2K x 72 ROM 1Port ROM 2 Port M144K (3), (4) Single-port 16K x 9 or 8K x 18 Single-port 4K x 36 True dual-port 16K x 9, 8K x 18, or 4K x 36 with read-during-write option set to Old Data Simple dual-port 16K x 9, 8K x 18, 4K x 36, or 2K x 72 with read-during-write option set to "Old Data" Simple dual-port 2K x 64 (with ECC) Min Pulse Width (Clock High Time) Min Pulse Width (Clock Low Time) True dual-port 16K x 9 or 8K x 18 True dual-port 4K x 36 Simple dual-port 16K x 9 or 8K x 18 Simple dual-port 4K x 36 or 2K x 72 ROM 1Port M144K (3), (5) ROM 2 Port Single-port 16K x 9 or 8K x 18 Single-port 4K x 36 True dual-port 16K x 9, 8K x 18, or 4K x 36 with read-during-write option set to Old Data Simple dual-port 16K x 9, 8K x 18, 4K x 36, or 2K x 72 with read-during-write option set to Old Data C3 C4 C4L I3 I4 I4L ALUTs TriMatrix Memory 1 1 1 1 1 1 1 1 1 VCCL = 1.1 V 350 520 350 565 580 545 385 580 325 VCCL = VCCL = VCCL = VCCL = VCCL= VCCL= VCCL= Unit 1.1 V 1.1 V 1.1 V 0.9 V 1.1 V 1.1 V 0.9 V 300 430 300 470 470 450 330 470 270 245 365 245 395 425 380 270 425 225 245 365 245 395 425 380 270 425 225 180 250 180 225 260 260 240 210 165 280 405 280 440 470 425 310 470 255 245 365 245 395 425 380 270 425 225 170 235 170 210 260 245 195 195 155 MHz MHz MHz MHz MHz MHz MHz MHz MHz 0 0 0 0 0 0 0 0 0 0 1 350 292 250 250 200 275 250 190 MHz 0 -- -- 0 0 0 0 0 0 0 0 0 1 -- -- 1 1 1 1 1 1 1 1 1 255 800 500 425 520 425 565 580 545 475 580 325 210 1000 625 360 430 360 470 470 450 405 470 270 180 1100 690 300 365 300 395 425 380 335 425 225 180 1100 690 300 365 300 395 425 380 335 425 225 130 1800 1100 210 250 210 225 260 260 210 210 165 195 1000 625 340 405 340 440 470 425 380 470 255 180 1100 690 300 365 300 395 425 380 335 425 225 120 1800 1100 195 235 195 210 260 245 195 195 155 MHz ps ps MHz MHz MHz MHz MHz MHz MHz MHz MHz 0 1 350 292 250 250 200 275 250 190 MHz (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-20 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1-22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 3 of 3) Memory Block Type M144K (3), (5) C2 (6) Mode Simple dual-port 2K x 64 (with ECC) Min Pulse Width (Clock High Time) Min Pulse Width (Clock Low Time) C3 C4 C4L I3 I4 I4L ALUTs 0 -- -- TriMatrix Memory 1 -- -- VCCL = 1.1 V 255 800 500 VCCL = VCCL = VCCL = VCCL = VCCL= VCCL= VCCL= Unit 1.1 V 1.1 V 1.1 V 0.9 V 1.1 V 1.1 V 0.9 V 210 1000 625 180 1100 690 180 1100 690 130 1800 1100 195 1000 625 180 1100 690 120 1800 1100 MHz ps ps Notes to Table 1-22: (1) Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block performance. Use the Quartus II software to report timing for this and other memory block clocking schemes. (2) The Fmax shown for M9K degrades 2% when you use the Error Detection CRC feature on the device, except for the C4L speed grade with VCCL = 0.9 V. For the C4L speed grade with VCCL = 0.9V, there is no degradation in Fmax when you use the Error Detection CRC feature. (3) The Fmax shown for M144K degrades 10 MHz when you use byte-enable support on M144K. (4) Fmax is applicable when the COMPTABILITY option is turned ON. (5) Fmax is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in Quartus II software. (6) The Fmax for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table. Configuration and JTAG Specifications Table 1-23 lists the Stratix III configuration mode specifications. Table 1-23. Configuration Mode Specifications for Stratix III Devices (Note 1) Programming Mode Passive Serial Fast Passive Parallel (2) Fast Active Serial (3) Notes to Table 1-23: (1) DCLK Fmax is restricted when you enable the Remote Update feature. For more information, refer to the Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide. (2) The data rate must be 4x slower than the clock when you use decompression and/or encryption. (3) For more information about the minimum and typical DCLK Fmax value in Fast Active Serial configuration, refer to the Configuring Stratix III Devices chapter. DCLK Fmax 100 100 40 Unit MHz MHz MHz Table 1-24 lists the JTAG timing parameters and values for Stratix III devices. Refer to the figure for "HIGH-SPEED I/O Block" in the "Glossary" on page 1-326 for the JTAG timing requirements. Table 1-24. JTAG Timing Parameters and Values for Stratix III Devices Symbol tJCP tJCH tJCL tJPSU (TDI) tJPSU (TMS) tJPH tJPCO tJPZX tJPXZ Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time for TDI JTAG port setup time for TMS JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Min 30 14 14 1 3 5 -- -- -- Max -- -- -- -- -- -- 11 14 14 Unit ns ns ns ns ns ns ns ns ns Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-21 Periphery Performance This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfacing, such as the LVDS high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. For example, Stratix III devices I/O configured with voltage referenced I/O standards can achieve up to the stated system interfacing speed as indicated in "External Memory Interface Specifications" on page 1-25. General-purpose I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS at 100MHz interfacing frequency with 10pF load. 1 Actual achievable frequency depends on design- and system-specific factors. You must perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specifications Refer to the "Glossary" on page 1-326 for the definitions of the high-speed timing specifications. Table 1-25 lists the true and emulated LVDS specifications for Stratix III devices. Table 1-25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 1 of 3) Symbol fHSCLK_in (input clock frequency)--True Differential I/O Standards fHSCLK_in (input clock frequency)--Single Ended I/O Standards (9) fHSCLK_out (output clock frequency) Transmitter Max Max Max Clock boost factor W = 1 to 40 (3) 5 -- 800 5 -- 717 5 -- 717 5 -- 717 Max Min Min Min Min Typ Typ Typ Typ Conditions MHz Clock boost factor W = 1 to 40 (3) 5 -- 800 5 -- 717 5 -- 717 5 -- 717 MHz -- 5 -- 800 (7) 5 -- 717 (7) 5 -- 717 (7) 5 -- 717 (7) MHz SERDES factor J = 3 to 10 (8) SERDES factor J = 2, Uses DDR Register SERDES factor J = 1, Uses SDR Register LVDS_E_3R -fHSDR (data rate) (4) -- 1600 (4) -- 1250 (4) -- 1250 (4) -- 1250 Mbps fHSDR (data rate) (4) -- (4) (4) -- (4) (4) -- (4) (4) -- (4) Mbps (4) -- (4) (4) -- (4) (4) -- (4) (4) -- (4) Mbps SERDES factor J = 4 to 10 (4) -- 1100 (4) -- 1100 (4) -- 800 (4) -- 800 Mbps (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Unit C2 C3, I3 C4, I4 C4L, I4L 1-22 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1-25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 2 of 3) Symbol LVDS_E_1R -fHSDR (data rate) Max Max Max SERDES factor J = 4 to 10 Total Jitter for Data Rate, 600 Mbps - 1.6 Gbps Total Jitter for Data Rate, < 600 Mbps TX output duty cycle for both True and Emulated Differential I/O True Differential I/O Standards Emulated Differential I/O Standards with Three External Output Resistor Network Emulated Differential I/O Standards with One External Output Resistor Network True Differential I/O Standards Emulated Differential I/O Standards (4) -- 311 (4) -- 200 (4) -- 200 (4) -- 200 Max Min Min Min Min Typ Typ Typ Typ Conditions Mbps -- -- 160 -- -- 160 -- -- 160 -- -- 160 ps tx Jitter (5) -- -- 0.1 -- -- 0.1 -- -- 0.1 -- -- 0.1 UI tDUTY 45 50 55 45 50 55 45 50 55 45 50 55 % tRISE & tFALL -- -- 160 -- -- 200 -- -- 200 -- -- 200 ps tRISE & tFALL -- -- 310 -- -- 310 -- -- 350 -- -- 350 ps tRISE & tFALL -- -- 460 -- -- 500 -- -- 500 -- -- 500 ps TCCS -- -- -- -- 100 250 -- -- -- -- 100 250 -- -- -- -- 100 250 -- -- -- -- 100 250 ps ps TCCS Receiver fHSDRDPA (data rate) SERDES factor J = 3 to 10 SERDES factor J = 3 to 10 150 (4) (4) -- -- -- 1600 (6) (6) 150 (4) (4) -- -- -- 1250 (6) (6) 150 (4) (4) -- -- -- 1250 (6) (6) 150 (4) (4) -- -- -- 1250 (6) (6) Mbps Mbps Mbps fHSDR (data rate) SERDES factor J = 2, Uses DDR Registers SERDES factor J = 1, Uses an SDR Register (4) -- (6) (4) -- (6) (4) -- (6) (4) -- (6) Mbps DPA DPA run length Soft CDR mode Soft-CDR PPM tolerance -- -- -- 10000 -- -- 10000 -- -- 10000 -- -- 10000 UI -- -- -- 300 -- -- 300 -- -- 300 -- -- 300 PPM Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Unit C2 C3, I3 C4, I4 C4L, I4L Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-23 Table 1-25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 3 of 3) Symbol Non DPA Mode Sampling Window Notes to Table 1-25: (1) When J = 3 to 10, the SERDES block is used. (2) When J = 1 or 2, the SERDES block is bypassed. (3) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate. (4) The minimum and maximum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate. (5) The txJitter specification is for the true LVDS I/O standard only. (6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. Consider the board skew margin, transmitter delay margin, as well as the receiver sampling margin to determine the maximum data rate supported. (7) This is achieved by using the LVDS and DPA clock network. (8) If the receiver (with DPA enabled) and the transmitter are using shared PLLs, the minimum data rate is 150 Mbps. (9) This is only applied to DPA and Soft-CDR modes. Max Max Max -- -- -- 300 -- -- 300 -- -- 300 -- -- 300 Max Min Min Min Min Typ Typ Typ Typ Conditions ps Table 1-26 lists the DPA lock time specifications for Stratix III devices. Table 1-26. DPA Lock Time Specifications for Stratix III Devices (Note 1), (2), (3) (Part 1 of 2) Number of Number of Data repetitions Transitions per 256 in one Data Repetition Transition of Training (4) Pattern Standard Training Pattern Condition (5) Min Typ Max SPI-4 0000000000 1111111111 without DPA PLL calibration 2 128 with DPA PLL calibration without DPA PLL calibration 256 data transitions 3x256 data transitions + 2x96 slow clock cycles (6) 256 data transitions 3x256 data transitions + 2x96 slow clock cycles (6) 256 data transitions 3x256 data transitions + 2x96 slow clock cycles (6) -- -- -- -- -- -- 00001111 Parallel Rapid I/O 10010000 2 128 with DPA PLL calibration without DPA PLL calibration -- -- -- -- 4 64 with DPA PLL calibration -- -- (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Unit C2 C3, I3 C4, I4 C4L, I4L 1-24 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1-26. DPA Lock Time Specifications for Stratix III Devices (Note 1), (2), (3) (Part 2 of 2) Number of Number of Data repetitions Transitions per 256 in one Data Repetition Transition of Training (4) Pattern Standard Training Pattern Condition (5) Min Typ Max without DPA PLL calibration 10101010 8 32 with DPA PLL calibration without DPA PLL calibration 01010101 8 32 with DPA PLL calibration 256 data transitions 3x256 data transitions + 2x96 slow clock cycles (6) 256 data transitions 3x256 data transitions + 2x96 slow clock cycles (6) -- -- -- -- Miscellaneous -- -- -- -- Notes to Table 1-26: (1) The DPA lock time is for one channel. (2) One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in this table applies to both commercial and industrial grade. (4) These are the number of repetitions for the stated training pattern to achieve 256 data transitions. (5) Altera recommends PLL re-calibration for the situations below to guarantee DPA locking: Sparse data transitions. For example: Repeating sequences of ten 1s and ten 0s. 0 PPM frequency difference and/or 0 phase difference between the clock and data. (6) Slow clock = data rate (Hz)/ Deserialization factor. Figure 1-2 shows the DPA time specification with DPA PLL calibration enabled. Figure 1-2. DPA Lock Time Specification with DPA PLL Calibration Enabled rx_reset DPA Lock Time rx_dpa_locked 256 data transitions 96 slow clock cycles 256 data transitions 96 slow clock cycles 256 data transitions Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-25 Figure 1-3 shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications for Stratix III devices. Figure 1-3. LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for Stratix III Devices Table 1-27 lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for Stratix III devices. Table 1-27. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Stratix III Devices Jitter Frequency (Hz) F1 F2 F3 F4 10,000 17,565 1,493,000 50,000,000 Jitter Amplitude 25.000 25.000 0.350 0.350 Unit UI UI UI UI External Memory Interface Specifications The following sections describe the external memory I/O timing specifications and the DLL and DQS block specifications. f For more information about the maximum clock rate support for external memory interfaces with a half-rate or full-rate controller, refer to Section III: System Performance Specifications of the External Memory Interfaces Handbook. External Memory I/O Timing Specifications Table 1-28 and Table 1-29 list Stratix III device timing uncertainties on the read and write data paths. Use these specifications to determine timing margins for source synchronous paths between the Stratix III FPGA and the external memory device. For more information, refer to the figure for "SW (sampling window)" in the "Glossary" on page 1-326. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-26 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics . Table 1-28. Sampling Window (SW)--Read Side (Note 1) C2 Memory Type I/O Standard VCCL = 1.1 V Width SW (ps) Setup DDR3 SDRAM (with 8 or 10 tap phase offset, 300 MHz-400 MHz) DDR3 SDRAM (with Deskew circuitry, 401 MHz-533 MHz) DDR3 SDRAM (Non-leveling interface) DDR2 SDRAM Differential DQS DDR2 SDRAM Single-ended DQS DDR SDRAM Single-ended DQS QDRII/II+ SRAM QDRII/II+ SRAM Emulation (2) QDRII/II+ SRAM QDRII/II+ SRAM Emulation (2) RLDRAM II RLDRAM II Notes to Table 1-28: (1) The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device. (2) For implementation, refer to the "Supporting x36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages" section in the External Memory Interfaces in Stratix III Devices chapter. C3, I3 VCCL = 1.1 V SW (ps) Setup 234 Hold 296 C4, I4 VCCL = 1.1 V SW (ps) Setup 257 Hold 311 C4L, I4L VCCL = 1.1 V SW (ps) Setup 257 Hold 311 C4L, I4L VCCL = 0.9 V SW (ps) Setup 257 Hold 311 Hold 296 1.5-V SSTL 1.5-V SSTL 1.5-V SSTL 1.8-V SSTL 1.8-V SSTL 2.5-V SSTL 1.5-V HSTL 1.5-V HSTL 1.8-V HSTL 1.8-V HSTL 1.5-V HSTL 1.8-V HSTL x4, x8 172 x4, x8 300 213 -- -- -- -- -- -- -- -- x4, x8 x4, x8 x4, x8 x4, x8 x9, x18, x36 x36 x9, x18, x36 x36 x9, x18 x9, x18 172 181 231 231 261 261 261 261 211 211 296 306 256 256 286 328 286 328 336 336 234 234 284 284 314 314 314 314 264 264 296 326 276 261 291 337 291 337 356 356 257 257 307 307 337 337 337 337 287 287 311 326 276 261 291 350 291 350 356 356 257 257 307 307 337 337 337 337 287 287 311 326 276 261 291 350 291 350 356 356 257 257 307 307 337 337 337 337 287 287 311 326 276 261 291 350 291 350 356 356 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-27 Table 1-29. Transmitter Channel-to-Channel Skew (TCCS)--Write Side (Note 1) (Part 1 of 2) C2 Memory Type I/O Standard VCCL = 1.1 V Width TCCS (ps) Lead DDR3 SDRAM (with Deskew circuitry, 401 MHz-533 MHz) DDR3 SDRAM (8-tap phase offset, 375 MHz-400 MHz) DDR3 SDRAM (8-tap phase offset, 360 MHz-375 MHz) DDR3 SDRAM (10-tap phase offset, 333 MHz-360 MHz) DDR3 SDRAM (10-tap phase offset, 300 MHz-333 MHz) DDR3 SDRAM (Non-leveling interface) DDR2 SDRAM Differential DQS DDR2 SDRAM Single-ended DQS DDR SDRAM Single-ended DQS QDRII/II+ SRAM QDRII/II+ SRAM Emulation (2) 1.5-V SSTL 1.5-V SSTL 1.5-V SSTL 1.5-V SSTL 1.5-V SSTL 1.5-V SSTL 1.8-V SSTL 1.8-V SSTL 2.5-V SSTL 1.5-V HSTL 1.5-V HSTL x4, x8 253 Lag 262 TCCS (ps) Lead -- Lag -- TCCS (ps) Lead -- Lag -- TCCS (ps) Lead -- Lag -- TCCS (ps) Lead -- Lag -- C3, I3 VCCL = 1.1 V C4, I4 VCCL = 1.1 V C4L, I4L VCCL = 1.1 V C4L, I4L VCCL = 0.9 V x4, x8 293 284 341 332 -- -- -- -- -- -- x4, x8 293 284 341 373 -- -- -- -- -- -- x4, x8 169 470 217 496 258 528 258 528 -- -- x4, x8 169 470 217 496 258 528 258 528 -- -- x4, x8 x4, x8 x4, x8 x4, x8 x9, x18, x36 x36 268 229 316 313 290 310 246 246 168 157 278 298 230 230 318 315 292 312 355 355 239 222 388 408 250 250 346 343 315 335 388 388 260 242 421 441 250 250 346 343 315 335 388 388 260 242 421 441 250 350 446 443 415 435 388 488 360 342 521 541 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-28 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Table 1-29. Transmitter Channel-to-Channel Skew (TCCS)--Write Side (Note 1) (Part 2 of 2) C2 Memory Type I/O Standard VCCL = 1.1 V Width TCCS (ps) Lead QDRII/II+ SRAM QDRII/II+ SRAM Emulation (2) RLDRAM II RLDRAM II Notes to Table 1-29: (1) The values apply to Column I/Os, Row I/Os, and Hybrid mode interfaces. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device. (2) For implementation, refer to the "Supporting x36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages" section in the External Memory Interfaces in Stratix III Devices chapter. C3, I3 VCCL = 1.1 V TCCS (ps) Lead 260 280 292 260 Lag 385 405 388 385 C4, I4 VCCL = 1.1 V TCCS (ps) Lead 280 300 315 280 Lag 418 438 421 418 C4L, I4L VCCL = 1.1 V TCCS (ps) Lead 280 300 315 280 Lag 418 438 421 418 C4L, I4L VCCL = 0.9 V TCCS (ps) Lead 380 400 415 380 Lag 518 538 521 518 Lag 276 296 278 276 1.8-V HSTL 1.8-V HSTL 1.5-V HSTL 1.8-V HSTL x9, x18, x36 x36 x9, x18 x9, x18 259 279 290 259 DLL and DQS Logic Block Specifications Table 1-30 lists the DLL frequency range specifications for Stratix III devices. Table 1-30. DLL Frequency Range Specifications for Stratix III Devices Frequency Mode 0 1 2 3 4 5 6 7 Frequency Range (MHz) Available Phase Shift C2 90 - 150 120 - 200 150 - 240 180 - 300 240 - 370 290 - 450 360 - 560 470 - 740 C3, I3 90 - 140 120 - 190 150 - 230 180 - 290 240 - 350 290 - 420 360 - 530 470 - 700 C4, I4 90 - 120 120 - 170 150 - 200 180 - 250 240 - 310 290 - 370 360 - 460 470 - 610 C4L, I4L 90 - 120 120 - 170 150 - 200 180 - 250 240 - 310 290 - 370 360 - 460 470 - 610 22.5, 45, 67.5, 90 30, 60, 90, 120 36, 72, 108, 144 45, 90,135, 180 30, 60, 90,120 36, 72, 108, 144 45, 90, 135, 180 60, 120, 180, 240 Number of Delay Chains 16 12 10 8 12 10 8 6 DQS Delay Buffer Mode (1) Low Low Low Low High High High High Note to Table 1-30: (1) "Low" indicates a 6-bit DQS delay setting; "high" indicates a 5-bit DQS delay setting. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics 1-29 Table 1-31 lists the average DQS phase offset delay per setting for Stratix III devices. Table 1-31. Average DQS Phase Offset Delay per Setting for Stratix III Devices (Note 1), (2), (3) Speed Grade C2 C3, I3 C4, I4 C4L, I4L Notes to Table 1-31: (1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 6. (2) The typical value equals the average of the minimum and maximum values. (3) The delay settings are linear with a cumulative delay variation of 20 ps for all speed grades. For example, when using a C2 speed grade and applying 10 phase offset settings to a 90 phase shift at 400 MHz, the expected minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps. Min 7 7 7 7 Typ 10 11 11.5 11.5 Max 13 15 16 16 Unit ps ps ps ps Table 1-32 lists the DQS phase shift error specification for DLL-delayed clock (tDQS_PSERR) for Stratix III devices. Table 1-32. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Stratix III Devices (Note 1) Number of DQS Delay Buffer 1 2 3 4 Note to Table 1-32: (1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C2 speed grade is 39 ps. C2 13 26 39 52 C3, I3 14 28 42 56 C4, C4L, I4, I4L 15 30 45 60 Unit ps ps ps ps Table 1-33 lists the memory output jitter specification for Stratix III devices. Table 1-33. Memory Output Clock Jitter Specification for Stratix III Devices (Note 1), (2) C2 Parameter Clock Network Regional Regional Regional Global Global Global Symbol VCCL = 1.1V Min Clock period jitter Cycle-to-cycle period jitter Duty cycle jitter Clock period jitter Cycle-to-cycle period jitter Duty cycle jitter Notes to Table 1-33: (1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard. (2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using the regional clock networks whenever possible. C3, I3 VCCL = 1.1V Min -85 -170 -90 -128 -255 -135 Max 85 170 90 128 255 135 C4, I4 VCCL = 1.1V Min -100 -190 -100 -150 -285 -150 Max 100 190 100 150 285 150 C4L, I4L VCCL = 1.1V Min -100 -190 -100 -150 -285 -150 Max 100 190 100 150 285 150 VCCL = 0.9V Min -120 -230 -140 -180 -340 -180 Max 120 230 140 180 340 180 ps ps ps ps ps ps Unit Max 75 150 80 113 225 120 tJIT(per) tJIT(cc) tJIT(duty) tJIT(per) tJIT(cc) -75 -150 -80 -113 -225 tJIT(duty) -120 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-30 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing OCT Calibration Block Specifications Table 1-34 lists the on-chip termination calibration block specifications for Stratix III devices. Table 1-34. On-Chip Termination Calibration Block Specification Symbol OCTUSRCLK tOCTCAL tOCTSHIFT tRS_RT Description Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT Rs and Rt calibration Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration block Time required to dynamically switch from Rs to Rt Min -- -- -- -- Typical -- 1000 28 2.5 Max 20 -- -- -- Unit MHz cycles cycles ns DCD Specifications Table 1-35 lists the worst case duty cycle distortion for Stratix III devices. Table 1-35. Duty Cycle Distortion on Stratix III I/O Pins (Note 1) C2 Symbol Min Output Duty Cycle Note to Table 1-35: (1) The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and general-purpose I/O pins. C3 Max 55 Min 45 Max 55 Min 45 C4 Unit Max 55 % 45 I/O Timing The following sections describe the timing models, preliminary and final timings, I/O timing measurement methodology, I/O default capacitive loading, programmable IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock pin timing. Timing Model The DirectDrive technology and MultiTrack interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix III device densities and speed grades. This section describes the performance of the Stratix III device I/Os. All specifications except the fast model are representative of worst-case supply voltage and junction temperature conditions. Fast model specifications are representative of best case process, supply voltage, and junction temperature conditions. The timing numbers listed in this section are extracted from the Quartus II software version 8.1. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-31 Preliminary and Final Timing Timing models can have either preliminary or final status. The Quartus II software issues an informational message during design compilation if the timing models are preliminary. Table 1-36 lists the status of the Stratix III device timing models. Preliminary status means that the timing models are subject to change in future Quartus II releases. Initially, timing numbers are created using simulation results, process data, and other known parameters. Parts of the timing models may be correlated to silicon measurements. Various tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing models are based on simulation models that are characterized versus the actual device measurements under all allowable operating conditions. When the timing models are final, all or most of the Stratix III family devices have been completely characterized and no further changes to the timing model are expected. Table 1-36. Timing Model Status for Stratix III Devices Device EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260 Preliminary -- -- -- -- -- -- -- -- -- -- Final v v v v v v v v v v I/O Timing Measurement Methodology Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (tsu) and hold time (th). The Quartus II software uses the following equations to calculate tsu and th timing for the Stratix III devices input signals. tsu = + data delay from the input pin to the input register + micro setup time of the input register - clock delay from the input pin to the input register th = - data delay from the input pin to the input register + micro hold time of the input register + clock delay from the input pin to the input register (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-32 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Figure 1-4 shows the setup and hold timing diagram for input registers. Figure 1-4. Input Register Setup and Hold Timing Diagram Input Data Delay micro tsu micro th Input Clock Delay For output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X, which use 10 pF) loading. The timing is specified up to the output pin of the FPGA device. The Quartus II software calculates I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards. The following measurements are made during device characterization. Altera measures clock-to-output delays (tco) at worst-case process, minimum voltage, and maximum temperature (PVT) for default loading conditions listed in Table 1-37 on page 1-34. The following equation describes clock-pin-to-output-pin timing for Stratix III devices. The tco from the clock pin to the I/O pin = + delay from the clock pad to the I/O output register + IOE output register clock-to-output delay + delay from the output register to the output pin Figure 1-5 shows the output register clock to output timing diagram. Figure 1-5. Output Register Clock to Output Timing Diagram Datain Clock Clock pad to output Register delay Output Register micro tCO Output Register to output pin delay Output Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the Stratix III Device Handbook. Perform the following steps: 1. Simulate the output driver of choice into the generalized test setup using values from Table 1-37. 2. Record the time to VMEAS at the far end of the PCB trace. 3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS at the far end of the PCB trace. Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-33 5. Compare the results of steps 2 and 4. The increase or decrease in delay must be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace. The Quartus II software reports the timing with the conditions listed in Table 1-37 using Equation 1-1 on page 1-7. Figure 1-6 shows the circuit that is represented by the output timing of the Quartus II software. Figure 1-6. Output Delay Timing Report Setup for Single-Ended Outputs and Dedicated Differential Outputs (Note 1) VTT VCCIO RT Output Buffer Output Outputp RD RS CL GND VMEAS Outputn GND Note to Figure 1-6: (1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay must be accounted for with IBIS model simulations. Figure 1-7 and Figure 1-8 show the circuit that is represented by the output timing of the Quartus II software for differential outputs with single and multiple external resistors, respectively. Figure 1-7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor Non-Dedicated Differential Outputs VMEAS RP VMEAS RD Figure 1-8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor Non-Dedicated Differential Outputs VMEAS RS RP RD VMEAS RS (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-34 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-37. Output Timing Measurement Methodology for Output Pins (Part 1 of 3) Loading and Termination I/O Standard RS 3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V 1.8-V 1.5-V 1.2-V PCI PCI-X SSTL-2 CLASS I SSTL-2 CLASS II SSTL-18 CLASS I SSTL-18 CLASS II SSTL-15 CLASS I SSTL-15 CLASS II 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II 1.2-V HSTL CLASS I 1.2-V HSTL CLASS II Differential SSTL-2 CLASS I Differential SSTL-2 CLASS II Differential SSTL-18 CLASS I Differential SSTL-18 CLASS II 1.8-V Differential HSTL CLASS I 1.8-V Differential HSTL CLASS II 1.5-V Differential HSTL CLASS I -- -- -- -- -- -- -- -- -- -- 25 25 25 25 25 25 -- -- -- -- -- -- 25 25 25 25 -- -- -- RD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RT -- -- -- -- -- -- -- -- -- -- 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 RP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VCCIO 3.135 3.135 2.85 2.85 2.375 1.71 1.425 1.14 2.85 2.85 2.325 2.325 1.66 1.66 1.375 1.375 1.66 1.66 1.375 1.375 1.09 1.09 2.325 2.325 1.66 1.66 1.66 1.66 1.375 VCCPD 3.135 3.135 2.85 2.85 2.375 2.375 2.375 2.375 2.85 2.85 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 VCC 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.05 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 VTT -- -- -- -- -- -- -- -- -- -- 1.25 1.25 0.90 0.90 0.75 0.75 0.90 0.90 0.75 0.75 0.60 0.60 1.25 1.25 0.90 0.90 0.90 0.90 0.75 CL (pF) 0 0 0 0 0 0 0 0 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Measurement Point VMEAS (v) 1.5675 1.5675 1.425 1.425 1.1875 0.855 0.7125 0.57 1.425 1.425 1.1625 1.1625 0.83 0.83 0.6875 0.6875 0.83 0.83 0.6875 0.6875 0.545 0.545 1.1625 1.1625 0.83 0.83 0.83 0.83 0.6875 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-35 Table 1-37. Output Timing Measurement Methodology for Output Pins (Part 2 of 3) Loading and Termination I/O Standard RS 1.5-V Differential HSTL CLASS II 1.2-V Differential HSTL CLASS I 1.2-V Differential HSTL CLASS II LVDS MINI-LVDS RSDS LVDS_E_1R LVDS_E_3R -- -- -- -- -- -- -- 120 RD -- -- -- 100 100 100 100 100 RT 25 50 25 -- -- -- -- -- RP -- -- -- -- -- -- 120 170 VCCIO 1.375 1.09 1.09 2.325 2.325 2.325 2.325 2.325 VCCPD 2.325 2.325 2.325 2.325 2.325 2.325 2.325 2.325 VCC 1.02 1.02 1.02 1.02 1.02 1.02 1.02 1.02 VTT 0.75 0.60 0.60 -- -- -- -- -- CL (pF) 0 0 0 0 0 0 0 0 Measurement Point VMEAS (v) 0.6875 0.545 0.545 1.1625 1.1625 1.1625 1.1625 1.1625 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-36 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3) Loading and Termination I/O Standard RS MINI-LVDS_E_1R MINI-LVDS_E_3R RSDS_E_1R RSDS_E_3R Notes to Table 1-37: (1) Hyper transport is not supported by Stratix III devices. (2) LVPECL outputs are not supported by Stratix III devices. (3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature. (4) VCC is nominally 1.1 V less 50 mV (1.05 V). (5) Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V). (6) Terminated I/O standards require an additional 50 mV IR drop on VCCIO and VCCPD. Measurement Point VCC 1.02 1.02 1.02 1.02 VTT -- -- -- -- CL (pF) 0 0 0 0 VMEAS (v) 1.1625 1.1625 1.1625 1.1625 RD 100 100 100 100 RT -- -- -- -- RP 120 170 120 170 VCCIO 2.325 2.325 2.325 2.325 VCCPD 2.325 2.325 2.325 2.325 -- 120 -- 120 I/O Default Capacitive Loading Table 1-38 lists the default capacitive loading of various I/O standards. Table 1-38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2) I/O Standard 3.3-V LVTTL 3.3-V LVCMOS 3.0-V LVTTL 3.0-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVTTL/LVCMOS 3.0-V PCI 3.0-V PCI-X SSTL-2 CLASS I SSTL-2 CLASS II SSTL-18 CLASS I SSTL-18 CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.2-V HSTL Differential SSTL-2 CLASS I Differential SSTL-2 CLASS II Differential SSTL-18 CLASS I Capacitive Load 0 0 0 0 0 0 0 10 10 0 0 0 0 0 0 0 0 0 0 0 0 Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-37 Table 1-38. Default Loading of Various I/O Standards for Stratix III Devices (Part 2 of 2) I/O Standard Differential SSTL-18 CLASS II 1.8-V Differential HSTL CLASS I 1.8-V Differential HSTL CLASS II 1.5-V Differential HSTL CLASS I 1.5-V Differential HSTL CLASS II 1.2-V Differential HSTL CLASS I 1.2-V Differential HSTL CLASS II LVDS Capacitive Load 0 0 0 0 0 0 0 0 Unit pF pF pF pF pF pF pF pF Programmable IOE Delay Table 1-39 lists the Stratix III IOE programmable delay settings. f For more information about the annotation of delays in the IOE, refer to Figure 7-7 in the Stratix III Device I/O Features chapter. Table 1-39. IOE Programmable Delay for Stratix III Devices (Note 1) Fast Model Commercial Min Offset (2) Industrial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V 833 411 3084 808 850 339 Parameter Available Settings Unit Max Max Max Max Max Max Max Max Max Max Max Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset D1 D2 D3 D4 D5 D6 15 7 7 15 15 6 0 0 0 0 0 0 442 248 1625 491 452 179 491 285 1806 517 503 199 748 387 2747 726 764 305 829 412 3058 872 801 337 916 442 3371 884 930 370 871 427 3218 844 887 354 833 411 3084 808 850 339 870 433 3210 845 889 354 957 464 3540 928 977 389 915 448 3382 887 932 371 ps ps ps ps ps ps Notes to Table 1-39: (1) You can set the parameter values in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column. (2) The minimum offset represented in this table does not include the intrinsic delay. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-38 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Programmable Output Buffer Delay Table 1-40 lists the delay chain settings that control the rising and falling edge delays of the output buffer. The default delay is 0 ps. Table 1-40. Programmable Output Buffer Delay (Note 1) Symbol Parameter Typical 0 (default) DOUTBUF Rising and/or Falling Edge delay 50 100 150 Note to Table 1-40: (1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges with the specific values stated in this table for the Output Buffer Delay assignment. Unit ps ps ps ps User I/O Pin Timing Table 1-41 through Table 1-140 list user I/O pin timing for Stratix III devices. I/O buffer tsu, th, and tco are reported for the cases when the I/O clock is driven by a non-PLL global clock (GCLK) and the PLL is driven by the global clock (GCLK-PLL). For tsu, th, and tco using the regional clock, add the value from the adder tables listed for each device to the GCLK/GCLK-PLL values for the device. EP3SL50 I/O Timing Parameters Table 1-41 through Table 1-44 list the maximum I/O timing parameters for EP3SL50 devices for single-ended I/O standards. Table 1-41 lists the EP3SL50 column pins input timing parameters for single-ended I/O standards. Table 1-41. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th -0.690 0.816 -0.975 1.226 -0.690 0.816 -0.975 1.226 -0.701 0.827 -0.986 1.237 -0.689 0.814 -0.975 1.226 -0.689 0.814 -0.975 1.226 -0.700 0.825 -0.986 1.237 -1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627 1.182 1.774 1.182 1.774 1.181 1.773 1.304 1.947 1.304 1.947 1.306 1.949 1.531 2.232 1.531 2.232 1.530 2.231 1.475 2.148 1.475 2.148 1.474 2.147 1.830 2.471 1.830 2.471 1.829 2.470 1.304 1.947 1.304 1.947 1.306 1.949 1.531 2.232 1.531 2.232 1.530 2.231 1.475 2.148 1.475 2.148 1.474 2.147 1.830 2.471 1.830 2.471 1.829 2.470 -1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026 -1.004 -1.103 -1.311 -1.266 -1.627 -1.103 -1.311 -1.266 -1.627 -1.405 -1.532 -1.773 -1.713 -2.026 -1.532 -1.773 -1.713 -2.026 -1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626 -1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772 -1.712 -2.025 GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-39 Table 1-41. EP3SL50 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK 3.0-V LVCMOS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.701 0.827 -0.986 1.237 -0.696 0.822 -0.981 1.232 -0.716 0.844 -1.003 1.256 -0.706 0.834 -0.993 1.246 -0.654 0.782 -0.941 1.194 -0.625 0.753 -0.912 1.165 -0.625 0.753 -0.912 1.165 -0.619 0.747 -0.906 1.159 -0.619 0.747 -0.906 1.159 -0.700 0.825 -0.986 1.237 -0.695 0.820 -0.981 1.232 -0.715 0.842 -1.003 1.256 -0.705 0.832 -0.993 1.246 -0.653 0.780 -0.941 1.194 -0.624 0.751 -0.912 1.165 -0.624 0.751 -0.912 1.165 -0.618 0.745 -0.906 1.159 -0.618 0.745 -0.906 1.159 -1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626 1.181 1.773 1.190 1.782 1.230 1.822 1.207 1.799 1.130 1.722 1.102 1.694 1.102 1.694 1.089 1.681 1.089 1.681 1.306 1.949 1.318 1.961 1.354 1.997 1.322 1.965 1.223 1.866 1.207 1.850 1.207 1.850 1.199 1.839 1.199 1.839 1.530 2.231 1.549 2.250 1.547 2.248 1.477 2.178 1.321 2.022 1.323 2.024 1.323 2.024 1.320 2.018 1.320 2.018 1.474 2.147 1.493 2.166 1.491 2.164 1.421 2.094 1.265 1.938 1.267 1.940 1.267 1.940 1.264 1.934 1.264 1.934 1.829 2.470 1.848 2.489 1.846 2.487 1.776 2.417 1.620 2.261 1.622 2.263 1.622 2.263 1.615 2.256 1.615 2.256 1.306 1.949 1.318 1.961 1.354 1.997 1.322 1.965 1.223 1.866 1.207 1.850 1.207 1.850 1.199 1.839 1.199 1.839 1.530 2.231 1.549 2.250 1.547 2.248 1.477 2.178 1.321 2.022 1.323 2.024 1.323 2.024 1.320 2.018 1.320 2.018 1.474 2.147 1.493 2.166 1.491 2.164 1.421 2.094 1.265 1.938 1.267 1.940 1.267 1.940 1.264 1.934 1.264 1.934 1.829 2.470 1.848 2.489 1.846 2.487 1.776 2.417 1.620 2.261 1.622 2.263 1.622 2.263 1.615 2.256 1.615 2.256 -1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772 -1.712 -2.025 -1.012 -1.117 -1.329 -1.284 -1.645 -1.117 -1.329 -1.284 -1.645 -1.413 -1.546 -1.791 -1.731 -2.044 -1.546 -1.791 -1.731 -2.044 -1.052 -1.153 -1.327 -1.282 -1.643 -1.153 -1.327 -1.282 -1.643 -1.453 -1.582 -1.789 -1.729 -2.042 -1.582 -1.789 -1.729 -2.042 -1.029 -1.121 -1.257 -1.212 -1.573 -1.121 -1.257 -1.212 -1.573 -1.430 -1.550 -1.719 -1.659 -1.972 -1.550 -1.719 -1.659 -1.972 -0.952 -1.022 -1.101 -1.056 -1.417 -1.022 -1.101 -1.056 -1.417 -1.353 -1.451 -1.563 -1.503 -1.816 -1.451 -1.563 -1.503 -1.816 -0.924 -1.006 -1.103 -1.058 -1.419 -1.006 -1.103 -1.058 -1.419 -1.325 -1.435 -1.565 -1.505 -1.818 -1.435 -1.565 -1.505 -1.818 -0.924 -1.006 -1.103 -1.058 -1.419 -1.006 -1.103 -1.058 -1.419 -1.325 -1.435 -1.565 -1.505 -1.818 -1.435 -1.565 -1.505 -1.818 -0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103 -1.056 -1.417 -1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562 -1.500 -1.816 -0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103 -1.056 -1.417 -1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562 -1.500 -1.816 GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-40 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-41. EP3SL50 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK SSTL-15 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.608 0.736 -0.895 1.148 -0.608 0.736 -0.895 1.148 -0.619 0.747 -0.906 1.159 -0.619 0.747 -0.906 1.159 -0.608 0.736 -0.895 1.148 -0.608 0.736 -0.895 1.148 -0.596 0.724 -0.883 1.136 -0.596 0.724 -0.883 1.136 -0.701 0.827 -0.986 1.237 -0.607 0.734 -0.895 1.148 -0.607 0.734 -0.895 1.148 -0.618 0.745 -0.906 1.159 -0.618 0.745 -0.906 1.159 -0.607 0.734 -0.895 1.148 -0.607 0.734 -0.895 1.148 -0.595 0.722 -0.883 1.136 -0.595 0.722 -0.883 1.136 -0.700 0.825 -0.986 1.237 -0.903 -0.990 -1.084 -1.037 -1.398 -0.990 -1.084 -1.037 -1.398 1.079 1.669 1.079 1.669 1.089 1.681 1.089 1.681 1.079 1.669 1.079 1.669 1.069 1.659 1.069 1.659 1.181 1.773 1.188 1.828 1.188 1.828 1.199 1.839 1.199 1.839 1.188 1.828 1.188 1.828 1.177 1.817 1.177 1.817 1.306 1.949 1.301 1.999 1.301 1.999 1.320 2.018 1.320 2.018 1.301 1.999 1.301 1.999 1.285 1.983 1.285 1.983 1.530 2.231 1.245 1.915 1.245 1.915 1.264 1.934 1.264 1.934 1.245 1.915 1.245 1.915 1.229 1.899 1.229 1.899 1.474 2.147 1.596 2.237 1.596 2.237 1.615 2.256 1.615 2.256 1.596 2.237 1.596 2.237 1.580 2.221 1.580 2.221 1.829 2.470 1.188 1.828 1.188 1.828 1.199 1.839 1.199 1.839 1.188 1.828 1.188 1.828 1.177 1.817 1.177 1.817 1.306 1.949 1.301 1.999 1.301 1.999 1.320 2.018 1.320 2.018 1.301 1.999 1.301 1.999 1.285 1.983 1.285 1.983 1.530 2.231 1.245 1.915 1.245 1.915 1.264 1.934 1.264 1.934 1.245 1.915 1.245 1.915 1.229 1.899 1.229 1.899 1.474 2.147 1.596 2.237 1.596 2.237 1.615 2.256 1.615 2.256 1.596 2.237 1.596 2.237 1.580 2.221 1.580 2.221 1.829 2.470 -1.301 -1.416 -1.543 -1.481 -1.797 -1.416 -1.543 -1.481 -1.797 -0.903 -0.990 -1.084 -1.037 -1.398 -0.990 -1.084 -1.037 -1.398 -1.301 -1.416 -1.543 -1.481 -1.797 -1.416 -1.543 -1.481 -1.797 -0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103 -1.056 -1.417 -1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562 -1.500 -1.816 -0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103 -1.056 -1.417 -1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562 -1.500 -1.816 -0.903 -0.990 -1.084 -1.037 -1.398 -0.990 -1.084 -1.037 -1.398 -1.301 -1.416 -1.543 -1.481 -1.797 -1.416 -1.543 -1.481 -1.797 -0.903 -0.990 -1.084 -1.037 -1.398 -0.990 -1.084 -1.037 -1.398 -1.301 -1.416 -1.543 -1.481 -1.797 -1.416 -1.543 -1.481 -1.797 -0.893 -0.979 -1.068 -1.021 -1.382 -0.979 -1.068 -1.021 -1.382 -1.291 -1.405 -1.527 -1.465 -1.781 -1.405 -1.527 -1.465 -1.781 -0.893 -0.979 -1.068 -1.021 -1.382 -0.979 -1.068 -1.021 -1.382 -1.291 -1.405 -1.527 -1.465 -1.781 -1.405 -1.527 -1.465 -1.781 -1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310 -1.265 -1.626 -1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772 -1.712 -2.025 GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II 1.2-V HSTL CLASS I 1.2-V HSTL CLASS II 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-41 Table 1-42 lists the EP3SL50 row pins input timing parameters for single-ended I/O standards. Table 1-42. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial -0.884 0.997 0.910 -0.661 -0.884 0.997 0.910 -0.661 -0.890 1.003 0.904 -0.655 -0.890 1.003 0.904 -0.655 -0.878 0.991 0.916 -0.667 -0.940 0.930 1.054 -0.930 0.940 1.044 -0.870 1.000 0.984 -0.821 0.973 0.935 Commercial -0.914 1.040 0.917 -0.656 -0.914 1.040 0.917 -0.656 -0.925 1.051 0.906 -0.645 -0.925 1.051 0.906 -0.645 -0.918 1.044 0.913 -0.652 -0.982 0.925 1.109 -0.971 0.936 1.098 -0.918 0.989 1.045 -0.860 0.971 0.987 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 1.554 1.476 1.774 1.619 1.924 1.864 1.808 1.796 1.834 2.057 1.768 1.645 1.931 1.878 1.777 1.814 1.885 2.090 GCLK PLL GCLK -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 1.554 1.476 1.473 1.557 1.473 1.482 1.548 1.482 1.551 1.554 1.551 1.575 1.530 1.654 1.451 1.634 1.396 1.692 1.413 -1.228 1.774 1.619 1.620 1.773 1.620 1.633 1.760 1.633 1.770 1.698 1.770 1.802 1.666 1.903 1.565 1.869 1.524 1.924 1.864 1.867 1.921 1.867 1.882 1.906 1.882 1.914 1.914 1.914 1.982 1.846 2.141 1.687 2.126 1.662 1.808 1.796 1.799 1.805 1.799 1.814 1.790 1.814 1.799 1.845 1.799 1.867 1.777 2.026 1.618 2.010 1.594 1.834 2.057 2.060 1.831 2.060 2.075 1.816 2.075 1.828 2.111 1.828 1.896 2.043 2.055 1.884 2.036 1.855 1.768 1.645 1.644 1.769 1.644 1.653 1.760 1.653 1.772 1.718 1.772 1.803 1.687 1.899 1.591 1.872 1.541 1.931 1.878 1.883 1.926 1.883 1.893 1.916 1.893 1.922 1.928 1.922 1.987 1.863 2.142 1.708 2.133 1.676 1.777 1.814 1.819 1.772 1.819 1.829 1.762 1.829 1.804 1.862 1.804 1.869 1.797 2.024 1.642 1.979 1.612 1.885 2.090 2.095 1.880 2.095 2.105 1.870 2.105 1.879 2.141 1.879 1.944 2.076 2.099 1.921 2.087 1.888 3.3-V LVCMOS GCLK PLL GCLK -1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 -1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS -1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890 GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V -1.369 -1.491 -1.684 -1.629 -1.895 -1.501 -1.688 -1.635 -1.926 GCLK PLL GCLK 1.5 V -1.345 -1.459 -1.616 -1.561 -1.827 -1.470 -1.623 -1.570 -1.861 -1.266 -1.358 -1.457 -1.402 -1.668 -1.374 -1.468 -1.415 -1.706 GCLK PLL GCLK 1.2 V -1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699 1.536 1.930 1.680 2.146 1.611 2.032 1.876 2.059 1.557 1.931 1.698 2.149 1.633 2.032 1.910 2.106 GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-42 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-42. EP3SL50 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial -0.821 0.973 0.935 -0.844 1.026 0.958 -0.844 1.026 0.958 -0.830 1.040 0.944 -0.844 1.026 0.958 -0.844 1.026 0.958 -0.830 1.040 0.944 -0.830 1.040 0.944 -0.821 1.049 0.935 -0.821 1.049 0.935 -0.890 1.003 0.904 -0.655 -0.890 1.003 Commercial -0.860 0.971 0.987 -0.883 1.024 1.010 -0.883 1.024 1.010 -0.871 1.036 0.998 -0.883 1.024 1.010 -0.883 1.024 1.010 -0.871 1.036 0.998 -0.871 1.036 0.998 -0.859 1.048 0.986 -0.859 1.048 0.986 -0.925 1.051 0.906 -0.645 -0.925 1.051 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK SSTL-2 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.692 1.413 1.692 1.413 1.930 2.146 2.032 2.059 1.931 2.149 2.032 2.106 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632 1.536 1.930 1.680 2.146 1.611 2.032 1.876 2.059 1.557 1.931 1.698 2.149 1.633 2.032 1.910 2.106 GCLK PLL GCLK -1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699 SSTL-2 CLASS II -1.228 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632 -1.309 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682 -1.213 1.399 1.692 1.413 1.692 1.413 -1.228 -1.309 1.399 1.707 -1.309 -1.318 1.390 1.716 -1.318 -1.318 1.557 1.473 -1.288 1.557 1.473 1.473 1.473 1.526 1.940 1.940 1.662 2.164 2.164 1.593 2.050 2.050 1.858 2.077 2.077 1.546 1.942 1.942 1.681 2.166 2.166 1.616 2.049 2.049 1.893 2.123 2.123 GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699 1.536 1.930 1.680 2.146 1.611 2.032 1.876 2.059 1.557 1.931 1.698 2.149 1.633 2.032 1.910 2.106 -1.228 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682 SSTL-18 CLASS II GCLK PLL GCLK -1.213 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699 1.536 1.930 1.940 1.680 2.146 2.164 1.611 2.032 2.050 1.876 2.059 2.077 1.557 1.931 1.942 1.698 2.149 2.166 1.633 2.032 2.049 1.910 2.106 2.123 SSTL-15 CLASS I GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL -1.213 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632 -1.204 -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682 1.526 1.940 1.950 1.662 2.164 2.180 1.593 2.050 2.066 1.858 2.077 2.093 1.546 1.942 1.951 1.681 2.166 2.182 1.616 2.049 2.065 1.893 2.123 2.139 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II -1.204 -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649 -1.288 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666 1.516 1.950 1.646 2.180 1.577 2.066 1.842 2.093 1.537 1.951 1.665 2.182 1.600 2.065 1.877 2.139 1.5-V HSTL CLASS I -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666 1.516 1.950 1.646 2.180 1.577 2.066 1.842 2.093 1.537 1.951 1.665 2.182 1.600 2.065 1.877 2.139 1.5-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-43 Table 1-42. EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial 0.904 -0.655 -0.884 0.997 0.910 -0.661 -0.884 0.997 0.910 -0.661 -0.890 1.003 0.904 -0.655 -0.890 1.003 Commercial 0.906 -0.645 -0.914 1.040 0.917 -0.656 -0.914 1.040 0.917 -0.656 -0.925 1.051 0.906 -0.645 -0.925 1.051 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.473 1.473 1.554 1.476 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666 1.774 1.619 1.924 1.864 1.808 1.796 1.834 2.057 1.768 1.645 1.931 1.878 1.777 1.814 1.885 2.090 -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 1.2-V HSTL CLASS II -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 -1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 1.554 1.476 1.473 1.557 1.473 1.482 1.774 1.619 1.620 1.773 1.620 1.633 1.924 1.864 1.867 1.921 1.867 1.882 1.808 1.796 1.799 1.805 1.799 1.814 1.834 2.057 2.060 1.831 2.060 2.075 1.768 1.645 1.644 1.769 1.644 1.653 1.931 1.878 1.883 1.926 1.883 1.893 1.777 1.814 1.819 1.772 1.819 1.829 1.885 2.090 2.095 1.880 2.095 2.105 3.0-V PCI -1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 -1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 GCLK PLL GCLK 3.0-V PCI-X GCLK PLL -1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-44 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-43 lists the EP3SL50 column pins output timing parameters for single-ended I/O standards. Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.168 3.524 3.101 3.457 3.015 3.371 3.008 3.364 3.174 3.530 3.019 3.375 3.026 3.382 3.010 3.366 3.132 3.488 3.021 3.377 2.985 3.341 2.967 3.323 3.156 3.524 3.089 3.457 3.003 3.371 2.996 3.364 3.162 3.530 3.007 3.375 3.014 3.382 2.998 3.366 3.120 3.488 3.009 3.377 2.973 3.341 2.955 3.323 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.382 4.905 4.273 4.796 4.170 4.692 4.153 4.675 4.387 4.909 4.180 4.702 4.174 4.696 4.151 4.674 4.349 4.872 4.219 4.742 4.156 4.679 4.127 4.650 4.742 5.210 5.304 5.820 4.631 5.097 5.193 5.707 4.532 5.005 5.094 5.615 4.504 4.964 5.066 5.574 4.747 5.217 5.309 5.827 4.549 5.016 5.111 5.626 4.528 4.990 5.090 5.600 4.503 4.961 5.065 5.571 4.710 5.177 5.272 5.787 4.576 5.040 5.138 5.650 4.507 4.966 5.069 5.576 4.479 4.937 5.041 5.547 5.092 5.677 4.979 5.564 4.887 5.472 4.846 5.431 5.099 5.684 4.898 5.483 4.872 5.457 4.843 5.428 5.059 5.644 4.923 5.508 4.849 5.434 4.819 5.404 5.294 5.944 5.181 5.831 5.089 5.739 5.048 5.698 5.301 5.951 5.100 5.750 5.074 5.724 5.045 5.695 5.261 5.911 5.122 5.773 5.049 5.699 5.021 5.671 4.742 5.304 4.631 5.193 4.532 5.094 4.504 5.066 4.747 5.309 4.549 5.111 4.528 5.090 4.503 5.065 4.710 5.272 4.576 5.138 4.507 5.069 4.479 5.041 5.210 5.092 5.820 5.677 5.097 4.979 5.707 5.564 5.005 4.887 5.615 5.472 4.964 4.846 5.574 5.431 5.217 5.099 5.827 5.684 5.016 4.898 5.626 5.483 4.990 4.872 5.600 5.457 4.961 4.843 5.571 5.428 5.177 5.059 5.787 5.644 5.040 4.923 5.650 5.508 4.966 4.849 5.576 5.434 4.937 4.819 5.547 5.404 5.294 5.944 5.181 5.831 5.089 5.739 5.048 5.698 5.301 5.951 5.100 5.750 5.074 5.724 5.045 5.695 5.261 5.911 5.122 5.773 5.049 5.699 5.021 5.671 4mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-45 Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.046 3.402 2.967 3.323 2.962 3.318 2.953 3.309 3.168 3.524 3.068 3.424 3.024 3.380 2.986 3.342 3.034 3.402 2.955 3.323 2.950 3.318 2.941 3.309 3.156 3.524 3.056 3.424 3.012 3.380 2.974 3.342 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.253 4.776 4.130 4.652 4.122 4.645 4.108 4.631 4.460 4.983 4.341 4.864 4.254 4.777 4.215 4.738 4.610 5.075 5.172 5.685 4.481 4.940 5.043 5.550 4.474 4.931 5.036 5.541 4.459 4.916 5.021 5.526 4.837 5.322 5.399 5.932 4.711 5.190 5.273 5.800 4.620 5.094 5.182 5.704 4.578 5.051 5.140 5.661 4.958 5.543 4.823 5.408 4.813 5.398 4.798 5.383 5.205 5.790 5.073 5.658 4.976 5.561 4.933 5.518 5.157 5.808 5.022 5.673 5.015 5.665 5.000 5.650 5.405 6.055 5.272 5.923 5.178 5.828 5.135 5.785 4.610 5.172 4.481 5.043 4.474 5.036 4.459 5.021 4.837 5.399 4.711 5.273 4.620 5.182 4.578 5.140 5.075 4.958 5.685 5.543 4.940 4.823 5.550 5.408 4.931 4.813 5.541 5.398 4.916 4.798 5.526 5.383 5.322 5.205 5.932 5.790 5.190 5.073 5.800 5.658 5.094 4.976 5.704 5.561 5.051 4.933 5.661 5.518 5.157 5.808 5.022 5.673 5.015 5.665 5.000 5.650 5.405 6.055 5.272 5.923 5.178 5.828 5.135 5.785 4mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-46 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.359 3.715 3.178 3.534 3.096 3.452 3.076 3.432 3.013 3.369 2.995 3.351 3.305 3.661 3.093 3.449 3.068 3.424 3.057 3.413 3.002 3.358 2.997 3.353 3.347 3.715 3.166 3.534 3.084 3.452 3.064 3.432 3.001 3.369 2.983 3.351 3.293 3.661 3.081 3.449 3.056 3.424 3.045 3.413 2.990 3.358 2.985 3.353 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.782 5.304 4.503 5.025 4.396 4.918 4.337 4.860 4.276 4.799 4.256 4.778 4.710 5.233 4.391 4.914 4.324 4.847 4.307 4.830 4.269 4.792 4.253 4.775 5.197 5.726 5.759 6.336 4.888 5.379 5.450 5.989 4.773 5.268 5.335 5.878 4.719 5.202 5.281 5.812 4.644 5.121 5.206 5.731 4.623 5.098 5.185 5.708 5.129 5.664 5.691 6.274 4.773 5.272 5.335 5.882 4.713 5.205 5.275 5.815 4.688 5.185 5.250 5.795 4.637 5.115 5.199 5.725 4.626 5.104 5.188 5.714 5.608 6.193 5.262 5.847 5.150 5.735 5.084 5.669 5.003 5.588 4.980 5.565 5.546 6.131 5.154 5.739 5.087 5.672 5.067 5.652 4.997 5.582 4.986 5.571 5.810 6.460 5.461 6.112 5.352 6.002 5.286 5.936 5.205 5.855 5.182 5.832 5.748 6.398 5.356 6.006 5.289 5.939 5.269 5.919 5.199 5.849 5.188 5.838 5.197 5.759 4.888 5.450 4.773 5.335 4.719 5.281 4.644 5.206 4.623 5.185 5.129 5.691 4.773 5.335 4.713 5.275 4.688 5.250 4.637 5.199 4.626 5.188 5.726 5.608 6.336 6.193 5.379 5.262 5.989 5.847 5.268 5.150 5.878 5.735 5.202 5.084 5.812 5.669 5.121 5.003 5.731 5.588 5.098 4.980 5.708 5.565 5.664 5.546 6.274 6.131 5.272 5.154 5.882 5.739 5.205 5.087 5.815 5.672 5.185 5.067 5.795 5.652 5.115 4.997 5.725 5.582 5.104 4.986 5.714 5.571 5.810 6.460 5.461 6.112 5.352 6.002 5.286 5.936 5.205 5.855 5.182 5.832 5.748 6.398 5.356 6.006 5.289 5.939 5.269 5.919 5.199 5.849 5.188 5.838 2mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-47 Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.221 3.577 3.098 3.454 3.060 3.416 3.013 3.369 3.013 3.369 3.010 3.366 3.008 3.364 2.999 3.355 3.020 3.376 3.016 3.372 3.005 3.361 2.994 3.350 2.994 3.350 3.209 3.577 3.086 3.454 3.048 3.416 3.001 3.369 3.001 3.369 2.998 3.366 2.996 3.364 2.987 3.355 3.008 3.376 3.004 3.372 2.993 3.361 2.982 3.350 2.982 3.350 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.636 5.159 4.411 4.933 4.318 4.841 4.290 4.813 4.247 4.770 4.244 4.767 4.244 4.767 4.230 4.752 4.259 4.782 4.257 4.780 4.247 4.770 4.235 4.757 4.234 4.757 5.065 5.608 5.627 6.218 4.803 5.322 5.365 5.932 4.714 5.209 5.276 5.819 4.665 5.153 5.227 5.763 4.612 5.084 5.174 5.694 4.609 5.080 5.171 5.690 4.610 5.081 5.172 5.691 4.594 5.066 5.156 5.676 4.626 5.100 5.188 5.710 4.624 5.098 5.186 5.708 4.615 5.089 5.177 5.699 4.602 5.076 5.164 5.686 4.602 5.076 5.164 5.686 5.490 6.075 5.204 5.789 5.091 5.676 5.035 5.620 4.966 5.551 4.962 5.547 4.963 5.548 4.948 5.533 4.982 5.567 4.980 5.565 4.971 5.556 4.958 5.543 4.958 5.543 5.692 6.342 5.406 6.056 5.293 5.943 5.237 5.887 5.168 5.818 5.164 5.814 5.165 5.815 5.150 5.800 5.184 5.834 5.182 5.832 5.173 5.823 5.160 5.810 5.160 5.810 5.065 5.627 4.803 5.365 4.714 5.276 4.665 5.227 4.612 5.174 4.609 5.171 4.610 5.172 4.594 5.156 4.626 5.188 4.624 5.186 4.615 5.177 4.602 5.164 4.602 5.164 5.608 5.490 6.218 6.075 5.322 5.204 5.932 5.789 5.209 5.091 5.819 5.676 5.153 5.035 5.763 5.620 5.084 4.966 5.694 5.551 5.080 4.962 5.690 5.547 5.081 4.963 5.691 5.548 5.066 4.948 5.676 5.533 5.100 4.982 5.710 5.567 5.098 4.980 5.708 5.565 5.089 4.971 5.699 5.556 5.076 4.958 5.686 5.543 5.076 4.958 5.686 5.543 5.692 6.342 5.406 6.056 5.293 5.943 5.237 5.887 5.168 5.818 5.164 5.814 5.165 5.815 5.150 5.800 5.184 5.834 5.182 5.832 5.173 5.823 5.160 5.810 5.160 5.810 2mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-48 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.000 3.356 3.003 3.359 3.024 3.380 3.010 3.366 2.999 3.355 2.998 3.354 2.995 3.351 2.997 3.353 3.000 3.356 2.988 3.356 2.991 3.359 3.012 3.380 2.998 3.366 2.987 3.355 2.986 3.354 2.983 3.351 2.985 3.353 2.988 3.356 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.233 4.756 4.241 4.764 4.269 4.791 4.258 4.781 4.245 4.767 4.248 4.770 4.242 4.765 4.231 4.754 4.238 4.761 4.599 5.071 5.161 5.681 4.608 5.083 5.170 5.693 4.638 5.113 5.200 5.723 4.628 5.104 5.190 5.714 4.614 5.090 5.176 5.700 4.617 5.094 5.179 5.704 4.612 5.088 5.174 5.698 4.598 5.071 5.160 5.681 4.607 5.082 5.169 5.692 4.953 5.538 4.965 5.550 4.995 5.580 4.986 5.571 4.972 5.557 4.976 5.561 4.970 5.555 4.953 5.538 4.964 5.549 5.155 5.805 5.167 5.817 5.197 5.847 5.188 5.838 5.174 5.824 5.178 5.828 5.172 5.822 5.155 5.805 5.166 5.816 4.599 5.161 4.608 5.170 4.638 5.200 4.628 5.190 4.614 5.176 4.617 5.179 4.612 5.174 4.598 5.160 4.607 5.169 5.071 4.953 5.681 5.538 5.083 4.965 5.693 5.550 5.113 4.995 5.723 5.580 5.104 4.986 5.714 5.571 5.090 4.972 5.700 5.557 5.094 4.976 5.704 5.561 5.088 4.970 5.698 5.555 5.071 4.953 5.681 5.538 5.082 4.964 5.692 5.549 5.155 5.805 5.167 5.817 5.197 5.847 5.188 5.838 5.174 5.824 5.178 5.828 5.172 5.822 5.155 5.805 5.166 5.816 8mA SSTL-18 CLASS II 16mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-49 Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.007 3.363 3.000 3.356 2.992 3.348 2.995 3.351 2.992 3.348 3.000 3.356 3.012 3.368 3.008 3.364 3.004 3.360 2.997 3.353 2.998 3.354 2.996 3.352 2.995 3.363 2.988 3.356 2.980 3.348 2.983 3.351 2.980 3.348 2.988 3.356 3.000 3.368 2.996 3.364 2.992 3.360 2.985 3.353 2.986 3.354 2.984 3.352 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.233 4.756 4.231 4.754 4.224 4.746 4.227 4.749 4.229 4.752 4.228 4.751 4.242 4.764 4.243 4.765 4.238 4.761 4.231 4.754 4.238 4.761 4.219 4.742 4.598 5.069 5.160 5.679 4.596 5.068 5.158 5.678 4.589 5.061 5.151 5.671 4.592 5.065 5.154 5.675 4.596 5.069 5.158 5.679 4.593 5.065 5.155 5.675 4.608 5.080 5.170 5.690 4.609 5.083 5.171 5.693 4.605 5.078 5.167 5.688 4.598 5.071 5.160 5.681 4.606 5.081 5.168 5.691 4.584 5.055 5.146 5.665 4.951 5.536 4.950 5.535 4.943 5.528 4.947 5.532 4.951 5.536 4.947 5.532 4.962 5.547 4.965 5.550 4.960 5.545 4.953 5.538 4.963 5.548 4.937 5.522 5.153 5.803 5.152 5.802 5.145 5.795 5.149 5.799 5.153 5.803 5.149 5.799 5.164 5.814 5.167 5.817 5.162 5.812 5.155 5.805 5.165 5.815 5.139 5.789 4.598 5.160 4.596 5.158 4.589 5.151 4.592 5.154 4.596 5.158 4.593 5.155 4.608 5.170 4.609 5.171 4.605 5.167 4.598 5.160 4.606 5.168 4.584 5.146 5.069 4.951 5.679 5.536 5.068 4.950 5.678 5.535 5.061 4.943 5.671 5.528 5.065 4.947 5.675 5.532 5.069 4.951 5.679 5.536 5.065 4.947 5.675 5.532 5.080 4.962 5.690 5.547 5.083 4.965 5.693 5.550 5.078 4.960 5.688 5.545 5.071 4.953 5.681 5.538 5.081 4.963 5.691 5.548 5.055 4.937 5.665 5.522 5.153 5.803 5.152 5.802 5.145 5.795 5.149 5.799 5.153 5.803 5.149 5.799 5.164 5.814 5.167 5.817 5.162 5.812 5.155 5.805 5.165 5.815 5.139 5.789 4mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-50 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-43. EP3SL50 Column Pins output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.015 3.371 3.007 3.363 3.008 3.364 2.997 3.353 2.997 3.353 3.018 3.374 3.121 3.477 3.121 3.477 3.003 3.371 2.995 3.363 2.996 3.364 2.985 3.353 2.985 3.353 3.006 3.374 3.109 3.477 3.109 3.477 C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Clock GCLK Units tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.256 4.778 4.247 4.769 4.254 4.777 4.241 4.764 4.241 4.764 4.257 4.780 4.302 4.825 4.302 4.825 4.625 5.101 5.187 5.711 4.616 5.092 5.178 5.702 4.624 5.101 5.186 5.711 4.611 5.087 5.173 5.697 4.611 5.088 5.173 5.698 4.626 5.101 5.188 5.711 4.660 5.126 5.222 5.736 4.660 5.126 5.222 5.736 4.983 5.568 4.974 5.559 4.983 5.568 4.969 5.554 4.970 5.555 4.983 5.568 5.008 5.593 5.008 5.593 5.185 5.835 5.176 5.826 5.185 5.835 5.171 5.821 5.172 5.822 5.185 5.835 5.210 5.860 5.210 5.860 4.625 5.187 4.616 5.178 4.624 5.186 4.611 5.173 4.611 5.173 4.626 5.188 4.660 5.222 4.660 5.222 5.101 4.983 5.711 5.568 5.092 4.974 5.702 5.559 5.101 4.983 5.711 5.568 5.087 4.969 5.697 5.554 5.088 4.970 5.698 5.555 5.101 4.983 5.711 5.568 5.126 5.008 5.736 5.593 5.126 5.008 5.736 5.593 5.185 ns 5.835 ns 5.176 ns 5.826 ns 5.185 ns 5.835 ns 5.171 ns 5.821 ns 5.172 ns 5.822 ns 5.185 ns 5.835 ns 5.210 ns 5.860 ns 5.210 ns 5.860 ns 4mA GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-51 Table 1-44 lists the EP3SL50 row pins output timing parameters for single-ended I/O standards. Table 1-44. EP3SL50 Row Pins output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.197 1.482 3.104 1.415 3.014 1.336 3.207 1.492 3.018 1.340 3.151 1.442 3.026 1.341 2.987 1.304 3.065 1.363 2.969 1.291 3.177 1.468 3.067 1.383 3.021 1.326 3.438 1.677 3.333 1.606 3.233 1.517 3.442 1.684 3.237 1.521 3.384 1.638 3.257 1.526 3.206 1.488 3.303 1.550 3.188 1.472 3.420 1.675 3.321 1.572 3.245 1.528 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.781 2.061 4.651 1.951 4.532 1.845 4.789 2.065 4.538 1.856 4.733 2.028 4.580 1.891 4.498 1.831 4.627 1.926 4.463 1.803 4.865 2.136 4.710 2.012 4.599 1.928 5.176 2.175 5.038 2.037 4.915 1.930 5.181 2.180 4.921 1.945 5.129 2.128 4.970 1.969 4.887 1.903 5.022 2.021 4.848 1.874 5.283 2.282 5.120 2.119 5.001 2.015 5.684 2.372 5.540 2.228 5.412 2.100 5.689 2.377 5.418 2.106 5.641 2.329 5.477 2.165 5.389 2.077 5.530 2.218 5.350 2.038 5.813 2.501 5.643 2.331 5.517 2.205 5.549 2.388 5.405 2.244 5.277 2.116 5.554 2.393 5.283 2.122 5.506 2.345 5.342 2.181 5.254 2.093 5.395 2.234 5.215 2.054 5.678 2.517 5.508 2.347 5.382 2.221 5.751 2.308 5.607 2.164 5.479 2.036 5.756 2.313 5.485 2.042 5.708 2.265 5.544 2.101 5.456 2.013 5.597 2.154 5.417 1.974 5.880 2.437 5.710 2.267 5.584 2.141 5.305 2.295 5.164 2.154 5.037 2.046 5.311 2.301 5.043 2.058 5.262 2.252 5.100 2.090 5.014 2.016 5.154 2.144 4.974 1.986 5.422 2.412 5.255 2.245 5.132 2.132 5.818 2.495 5.669 2.346 5.537 2.214 5.823 2.500 5.544 2.221 5.776 2.453 5.612 2.289 5.519 2.196 5.665 2.342 5.479 2.156 5.955 2.632 5.781 2.458 5.651 2.328 5.682 2.512 5.533 2.363 5.401 2.260 5.687 2.517 5.408 2.269 5.640 2.470 5.475 2.305 5.382 2.222 5.528 2.358 5.342 2.193 5.818 2.648 5.644 2.474 5.514 2.354 5.828 2.303 5.679 2.154 5.547 2.022 5.833 2.308 5.554 2.029 5.786 2.261 5.621 2.096 5.528 2.003 5.674 2.149 5.488 1.963 5.964 2.439 5.790 2.265 5.660 2.135 4mA GCLK PLL GCLK 3.3-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-52 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-44. EP3SL50 Row Pins output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.410 1.695 3.191 1.470 3.120 1.405 3.098 1.367 3.321 1.606 3.114 1.383 3.087 1.356 3.068 1.337 3.264 1.549 3.119 1.388 3.008 1.330 3.003 1.325 2.994 1.316 3.667 1.941 3.465 1.739 3.363 1.637 3.327 1.563 3.585 1.859 3.344 1.602 3.318 1.554 3.307 1.545 3.510 1.784 3.348 1.595 3.232 1.516 3.228 1.512 3.217 1.501 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 5.251 2.589 4.924 2.262 4.771 2.109 4.698 2.032 5.161 2.499 4.756 2.094 4.683 2.021 4.666 1.999 5.071 2.409 4.778 2.116 4.577 1.921 4.571 1.918 4.556 1.903 5.711 2.710 5.343 2.342 5.193 2.192 5.111 2.099 5.625 2.624 5.188 2.187 5.103 2.091 5.079 2.073 5.539 2.538 5.216 2.215 4.973 2.006 4.968 2.004 4.952 1.988 6.288 2.976 5.883 2.571 5.724 2.412 5.630 2.316 6.216 2.904 5.725 2.413 5.630 2.307 5.611 2.288 6.141 2.829 5.766 2.454 5.485 2.173 5.477 2.166 5.450 2.149 6.153 2.992 5.748 2.587 5.589 2.428 5.494 2.332 6.081 2.920 5.590 2.429 5.494 2.323 5.475 2.304 6.006 2.845 5.631 2.470 5.350 2.189 5.342 2.184 5.315 2.167 6.355 2.912 5.950 2.507 5.791 2.348 5.701 2.252 6.283 2.840 5.792 2.349 5.701 2.243 5.682 2.224 6.208 2.765 5.833 2.390 5.552 2.109 5.544 2.106 5.517 2.089 5.859 2.849 5.494 2.484 5.326 2.316 5.242 2.221 5.766 2.756 5.320 2.310 5.235 2.212 5.211 2.194 5.678 2.668 5.345 2.335 5.099 2.119 5.095 2.118 5.078 2.101 6.439 3.116 6.033 2.710 5.860 2.537 5.766 2.443 6.363 3.040 5.859 2.536 5.762 2.431 5.743 2.409 6.279 2.956 5.901 2.578 5.613 2.290 5.606 2.284 5.579 2.266 6.303 3.133 5.896 2.726 5.724 2.554 5.630 2.460 6.227 3.057 5.723 2.553 5.627 2.448 5.608 2.426 6.143 2.973 5.765 2.595 5.477 2.340 5.470 2.339 5.452 2.321 6.449 2.924 6.042 2.517 5.870 2.345 5.776 2.251 6.373 2.848 5.869 2.344 5.773 2.239 5.754 2.217 6.289 2.764 5.911 2.386 5.623 2.098 5.616 2.096 5.589 2.078 2mA GCLK PLL GCLK 4mA 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-53 Table 1-44. EP3SL50 Row Pins output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.047 1.316 3.042 1.311 3.031 1.300 3.020 1.289 3.020 1.289 3.028 1.297 3.029 1.298 3.050 1.319 3.036 1.305 3.025 1.294 3.271 1.519 3.266 1.505 3.255 1.493 3.244 1.476 3.243 1.475 3.250 1.482 3.253 1.485 3.274 1.515 3.260 1.493 3.248 1.480 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.617 1.927 4.615 1.924 4.605 1.907 4.592 1.891 4.592 1.890 4.591 1.888 4.597 1.892 4.626 1.938 4.615 1.920 4.602 1.903 5.015 1.998 5.014 1.997 5.004 1.987 4.991 1.974 4.991 1.974 4.988 1.971 4.996 1.979 5.026 2.009 5.016 1.999 5.003 1.986 5.525 2.198 5.524 2.197 5.514 2.187 5.501 2.174 5.501 2.174 5.496 2.169 5.506 2.179 5.538 2.211 5.528 2.201 5.515 2.188 5.389 2.216 5.388 2.215 5.378 2.205 5.365 2.192 5.365 2.192 5.360 2.187 5.370 2.197 5.402 2.229 5.392 2.219 5.379 2.206 5.596 2.138 5.595 2.137 5.585 2.127 5.572 2.114 5.572 2.114 5.567 2.109 5.577 2.119 5.609 2.151 5.599 2.141 5.586 2.128 5.141 2.111 5.139 2.109 5.130 2.100 5.118 2.088 5.117 2.087 5.113 2.083 5.122 2.092 5.151 2.121 5.142 2.112 5.129 2.099 5.653 2.316 5.651 2.314 5.642 2.305 5.630 2.293 5.630 2.293 5.624 2.287 5.635 2.298 5.665 2.328 5.656 2.319 5.643 2.306 5.518 2.333 5.516 2.331 5.507 2.322 5.495 2.310 5.495 2.310 5.489 2.304 5.500 2.315 5.530 2.345 5.521 2.336 5.508 2.323 5.664 2.127 5.662 2.125 5.653 2.116 5.641 2.104 5.641 2.104 5.635 2.098 5.646 2.109 5.676 2.139 5.667 2.130 5.654 2.117 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK SSTL-18 CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-54 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-44. EP3SL50 Row Pins output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial 3.035 1.304 3.028 1.297 3.019 1.288 3.022 1.291 3.018 1.287 3.026 1.295 3.041 1.310 3.035 1.304 3.031 1.300 3.043 1.312 3.034 1.303 3.033 1.302 3.114 1.436 3.114 1.436 3.256 1.491 3.250 1.482 3.242 1.474 3.244 1.476 3.241 1.473 3.249 1.481 3.262 1.498 3.257 1.489 3.253 1.485 3.264 1.497 3.256 1.488 3.256 1.488 3.338 1.622 3.338 1.622 C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Clock GCLK Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 4.590 1.894 4.588 1.885 4.581 1.877 4.584 1.879 4.586 1.881 4.584 1.879 4.599 1.905 4.600 1.901 4.595 1.895 4.612 1.916 4.603 1.905 4.610 1.909 4.626 1.973 4.626 1.973 4.986 1.969 4.985 1.968 4.978 1.961 4.981 1.964 4.984 1.967 4.981 1.964 4.996 1.979 4.998 1.981 4.993 1.976 5.012 1.995 5.003 1.986 5.011 1.994 5.016 2.052 5.016 2.052 5.494 2.167 5.493 2.166 5.486 2.159 5.490 2.163 5.493 2.166 5.489 2.162 5.505 2.178 5.507 2.180 5.502 2.175 5.524 2.197 5.515 2.188 5.524 2.197 5.494 2.208 5.494 2.208 5.358 2.185 5.357 2.184 5.350 2.177 5.354 2.181 5.357 2.184 5.353 2.180 5.369 2.196 5.371 2.198 5.366 2.193 5.388 2.215 5.379 2.206 5.388 2.215 5.359 2.226 5.359 2.226 5.565 2.107 5.564 2.106 5.557 2.099 5.561 2.103 5.564 2.106 5.560 2.102 5.576 2.118 5.578 2.120 5.573 2.115 5.595 2.137 5.586 2.128 5.595 2.137 5.561 2.148 5.561 2.148 5.112 2.082 5.111 2.081 5.104 2.074 5.107 2.077 5.110 2.080 5.106 2.076 5.121 2.091 5.123 2.093 5.118 2.088 5.137 2.107 5.128 2.098 5.137 2.107 5.144 2.167 5.144 2.167 5.621 2.284 5.621 2.284 5.614 2.277 5.617 2.280 5.622 2.285 5.616 2.279 5.632 2.295 5.635 2.298 5.629 2.292 5.651 2.314 5.642 2.305 5.652 2.315 5.625 2.327 5.625 2.327 5.486 2.301 5.486 2.301 5.479 2.294 5.482 2.297 5.487 2.302 5.481 2.296 5.497 2.312 5.500 2.315 5.494 2.309 5.516 2.331 5.507 2.322 5.517 2.332 5.513 2.382 5.513 2.382 5.632 2.095 5.632 2.095 5.625 2.088 5.628 2.091 5.633 2.096 5.627 2.090 5.643 2.106 5.646 2.109 5.640 2.103 5.662 2.125 5.653 2.116 5.663 2.126 5.635 2.139 5.635 2.139 4mA GCLK PLL GCLK 6mA 1.8-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 1.8-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA 1.5-V HSTL CLASS I GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 1.2-V HSTL CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-55 Table 1-45 through Table 1-48 list the maximum I/O timing parameters for EP3SL50 devices for differential I/O standards. Table 1-45 lists the EP3SL50 column pins input timing parameters for differential I/O standards. Table 1-45. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK tsu th -0.697 0.814 1.143 -0.892 -0.697 0.814 1.143 -0.892 -0.705 0.822 1.135 -0.884 -0.705 0.822 1.135 -0.884 -0.717 0.834 1.123 -0.872 -0.717 0.834 1.123 -0.872 -0.705 0.822 1.135 -0.884 -0.705 0.822 1.135 -0.884 -0.717 0.849 1.159 -0.893 -0.717 0.849 1.159 -0.893 -0.729 0.861 1.147 -0.881 -0.729 0.861 1.147 -0.881 -0.740 0.872 1.136 -0.870 -0.740 0.872 1.136 -0.870 -0.729 0.861 1.147 -0.881 -0.729 0.861 1.147 -0.881 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.2-V HSTL CLASS I -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.2-V HSTL CLASS II -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.5-V HSTL CLASS I -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.5-V HSTL CLASS II -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.8-V HSTL CLASS I -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-56 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-45. EP3SL50 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.717 0.834 1.123 -0.872 -0.717 0.834 1.123 -0.872 -0.724 0.841 1.116 -0.865 -0.724 0.841 1.116 -0.865 -0.697 0.814 1.143 -0.892 -0.697 0.814 1.143 -0.892 -0.705 0.822 1.135 -0.884 -0.740 0.872 1.136 -0.870 -0.740 0.872 1.136 -0.870 -0.746 0.878 1.130 -0.864 -0.746 0.878 1.130 -0.864 -0.717 0.849 1.159 -0.893 -0.717 0.849 1.159 -0.893 -0.729 0.861 1.147 -0.881 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.5-V SSTL CLASS I -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 1.290 1.790 1.419 2.026 1.560 2.244 1.492 2.129 1.779 2.138 1.427 2.037 1.565 2.260 1.501 2.142 1.811 2.190 DIFFERENTIAL 1.5-V SSTL CLASS II -1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 -1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 1.290 1.790 1.419 2.026 1.560 2.244 1.492 2.129 1.779 2.138 1.427 2.037 1.565 2.260 1.501 2.142 1.811 2.190 DIFFERENTIAL 1.8-V SSTL CLASS I -1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 DIFFERENTIAL 1.8-V SSTL CLASS II -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 DIFFERENTIAL 2.5-V SSTL CLASS I -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 2.5-V SSTL CLASS II -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-57 Table 1-46 lists the EP3SL50 row pins input timing parameters for differential I/O standards. Table 1-46. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK LVDS GCLK PLL GCLK MINI-LVDS GCLK PLL GCLK RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.919 1.042 0.882 -0.625 -0.919 1.042 0.882 -0.625 -0.919 1.042 0.882 -0.625 -0.734 0.850 1.077 -0.827 -0.734 0.850 1.077 -0.827 -0.743 0.859 1.068 -0.818 -0.743 0.859 1.068 -0.818 -0.757 0.873 1.054 -0.804 -0.939 1.077 0.896 -0.625 -0.939 1.077 0.896 -0.625 -0.939 1.077 0.896 -0.625 -0.764 0.893 1.081 -0.819 -0.764 0.893 1.081 -0.819 -0.776 0.905 1.069 -0.807 -0.776 0.905 1.069 -0.807 -0.788 0.917 1.057 -0.795 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 1.613 2.393 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 1.613 2.393 -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 1.613 2.393 -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 -1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 1.274 1.776 1.394 2.019 1.516 2.257 1.451 2.138 1.720 2.163 1.410 2.024 1.531 2.263 1.470 2.144 1.758 2.209 DIFFERENTIAL 1.2-V HSTL CLASS I -1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 -1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 1.274 1.776 1.394 2.019 1.516 2.257 1.451 2.138 1.720 2.163 1.410 2.024 1.531 2.263 1.470 2.144 1.758 2.209 DIFFERENTIAL 1.2-V HSTL CLASS II -1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 1.774 2.193 DIFFERENTIAL 1.5-V HSTL CLASS I -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 1.774 2.193 DIFFERENTIAL 1.5-V HSTL CLASS II -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 1.791 2.176 DIFFERENTIAL 1.8-V HSTL CLASS I -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-58 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-46. EP3SL50 Row Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.757 0.873 1.054 -0.804 -0.743 0.859 1.068 -0.818 -0.743 0.859 1.068 -0.818 -0.757 0.873 1.054 -0.804 -0.757 0.873 1.054 -0.804 -0.756 0.872 1.045 -0.795 -0.756 0.872 1.045 -0.795 -0.788 0.917 1.057 -0.795 -0.776 0.905 1.069 -0.807 -0.776 0.905 1.069 -0.807 -0.788 0.917 1.057 -0.795 -0.788 0.917 1.057 -0.795 -0.787 0.916 1.048 -0.786 -0.787 0.916 1.048 -0.786 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 1.791 2.176 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 1.774 2.193 DIFFERENTIAL 1.5-V SSTL CLASS I -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 1.774 2.193 DIFFERENTIAL 1.5-V SSTL CLASS II -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 1.791 2.176 DIFFERENTIAL 1.8-V SSTL CLASS I -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 1.791 2.176 DIFFERENTIAL 1.8-V SSTL CLASS II -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 -1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 1.300 1.739 1.422 1.983 1.554 2.212 1.489 2.092 1.759 2.118 1.434 1.993 1.563 2.224 1.502 2.103 1.792 2.169 DIFFERENTIAL 2.5-V SSTL CLASS I -1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 -1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 1.300 1.739 1.422 1.983 1.554 2.212 1.489 2.092 1.759 2.118 1.434 1.993 1.563 2.224 1.502 2.103 1.792 2.169 DIFFERENTIAL 2.5-V SSTL CLASS II -1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-59 Table 1-47 lists the EP3SL50 column pins output timing parameters for differential I/O standards. Table 1-47. EP3SL50 Column Pins Output Timing Parameters (Part 1 of 4) Parameter Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.029 3.025 3.029 3.025 3.029 3.025 3.056 3.046 3.046 3.039 3.038 3.060 3.050 3.045 3.043 3.035 3.036 3.035 3.047 3.043 3.033 3.031 3.031 3.035 3.246 3.249 3.246 3.249 3.246 3.249 3.279 3.269 3.269 3.263 3.261 3.283 3.272 3.268 3.266 3.257 3.259 3.256 3.269 3.266 3.255 3.253 3.254 3.257 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-60 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-47. EP3SL50 Column Pins Output Timing Parameters (Part 2 of 4) Parameter Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.061 3.047 3.035 3.035 3.031 3.035 3.036 3.064 3.053 3.048 3.034 3.032 3.036 3.036 3.052 3.052 3.042 3.035 3.029 3.025 3.029 3.025 3.029 3.025 3.286 3.272 3.259 3.259 3.255 3.257 3.259 3.289 3.277 3.273 3.258 3.256 3.258 3.259 3.276 3.276 3.266 3.258 3.246 3.249 3.246 3.249 3.246 3.249 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 4.646 5.055 5.573 5.433 5.651 5.183 5.701 5.563 5.720 4.629 5.037 5.555 5.415 5.633 5.165 5.683 5.545 5.702 4.632 5.041 5.559 5.419 5.637 5.169 5.688 5.550 5.707 4.625 5.033 5.552 5.412 5.630 5.162 5.680 5.542 5.699 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.626 5.034 5.551 5.411 5.629 5.161 5.679 5.541 5.698 4.657 5.064 5.581 5.441 5.659 5.192 5.708 5.570 5.727 4.645 5.052 5.569 5.429 5.647 5.180 5.696 5.558 5.715 4.645 5.053 5.570 5.430 5.648 5.181 5.698 5.560 5.717 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-61 Table 1-47. EP3SL50 Column Pins Output Timing Parameters (Part 3 of 4) Parameter Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.056 3.046 3.046 3.039 3.038 3.060 3.050 3.045 3.043 3.035 3.036 3.035 3.047 3.043 3.033 3.031 3.031 3.035 3.061 3.047 3.035 3.035 3.031 3.035 3.036 3.064 3.053 3.048 3.279 3.269 3.269 3.263 3.261 3.283 3.272 3.268 3.266 3.257 3.259 3.256 3.269 3.266 3.255 3.253 3.254 3.257 3.286 3.272 3.259 3.259 3.255 3.257 3.259 3.289 3.277 3.273 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 4.646 5.055 5.573 5.433 5.651 5.183 5.701 5.563 5.720 4.629 5.037 5.555 5.415 5.633 5.165 5.683 5.545 5.702 4.632 5.041 5.559 5.419 5.637 5.169 5.688 5.550 5.707 4.625 5.033 5.552 5.412 5.630 5.162 5.680 5.542 5.699 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.626 5.034 5.551 5.411 5.629 5.161 5.679 5.541 5.698 4.657 5.064 5.581 5.441 5.659 5.192 5.708 5.570 5.727 4.645 5.052 5.569 5.429 5.647 5.180 5.696 5.558 5.715 4.645 5.053 5.570 5.430 5.648 5.181 5.698 5.560 5.717 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-62 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-47. EP3SL50 Column Pins Output Timing Parameters (Part 4 of 4) Parameter Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco 3.034 3.032 3.036 3.036 3.052 3.052 3.042 3.035 3.258 3.256 3.258 3.259 3.276 3.276 3.266 3.258 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II Table 1-48 lists the EP3SL50 row pins output timing parameters for differential I/O standards. Table 1-48. EP3SL50 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.668 3.062 3.044 2.668 3.062 3.044 2.668 3.062 3.044 3.098 3.084 3.080 3.096 3.085 2.842 3.288 3.278 2.842 3.288 3.278 2.842 3.288 3.278 3.331 3.317 3.313 3.328 3.318 3.979 4.646 4.684 3.979 4.646 4.684 3.979 4.646 4.684 4.730 4.717 4.715 4.716 4.712 4.346 5.055 5.101 4.346 5.055 5.101 4.346 5.055 5.101 5.145 5.132 5.132 5.129 5.125 4.821 5.575 5.629 4.821 5.575 5.629 4.821 5.575 5.629 5.672 5.659 5.660 5.654 5.651 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 5.528 5.727 5.280 5.809 5.665 5.794 5.515 5.714 5.266 5.796 5.652 5.781 5.516 5.715 5.266 5.798 5.654 5.783 5.510 5.709 5.263 5.791 5.647 5.776 5.507 5.706 5.260 5.788 5.644 5.773 ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-63 Table 1-48. EP3SL50 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK RSDS_E_1R -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.082 3.093 3.083 3.069 3.066 3.063 3.064 3.113 3.089 3.071 3.117 3.102 3.091 3.071 3.068 3.073 3.066 3.094 3.076 3.062 2.668 3.062 3.044 2.668 3.062 3.044 3.315 3.325 3.316 3.302 3.298 3.296 3.296 3.349 3.325 3.306 3.352 3.337 3.326 3.306 3.302 3.306 3.299 3.328 3.311 3.295 2.842 3.288 3.278 2.842 3.288 3.278 4.710 4.711 4.709 4.694 4.690 4.691 4.681 4.752 4.734 4.712 4.752 4.738 4.733 4.710 4.706 4.697 4.696 4.724 4.709 4.686 3.979 4.646 4.684 3.979 4.646 4.684 5.123 5.124 5.122 5.107 5.103 5.106 5.094 5.167 5.150 5.128 5.167 5.152 5.149 5.125 5.122 5.110 5.111 5.138 5.123 5.099 4.346 5.055 5.101 4.346 5.055 5.101 5.649 5.648 5.647 5.633 5.629 5.632 5.619 5.695 5.678 5.656 5.694 5.679 5.676 5.653 5.649 5.635 5.638 5.664 5.649 5.624 4.821 5.575 5.629 4.821 5.575 5.629 5.505 5.704 5.258 5.787 5.643 5.772 5.504 5.703 5.257 5.785 5.641 5.770 5.503 5.702 5.257 5.785 5.641 5.770 5.489 5.688 5.242 5.770 5.626 5.755 5.485 5.684 5.238 5.766 5.622 5.751 5.488 5.687 5.241 5.770 5.626 5.755 5.475 5.674 5.228 5.756 5.612 5.741 5.551 5.750 5.302 5.832 5.688 5.817 5.534 5.733 5.285 5.817 5.673 5.802 5.512 5.711 5.263 5.795 5.651 5.780 5.550 5.749 5.302 5.832 5.688 5.817 5.535 5.734 5.287 5.817 5.673 5.802 5.532 5.731 5.284 5.815 5.671 5.800 5.509 5.708 5.261 5.791 5.647 5.776 5.505 5.704 5.257 5.788 5.644 5.773 5.491 5.690 5.244 5.772 5.628 5.757 5.494 5.693 5.247 5.777 5.633 5.762 5.520 5.719 5.273 5.802 5.658 5.787 5.505 5.704 5.258 5.787 5.643 5.772 5.480 5.679 5.234 5.762 5.618 5.747 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL RSDS_E_3R -- DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I 4mA 6mA 8mA 4mA 6mA 8mA 4mA 6mA 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-64 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-48. EP3SL50 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock DIFFERENTIAL 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS I GCLK 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.668 3.062 3.044 3.098 3.084 3.080 3.096 3.085 3.082 3.093 3.083 3.069 3.066 3.063 3.064 3.113 3.089 3.071 3.117 3.102 3.091 3.071 3.068 3.073 3.066 3.094 2.842 3.288 3.278 3.331 3.317 3.313 3.328 3.318 3.315 3.325 3.316 3.302 3.298 3.296 3.296 3.349 3.325 3.306 3.352 3.337 3.326 3.306 3.302 3.306 3.299 3.328 3.979 4.646 4.684 4.730 4.717 4.715 4.716 4.712 4.710 4.711 4.709 4.694 4.690 4.691 4.681 4.752 4.734 4.712 4.752 4.738 4.733 4.710 4.706 4.697 4.696 4.724 4.346 5.055 5.101 5.145 5.132 5.132 5.129 5.125 5.123 5.124 5.122 5.107 5.103 5.106 5.094 5.167 5.150 5.128 5.167 5.152 5.149 5.125 5.122 5.110 5.111 5.138 4.821 5.575 5.629 5.672 5.659 5.660 5.654 5.651 5.649 5.648 5.647 5.633 5.629 5.632 5.619 5.695 5.678 5.656 5.694 5.679 5.676 5.653 5.649 5.635 5.638 5.664 4.685 4.892 4.453 4.930 4.795 4.940 5.431 5.630 5.186 5.709 5.565 5.694 5.485 5.684 5.237 5.770 5.626 5.755 5.528 5.727 5.280 5.809 5.665 5.794 5.515 5.714 5.266 5.796 5.652 5.781 5.516 5.715 5.266 5.798 5.654 5.783 5.510 5.709 5.263 5.791 5.647 5.776 5.507 5.706 5.260 5.788 5.644 5.773 5.505 5.704 5.258 5.787 5.643 5.772 5.504 5.703 5.257 5.785 5.641 5.770 5.503 5.702 5.257 5.785 5.641 5.770 5.489 5.688 5.242 5.770 5.626 5.755 5.485 5.684 5.238 5.766 5.622 5.751 5.488 5.687 5.241 5.770 5.626 5.755 5.475 5.674 5.228 5.756 5.612 5.741 5.551 5.750 5.302 5.832 5.688 5.817 5.534 5.733 5.285 5.817 5.673 5.802 5.512 5.711 5.263 5.795 5.651 5.780 5.550 5.749 5.302 5.832 5.688 5.817 5.535 5.734 5.287 5.817 5.673 5.802 5.532 5.731 5.284 5.815 5.671 5.800 5.509 5.708 5.261 5.791 5.647 5.776 5.505 5.704 5.257 5.788 5.644 5.773 5.491 5.690 5.244 5.772 5.628 5.757 5.494 5.693 5.247 5.777 5.633 5.762 5.520 5.719 5.273 5.802 5.658 5.787 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 8mA 4mA 6mA 8mA 10mA 12mA 8mA 16mA 8mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-65 Table 1-48. EP3SL50 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock DIFFERENTIAL 2.5-V SSTL CLASS II GCLK 16mA tco tco 3.076 3.062 3.311 3.295 4.709 4.686 5.123 5.099 5.649 5.624 5.505 5.704 5.258 5.787 5.643 5.772 5.480 5.679 5.234 5.762 5.618 5.747 ns ns GCLK PLL Table 1-49 and Table 1-50 list the EP3SL50 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-49 lists the EP3SL50 column pin delay adders when using the regional clock. Table 1-49. EP3SL50 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.239 0.008 -0.068 1.614 0.258 0.009 -0.07 1.649 0.341 0.014 -0.09 2.575 0.365 0.017 2.89 0.39 0.019 3.164 0.377 0.017 3.011 0.439 0.02 3.22 0.375 0.018 2.908 0.399 0.019 3.217 0.388 0.017 -0.09 3.063 0.441 0.02 -0.17 3.338 ns ns ns ns -0.092 -0.094 -0.091 -0.169 -0.086 -0.087 Table 1-50 lists the EP3SL50 row pin delay adders when using the regional clock. Table 1-50. EP3SL50 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.111 0.101 -0.113 -0.107 0.124 0.107 -0.127 -0.113 0.178 0.156 0.193 0.174 0.208 0.194 0.2 0.184 -0.2 0.263 0.251 0.197 0.177 0.213 0.196 0.203 0.188 0.266 0.249 ns ns ns ns -0.181 -0.196 -0.213 -0.205 -0.271 -0.199 -0.217 -0.209 -0.273 -0.164 -0.185 -0.213 -0.266 -0.184 -0.212 -0.198 -0.262 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-66 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing EP3SL70 I/O Timing Parameters Table 1-51 through Table 1-54 list the maximum I/O timing parameters for EP3SL70 devices for single-ended I/O standards. Table 1-51 lists the EP3SL70 column pins input timing parameters for single-ended I/O standards. Table 1-51. EP3SL70 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK 3.3-V LVTTL GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.812 0.934 -0.965 1.216 -0.812 0.934 -0.965 1.216 -0.823 0.945 -0.976 1.227 -0.823 0.945 -0.976 1.227 -0.818 0.940 -0.971 1.222 -0.840 0.964 -0.993 1.246 -0.830 0.954 -0.983 1.236 -0.778 0.902 -0.931 1.184 -0.811 0.934 -0.965 1.216 -0.811 0.934 -0.965 1.216 -0.822 0.945 -0.976 1.227 -0.822 0.945 -0.976 1.227 -0.817 0.940 -0.971 1.222 -0.839 0.964 -0.993 1.246 -0.829 0.954 -0.983 1.236 -0.777 0.902 -0.931 1.184 -1.154 -1.261 -1.312 -1.266 -1.645 -1.261 -1.312 -1.266 -1.645 1.327 1.764 1.327 1.764 1.326 1.763 1.326 1.763 1.335 1.772 1.375 1.812 1.352 1.789 1.275 1.712 1.457 1.937 1.457 1.937 1.459 1.939 1.459 1.939 1.471 1.951 1.507 1.987 1.475 1.955 1.376 1.856 1.533 2.222 1.533 2.222 1.532 2.221 1.532 2.221 1.551 2.240 1.549 2.238 1.479 2.168 1.323 2.012 1.475 2.138 1.475 2.138 1.474 2.137 1.474 2.137 1.493 2.156 1.491 2.154 1.421 2.084 1.265 1.928 1.850 2.540 1.850 2.540 1.849 2.539 1.849 2.539 1.868 2.558 1.866 2.556 1.796 2.486 1.640 2.330 1.457 1.937 1.457 1.937 1.459 1.939 1.459 1.939 1.471 1.951 1.507 1.987 1.475 1.955 1.376 1.856 1.533 2.222 1.533 2.222 1.532 2.221 1.532 2.221 1.551 2.240 1.549 2.238 1.479 2.168 1.323 2.012 1.475 2.138 1.475 2.138 1.474 2.137 1.474 2.137 1.493 2.156 1.491 2.154 1.421 2.084 1.265 1.928 1.850 2.540 1.850 2.540 1.849 2.539 1.849 2.539 1.868 2.558 1.866 2.556 1.796 2.486 1.640 2.330 -1.395 -1.522 -1.763 -1.703 -2.094 -1.522 -1.763 -1.703 -2.094 -1.154 -1.261 -1.312 -1.266 -1.645 -1.261 -1.312 -1.266 -1.645 -1.395 -1.522 -1.763 -1.703 -2.094 -1.522 -1.763 -1.703 -2.094 -1.153 -1.263 -1.311 -1.265 -1.644 -1.263 -1.311 -1.265 -1.644 -1.394 -1.524 -1.762 -1.702 -2.093 -1.524 -1.762 -1.702 -2.093 -1.153 -1.263 -1.311 -1.265 -1.644 -1.263 -1.311 -1.265 -1.644 -1.394 -1.524 -1.762 -1.702 -2.093 -1.524 -1.762 -1.702 -2.093 -1.162 -1.275 -1.330 -1.284 -1.663 -1.275 -1.330 -1.284 -1.663 -1.403 -1.536 -1.781 -1.721 -2.112 -1.536 -1.781 -1.721 -2.112 -1.202 -1.311 -1.328 -1.282 -1.661 -1.311 -1.328 -1.282 -1.661 -1.443 -1.572 -1.779 -1.719 -2.110 -1.572 -1.779 -1.719 -2.110 -1.179 -1.279 -1.258 -1.212 -1.591 -1.279 -1.258 -1.212 -1.591 -1.420 -1.540 -1.709 -1.649 -2.040 -1.540 -1.709 -1.649 -2.040 -1.102 -1.180 -1.102 -1.056 -1.435 -1.180 -1.102 -1.056 -1.435 -1.343 -1.441 -1.553 -1.493 -1.884 -1.441 -1.553 -1.493 -1.884 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-67 Table 1-51. EP3SL70 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.749 0.873 -0.902 1.155 -0.749 0.873 -0.902 1.155 -0.743 0.867 -0.896 1.149 -0.743 0.867 -0.896 1.149 -0.732 0.856 -0.885 1.138 -0.732 0.856 -0.885 1.138 -0.743 0.867 -0.896 1.149 -0.743 0.867 -0.896 1.149 -0.732 0.856 -0.885 1.138 -0.748 0.873 -0.902 1.155 -0.748 0.873 -0.902 1.155 -0.742 0.867 -0.896 1.149 -0.742 0.867 -0.896 1.149 -0.731 0.856 -0.885 1.138 -0.731 0.856 -0.885 1.138 -0.742 0.867 -0.896 1.149 -0.742 0.867 -0.896 1.149 -0.731 0.856 -0.885 1.138 -1.074 -1.164 -1.104 -1.058 -1.437 -1.164 -1.104 -1.058 -1.437 1.247 1.684 1.247 1.684 1.234 1.671 1.234 1.671 1.222 1.659 1.222 1.659 1.234 1.671 1.234 1.671 1.222 1.659 1.360 1.840 1.360 1.840 1.349 1.829 1.349 1.829 1.338 1.818 1.338 1.818 1.349 1.829 1.349 1.829 1.338 1.818 1.325 2.014 1.325 2.014 1.322 2.008 1.322 2.008 1.303 1.989 1.303 1.989 1.322 2.008 1.322 2.008 1.303 1.989 1.267 1.930 1.267 1.930 1.264 1.924 1.264 1.924 1.245 1.905 1.245 1.905 1.264 1.924 1.264 1.924 1.245 1.905 1.642 2.332 1.642 2.332 1.635 2.325 1.635 2.325 1.616 2.306 1.616 2.306 1.635 2.325 1.635 2.325 1.616 2.306 1.360 1.840 1.360 1.840 1.349 1.829 1.349 1.829 1.338 1.818 1.338 1.818 1.349 1.829 1.349 1.829 1.338 1.818 1.325 2.014 1.325 2.014 1.322 2.008 1.322 2.008 1.303 1.989 1.303 1.989 1.322 2.008 1.322 2.008 1.303 1.989 1.267 1.930 1.267 1.930 1.264 1.924 1.264 1.924 1.245 1.905 1.245 1.905 1.264 1.924 1.264 1.924 1.245 1.905 1.642 2.332 1.642 2.332 1.635 2.325 1.635 2.325 1.616 2.306 1.616 2.306 1.635 2.325 1.635 2.325 1.616 2.306 -1.315 -1.425 -1.555 -1.495 -1.886 -1.425 -1.555 -1.495 -1.886 -1.074 -1.164 -1.104 -1.058 -1.437 -1.164 -1.104 -1.058 -1.437 -1.315 -1.425 -1.555 -1.495 -1.886 -1.425 -1.555 -1.495 -1.886 -1.061 -1.156 -1.104 -1.056 -1.435 -1.156 -1.104 -1.056 -1.435 -1.302 -1.417 -1.552 -1.490 -1.884 -1.417 -1.552 -1.490 -1.884 -1.061 -1.156 -1.104 -1.056 -1.435 -1.156 -1.104 -1.056 -1.435 -1.302 -1.417 -1.552 -1.490 -1.884 -1.417 -1.552 -1.490 -1.884 -1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 -1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865 -1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 -1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865 -1.061 -1.156 -1.104 -1.056 -1.435 -1.156 -1.104 -1.056 -1.435 -1.302 -1.417 -1.552 -1.490 -1.884 -1.417 -1.552 -1.490 -1.884 -1.061 -1.156 -1.104 -1.056 -1.435 -1.156 -1.104 -1.056 -1.435 -1.302 -1.417 -1.552 -1.490 -1.884 -1.417 -1.552 -1.490 -1.884 -1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 -1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-68 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-51. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V I/O Standard Clock Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.732 0.856 -0.885 1.138 -0.720 0.844 -0.873 1.126 -0.720 0.844 -0.873 1.126 -0.823 0.945 -0.976 1.227 -0.731 0.856 -0.885 1.138 -0.719 0.844 -0.873 1.126 -0.719 0.844 -0.873 1.126 -0.822 0.945 -0.976 1.227 -1.050 -1.145 -1.085 -1.037 -1.416 -1.145 -1.085 -1.037 -1.416 1.222 1.659 1.212 1.649 1.212 1.649 1.326 1.763 1.338 1.818 1.327 1.807 1.327 1.807 1.459 1.939 1.303 1.989 1.287 1.973 1.287 1.973 1.532 2.221 1.245 1.905 1.229 1.889 1.229 1.889 1.474 2.137 1.616 2.306 1.600 2.290 1.600 2.290 1.849 2.539 1.338 1.818 1.327 1.807 1.327 1.807 1.459 1.939 1.303 1.989 1.287 1.973 1.287 1.973 1.532 2.221 1.245 1.905 1.229 1.889 1.229 1.889 1.474 2.137 1.616 2.306 1.600 2.290 1.600 2.290 1.849 2.539 -1.291 -1.406 -1.533 -1.471 -1.865 -1.406 -1.533 -1.471 -1.865 -1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400 -1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849 -1.040 -1.134 -1.069 -1.021 -1.400 -1.134 -1.069 -1.021 -1.400 -1.281 -1.395 -1.517 -1.455 -1.849 -1.395 -1.517 -1.455 -1.849 -1.153 -1.263 -1.311 -1.265 -1.644 -1.263 -1.311 -1.265 -1.644 -1.394 -1.524 -1.762 -1.702 -2.093 -1.524 -1.762 -1.702 -2.093 Table 1-52 lists the EP3SL70 row pins input timing parameters for single-ended I/O standards. Table 1-52. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th -0.811 0.925 0.937 -0.688 -0.811 0.925 0.937 -0.688 -0.817 0.931 0.931 -0.682 -0.836 0.962 0.945 -0.684 -0.836 0.962 0.945 -0.684 -0.847 0.973 0.934 -0.673 -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 1.582 1.371 1.801 1.505 1.915 1.747 1.799 1.679 1.814 1.951 1.796 1.526 1.923 1.756 1.804 1.693 1.865 1.982 ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 1.582 1.371 1.368 1.585 1.368 1.801 1.505 1.506 1.800 1.506 1.915 1.747 1.750 1.912 1.750 1.799 1.679 1.682 1.796 1.682 1.814 1.951 1.954 1.811 1.954 1.796 1.526 1.525 1.797 1.525 1.923 1.756 1.761 1.918 1.761 1.804 1.693 1.698 1.799 1.698 1.865 1.982 1.987 1.860 1.987 GCLK PLL GCLK -1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 -1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 3.0-V LVTTL GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-69 Table 1-52. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVCMOS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.817 0.931 0.931 -0.682 -0.805 0.919 0.943 -0.694 -0.946 0.914 1.060 -0.936 0.924 1.050 -0.876 0.984 0.990 -0.747 1.000 0.862 -0.747 1.000 0.862 -0.850 1.010 0.964 -0.850 1.010 0.964 -0.836 1.024 0.950 -0.850 1.010 0.964 -0.850 -0.847 0.973 0.934 -0.673 -0.840 0.966 0.941 -0.680 -0.899 0.891 1.028 -0.888 0.902 1.017 -0.835 0.955 0.964 -0.781 0.999 0.908 -0.781 0.999 0.908 -0.800 0.990 0.929 -0.800 0.990 0.929 -0.788 1.002 0.917 -0.800 0.990 0.929 -0.800 1.377 1.576 1.377 1.518 1.447 1.518 1.542 1.423 1.621 1.344 1.662 1.291 1.659 1.306 -1.118 1.659 1.306 1.659 1.306 1.519 1.787 1.519 1.758 1.676 1.758 1.790 1.644 1.891 1.543 1.896 1.410 1.765 1.897 1.765 1.994 1.892 1.994 2.062 1.824 2.221 1.665 2.117 1.545 1.697 1.781 1.697 1.874 1.823 1.874 1.942 1.755 2.101 1.596 2.001 1.477 1.969 1.796 1.969 1.798 2.114 1.798 1.866 2.046 2.025 1.887 2.016 1.749 1.534 1.788 1.534 1.758 1.723 1.758 1.789 1.692 1.885 1.596 1.900 1.422 1.771 1.908 1.771 1.917 1.933 1.917 1.982 1.868 2.137 1.713 2.125 1.554 1.708 1.789 1.708 1.798 1.867 1.798 1.863 1.802 2.018 1.647 2.006 1.491 1.997 1.850 1.997 1.849 2.146 1.849 1.914 2.081 2.069 1.926 2.067 1.780 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778 GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V -1.259 -1.469 -1.662 -1.607 -1.898 -1.507 -1.694 -1.641 -1.931 GCLK PLL GCLK 1.5 V -1.235 -1.437 -1.594 -1.539 -1.830 -1.476 -1.629 -1.576 -1.866 -1.156 -1.336 -1.435 -1.380 -1.671 -1.380 -1.474 -1.421 -1.711 GCLK PLL GCLK 1.2 V -1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 1.514 1.918 1.918 1.658 2.223 2.223 1.589 2.104 2.104 1.879 2.029 2.029 1.562 1.917 1.917 1.703 2.144 2.144 1.638 2.026 2.026 1.915 2.076 2.076 GCLK PLL GCLK SSTL-2 CLASS I -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 1.514 1.918 1.658 2.223 1.589 2.104 1.879 2.029 1.562 1.917 1.703 2.144 1.638 2.026 1.915 2.076 GCLK PLL GCLK -1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 SSTL-2 CLASS II -1.118 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 -1.276 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 -1.105 1.294 1.659 1.306 1.659 1.306 -1.118 -1.276 1.504 1.928 1.928 1.640 2.241 2.241 1.571 2.122 2.122 1.861 2.047 2.047 1.551 1.928 1.928 1.686 2.161 2.161 1.621 2.043 2.043 1.898 2.093 2.093 GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 1.514 1.918 1.658 2.223 1.589 2.104 1.879 2.029 1.562 1.917 1.703 2.144 1.638 2.026 1.915 2.076 -1.118 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 SSTL-18 CLASS II GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-70 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-52. EP3SL70 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-15 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.010 0.964 -0.836 1.024 0.950 -0.836 1.024 0.950 -0.827 1.033 0.941 -0.827 1.033 0.941 -0.817 0.931 0.931 -0.682 -0.817 0.931 0.931 -0.682 -0.811 0.925 0.937 -0.688 -0.811 0.925 0.937 -0.688 -0.817 0.931 0.931 -0.682 -0.817 0.931 0.990 0.929 -0.788 1.002 0.917 -0.788 1.002 0.917 -0.776 1.014 0.905 -0.776 1.014 0.905 -0.847 0.973 0.934 -0.673 -0.847 0.973 0.934 -0.673 -0.836 0.962 0.945 -0.684 -0.836 0.962 0.945 -0.684 -0.847 0.973 0.934 -0.673 -0.847 0.973 -1.105 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 1.294 1.674 -1.276 -1.285 1.285 1.683 -1.285 -1.285 1.585 1.368 -1.182 1.585 1.368 1.368 1.368 1.368 1.368 1.582 1.371 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 1.514 1.918 1.928 1.658 2.223 2.241 1.589 2.104 2.122 1.879 2.029 2.047 1.562 1.917 1.928 1.703 2.144 2.161 1.638 2.026 2.043 1.915 2.076 2.093 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.105 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 -1.096 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 1.504 1.928 1.938 1.640 2.241 2.257 1.571 2.122 2.138 1.861 2.047 2.063 1.551 1.928 1.937 1.686 2.161 2.177 1.621 2.043 2.059 1.898 2.093 2.109 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK -1.096 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 -1.182 -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634 -1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671 1.494 1.938 1.624 2.257 1.555 2.138 1.845 2.063 1.542 1.937 1.670 2.177 1.605 2.059 1.882 2.109 1.5-V HSTL CLASS I GCLK PLL GCLK -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634 -1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671 1.494 1.938 1.624 2.257 1.555 2.138 1.845 2.063 1.542 1.937 1.670 2.177 1.605 2.059 1.882 2.109 1.5-V HSTL CLASS II GCLK PLL GCLK -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634 -1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671 1.801 1.505 1.915 1.747 1.799 1.679 1.814 1.951 1.796 1.526 1.923 1.756 1.804 1.693 1.865 1.982 1.2-V HSTL CLASS I GCLK PLL GCLK -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 1.2-V HSTL CLASS II -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 -1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 1.582 1.371 1.368 1.585 1.368 1.377 1.801 1.505 1.506 1.800 1.506 1.519 1.915 1.747 1.750 1.912 1.750 1.765 1.799 1.679 1.682 1.796 1.682 1.697 1.814 1.951 1.954 1.811 1.954 1.969 1.796 1.526 1.525 1.797 1.525 1.534 1.923 1.756 1.761 1.918 1.761 1.771 1.804 1.693 1.698 1.799 1.698 1.708 1.865 1.982 1.987 1.860 1.987 1.997 GCLK PLL GCLK 3.0-V PCI -1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 -1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 GCLK PLL GCLK 3.0-V PCI-X GCLK PLL -1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-71 Table 1-53 lists the EP3SL70 column pins output timing parameters for single-ended I/O standards. Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.187 3.514 3.120 3.447 3.034 3.361 3.028 3.354 3.193 3.520 3.038 3.365 3.045 3.372 3.029 3.356 3.150 3.478 3.043 3.367 3.005 3.331 2.986 3.313 3.187 3.514 3.120 3.447 3.034 3.361 3.028 3.354 3.193 3.520 3.038 3.365 3.045 3.372 3.029 3.356 3.150 3.478 3.043 3.367 3.005 3.331 2.986 3.313 4.411 4.895 4.302 4.786 4.198 4.682 4.182 4.665 4.415 4.899 4.209 4.692 4.203 4.686 4.180 4.664 4.378 4.862 4.250 4.732 4.184 4.669 4.156 4.640 4.765 5.293 4.654 5.182 4.556 5.083 4.528 5.055 4.770 5.298 4.573 5.100 4.552 5.079 4.527 5.054 4.733 5.261 4.602 5.127 4.530 5.058 4.503 5.030 5.226 5.105 5.823 5.680 5.113 4.992 5.710 5.567 5.021 4.900 5.618 5.475 4.980 4.859 5.577 5.434 5.233 5.112 5.830 5.687 5.032 4.911 5.629 5.486 5.006 4.885 5.603 5.460 4.977 4.856 5.574 5.431 5.193 5.072 5.790 5.647 5.056 4.936 5.652 5.510 4.982 4.862 5.578 5.436 4.953 4.832 5.550 5.407 5.313 5.963 5.200 5.850 5.108 5.760 5.067 5.718 5.320 5.971 5.119 5.770 5.093 5.746 5.064 5.717 5.280 5.954 5.142 5.837 5.068 5.773 5.040 5.750 4.765 5.226 5.293 5.823 4.654 5.113 5.182 5.710 4.556 5.021 5.083 5.618 4.528 4.980 5.055 5.577 4.770 5.233 5.298 5.830 4.573 5.032 5.100 5.629 4.552 5.006 5.079 5.603 4.527 4.977 5.054 5.574 4.733 5.193 5.261 5.790 4.602 5.056 5.127 5.652 4.530 4.982 5.058 5.578 4.503 4.953 5.030 5.550 5.105 5.680 4.992 5.567 4.900 5.475 4.859 5.434 5.112 5.687 4.911 5.486 4.885 5.460 4.856 5.431 5.072 5.647 4.936 5.510 4.862 5.436 4.832 5.407 5.313 5.963 5.200 5.850 5.108 5.760 5.067 5.718 5.320 5.971 5.119 5.770 5.093 5.746 5.064 5.717 5.280 5.954 5.142 5.837 5.068 5.773 5.040 5.750 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-72 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.067 3.392 2.988 3.313 2.981 3.308 2.972 3.299 3.187 3.514 3.090 3.414 3.045 3.370 3.006 3.332 3.067 3.392 2.988 3.313 2.981 3.308 2.972 3.299 3.187 3.514 3.090 3.414 3.045 3.370 3.006 3.332 4.284 4.766 4.160 4.642 4.152 4.635 4.137 4.621 4.490 4.973 4.371 4.854 4.284 4.767 4.245 4.728 4.635 5.161 4.505 5.032 4.498 5.025 4.482 5.010 4.860 5.388 4.735 5.262 4.644 5.171 4.602 5.129 5.091 4.971 5.687 5.545 4.956 4.836 5.552 5.410 4.947 4.826 5.544 5.401 4.932 4.811 5.529 5.386 5.338 5.218 5.934 5.792 5.206 5.086 5.802 5.660 5.110 4.989 5.707 5.564 5.067 4.946 5.664 5.521 5.177 5.873 5.042 5.763 5.034 5.732 5.019 5.737 5.424 6.081 5.292 5.957 5.197 5.879 5.154 5.822 4.635 5.091 5.161 5.687 4.505 4.956 5.032 5.552 4.498 4.947 5.025 5.544 4.482 4.932 5.010 5.529 4.860 5.338 5.388 5.934 4.735 5.206 5.262 5.802 4.644 5.110 5.171 5.707 4.602 5.067 5.129 5.664 4.971 5.545 4.836 5.410 4.826 5.401 4.811 5.386 5.218 5.792 5.086 5.660 4.989 5.564 4.946 5.521 5.177 5.873 5.042 5.763 5.034 5.732 5.019 5.737 5.424 6.081 5.292 5.957 5.197 5.879 5.154 5.822 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-73 Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.378 3.705 3.200 3.524 3.115 3.442 3.095 3.422 3.032 3.359 3.015 3.341 3.324 3.651 3.112 3.439 3.088 3.414 3.076 3.403 3.021 3.348 3.015 3.343 3.378 3.705 3.200 3.524 3.115 3.442 3.095 3.422 3.032 3.359 3.015 3.341 3.324 3.651 3.112 3.439 3.088 3.414 3.076 3.403 3.021 3.348 3.015 3.343 4.810 5.294 4.533 5.015 4.424 4.908 4.366 4.850 4.306 4.789 4.285 4.768 4.739 5.223 4.420 4.904 4.353 4.837 4.337 4.820 4.298 4.782 4.281 4.765 5.219 5.748 4.912 5.439 4.796 5.324 4.742 5.270 4.668 5.195 4.647 5.174 5.152 5.680 4.795 5.324 4.737 5.264 4.712 5.239 4.661 5.188 4.648 5.177 5.742 5.621 6.339 6.196 5.395 5.275 5.991 5.849 5.284 5.163 5.881 5.738 5.218 5.097 5.815 5.672 5.137 5.016 5.734 5.591 5.114 4.993 5.711 5.568 5.680 5.559 6.277 6.134 5.288 5.167 5.885 5.742 5.221 5.100 5.818 5.675 5.201 5.080 5.798 5.655 5.131 5.010 5.728 5.585 5.120 4.999 5.717 5.574 5.829 6.478 5.481 6.147 5.371 6.035 5.305 5.958 5.224 5.889 5.201 5.856 5.767 6.423 5.375 6.037 5.308 5.960 5.288 5.943 5.218 5.880 5.207 5.859 5.219 5.742 5.748 6.339 4.912 5.395 5.439 5.991 4.796 5.284 5.324 5.881 4.742 5.218 5.270 5.815 4.668 5.137 5.195 5.734 4.647 5.114 5.174 5.711 5.152 5.680 5.680 6.277 4.795 5.288 5.324 5.885 4.737 5.221 5.264 5.818 4.712 5.201 5.239 5.798 4.661 5.131 5.188 5.728 4.648 5.120 5.177 5.717 5.621 6.196 5.275 5.849 5.163 5.738 5.097 5.672 5.016 5.591 4.993 5.568 5.559 6.134 5.167 5.742 5.100 5.675 5.080 5.655 5.010 5.585 4.999 5.574 5.829 6.478 5.481 6.147 5.371 6.035 5.305 5.958 5.224 5.889 5.201 5.856 5.767 6.423 5.375 6.037 5.308 5.960 5.288 5.943 5.218 5.880 5.207 5.859 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-74 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.240 3.567 3.118 3.444 3.080 3.406 3.031 3.359 3.032 3.359 3.029 3.356 3.028 3.354 3.019 3.345 3.039 3.366 3.035 3.362 3.025 3.351 3.013 3.340 3.013 3.340 3.240 3.567 3.118 3.444 3.080 3.406 3.031 3.359 3.032 3.359 3.029 3.356 3.028 3.354 3.019 3.345 3.039 3.366 3.035 3.362 3.025 3.351 3.013 3.340 3.013 3.340 4.665 5.149 4.440 4.923 4.347 4.831 4.318 4.803 4.275 4.760 4.272 4.757 4.272 4.757 4.259 4.742 4.287 4.772 4.285 4.770 4.276 4.760 4.263 4.747 4.263 4.747 5.087 5.616 4.827 5.354 4.737 5.265 4.687 5.216 4.634 5.163 4.630 5.160 4.631 5.161 4.617 5.145 4.648 5.177 4.646 5.175 4.637 5.166 4.624 5.153 4.624 5.153 5.624 5.503 6.221 6.078 5.338 5.217 5.935 5.792 5.225 5.104 5.822 5.679 5.169 5.048 5.766 5.623 5.100 4.979 5.697 5.554 5.096 4.975 5.693 5.550 5.097 4.976 5.694 5.551 5.082 4.961 5.679 5.536 5.116 4.995 5.713 5.570 5.114 4.993 5.711 5.568 5.105 4.984 5.702 5.559 5.092 4.971 5.689 5.546 5.092 4.971 5.689 5.546 5.711 6.363 5.425 6.078 5.312 5.964 5.256 5.917 5.187 5.874 5.183 5.869 5.184 5.870 5.169 5.854 5.203 5.893 5.201 5.891 5.192 5.889 5.179 5.864 5.179 5.863 5.087 5.624 5.616 6.221 4.827 5.338 5.354 5.935 4.737 5.225 5.265 5.822 4.687 5.169 5.216 5.766 4.634 5.100 5.163 5.697 4.630 5.096 5.160 5.693 4.631 5.097 5.161 5.694 4.617 5.082 5.145 5.679 4.648 5.116 5.177 5.713 4.646 5.114 5.175 5.711 4.637 5.105 5.166 5.702 4.624 5.092 5.153 5.689 4.624 5.092 5.153 5.689 5.503 6.078 5.217 5.792 5.104 5.679 5.048 5.623 4.979 5.554 4.975 5.550 4.976 5.551 4.961 5.536 4.995 5.570 4.993 5.568 4.984 5.559 4.971 5.546 4.971 5.546 5.711 6.363 5.425 6.078 5.312 5.964 5.256 5.917 5.187 5.874 5.183 5.869 5.184 5.870 5.169 5.854 5.203 5.893 5.201 5.891 5.192 5.889 5.179 5.864 5.179 5.863 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-75 Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 8mA SSTL-18 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.020 3.346 3.022 3.349 3.042 3.370 3.030 3.356 3.018 3.345 3.017 3.344 3.014 3.341 3.016 3.343 3.019 3.346 3.020 3.346 3.022 3.349 3.042 3.370 3.030 3.356 3.018 3.345 3.017 3.344 3.014 3.341 3.016 3.343 3.019 3.346 4.262 4.746 4.269 4.754 4.297 4.781 4.287 4.771 4.273 4.757 4.275 4.760 4.270 4.755 4.260 4.744 4.267 4.751 4.621 5.150 4.630 5.159 4.659 5.189 4.650 5.179 4.636 5.165 4.639 5.168 4.633 5.163 4.620 5.149 4.628 5.158 5.087 4.966 5.684 5.541 5.099 4.978 5.696 5.553 5.129 5.008 5.726 5.583 5.120 4.999 5.717 5.574 5.106 4.985 5.703 5.560 5.110 4.989 5.707 5.564 5.104 4.983 5.701 5.558 5.087 4.966 5.684 5.541 5.098 4.977 5.695 5.552 5.174 5.866 5.186 5.889 5.216 5.908 5.207 5.894 5.193 5.879 5.197 5.876 5.191 5.870 5.174 5.867 5.185 5.891 4.621 5.087 5.150 5.684 4.630 5.099 5.159 5.696 4.659 5.129 5.189 5.726 4.650 5.120 5.179 5.717 4.636 5.106 5.165 5.703 4.639 5.110 5.168 5.707 4.633 5.104 5.163 5.701 4.620 5.087 5.149 5.684 4.628 5.098 5.158 5.695 4.966 5.541 4.978 5.553 5.008 5.583 4.999 5.574 4.985 5.560 4.989 5.564 4.983 5.558 4.966 5.541 4.977 5.552 5.174 5.866 5.186 5.889 5.216 5.908 5.207 5.894 5.193 5.879 5.197 5.876 5.191 5.870 5.174 5.867 5.185 5.891 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-76 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.026 3.353 3.020 3.346 3.012 3.338 3.014 3.341 3.011 3.338 3.019 3.346 3.031 3.358 3.027 3.354 3.023 3.350 3.016 3.343 3.016 3.344 3.014 3.342 3.026 3.353 3.020 3.346 3.012 3.338 3.014 3.341 3.011 3.338 3.019 3.346 3.031 3.358 3.027 3.354 3.023 3.350 3.016 3.343 3.016 3.344 3.014 3.342 4.261 4.746 4.260 4.744 4.252 4.736 4.255 4.739 4.257 4.742 4.256 4.741 4.269 4.754 4.272 4.755 4.267 4.751 4.260 4.744 4.266 4.751 4.247 4.732 4.619 5.149 4.619 5.147 4.611 5.140 4.614 5.143 4.617 5.147 4.615 5.144 4.629 5.159 4.632 5.160 4.627 5.156 4.620 5.149 4.627 5.157 4.605 5.135 5.085 4.964 5.682 5.539 5.084 4.963 5.681 5.538 5.077 4.956 5.674 5.531 5.081 4.960 5.678 5.535 5.085 4.964 5.682 5.539 5.081 4.960 5.678 5.535 5.096 4.975 5.693 5.550 5.099 4.978 5.696 5.553 5.094 4.973 5.691 5.548 5.087 4.966 5.684 5.541 5.097 4.976 5.694 5.551 5.071 4.950 5.668 5.525 5.172 5.868 5.171 5.873 5.164 5.855 5.168 5.858 5.172 5.865 5.168 5.869 5.183 5.881 5.186 5.878 5.181 5.873 5.174 5.867 5.184 5.870 5.158 5.855 4.619 5.085 5.149 5.682 4.619 5.084 5.147 5.681 4.611 5.077 5.140 5.674 4.614 5.081 5.143 5.678 4.617 5.085 5.147 5.682 4.615 5.081 5.144 5.678 4.629 5.096 5.159 5.693 4.632 5.099 5.160 5.696 4.627 5.094 5.156 5.691 4.620 5.087 5.149 5.684 4.627 5.097 5.157 5.694 4.605 5.071 5.135 5.668 4.964 5.539 4.963 5.538 4.956 5.531 4.960 5.535 4.964 5.539 4.960 5.535 4.975 5.550 4.978 5.553 4.973 5.548 4.966 5.541 4.976 5.551 4.950 5.525 5.172 5.868 5.171 5.873 5.164 5.855 5.168 5.858 5.172 5.865 5.168 5.869 5.183 5.881 5.186 5.878 5.181 5.873 5.174 5.867 5.184 5.870 5.158 5.855 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-77 Table 1-53. EP3SL70 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.035 3.361 3.026 3.353 3.026 3.354 3.016 3.343 3.016 3.343 3.037 3.364 3.140 3.467 3.140 3.467 3.035 3.361 3.026 3.353 3.026 3.354 3.016 3.343 3.016 3.343 3.037 3.364 3.140 3.467 3.140 3.467 4.284 4.768 4.275 4.759 4.282 4.767 4.269 4.754 4.270 4.754 4.286 4.770 4.331 4.815 4.331 4.815 4.647 5.176 4.638 5.167 4.646 5.175 4.632 5.162 4.633 5.162 4.648 5.177 4.684 5.211 4.684 5.211 5.117 4.996 5.714 5.571 5.108 4.987 5.705 5.562 5.117 4.996 5.714 5.571 5.103 4.982 5.700 5.557 5.104 4.983 5.701 5.558 5.117 4.996 5.714 5.571 5.142 5.021 5.739 5.596 5.142 5.021 5.739 5.596 5.204 5.900 5.195 5.888 5.204 5.891 5.190 5.885 5.191 5.877 5.204 5.914 5.229 5.945 5.229 5.945 4.647 5.117 5.176 5.714 4.638 5.108 5.167 5.705 4.646 5.117 5.175 5.714 4.632 5.103 5.162 5.700 4.633 5.104 5.162 5.701 4.648 5.117 5.177 5.714 4.684 5.142 5.211 5.739 4.684 5.142 5.211 5.739 4.996 5.571 4.987 5.562 4.996 5.571 4.982 5.557 4.983 5.558 4.996 5.571 5.021 5.596 5.021 5.596 5.204 5.900 5.195 5.888 5.204 5.891 5.190 5.885 5.191 5.877 5.204 5.914 5.229 5.945 5.229 5.945 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-78 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-54 lists the EP3SL70 row pins output timing parameters for single-ended I/O standards. Table 1-54. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.182 1.474 3.089 1.408 2.990 1.329 3.192 1.476 2.994 1.333 3.136 1.435 3.011 1.334 2.972 1.297 3.050 1.356 2.950 1.284 3.162 1.461 3.052 1.376 3.006 1.319 3.424 1.669 3.319 1.598 3.213 1.509 3.428 1.676 3.219 1.513 3.370 1.630 3.243 1.518 3.192 1.480 3.289 1.542 3.170 1.464 3.406 1.667 3.307 1.564 3.231 1.520 4.767 5.163 5.668 5.532 5.739 5.293 5.802 5.667 5.813 2.054 2.135 2.377 2.393 2.266 2.251 2.501 2.515 2.258 4.637 5.025 5.524 5.388 5.595 5.152 5.653 5.518 5.664 1.944 2.023 2.233 2.249 2.152 2.138 2.352 2.366 2.142 4.518 4.902 5.396 5.260 5.467 5.025 5.521 5.386 5.532 1.838 1.923 2.119 2.138 2.056 2.039 2.235 2.252 2.043 4.775 5.168 5.673 5.537 5.744 5.299 5.807 5.672 5.818 2.058 2.140 2.382 2.398 2.275 2.259 2.506 2.520 2.270 4.524 4.908 5.402 5.266 5.473 5.031 5.528 5.393 5.539 1.849 1.938 2.129 2.148 2.066 2.051 2.244 2.261 2.052 4.719 5.116 5.625 5.489 5.696 5.250 5.760 5.625 5.771 2.021 2.103 2.334 2.350 2.232 2.219 2.459 2.473 2.224 4.566 4.957 5.461 5.325 5.532 5.088 5.596 5.460 5.606 1.884 1.961 2.170 2.186 2.087 2.077 2.295 2.308 2.078 4.484 4.874 5.373 5.237 5.444 5.002 5.503 5.367 5.513 1.824 1.896 2.082 2.099 2.017 2.009 2.202 2.215 2.005 4.613 5.009 5.514 5.378 5.585 5.142 5.649 5.513 5.659 1.919 1.996 2.223 2.239 2.123 2.111 2.348 2.361 2.114 4.449 4.835 5.334 5.198 5.405 4.962 5.463 5.327 5.473 1.796 1.867 2.052 2.071 1.989 1.979 2.169 2.185 1.976 4.851 5.270 5.797 5.661 5.868 5.410 5.939 5.803 5.949 2.129 2.229 2.506 2.522 2.377 2.351 2.638 2.651 2.376 4.696 5.107 5.627 5.491 5.698 5.243 5.765 5.629 5.775 2.005 2.094 2.336 2.352 2.235 2.214 2.464 2.477 2.231 4.585 4.988 5.501 5.365 5.572 5.120 5.635 5.499 5.645 1.921 2.008 2.210 2.226 2.144 2.125 2.334 2.347 2.137 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVTTL 3.3-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 4mA 3.0-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-79 Table 1-54. EP3SL70 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.350 1.728 3.177 1.503 3.102 1.438 3.084 1.378 3.292 1.639 3.100 1.397 3.073 1.370 3.054 1.361 3.222 1.582 3.105 1.402 2.991 1.323 2.979 1.318 2.963 1.309 3.691 1.915 3.489 1.713 3.387 1.611 3.313 1.557 3.609 1.833 3.352 1.576 3.304 1.548 3.295 1.537 3.534 1.758 3.345 1.578 3.217 1.508 3.205 1.504 3.187 1.493 5.275 5.573 6.134 5.998 6.210 5.723 6.286 6.151 6.297 2.562 2.717 2.981 2.999 2.946 2.881 3.150 3.167 2.958 4.948 5.247 5.774 5.638 5.850 5.397 5.925 5.789 5.935 2.235 2.349 2.576 2.594 2.541 2.516 2.744 2.760 2.551 4.795 5.142 5.673 5.537 5.749 5.283 5.819 5.684 5.830 2.082 2.199 2.417 2.435 2.382 2.348 2.571 2.588 2.379 4.718 5.089 5.608 5.472 5.684 5.227 5.747 5.612 5.758 2.005 2.106 2.321 2.339 2.286 2.253 2.477 2.494 2.285 5.185 5.500 6.071 5.935 6.147 5.644 6.221 6.086 6.232 2.472 2.631 2.909 2.927 2.874 2.788 3.074 3.091 2.882 4.780 5.142 5.677 5.541 5.753 5.280 5.820 5.685 5.831 2.067 2.194 2.418 2.436 2.383 2.342 2.570 2.587 2.378 4.707 5.081 5.608 5.472 5.684 5.220 5.747 5.612 5.758 1.994 2.098 2.312 2.330 2.277 2.244 2.465 2.482 2.273 4.685 5.057 5.589 5.453 5.665 5.196 5.728 5.593 5.739 1.972 2.080 2.293 2.311 2.258 2.226 2.443 2.460 2.251 5.095 5.432 6.010 5.874 6.086 5.576 6.152 6.017 6.163 2.382 2.545 2.834 2.852 2.799 2.700 2.990 3.007 2.798 4.802 5.170 5.725 5.589 5.801 5.309 5.864 5.729 5.875 2.089 2.222 2.459 2.477 2.424 2.367 2.612 2.629 2.420 4.563 4.960 5.469 5.333 5.540 5.087 5.597 5.462 5.608 1.914 1.999 2.197 2.216 2.134 2.112 2.315 2.332 2.123 4.555 4.952 5.461 5.325 5.532 5.079 5.590 5.455 5.601 1.911 1.997 2.195 2.214 2.132 2.111 2.314 2.331 2.122 4.530 4.927 5.434 5.298 5.505 5.053 5.563 5.428 5.574 1.896 1.981 2.178 2.197 2.115 2.094 2.296 2.313 2.104 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V 1.5 V 1.2 V SSTL-2 CLASS I 12mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-80 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-54. EP3SL70 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.033 1.339 3.028 1.324 3.017 1.313 3.006 1.290 3.006 1.290 3.014 1.299 3.015 1.299 3.036 1.335 3.022 1.312 3.011 1.295 3.269 1.501 3.255 1.496 3.243 1.485 3.220 1.474 3.219 1.473 3.228 1.480 3.223 1.483 3.265 1.504 3.243 1.490 3.226 1.478 4.613 4.993 5.503 5.367 5.579 5.126 5.638 5.503 5.649 1.909 1.997 2.194 2.212 2.159 2.134 2.340 2.357 2.148 4.610 4.992 5.502 5.366 5.578 5.124 5.636 5.501 5.647 1.907 1.996 2.192 2.210 2.157 2.132 2.338 2.355 2.146 4.593 4.982 5.492 5.356 5.568 5.115 5.627 5.492 5.638 1.897 1.986 2.175 2.193 2.140 2.115 2.322 2.339 2.130 4.577 4.969 5.479 5.343 5.555 5.103 5.615 5.480 5.626 1.884 1.973 2.160 2.178 2.125 2.100 2.307 2.324 2.115 4.576 4.969 5.479 5.343 5.555 5.102 5.615 5.480 5.626 1.884 1.973 2.159 2.177 2.124 2.099 2.306 2.323 2.114 4.574 4.966 5.474 5.338 5.550 5.098 5.609 5.474 5.620 1.883 1.970 2.153 2.171 2.118 2.094 2.299 2.316 2.107 4.573 4.974 5.484 5.348 5.560 5.107 5.620 5.485 5.631 1.889 1.978 2.155 2.173 2.120 2.096 2.303 2.320 2.111 4.624 5.004 5.516 5.380 5.592 5.136 5.650 5.515 5.661 1.918 2.008 2.211 2.229 2.176 2.147 2.356 2.373 2.164 4.606 4.994 5.506 5.370 5.582 5.127 5.641 5.506 5.652 1.907 1.998 2.194 2.212 2.159 2.131 2.340 2.357 2.148 4.589 4.981 5.493 5.357 5.569 5.114 5.628 5.493 5.639 1.894 1.985 2.176 2.194 2.141 2.113 2.323 2.340 2.131 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-18 CLASS II 16mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-81 Table 1-54. EP3SL70 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.021 1.314 3.014 1.302 3.005 1.289 3.008 1.292 3.004 1.288 3.012 1.296 3.027 1.321 3.021 1.309 3.017 1.305 3.029 1.320 3.020 1.308 3.019 1.305 3.076 1.429 3.076 1.429 3.241 1.486 3.229 1.480 3.217 1.472 3.219 1.474 3.214 1.471 3.218 1.479 3.248 1.492 3.238 1.487 3.233 1.483 3.247 1.494 3.235 1.486 3.233 1.486 3.300 1.614 3.300 1.614 4.580 4.964 5.472 5.336 5.548 5.097 5.606 5.471 5.617 1.882 1.968 2.156 2.174 2.121 2.098 2.302 2.319 2.110 4.571 4.963 5.471 5.335 5.547 5.096 5.606 5.471 5.617 1.880 1.967 2.148 2.166 2.113 2.090 2.295 2.312 2.103 4.563 4.956 5.464 5.328 5.540 5.089 5.599 5.464 5.610 1.873 1.960 2.140 2.158 2.105 2.082 2.287 2.304 2.095 4.565 4.959 5.468 5.332 5.544 5.092 5.602 5.467 5.613 1.876 1.963 2.143 2.161 2.108 2.085 2.290 2.307 2.098 4.563 4.962 5.471 5.335 5.547 5.095 5.607 5.472 5.618 1.878 1.966 2.143 2.161 2.108 2.085 2.291 2.308 2.099 4.558 4.959 5.467 5.331 5.543 5.091 5.601 5.466 5.612 1.876 1.963 2.134 2.152 2.099 2.078 2.280 2.297 2.088 4.591 4.974 5.483 5.347 5.559 5.106 5.617 5.482 5.628 1.891 1.978 2.171 2.189 2.136 2.110 2.316 2.333 2.124 4.587 4.976 5.485 5.349 5.561 5.108 5.620 5.485 5.631 1.892 1.980 2.167 2.185 2.132 2.107 2.313 2.330 2.121 4.581 4.971 5.480 5.344 5.556 5.103 5.614 5.479 5.625 1.887 1.975 2.161 2.179 2.126 2.101 2.307 2.324 2.115 4.602 4.990 5.502 5.366 5.578 5.122 5.636 5.501 5.647 1.904 1.994 2.189 2.207 2.154 2.124 2.333 2.350 2.141 4.591 4.981 5.493 5.357 5.569 5.113 5.627 5.492 5.638 1.895 1.985 2.177 2.195 2.142 2.113 2.322 2.339 2.130 4.595 4.989 5.502 5.366 5.578 5.122 5.637 5.502 5.648 1.902 1.993 2.183 2.201 2.148 2.119 2.329 2.346 2.137 4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621 1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165 4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621 1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-82 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-55 through Table 1-60 list the maximum I/O timing parameters for EP3SL70 devices for differential I/O standards. Table 1-55 lists the EP3SL70 column pins input timing parameters for differential I/O standards. Table 1-55. EP3SL70 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK tsu th -0.697 0.814 1.143 -0.892 -0.697 0.814 1.143 -0.892 -0.705 0.822 1.135 -0.884 -0.705 0.822 1.135 -0.884 -0.717 0.834 1.123 -0.872 -0.717 0.834 1.123 -0.872 -0.705 0.822 1.135 -0.884 -0.705 0.822 1.135 -0.884 -0.717 0.849 1.159 -0.893 -0.717 0.849 1.159 -0.893 -0.729 0.861 1.147 -0.881 -0.729 0.861 1.147 -0.881 -0.740 0.872 1.136 -0.870 -0.740 0.872 1.136 -0.870 -0.729 0.861 1.147 -0.881 -0.729 0.861 1.147 -0.881 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.2-V HSTL CLASS I -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.2-V HSTL CLASS II -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.5-V HSTL CLASS I -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.5-V HSTL CLASS II -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 1.8-V HSTL CLASS I -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-83 Table 1-55. EP3SL70 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.717 0.834 1.123 -0.872 -0.717 0.834 1.123 -0.872 -0.724 0.841 1.116 -0.865 -0.724 0.841 1.116 -0.865 -0.697 0.814 1.143 -0.892 -0.697 0.814 1.143 -0.892 -0.705 0.822 1.135 -0.884 -0.740 0.872 1.136 -0.870 -0.740 0.872 1.136 -0.870 -0.746 0.878 1.130 -0.864 -0.746 0.878 1.130 -0.864 -0.717 0.849 1.159 -0.893 -0.717 0.849 1.159 -0.893 -0.729 0.861 1.147 -0.881 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 1.277 1.802 1.411 2.031 1.557 2.244 1.489 2.131 1.775 2.137 1.420 2.041 1.565 2.255 1.502 2.140 1.810 2.186 DIFFERENTIAL 1.5-V SSTL CLASS I -1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 -1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 1.290 1.790 1.419 2.026 1.560 2.244 1.492 2.129 1.779 2.138 1.427 2.037 1.565 2.260 1.501 2.142 1.811 2.190 DIFFERENTIAL 1.5-V SSTL CLASS II -1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 -1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 1.290 1.790 1.419 2.026 1.560 2.244 1.492 2.129 1.779 2.138 1.427 2.037 1.565 2.260 1.501 2.142 1.811 2.190 DIFFERENTIAL 1.8-V SSTL CLASS I -1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 DIFFERENTIAL 1.8-V SSTL CLASS II -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 1.257 1.821 1.389 2.053 1.522 2.279 1.454 2.166 1.740 2.172 1.398 2.063 1.532 2.288 1.469 2.173 1.777 2.219 DIFFERENTIAL 2.5-V SSTL CLASS I -1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 -1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 1.267 1.811 1.400 2.042 1.538 2.263 1.470 2.150 1.756 2.156 1.409 2.052 1.547 2.273 1.484 2.158 1.792 2.204 DIFFERENTIAL 2.5-V SSTL CLASS II -1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-84 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-56 lists the EP3SL70 row pins input timing parameters for differential I/O standards. Table 1-56. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK LVDS GCLK PLL GCLK MINI-LVDS GCLK PLL GCLK RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.919 1.042 0.882 -0.625 -0.919 1.042 0.882 -0.625 -0.919 1.042 0.882 -0.625 -0.734 0.850 1.077 -0.827 -0.734 0.850 1.077 -0.827 -0.743 0.859 1.068 -0.818 -0.743 0.859 1.068 -0.818 -0.757 0.873 1.054 -0.804 -0.939 1.077 0.896 -0.625 -0.939 1.077 0.896 -0.625 -0.939 1.077 0.896 -0.625 -0.764 0.893 1.081 -0.819 -0.764 0.893 1.081 -0.819 -0.776 0.905 1.069 -0.807 -0.776 0.905 1.069 -0.807 -0.788 0.917 1.057 -0.795 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 -1.349 1.613 2.393 -1.865 -1.349 1.613 2.393 -1.865 -1.349 1.613 2.393 -1.865 -1.543 1.758 2.209 -1.730 -1.543 1.758 2.209 -1.730 -1.559 1.774 2.193 -1.714 -1.559 1.774 2.193 -1.714 -1.576 1.791 2.176 -1.697 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 1.209 1.863 1.205 2.243 1.369 2.446 1.306 2.322 1.580 2.342 1.182 2.291 1.339 2.500 1.280 2.376 -1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 1.274 1.776 1.394 2.019 1.516 2.257 1.451 2.138 1.720 2.163 1.410 2.024 1.531 2.263 1.470 2.144 DIFFERENTIAL 1.2-V HSTL CLASS I -1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 1.274 1.776 1.394 2.019 1.516 2.257 1.451 2.138 1.720 2.163 1.410 2.024 1.531 2.263 1.470 2.144 DIFFERENTIAL 1.2-V HSTL CLASS II -1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 DIFFERENTIAL 1.5-V HSTL CLASS I -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 DIFFERENTIAL 1.5-V HSTL CLASS II -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 DIFFERENTIAL 1.8-V HSTL CLASS I -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-85 Table 1-56. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.757 0.873 1.054 -0.804 -0.743 0.859 1.068 -0.818 -0.743 0.859 1.068 -0.818 -0.757 0.873 1.054 -0.804 -0.757 0.873 1.054 -0.804 -0.756 0.872 1.045 -0.795 -0.756 0.872 1.045 -0.795 -0.788 0.917 1.057 -0.795 -0.776 0.905 1.069 -0.807 -0.776 0.905 1.069 -0.807 -0.788 0.917 1.057 -0.795 -0.788 0.917 1.057 -0.795 -0.787 0.916 1.048 -0.786 -0.787 0.916 1.048 -0.786 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 -1.576 1.791 2.176 -1.697 -1.559 1.774 2.193 -1.714 -1.559 1.774 2.193 -1.714 -1.576 1.791 2.176 -1.697 -1.576 1.791 2.176 -1.697 -1.573 1.792 2.169 -1.686 -1.573 1.792 2.169 -1.686 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 DIFFERENTIAL 1.5-V SSTL CLASS I -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 1.283 1.767 1.404 2.009 1.532 2.241 1.467 2.122 1.736 2.147 1.419 2.015 1.547 2.247 1.486 2.128 DIFFERENTIAL 1.5-V SSTL CLASS II -1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 DIFFERENTIAL 1.8-V SSTL CLASS I -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 1.295 1.754 1.414 1.999 1.550 2.223 1.485 2.104 1.754 2.129 1.430 2.004 1.564 2.230 1.503 2.111 DIFFERENTIAL 1.8-V SSTL CLASS II -1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 1.300 1.739 1.422 1.983 1.554 2.212 1.489 2.092 1.759 2.118 1.434 1.993 1.563 2.224 1.502 2.103 DIFFERENTIAL 2.5-V SSTL CLASS I -1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 1.300 1.739 1.422 1.983 1.554 2.212 1.489 2.092 1.759 2.118 1.434 1.993 1.563 2.224 1.502 2.103 DIFFERENTIAL 2.5-V SSTL CLASS II -1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-86 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-57 lists the EP3SL70 column pins output timing parameters for differential I/O standards. Table 1-57. EP3SL70 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.029 3.025 3.029 3.025 3.029 3.025 3.056 3.046 3.046 3.039 3.038 3.060 3.050 3.045 3.043 3.035 3.036 3.035 3.047 3.043 3.033 3.031 3.031 3.035 3.246 3.249 3.246 3.249 3.246 3.249 3.279 3.269 3.269 3.263 3.261 3.283 3.272 3.268 3.266 3.257 3.259 3.256 3.269 3.266 3.255 3.253 3.254 3.257 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-87 Table 1-57. EP3SL70 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.061 3.047 3.035 3.035 3.031 3.035 3.036 3.064 3.053 3.048 3.034 3.032 3.036 3.036 3.052 3.052 3.042 3.035 3.029 3.025 3.029 3.025 3.029 3.025 3.286 3.272 3.259 3.259 3.255 3.257 3.259 3.289 3.277 3.273 3.258 3.256 3.258 3.259 3.276 3.276 3.266 3.258 3.246 3.249 3.246 3.249 3.246 3.249 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 4.646 5.055 5.573 5.433 5.651 5.183 5.701 5.563 5.720 4.629 5.037 5.555 5.415 5.633 5.165 5.683 5.545 5.702 4.632 5.041 5.559 5.419 5.637 5.169 5.688 5.550 5.707 4.625 5.033 5.552 5.412 5.630 5.162 5.680 5.542 5.699 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.626 5.034 5.551 5.411 5.629 5.161 5.679 5.541 5.698 4.657 5.064 5.581 5.441 5.659 5.192 5.708 5.570 5.727 4.645 5.052 5.569 5.429 5.647 5.180 5.696 5.558 5.715 4.645 5.053 5.570 5.430 5.648 5.181 5.698 5.560 5.717 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-88 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-57. EP3SL70 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.056 3.046 3.046 3.039 3.038 3.060 3.050 3.045 3.043 3.035 3.036 3.035 3.047 3.043 3.033 3.031 3.031 3.035 3.061 3.047 3.035 3.035 3.031 3.035 3.036 3.064 3.053 3.048 3.279 3.269 3.269 3.263 3.261 3.283 3.272 3.268 3.266 3.257 3.259 3.256 3.269 3.266 3.255 3.253 3.254 3.257 3.286 3.272 3.259 3.259 3.255 3.257 3.259 3.289 3.277 3.273 4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 4.658 5.066 5.583 5.443 5.661 5.193 5.710 5.572 5.729 4.646 5.055 5.573 5.433 5.651 5.183 5.701 5.563 5.720 4.629 5.037 5.555 5.415 5.633 5.165 5.683 5.545 5.702 4.632 5.041 5.559 5.419 5.637 5.169 5.688 5.550 5.707 4.625 5.033 5.552 5.412 5.630 5.162 5.680 5.542 5.699 4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 4.626 5.034 5.551 5.411 5.629 5.161 5.679 5.541 5.698 4.657 5.064 5.581 5.441 5.659 5.192 5.708 5.570 5.727 4.645 5.052 5.569 5.429 5.647 5.180 5.696 5.558 5.715 4.645 5.053 5.570 5.430 5.648 5.181 5.698 5.560 5.717 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-89 Table 1-57. EP3SL70 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco 3.034 3.032 3.036 3.036 3.052 3.052 3.042 3.035 3.258 3.256 3.258 3.259 3.276 3.276 3.266 3.258 4.627 5.034 5.551 5.411 5.629 5.162 5.680 5.542 5.699 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 4.625 5.032 5.549 5.409 5.627 5.160 5.677 5.539 5.696 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.641 5.047 5.563 5.423 5.641 5.175 5.690 5.552 5.709 4.631 5.037 5.553 5.413 5.631 5.165 5.681 5.543 5.700 4.617 5.022 5.537 5.397 5.615 5.149 5.664 5.526 5.683 ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-90 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-58 lists the EP3SL70 row pins output timing parameters for differential I/O standards. Table 1-58. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK tco LVDS 2.668 3.062 3.044 2.668 3.062 3.044 2.668 3.062 3.044 3.098 3.084 3.080 3.096 3.085 3.082 3.093 3.083 3.069 3.066 3.063 3.064 3.113 3.089 3.071 3.117 3.102 2.842 3.288 3.278 2.842 3.288 3.278 2.842 3.288 3.278 3.331 3.317 3.313 3.328 3.318 3.315 3.325 3.316 3.302 3.298 3.296 3.296 3.349 3.325 3.306 3.352 3.337 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 4.730 5.145 5.672 5.528 5.727 5.280 5.809 4.717 5.132 5.659 5.515 5.714 5.266 5.796 4.715 5.132 5.660 5.516 5.715 5.266 5.798 4.716 5.129 5.654 5.510 5.709 5.263 5.791 4.712 5.125 5.651 5.507 5.706 5.260 5.788 4.710 5.123 5.649 5.505 5.704 5.258 5.787 4.711 5.124 5.648 5.504 5.703 5.257 5.785 4.709 5.122 5.647 5.503 5.702 5.257 5.785 4.694 5.107 5.633 5.489 5.688 5.242 5.770 4.690 5.103 5.629 5.485 5.684 5.238 5.766 4.691 5.106 5.632 5.488 5.687 5.241 5.770 4.681 5.094 5.619 5.475 5.674 5.228 5.756 4.752 5.167 5.695 5.551 5.750 5.302 5.832 4.734 5.150 5.678 5.534 5.733 5.285 5.817 4.712 5.128 5.656 5.512 5.711 5.263 5.795 4.752 5.167 5.694 5.550 5.749 5.302 5.832 4.738 5.152 5.679 5.535 5.734 5.287 5.817 4.795 5.565 5.626 4.795 5.565 5.626 4.795 5.565 5.626 5.665 5.652 5.654 5.647 5.644 5.643 5.641 5.641 5.626 5.622 5.626 5.612 5.688 5.673 5.651 5.688 5.673 4.940 5.694 5.755 4.940 5.694 5.755 4.940 5.694 5.755 5.794 5.781 5.783 5.776 5.773 5.772 5.770 5.770 5.755 5.751 5.755 5.741 5.817 5.802 5.780 5.817 5.802 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL GCLK tco GCLK tco PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I 4mA 6mA 8mA 4mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-91 Table 1-58. EP3SL70 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I GCLK tco 6mA GCLK tco PLL GCLK tco 8mA GCLK tco PLL GCLK tco 4mA GCLK tco PLL GCLK tco 6mA GCLK tco PLL GCLK tco 8mA GCLK tco PLL GCLK tco 10mA GCLK tco PLL GCLK tco 12mA GCLK tco PLL GCLK tco 16mA GCLK tco PLL GCLK tco 4mA GCLK tco PLL GCLK tco 6mA GCLK tco PLL GCLK tco 8mA GCLK tco PLL GCLK tco 4mA GCLK tco PLL GCLK tco 6mA GCLK tco PLL 3.091 3.071 3.068 3.073 3.066 3.094 3.076 3.062 2.668 3.062 3.044 2.668 3.062 3.044 2.668 3.062 3.044 3.098 3.084 3.080 3.096 3.085 3.082 3.093 3.083 3.069 3.326 3.306 3.302 3.306 3.299 3.328 3.311 3.295 2.842 3.288 3.278 2.842 3.288 3.278 2.842 3.288 3.278 3.331 3.317 3.313 3.328 3.318 3.315 3.325 3.316 3.302 4.733 5.149 5.676 5.532 5.731 5.284 5.815 4.710 5.125 5.653 5.509 5.708 5.261 5.791 4.706 5.122 5.649 5.505 5.704 5.257 5.788 4.697 5.110 5.635 5.491 5.690 5.244 5.772 4.696 5.111 5.638 5.494 5.693 5.247 5.777 4.724 5.138 5.664 5.520 5.719 5.273 5.802 4.709 5.123 5.649 5.505 5.704 5.258 5.787 4.686 5.099 5.624 5.480 5.679 5.234 5.762 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 3.979 4.346 4.821 4.685 4.892 4.453 4.930 4.646 5.055 5.575 5.431 5.630 5.186 5.709 4.684 5.101 5.629 5.485 5.684 5.237 5.770 4.730 5.145 5.672 5.528 5.727 5.280 5.809 4.717 5.132 5.659 5.515 5.714 5.266 5.796 4.715 5.132 5.660 5.516 5.715 5.266 5.798 4.716 5.129 5.654 5.510 5.709 5.263 5.791 4.712 5.125 5.651 5.507 5.706 5.260 5.788 4.710 5.123 5.649 5.505 5.704 5.258 5.787 4.711 5.124 5.648 5.504 5.703 5.257 5.785 4.709 5.122 5.647 5.503 5.702 5.257 5.785 4.694 5.107 5.633 5.489 5.688 5.242 5.770 5.671 5.647 5.644 5.628 5.633 5.658 5.643 5.618 4.795 5.565 5.626 4.795 5.565 5.626 4.795 5.565 5.626 5.665 5.652 5.654 5.647 5.644 5.643 5.641 5.641 5.626 5.800 5.776 5.773 5.757 5.762 5.787 5.772 5.747 4.940 5.694 5.755 4.940 5.694 5.755 4.940 5.694 5.755 5.794 5.781 5.783 5.776 5.773 5.772 5.770 5.770 5.755 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-92 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-58. EP3SL70 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II GCLK tco 8mA GCLK tco PLL 3.066 3.063 3.064 3.113 3.089 3.071 3.117 3.102 3.091 3.071 3.068 3.073 3.066 3.094 3.076 3.062 3.298 3.296 3.296 3.349 3.325 3.306 3.352 3.337 3.326 3.306 3.302 3.306 3.299 3.328 3.311 3.295 4.690 5.103 5.629 5.485 5.684 5.238 5.766 4.691 5.106 5.632 5.488 5.687 5.241 5.770 4.681 5.094 5.619 5.475 5.674 5.228 5.756 4.752 5.167 5.695 5.551 5.750 5.302 5.832 4.734 5.150 5.678 5.534 5.733 5.285 5.817 4.712 5.128 5.656 5.512 5.711 5.263 5.795 4.752 5.167 5.694 5.550 5.749 5.302 5.832 4.738 5.152 5.679 5.535 5.734 5.287 5.817 4.733 5.149 5.676 5.532 5.731 5.284 5.815 4.710 5.125 5.653 5.509 5.708 5.261 5.791 4.706 5.122 5.649 5.505 5.704 5.257 5.788 4.697 5.110 5.635 5.491 5.690 5.244 5.772 4.696 5.111 5.638 5.494 5.693 5.247 5.777 4.724 5.138 5.664 5.520 5.719 5.273 5.802 4.709 5.123 5.649 5.505 5.704 5.258 5.787 4.686 5.099 5.624 5.480 5.679 5.234 5.762 5.622 5.626 5.612 5.688 5.673 5.651 5.688 5.673 5.671 5.647 5.644 5.628 5.633 5.658 5.643 5.618 5.751 5.755 5.741 5.817 5.802 5.780 5.817 5.802 5.800 5.776 5.773 5.757 5.762 5.787 5.772 5.747 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK tco 10mA GCLK tco PLL GCLK tco 12mA GCLK tco PLL GCLK tco 8mA GCLK tco PLL GCLK tco 16mA GCLK tco PLL GCLK tco 8mA GCLK tco PLL GCLK tco 12mA GCLK tco PLL GCLK tco 16mA GCLK tco PLL Table 1-59 and Table 1-60 list the EP3SL70 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-59 lists the EP3SL70 column pin delay adders when using the regional clock. Table 1-59. EP3SL70 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units 0.158 -0.014 -0.114 1.642 0.168 -0.012 -0.116 1.675 0.225 -0.007 -0.137 2.599 0.241 -0.003 -0.139 2.912 0.257 -0.002 -0.141 3.223 0.247 -0.005 -0.137 3.071 0.313 0.191 -0.215 3.22 0.244 -0.003 -0.132 2.931 0.258 -0.003 -0.133 3.238 0.252 -0.004 -0.136 3.083 0.315 0.191 -0.215 3.338 ns ns ns ns Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-93 Table 1-60 lists the EP3SL70 row pin delay adders when using the regional clock. Table 1-60. EP3SL70 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.111 0.099 -0.113 -0.107 0.123 0.105 -0.127 -0.112 0.177 0.156 0.192 0.175 0.207 0.195 0.198 0.185 0.263 0.263 0.194 0.177 0.212 0.195 0.201 0.188 -0.21 0.266 0.263 -0.273 ns ns ns ns -0.183 -0.198 -0.213 -0.205 -0.272 -0.202 -0.216 -0.164 -0.185 -0.202 -0.193 -0.258 -0.184 -0.204 -0.197 -0.257 EP3SL110 I/O Timing Parameters Table 1-61 through Table 1-65 list the maximum I/O timing parameters for EP3SL110 devices for single-ended I/O standards. Table 1-61 lists the EP3SL110 column pins input timing parameters for single-ended I/O standards. Table 1-61. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.917 1.053 -1.234 1.512 -0.917 1.053 -1.234 1.512 -0.928 1.064 -1.245 1.523 -0.928 1.064 -1.245 1.523 -0.923 1.059 -1.240 1.518 -0.917 1.053 -1.176 1.460 -0.917 1.053 -1.176 1.460 -0.928 1.064 -1.187 1.471 -0.928 1.064 -1.187 1.471 -0.923 1.059 -1.182 1.466 -1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980 1.524 2.116 1.524 2.116 1.523 2.115 1.523 2.115 1.532 2.124 1.667 2.394 1.667 2.394 1.669 2.396 1.669 2.396 1.681 2.408 1.918 2.710 1.918 2.710 1.917 2.709 1.917 2.709 1.936 2.728 1.850 2.610 1.850 2.610 1.849 2.609 1.849 2.609 1.868 2.628 2.205 2.971 2.205 2.971 2.204 2.970 2.204 2.970 2.223 2.989 1.667 2.394 1.667 2.394 1.669 2.396 1.669 2.396 1.681 2.408 1.918 2.710 1.918 2.710 1.917 2.709 1.917 2.709 1.936 2.728 1.850 2.610 1.850 2.610 1.849 2.609 1.849 2.609 1.868 2.628 2.205 2.971 2.205 2.971 2.204 2.970 2.204 2.970 2.223 2.989 -1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470 -1.333 -1.452 -1.682 -1.627 -1.980 -1.452 -1.682 -1.627 -1.980 -1.704 -1.940 -2.210 -2.135 -2.470 -1.940 -2.210 -2.135 -2.470 -1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979 -1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469 -1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979 -1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469 -1.341 -1.466 -1.700 -1.645 -1.998 -1.466 -1.700 -1.645 -1.998 -1.712 -1.954 -2.228 -2.153 -2.488 -1.954 -2.228 -2.153 -2.488 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-94 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-61. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 1.8 V tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.943 1.081 -1.262 1.542 -0.933 1.071 -1.252 1.532 -0.881 1.019 -1.200 1.480 -0.852 0.990 -1.171 1.451 -0.852 0.990 -1.171 1.451 -0.846 0.984 -1.165 1.445 -0.846 0.984 -1.165 1.445 -0.835 0.973 -1.154 1.434 -0.835 0.973 -1.154 1.434 -0.943 1.081 -1.202 1.488 -0.933 1.071 -1.192 1.478 -0.881 1.019 -1.140 1.426 -0.852 0.990 -1.111 1.397 -0.852 0.990 -1.111 1.397 -0.846 0.984 -1.105 1.391 -0.846 0.984 -1.105 1.391 -0.835 0.973 -1.094 1.380 -0.835 0.973 -1.094 1.380 -1.381 -1.502 -1.698 -1.643 -1.996 -1.502 -1.698 -1.643 -1.996 1.572 2.164 1.549 2.141 1.472 2.064 1.444 2.036 1.444 2.036 1.431 2.023 1.431 2.023 1.421 2.013 1.421 2.013 1.717 2.444 1.685 2.412 1.586 2.313 1.570 2.297 1.570 2.297 1.562 2.286 1.562 2.286 1.551 2.275 1.551 2.275 1.934 2.726 1.864 2.656 1.708 2.500 1.710 2.502 1.710 2.502 1.707 2.496 1.707 2.496 1.688 2.477 1.688 2.477 1.866 2.626 1.796 2.556 1.640 2.400 1.642 2.402 1.642 2.402 1.639 2.396 1.639 2.396 1.620 2.377 1.620 2.377 2.221 2.987 2.151 2.917 1.995 2.761 1.997 2.763 1.997 2.763 1.993 2.759 1.993 2.759 1.974 2.740 1.974 2.740 1.717 2.444 1.685 2.412 1.586 2.313 1.570 2.297 1.570 2.297 1.562 2.286 1.562 2.286 1.551 2.275 1.551 2.275 1.934 2.726 1.864 2.656 1.708 2.500 1.710 2.502 1.710 2.502 1.707 2.496 1.707 2.496 1.688 2.477 1.688 2.477 1.866 2.626 1.796 2.556 1.640 2.400 1.642 2.402 1.642 2.402 1.639 2.396 1.639 2.396 1.620 2.377 1.620 2.377 2.221 2.987 2.151 2.917 1.995 2.761 1.997 2.763 1.997 2.763 1.993 2.759 1.993 2.759 1.974 2.740 1.974 2.740 -1.752 -1.990 -2.226 -2.151 -2.486 -1.990 -2.226 -2.151 -2.486 -1.358 -1.470 -1.628 -1.573 -1.926 -1.470 -1.628 -1.573 -1.926 -1.729 -1.958 -2.156 -2.081 -2.416 -1.958 -2.156 -2.081 -2.416 -1.281 -1.371 -1.472 -1.417 -1.770 -1.371 -1.472 -1.417 -1.770 -1.652 -1.859 -2.000 -1.925 -2.260 -1.859 -2.000 -1.925 -2.260 -1.253 -1.355 -1.474 -1.419 -1.772 -1.355 -1.474 -1.419 -1.772 -1.624 -1.843 -2.002 -1.927 -2.262 -1.843 -2.002 -1.927 -2.262 -1.253 -1.355 -1.474 -1.419 -1.772 -1.355 -1.474 -1.419 -1.772 -1.624 -1.843 -2.002 -1.927 -2.262 -1.843 -2.002 -1.927 -2.262 -1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417 -1.773 -1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922 -2.263 -1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417 -1.773 -1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922 -2.263 -1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398 -1.754 -1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903 -2.244 -1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398 -1.754 -1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903 -2.244 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-95 Table 1-61. EP3SL110 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 1.8-V HSTL CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.846 0.984 -1.165 1.445 -0.846 0.984 -1.165 1.445 -0.835 0.973 -1.154 1.434 -0.835 0.973 -1.154 1.434 -0.823 0.961 -1.142 1.422 -0.823 0.961 -1.142 1.422 -0.928 1.064 -1.245 1.523 -0.846 0.984 -1.105 1.391 -0.846 0.984 -1.105 1.391 -0.835 0.973 -1.094 1.380 -0.835 0.973 -1.094 1.380 -0.823 0.961 -1.082 1.368 -0.823 0.961 -1.082 1.368 -0.928 1.064 -1.187 1.471 -1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417 -1.773 1.431 2.023 1.431 2.023 1.421 2.013 1.421 2.013 1.411 2.003 1.411 2.003 1.523 2.115 1.562 2.286 1.562 2.286 1.551 2.275 1.551 2.275 1.540 2.264 1.540 2.264 1.669 2.396 1.707 2.496 1.707 2.496 1.688 2.477 1.688 2.477 1.672 2.461 1.672 2.461 1.917 2.709 1.639 2.396 1.639 2.396 1.620 2.377 1.620 2.377 1.604 2.361 1.604 2.361 1.849 2.609 1.993 2.759 1.993 2.759 1.974 2.740 1.974 2.740 1.958 2.724 1.958 2.724 2.204 2.970 1.562 2.286 1.562 2.286 1.551 2.275 1.551 2.275 1.540 2.264 1.540 2.264 1.669 2.396 1.707 2.496 1.707 2.496 1.688 2.477 1.688 2.477 1.672 2.461 1.672 2.461 1.917 2.709 1.639 2.396 1.639 2.396 1.620 2.377 1.620 2.377 1.604 2.361 1.604 2.361 1.849 2.609 1.993 2.759 1.993 2.759 1.974 2.740 1.974 2.740 1.958 2.724 1.958 2.724 2.204 2.970 -1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922 -2.263 -1.241 -1.350 -1.474 -1.417 -1.773 -1.350 -1.474 -1.417 -1.773 -1.612 -1.835 -1.999 -1.922 -2.263 -1.835 -1.999 -1.922 -2.263 -1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398 -1.754 -1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903 -2.244 -1.232 -1.339 -1.455 -1.398 -1.754 -1.339 -1.455 -1.398 -1.754 -1.603 -1.824 -1.980 -1.903 -2.244 -1.824 -1.980 -1.903 -2.244 -1.222 -1.328 -1.439 -1.382 -1.738 -1.328 -1.439 -1.382 -1.738 -1.593 -1.813 -1.964 -1.887 -2.228 -1.813 -1.964 -1.887 -2.228 -1.222 -1.328 -1.439 -1.382 -1.738 -1.328 -1.439 -1.382 -1.738 -1.593 -1.813 -1.964 -1.887 -2.228 -1.813 -1.964 -1.887 -2.228 -1.332 -1.454 -1.681 -1.626 -1.979 -1.454 -1.681 -1.626 -1.979 -1.703 -1.942 -2.209 -2.134 -2.469 -1.942 -2.209 -2.134 -2.469 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-96 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-62 lists the EP3SL110 row pins input timing parameters for single-ended I/O standards. Table 1-62. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.910 1.025 0.992 -0.741 -0.910 1.025 0.992 -0.741 -0.916 1.031 0.986 -0.735 -0.916 1.031 0.986 -0.735 -0.904 1.019 0.998 -0.747 -0.873 0.990 0.968 -0.716 -0.863 0.980 0.978 -0.726 -0.803 0.920 1.038 -0.786 -0.883 1.015 1.013 -0.746 -0.883 1.015 1.013 -0.746 -0.894 1.026 1.002 -0.735 -0.894 1.026 1.002 -0.735 -0.887 1.019 1.009 -0.742 -0.918 1.051 0.977 -0.709 -0.907 1.040 0.988 -0.720 -0.854 0.987 1.041 -0.773 -1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881 1.440 1.646 1.648 1.862 1.792 1.976 1.822 1.860 2.066 1.804 1.682 1.870 1.794 1.998 1.831 1.880 2.104 1.856 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS -1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371 -1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881 1.440 1.646 1.648 1.862 1.792 1.976 1.822 1.860 2.066 1.804 1.682 1.870 1.794 1.998 1.831 1.880 2.104 1.856 GCLK PLL GCLK -1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 1.437 1.649 1.649 1.861 1.795 1.973 1.825 1.857 2.069 1.801 1.681 1.871 1.799 1.993 1.836 1.875 2.109 1.851 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 1.437 1.649 1.649 1.861 1.795 1.973 1.825 1.857 2.069 1.801 1.681 1.871 1.799 1.993 1.836 1.875 2.109 1.851 GCLK PLL GCLK -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 -1.258 -1.455 -1.577 -1.622 -1.861 -1.473 -1.566 -1.620 -1.896 1.446 1.640 1.662 1.848 1.810 1.958 1.840 1.842 2.084 1.786 1.690 1.862 1.809 1.983 1.846 1.865 2.119 1.841 2.5 V GCLK PLL GCLK 1.8 V -1.240 -1.398 -1.457 -1.370 -1.304 -1.403 -1.471 -1.383 -1.356 -1.298 -1.402 -1.575 -1.530 -1.859 -1.402 -1.567 -1.526 -1.897 1.486 1.600 1.612 1.815 1.808 1.960 1.751 1.844 2.082 1.788 1.622 1.829 1.810 1.982 1.756 1.864 2.120 1.840 GCLK PLL GCLK 1.5 V -1.200 -1.365 -1.459 -1.372 -1.306 -1.370 -1.470 -1.382 -1.355 -1.274 -1.370 -1.507 -1.462 -1.791 -1.371 -1.502 -1.461 -1.832 1.462 1.624 1.580 1.847 1.740 2.028 1.683 1.912 2.014 1.856 1.591 1.860 1.745 2.047 1.691 1.929 2.055 1.905 GCLK PLL GCLK 1.2 V -1.224 -1.397 -1.527 -1.440 -1.374 -1.401 -1.535 -1.447 -1.420 -1.195 -1.269 -1.348 -1.303 -1.632 -1.275 -1.347 -1.306 -1.677 1.383 1.703 1.479 1.948 1.581 2.187 1.524 2.071 1.855 2.015 1.495 1.956 1.590 2.202 1.536 2.084 1.900 2.060 GCLK PLL -1.303 -1.498 -1.686 -1.599 -1.533 -1.497 -1.690 -1.602 -1.575 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-97 Table 1-62. EP3SL110 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK SSTL-2 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.847 0.963 1.055 -0.803 -0.847 0.963 1.055 -0.803 -0.777 0.894 1.064 -0.812 -0.777 0.894 1.064 -0.812 -0.763 0.880 1.078 -0.826 -0.777 0.894 1.064 -0.812 -0.777 0.894 1.064 -0.812 -0.763 0.880 1.078 -0.826 -0.763 0.880 1.078 -0.826 -0.828 0.961 1.067 -0.799 -0.828 0.961 1.067 -0.799 -0.819 0.952 1.076 -0.808 -0.819 0.952 1.076 -0.808 -0.807 0.940 1.088 -0.820 -0.819 0.952 1.076 -0.808 -0.819 0.952 1.076 -0.808 -0.807 0.940 1.088 -0.820 -0.807 0.940 1.088 -0.820 -1.172 -1.346 -1.357 -1.402 -1.641 -1.361 -1.349 -1.403 -1.679 1.360 1.726 1.553 1.957 1.590 2.178 1.620 2.062 1.864 2.006 1.578 1.974 1.592 2.200 1.629 2.082 1.902 2.058 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.326 -1.507 -1.677 -1.590 -1.524 -1.515 -1.688 -1.600 -1.573 -1.172 -1.346 -1.357 -1.402 -1.641 -1.361 -1.349 -1.403 -1.679 1.360 1.726 1.553 1.957 1.590 2.178 1.620 2.062 1.864 2.006 1.578 1.974 1.592 2.200 1.629 2.082 1.902 2.058 SSTL-2 CLASS II GCLK PLL GCLK -1.326 -1.507 -1.677 -1.590 -1.524 -1.515 -1.688 -1.600 -1.573 -1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672 1.345 1.741 1.452 1.975 1.576 2.192 1.519 2.077 1.849 2.019 1.463 1.988 1.583 2.209 1.529 2.092 1.891 2.067 SSTL-18 CLASS I GCLK PLL GCLK -1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586 -1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672 1.345 1.741 1.452 1.975 1.576 2.192 1.519 2.077 1.849 2.019 1.463 1.988 1.583 2.209 1.529 2.092 1.891 2.067 SSTL-18 CLASS II GCLK PLL GCLK -1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586 -1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655 1.333 1.756 1.442 1.985 1.558 2.210 1.501 2.095 1.831 2.037 1.452 1.999 1.566 2.226 1.512 2.109 1.874 2.084 SSTL-15 CLASS I GCLK PLL GCLK -1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603 -1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672 1.345 1.741 1.452 1.975 1.576 2.192 1.519 2.077 1.849 2.019 1.463 1.988 1.583 2.209 1.529 2.092 1.891 2.067 1.8-V HSTL CLASS I GCLK PLL GCLK -1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586 -1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672 1.345 1.741 1.452 1.975 1.576 2.192 1.519 2.077 1.849 2.019 1.463 1.988 1.583 2.209 1.529 2.092 1.891 2.067 1.8-V HSTL CLASS II GCLK PLL GCLK -1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586 -1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655 1.333 1.756 1.442 1.985 1.558 2.210 1.501 2.095 1.831 2.037 1.452 1.999 1.566 2.226 1.512 2.109 1.874 2.084 1.5-V HSTL CLASS I GCLK PLL GCLK -1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603 -1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655 1.333 1.756 1.442 1.985 1.558 2.210 1.501 2.095 1.831 2.037 1.452 1.999 1.566 2.226 1.512 2.109 1.874 2.084 1.5-V HSTL CLASS II GCLK PLL -1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-98 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-62. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 1.2-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.754 0.871 1.087 -0.835 -0.754 0.871 1.087 -0.835 -0.916 1.031 0.986 -0.735 -0.916 1.031 0.986 -0.735 -0.795 0.928 1.100 -0.832 -0.795 0.928 1.100 -0.832 -0.894 1.026 1.002 -0.735 -0.894 1.026 1.002 -0.735 -1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639 1.324 1.765 1.432 1.995 1.542 2.226 1.485 2.111 1.815 2.053 1.443 2.008 1.550 2.242 1.496 2.125 1.858 2.100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619 -1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639 1.324 1.765 1.432 1.995 1.542 2.226 1.485 2.111 1.815 2.053 1.443 2.008 1.550 2.242 1.496 2.125 1.858 2.100 1.2-V HSTL CLASS II GCLK PLL GCLK -1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 1.437 1.649 1.649 1.861 1.795 1.973 1.825 1.857 2.069 1.801 1.681 1.871 1.799 1.993 1.836 1.875 2.109 1.851 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 -1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886 1.437 1.649 1.649 1.861 1.795 1.973 1.825 1.857 2.069 1.801 1.681 1.871 1.799 1.993 1.836 1.875 2.109 1.851 GCLK PLL -1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366 Table 1-63 lists the EP3SL110 column pins output timing parameters for single-ended I/O standards. Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco 3.439 3.829 3.372 3.762 3.286 3.676 3.279 3.669 3.439 3.829 3.372 3.762 3.286 3.676 3.279 3.669 4.768 5.344 4.659 5.235 4.556 5.131 4.539 5.114 5.145 5.638 5.507 5.801 5.145 5.638 5.507 5.801 5.778 6.326 6.168 6.550 5.778 6.326 6.168 6.550 5.034 5.525 5.394 5.688 5.034 5.525 5.394 5.688 5.667 6.213 6.055 6.437 5.667 6.213 6.055 6.437 4.936 5.433 5.302 5.596 4.936 5.433 5.302 5.596 5.568 6.121 5.963 6.345 5.568 6.121 5.963 6.345 4.908 5.392 5.261 5.555 4.908 5.392 5.261 5.555 5.540 6.080 5.922 6.304 5.540 6.080 5.922 6.304 ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-99 Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.445 3.835 3.290 3.680 3.297 3.687 3.281 3.671 3.403 3.793 3.292 3.682 3.256 3.646 3.238 3.628 3.317 3.707 3.238 3.628 3.233 3.623 3.224 3.614 3.445 3.835 3.290 3.680 3.297 3.687 3.281 3.671 3.403 3.793 3.292 3.682 3.256 3.646 3.238 3.628 3.317 3.707 3.238 3.628 3.233 3.623 3.224 3.614 4.773 5.348 4.566 5.141 4.560 5.135 4.537 5.113 4.735 5.311 4.605 5.181 4.542 5.118 4.513 5.089 4.639 5.215 4.516 5.091 4.508 5.084 4.494 5.070 5.150 5.645 5.514 5.808 5.150 5.645 5.514 5.808 5.783 6.333 6.175 6.557 5.783 6.333 6.175 6.557 4.953 5.444 5.313 5.607 4.953 5.444 5.313 5.607 5.585 6.132 5.974 6.356 5.585 6.132 5.974 6.356 4.932 5.418 5.287 5.581 4.932 5.418 5.287 5.581 5.564 6.106 5.948 6.330 5.564 6.106 5.948 6.330 4.906 5.389 5.258 5.552 4.906 5.389 5.258 5.552 5.539 6.077 5.919 6.301 5.539 6.077 5.919 6.301 5.114 5.605 5.474 5.768 5.114 5.605 5.474 5.768 5.746 6.293 6.135 6.517 5.746 6.293 6.135 6.517 4.980 5.467 5.337 5.629 4.980 5.467 5.337 5.629 5.612 6.156 5.999 6.379 5.612 6.156 5.999 6.379 4.911 5.393 5.263 5.556 4.911 5.393 5.263 5.556 5.543 6.082 5.925 6.305 5.543 6.082 5.925 6.305 4.883 5.365 5.234 5.528 4.883 5.365 5.234 5.528 5.515 6.053 5.895 6.277 5.515 6.053 5.895 6.277 5.013 5.502 5.372 5.664 5.013 5.502 5.372 5.664 5.646 6.191 6.034 6.414 5.646 6.191 6.034 6.414 4.884 5.367 5.237 5.529 4.884 5.367 5.237 5.529 5.517 6.056 5.899 6.279 5.517 6.056 5.899 6.279 4.877 5.359 5.228 5.522 4.877 5.359 5.228 5.522 5.510 6.047 5.889 6.271 5.510 6.047 5.889 6.271 4.862 5.344 5.213 5.507 4.862 5.344 5.213 5.507 5.495 6.032 5.874 6.256 5.495 6.032 5.874 6.256 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA 4mA 8mA 3.0-V LVCMOS 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-100 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.439 3.829 3.339 3.729 3.295 3.685 3.257 3.647 3.630 4.020 3.449 3.839 3.367 3.757 3.347 3.737 3.284 3.674 3.266 3.656 3.439 3.829 3.339 3.729 3.295 3.685 3.257 3.647 3.630 4.020 3.449 3.839 3.367 3.757 3.347 3.737 3.284 3.674 3.266 3.656 4.846 5.422 4.727 5.303 4.640 5.216 4.601 5.177 5.168 5.743 4.889 5.464 4.782 5.357 4.723 5.299 4.662 5.238 4.642 5.217 5.240 5.749 5.619 5.912 5.240 5.749 5.619 5.912 5.873 6.438 6.281 6.661 5.873 6.438 6.281 6.661 5.114 5.617 5.487 5.779 5.114 5.617 5.487 5.779 5.747 6.306 6.149 6.529 5.747 6.306 6.149 6.529 5.024 5.522 5.391 5.685 5.024 5.522 5.391 5.685 5.656 6.210 6.052 6.434 5.656 6.210 6.052 6.434 4.981 5.479 5.348 5.642 4.981 5.479 5.348 5.642 5.614 6.167 6.009 6.391 5.614 6.167 6.009 6.391 5.600 6.154 6.023 6.317 5.600 6.154 6.023 6.317 6.233 6.842 6.684 7.066 6.233 6.842 6.684 7.066 5.291 5.806 5.676 5.968 5.291 5.806 5.676 5.968 5.924 6.495 6.338 6.718 5.924 6.495 6.338 6.718 5.176 5.696 5.565 5.859 5.176 5.696 5.565 5.859 5.809 6.384 6.226 6.608 5.809 6.384 6.226 6.608 5.123 5.630 5.499 5.793 5.123 5.630 5.499 5.793 5.755 6.318 6.160 6.542 5.755 6.318 6.160 6.542 5.048 5.549 5.418 5.712 5.048 5.549 5.418 5.712 5.680 6.237 6.079 6.461 5.680 6.237 6.079 6.461 5.026 5.526 5.395 5.689 5.026 5.526 5.395 5.689 5.659 6.214 6.056 6.438 5.659 6.214 6.056 6.438 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 2.5 V 12mA 16mA 2mA 4mA 6mA 1.8 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-101 Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.576 3.966 3.364 3.754 3.339 3.729 3.328 3.718 3.273 3.663 3.268 3.658 3.492 3.882 3.369 3.759 3.331 3.721 3.284 3.674 3.284 3.674 3.281 3.671 3.279 3.669 3.576 3.966 3.364 3.754 3.339 3.729 3.328 3.718 3.273 3.663 3.268 3.658 3.492 3.882 3.369 3.759 3.331 3.721 3.284 3.674 3.284 3.674 3.281 3.671 3.279 3.669 5.096 5.672 4.777 5.353 4.710 5.286 4.693 5.269 4.655 5.231 4.639 5.214 5.022 5.598 4.797 5.372 4.704 5.280 4.676 5.252 4.633 5.209 4.630 5.206 4.630 5.206 5.533 6.092 5.961 6.255 5.533 6.092 5.961 6.255 6.165 6.780 6.622 7.004 6.165 6.780 6.622 7.004 5.176 5.700 5.569 5.863 5.176 5.700 5.569 5.863 5.809 6.388 6.230 6.612 5.809 6.388 6.230 6.612 5.116 5.633 5.502 5.796 5.116 5.633 5.502 5.796 5.749 6.321 6.163 6.545 5.749 6.321 6.163 6.545 5.091 5.613 5.482 5.776 5.091 5.613 5.482 5.776 5.724 6.301 6.143 6.525 5.724 6.301 6.143 6.525 5.041 5.543 5.412 5.706 5.041 5.543 5.412 5.706 5.673 6.231 6.073 6.455 5.673 6.231 6.073 6.455 5.029 5.532 5.401 5.695 5.029 5.532 5.401 5.695 5.662 6.220 6.062 6.444 5.662 6.220 6.062 6.444 5.468 6.036 5.905 6.199 5.468 6.036 5.905 6.199 6.101 6.724 6.566 6.948 6.101 6.724 6.566 6.948 5.207 5.750 5.619 5.913 5.207 5.750 5.619 5.913 5.839 6.438 6.280 6.662 5.839 6.438 6.280 6.662 5.117 5.637 5.506 5.800 5.117 5.637 5.506 5.800 5.750 6.325 6.167 6.549 5.750 6.325 6.167 6.549 5.068 5.581 5.450 5.744 5.068 5.581 5.450 5.744 5.701 6.269 6.111 6.493 5.701 6.269 6.111 6.493 5.016 5.512 5.381 5.675 5.016 5.512 5.381 5.675 5.648 6.200 6.042 6.424 5.648 6.200 6.042 6.424 5.012 5.508 5.377 5.671 5.012 5.508 5.377 5.671 5.645 6.196 6.038 6.420 5.645 6.196 6.038 6.420 5.013 5.509 5.378 5.672 5.013 5.509 5.378 5.672 5.646 6.197 6.039 6.421 5.646 6.197 6.039 6.421 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.5 V 8mA 10mA 12mA 2mA 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-102 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock SSTL-2 CLASS II GCLK 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.270 3.660 3.291 3.681 3.287 3.677 3.276 3.666 3.265 3.655 3.265 3.655 3.271 3.661 3.274 3.664 3.295 3.685 3.281 3.671 3.270 3.660 3.269 3.659 3.266 3.656 3.270 3.660 3.291 3.681 3.287 3.677 3.276 3.666 3.265 3.655 3.265 3.655 3.271 3.661 3.274 3.664 3.295 3.685 3.281 3.671 3.270 3.660 3.269 3.659 3.266 3.656 4.616 5.191 4.645 5.221 4.643 5.219 4.633 5.209 4.621 5.196 4.620 5.196 4.619 5.195 4.627 5.203 4.655 5.230 4.644 5.220 4.631 5.206 4.634 5.209 4.628 5.204 4.998 5.494 5.363 5.657 4.998 5.494 5.363 5.657 5.630 6.182 6.024 6.406 5.630 6.182 6.024 6.406 5.030 5.528 5.397 5.691 5.030 5.528 5.397 5.691 5.662 6.216 6.058 6.440 5.662 6.216 6.058 6.440 5.028 5.526 5.395 5.689 5.028 5.526 5.395 5.689 5.660 6.214 6.056 6.438 5.660 6.214 6.056 6.438 5.018 5.517 5.386 5.680 5.018 5.517 5.386 5.680 5.651 6.205 6.047 6.429 5.651 6.205 6.047 6.429 5.005 5.504 5.373 5.667 5.005 5.504 5.373 5.667 5.638 6.192 6.034 6.416 5.638 6.192 6.034 6.416 5.005 5.504 5.373 5.667 5.005 5.504 5.373 5.667 5.638 6.192 6.034 6.416 5.638 6.192 6.034 6.416 5.002 5.499 5.368 5.662 5.002 5.499 5.368 5.662 5.635 6.187 6.029 6.411 5.635 6.187 6.029 6.411 5.012 5.511 5.380 5.674 5.012 5.511 5.380 5.674 5.644 6.199 6.041 6.423 5.644 6.199 6.041 6.423 5.041 5.541 5.410 5.704 5.041 5.541 5.410 5.704 5.674 6.229 6.071 6.453 5.674 6.229 6.071 6.453 5.031 5.532 5.401 5.695 5.031 5.532 5.401 5.695 5.664 6.220 6.062 6.444 5.664 6.220 6.062 6.444 5.017 5.518 5.387 5.681 5.017 5.518 5.387 5.681 5.650 6.206 6.048 6.430 5.650 6.206 6.048 6.430 5.021 5.522 5.391 5.685 5.021 5.522 5.391 5.685 5.653 6.210 6.052 6.434 5.653 6.210 6.052 6.434 5.015 5.516 5.385 5.679 5.015 5.516 5.385 5.679 5.648 6.204 6.046 6.428 5.648 6.204 6.046 6.428 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA 8mA SSTL-18 CLASS II 16mA 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-103 Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA SSTL-15 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.268 3.658 3.271 3.661 3.278 3.668 3.271 3.661 3.263 3.653 3.266 3.656 3.263 3.653 3.271 3.661 3.283 3.673 3.279 3.669 3.275 3.665 3.268 3.658 3.269 3.659 3.268 3.658 3.271 3.661 3.278 3.668 3.271 3.661 3.263 3.653 3.266 3.656 3.263 3.653 3.271 3.661 3.283 3.673 3.279 3.669 3.275 3.665 3.268 3.658 3.269 3.659 4.617 5.193 4.624 5.200 4.619 5.195 4.617 5.193 4.610 5.185 4.613 5.188 4.615 5.191 4.614 5.190 4.628 5.203 4.629 5.204 4.624 5.200 4.617 5.193 4.624 5.200 5.001 5.499 5.368 5.662 5.001 5.499 5.368 5.662 5.634 6.187 6.029 6.411 5.634 6.187 6.029 6.411 5.010 5.510 5.379 5.673 5.010 5.510 5.379 5.673 5.643 6.198 6.040 6.422 5.643 6.198 6.040 6.422 5.001 5.497 5.366 5.660 5.001 5.497 5.366 5.660 5.634 6.185 6.027 6.409 5.634 6.185 6.027 6.409 5.000 5.496 5.365 5.659 5.000 5.496 5.365 5.659 5.632 6.184 6.026 6.408 5.632 6.184 6.026 6.408 4.992 5.489 5.358 5.652 4.992 5.489 5.358 5.652 5.625 6.177 6.019 6.401 5.625 6.177 6.019 6.401 4.996 5.493 5.362 5.656 4.996 5.493 5.362 5.656 5.628 6.181 6.023 6.405 5.628 6.181 6.023 6.405 4.999 5.497 5.366 5.660 4.999 5.497 5.366 5.660 5.632 6.185 6.027 6.409 5.632 6.185 6.027 6.409 4.997 5.493 5.362 5.656 4.997 5.493 5.362 5.656 5.629 6.181 6.023 6.405 5.629 6.181 6.023 6.405 5.011 5.508 5.377 5.671 5.011 5.508 5.377 5.671 5.644 6.196 6.038 6.420 5.644 6.196 6.038 6.420 5.013 5.511 5.380 5.674 5.013 5.511 5.380 5.674 5.645 6.199 6.041 6.423 5.645 6.199 6.041 6.423 5.008 5.506 5.375 5.669 5.008 5.506 5.375 5.669 5.641 6.194 6.036 6.418 5.641 6.194 6.036 6.418 5.001 5.499 5.368 5.662 5.001 5.499 5.368 5.662 5.634 6.187 6.029 6.411 5.634 6.187 6.029 6.411 5.009 5.509 5.378 5.672 5.009 5.509 5.378 5.672 5.642 6.197 6.039 6.421 5.642 6.197 6.039 6.421 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-104 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-63. EP3SL110 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard 1.5-V HSTL CLASS II Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.267 3.657 3.286 3.676 3.278 3.668 3.279 3.669 3.268 3.658 3.268 3.658 3.289 3.679 3.392 3.782 3.392 3.782 3.267 3.657 3.286 3.676 3.278 3.668 3.279 3.669 3.268 3.658 3.268 3.658 3.289 3.679 3.392 3.782 3.392 3.782 4.605 5.181 4.642 5.217 4.633 5.208 4.640 5.216 4.627 5.203 4.627 5.203 4.643 5.219 4.688 5.264 4.688 5.264 4.987 5.483 5.352 5.646 4.987 5.483 5.352 5.646 5.620 6.171 6.013 6.395 5.620 6.171 6.013 6.395 5.028 5.529 5.398 5.692 5.028 5.529 5.398 5.692 5.661 6.217 6.059 6.441 5.661 6.217 6.059 6.441 5.019 5.520 5.389 5.683 5.019 5.520 5.389 5.683 5.652 6.208 6.050 6.432 5.652 6.208 6.050 6.432 5.028 5.529 5.398 5.692 5.028 5.529 5.398 5.692 5.660 6.217 6.059 6.441 5.660 6.217 6.059 6.441 5.014 5.515 5.384 5.678 5.014 5.515 5.384 5.678 5.647 6.203 6.045 6.427 5.647 6.203 6.045 6.427 5.014 5.516 5.385 5.679 5.014 5.516 5.385 5.679 5.647 6.204 6.046 6.428 5.647 6.204 6.046 6.428 5.029 5.529 5.398 5.692 5.029 5.529 5.398 5.692 5.662 6.217 6.059 6.441 5.662 6.217 6.059 6.441 5.063 5.554 5.423 5.717 5.063 5.554 5.423 5.717 5.696 6.242 6.084 6.466 5.696 6.242 6.084 6.466 5.063 5.554 5.423 5.717 5.063 5.554 5.423 5.717 5.696 6.242 6.084 6.466 5.696 6.242 6.084 6.466 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-105 Table 1-64 lists the EP3SL110 row pins output timing parameters for single-ended I/O standards. Table 1-64. EP3SL110 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.182 1.457 3.116 1.364 3.037 1.265 3.184 1.467 3.041 1.269 3.143 1.411 3.042 1.286 3.005 1.247 3.064 1.325 2.992 1.225 3.169 1.437 3.084 1.327 3.027 1.281 3.481 1.650 3.376 1.545 3.270 1.439 3.485 1.654 3.276 1.445 3.427 1.596 3.300 1.469 3.249 1.418 3.346 1.515 3.227 1.396 3.463 1.632 3.365 1.534 3.288 1.457 4.833 5.216 5.678 5.579 5.814 5.256 5.802 5.703 5.896 2.051 2.136 2.329 2.349 2.337 2.239 2.435 2.454 2.331 4.703 5.078 5.533 5.434 5.669 5.143 5.653 5.554 5.747 1.921 1.998 2.184 2.204 2.192 2.098 2.286 2.305 2.182 4.584 4.955 5.405 5.306 5.541 5.044 5.521 5.422 5.615 1.802 1.875 2.056 2.076 2.064 1.971 2.154 2.173 2.050 4.841 5.221 5.682 5.583 5.818 5.264 5.806 5.707 5.900 2.059 2.141 2.333 2.353 2.341 2.245 2.439 2.458 2.335 4.590 4.961 5.411 5.312 5.548 5.056 5.528 5.429 5.622 1.808 1.881 2.062 2.082 2.070 1.977 2.161 2.180 2.057 4.785 5.169 5.634 5.535 5.770 5.224 5.760 5.661 5.854 2.003 2.089 2.285 2.305 2.293 2.196 2.393 2.412 2.289 4.632 5.010 5.470 5.371 5.606 5.082 5.596 5.496 5.689 1.850 1.930 2.121 2.141 2.129 2.034 2.229 2.247 2.124 4.550 4.927 5.382 5.283 5.518 5.014 5.503 5.403 5.596 1.768 1.847 2.033 2.053 2.041 1.948 2.136 2.154 2.031 4.679 5.062 5.524 5.425 5.660 5.115 5.649 5.549 5.742 1.897 1.982 2.175 2.195 2.183 2.088 2.282 2.300 2.177 4.515 4.888 5.343 5.244 5.479 4.984 5.463 5.363 5.556 1.733 1.808 1.994 2.014 2.002 1.908 2.096 2.114 1.991 4.917 5.323 5.806 5.707 5.942 5.356 5.939 5.839 6.032 2.135 2.243 2.457 2.477 2.465 2.356 2.572 2.590 2.467 4.762 5.160 5.636 5.537 5.772 5.219 5.765 5.665 5.858 1.980 2.080 2.287 2.307 2.295 2.189 2.398 2.416 2.293 4.651 5.041 5.510 5.411 5.646 5.130 5.635 5.535 5.728 1.869 1.961 2.161 2.181 2.169 2.066 2.268 2.286 2.163 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVTTL 3.3-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 4mA 3.0-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-106 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-64. EP3SL110 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.438 1.670 3.213 1.445 3.148 1.380 3.088 1.320 3.349 1.581 3.107 1.339 3.080 1.312 3.071 1.303 3.292 1.524 3.112 1.344 3.031 1.266 3.026 1.254 3.017 1.238 3.706 1.879 3.504 1.677 3.402 1.575 3.328 1.501 3.624 1.797 3.366 1.539 3.319 1.492 3.310 1.483 3.549 1.722 3.360 1.533 3.274 1.443 3.262 1.431 3.244 1.413 5.298 5.747 6.303 6.177 6.439 5.888 6.445 6.318 6.538 2.521 2.672 2.932 2.952 2.937 2.793 3.056 3.075 2.949 4.971 5.378 5.898 5.772 6.034 5.523 6.039 5.911 6.131 2.194 2.303 2.527 2.547 2.532 2.428 2.650 2.668 2.542 4.818 5.228 5.739 5.613 5.875 5.355 5.866 5.739 5.959 2.041 2.153 2.368 2.388 2.373 2.260 2.477 2.496 2.370 4.741 5.134 5.642 5.516 5.778 5.260 5.772 5.645 5.865 1.964 2.059 2.271 2.291 2.276 2.165 2.383 2.402 2.276 5.208 5.660 6.231 6.105 6.367 5.795 6.369 6.242 6.462 2.431 2.585 2.860 2.880 2.865 2.700 2.980 2.999 2.873 4.803 5.223 5.740 5.614 5.876 5.349 5.865 5.738 5.958 2.026 2.148 2.369 2.389 2.374 2.254 2.476 2.495 2.369 4.730 5.127 5.634 5.508 5.770 5.251 5.760 5.633 5.853 1.953 2.052 2.263 2.283 2.268 2.156 2.371 2.390 2.264 4.708 5.109 5.615 5.489 5.751 5.233 5.738 5.611 5.831 1.931 2.034 2.244 2.264 2.249 2.138 2.349 2.368 2.242 5.118 5.574 6.156 6.030 6.292 5.707 6.285 6.158 6.378 2.341 2.499 2.785 2.805 2.790 2.612 2.896 2.915 2.789 4.825 5.251 5.781 5.655 5.917 5.374 5.907 5.780 6.000 2.048 2.176 2.410 2.430 2.415 2.279 2.518 2.537 2.411 4.629 5.013 5.478 5.379 5.616 5.117 5.597 5.498 5.692 1.847 1.933 2.129 2.149 2.137 2.033 2.230 2.249 2.126 4.621 5.005 5.476 5.371 5.614 5.116 5.596 5.491 5.691 1.839 1.925 2.121 2.141 2.129 2.025 2.223 2.242 2.119 4.596 4.980 5.459 5.344 5.597 5.099 5.578 5.464 5.673 1.814 1.900 2.094 2.114 2.102 1.999 2.196 2.215 2.092 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V 1.5 V 1.2 V SSTL-2 CLASS I 12mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-107 Table 1-64. EP3SL110 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.049 1.281 3.034 1.266 3.023 1.255 2.999 1.231 2.999 1.231 3.009 1.241 3.004 1.235 3.045 1.277 3.022 1.254 3.005 1.237 3.284 1.457 3.270 1.443 3.258 1.431 3.235 1.408 3.234 1.407 3.243 1.416 3.238 1.411 3.280 1.453 3.258 1.431 3.241 1.414 4.636 5.022 5.516 5.390 5.652 5.141 5.635 5.508 5.728 1.859 1.947 2.145 2.165 2.150 2.046 2.246 2.265 2.139 4.633 5.020 5.514 5.388 5.650 5.139 5.633 5.506 5.726 1.856 1.945 2.143 2.163 2.148 2.044 2.244 2.263 2.137 4.616 5.003 5.497 5.371 5.633 5.122 5.617 5.490 5.710 1.839 1.928 2.126 2.146 2.131 2.027 2.228 2.247 2.121 4.600 4.987 5.482 5.356 5.618 5.107 5.602 5.475 5.695 1.823 1.912 2.111 2.131 2.116 2.012 2.213 2.232 2.106 4.599 4.986 5.481 5.355 5.617 5.106 5.601 5.474 5.694 1.822 1.911 2.110 2.130 2.116 2.011 2.212 2.231 2.106 4.597 4.982 5.475 5.349 5.611 5.101 5.594 5.467 5.687 1.820 1.907 2.104 2.124 2.111 2.006 2.205 2.224 2.100 4.596 4.983 5.477 5.351 5.613 5.103 5.598 5.471 5.691 1.819 1.908 2.106 2.126 2.121 2.008 2.209 2.228 2.111 4.647 5.036 5.533 5.407 5.669 5.154 5.651 5.524 5.744 1.870 1.961 2.162 2.182 2.167 2.059 2.262 2.281 2.155 4.629 5.019 5.516 5.390 5.652 5.138 5.635 5.508 5.728 1.852 1.944 2.145 2.165 2.150 2.043 2.246 2.265 2.139 4.612 5.001 5.498 5.372 5.634 5.120 5.618 5.491 5.711 1.835 1.926 2.127 2.147 2.132 2.025 2.229 2.248 2.122 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-18 CLASS II 16mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-108 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-64. EP3SL110 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.024 1.256 3.012 1.244 2.999 1.231 3.001 1.233 2.994 1.226 3.001 1.232 3.031 1.263 3.019 1.251 3.015 1.247 3.030 1.262 3.018 1.250 3.014 1.246 3.137 1.351 3.137 1.351 3.256 1.429 3.244 1.417 3.232 1.405 3.234 1.407 3.229 1.402 3.234 1.406 3.263 1.436 3.253 1.426 3.248 1.421 3.262 1.435 3.250 1.423 3.248 1.421 3.357 1.526 3.357 1.526 4.603 4.987 5.478 5.352 5.614 5.105 5.597 5.470 5.690 1.826 1.912 2.107 2.127 2.112 2.010 2.208 2.227 2.101 4.594 4.979 5.470 5.344 5.606 5.097 5.590 5.463 5.683 1.817 1.904 2.099 2.119 2.108 2.002 2.201 2.220 2.097 4.585 4.970 5.462 5.336 5.598 5.089 5.582 5.455 5.675 1.808 1.895 2.091 2.111 2.101 1.994 2.193 2.212 2.090 4.588 4.973 5.465 5.339 5.601 5.092 5.585 5.458 5.678 1.811 1.898 2.094 2.114 2.105 1.997 2.196 2.215 2.093 4.586 4.972 5.465 5.339 5.601 5.092 5.586 5.459 5.679 1.809 1.897 2.094 2.114 2.108 1.997 2.197 2.216 2.098 4.581 4.964 5.457 5.330 5.595 5.083 5.575 5.448 5.670 1.804 1.889 2.085 2.105 2.104 1.988 2.186 2.205 2.092 4.614 5.000 5.493 5.367 5.629 5.117 5.611 5.484 5.704 1.837 1.925 2.122 2.142 2.127 2.022 2.222 2.241 2.115 4.610 4.996 5.489 5.363 5.625 5.114 5.608 5.481 5.701 1.833 1.921 2.118 2.138 2.123 2.019 2.219 2.238 2.112 4.604 4.990 5.483 5.357 5.619 5.108 5.602 5.475 5.695 1.827 1.915 2.112 2.132 2.117 2.013 2.213 2.232 2.106 4.625 5.014 5.511 5.385 5.647 5.131 5.628 5.501 5.721 1.848 1.939 2.140 2.160 2.145 2.036 2.239 2.258 2.132 4.614 5.002 5.499 5.373 5.635 5.120 5.617 5.490 5.710 1.837 1.927 2.128 2.148 2.133 2.025 2.228 2.247 2.121 4.618 5.007 5.505 5.379 5.641 5.126 5.624 5.497 5.717 1.841 1.932 2.134 2.154 2.139 2.031 2.235 2.254 2.128 4.654 5.031 5.518 5.390 5.656 5.165 5.639 5.511 5.734 1.872 1.951 2.138 2.158 2.146 2.051 2.242 2.261 2.138 4.654 5.031 5.518 5.390 5.656 5.165 5.639 5.511 5.734 1.872 1.951 2.138 2.158 2.146 2.051 2.242 2.261 2.138 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-109 Table 1-65 through Table 1-70 list the maximum I/O timing parameters for EP3SL110 devices for differential I/O standards. Table 1-65 lists the EP3SL110 column pins input timing parameters for differential I/O standards. Table 1-65. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -0.978 1.104 0.967 -0.707 -0.978 1.104 0.967 -0.707 -0.978 1.104 0.967 -0.707 -0.794 0.913 1.151 -0.898 -0.794 0.913 1.151 -0.898 -0.802 0.921 1.143 -0.890 -0.802 0.921 1.143 -0.890 -0.814 0.933 1.131 -0.878 -1.006 1.152 1.001 -0.719 -1.006 1.152 1.001 -0.719 -1.006 1.152 1.001 -0.719 -0.829 0.967 1.178 -0.904 -0.829 0.967 1.178 -0.904 -0.841 0.979 1.166 -0.892 -0.841 0.979 1.166 -0.892 -0.852 0.990 1.155 -0.881 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786 1.416 1.808 1.546 2.031 1.677 2.245 1.610 2.139 1.964 2.048 1.554 2.049 1.684 2.266 1.621 2.155 2.007 2.095 DIFFERENTIAL 1.2-V HSTL CLASS I -1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609 -1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786 1.416 1.808 1.546 2.031 1.677 2.245 1.610 2.139 1.964 2.048 1.554 2.049 1.684 2.266 1.621 2.155 2.007 2.095 DIFFERENTIAL 1.2-V HSTL CLASS II -1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V HSTL CLASS I -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V HSTL CLASS II -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V HSTL CLASS I -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-110 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-65. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.814 0.933 1.131 -0.878 -0.802 0.921 1.143 -0.890 -0.802 0.921 1.143 -0.890 -0.814 0.933 1.131 -0.878 -0.814 0.933 1.131 -0.878 -0.821 0.940 1.124 -0.871 -0.821 0.940 1.124 -0.871 -0.852 0.990 1.155 -0.881 -0.841 0.979 1.166 -0.892 -0.841 0.979 1.166 -0.892 -0.852 0.990 1.155 -0.881 -0.852 0.990 1.155 -0.881 -0.858 0.996 1.149 -0.875 -0.858 0.996 1.149 -0.875 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V SSTL CLASS I -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V SSTL CLASS II -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V SSTL CLASS I -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V SSTL CLASS II -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 1.449 1.777 1.576 2.004 1.715 2.210 1.648 2.102 2.003 2.014 1.583 2.023 1.717 2.238 1.653 2.124 2.041 2.066 DIFFERENTIAL 2.5-V SSTL CLASS I -1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 -1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 1.449 1.777 1.576 2.004 1.715 2.210 1.648 2.102 2.003 2.014 1.583 2.023 1.717 2.238 1.653 2.124 2.041 2.066 DIFFERENTIAL 2.5-V SSTL CLASS II -1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 Table 1-66 lists the EP3SL110 parameters for differential I/O standards. Table 1-66. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK LVDS GCLK PLL tsu th tsu th -0.919 1.043 0.959 -0.698 -0.950 1.092 0.987 -0.708 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 -1.066 1.358 2.597 -2.032 -1.023 1.303 2.470 -1.933 -1.442 1.711 2.387 -1.853 ns ns ns ns -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-111 Table 1-66. EP3SL110 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK MINI-LVDS GCLK PLL GCLK RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.919 1.043 0.959 -0.698 -0.919 1.043 0.959 -0.698 -0.724 0.841 1.154 -0.900 -0.724 0.841 1.154 -0.900 -0.733 0.850 1.145 -0.891 -0.733 0.850 1.145 -0.891 -0.747 0.864 1.131 -0.877 -0.747 0.864 1.131 -0.877 -0.733 0.850 1.145 -0.891 -0.950 1.092 0.987 -0.708 -0.950 1.092 0.987 -0.708 -0.765 0.898 1.172 -0.902 -0.765 0.898 1.172 -0.902 -0.777 0.910 1.160 -0.890 -0.777 0.910 1.160 -0.890 -0.789 0.922 1.148 -0.878 -0.789 0.922 1.148 -0.878 -0.777 0.910 1.160 -0.890 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 -1.066 1.358 2.597 -2.032 -1.066 1.358 2.597 -2.032 -1.303 1.543 2.360 -1.847 -1.303 1.543 2.360 -1.847 -1.319 1.559 2.344 -1.831 -1.319 1.559 2.344 -1.831 -1.336 1.576 2.327 -1.814 -1.336 1.576 2.327 -1.814 -1.319 1.559 2.344 -1.831 -1.023 1.303 2.470 -1.933 -1.023 1.303 2.470 -1.933 -1.255 1.483 2.238 -1.753 -1.255 1.483 2.238 -1.753 -1.271 1.499 2.222 -1.737 -1.271 1.499 2.222 -1.737 -1.288 1.516 2.205 -1.720 -1.288 1.516 2.205 -1.720 -1.271 1.499 2.222 -1.737 -1.442 1.711 2.387 -1.853 -1.442 1.711 2.387 -1.853 -1.626 1.846 2.203 -1.718 -1.626 1.846 2.203 -1.718 -1.642 1.862 2.187 -1.702 -1.642 1.862 2.187 -1.702 -1.659 1.879 2.170 -1.685 -1.659 1.879 2.170 -1.685 -1.642 1.862 2.187 -1.702 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -1.113 -1.210 -1.304 -1.254 -1.583 -1.211 1.302 1.862 1.420 2.100 1.535 2.338 1.474 2.219 1.802 2.155 1.429 2.117 DIFFERENTIAL 1.2-V HSTL CLASS I -1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.113 -1.210 -1.304 -1.254 -1.583 -1.211 1.302 1.862 1.420 2.100 1.535 2.338 1.474 2.219 1.802 2.155 1.429 2.117 DIFFERENTIAL 1.2-V HSTL CLASS II -1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 DIFFERENTIAL 1.5-V HSTL CLASS I -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 DIFFERENTIAL 1.5-V HSTL CLASS II -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 DIFFERENTIAL 1.8-V HSTL CLASS I -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 GCLK DIFFERENTIAL 1.8-V HSTL CLASS II GCLK PLL GCLK GCLK PLL -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 DIFFERENTIAL 1.5-V SSTL CLASS I tsu th -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-112 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-66. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.5-V SSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.733 0.850 1.145 -0.891 -0.747 0.864 1.131 -0.877 -0.747 0.864 1.131 -0.877 -0.756 0.873 1.122 -0.868 -0.756 0.873 1.122 -0.868 -0.777 0.910 1.160 -0.890 -0.789 0.922 1.148 -0.878 -0.789 0.922 1.148 -0.878 -0.798 0.931 1.139 -0.869 -0.798 0.931 1.139 -0.869 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 -1.319 1.559 2.344 -1.831 -1.336 1.576 2.327 -1.814 -1.336 1.576 2.327 -1.814 -1.337 1.582 2.321 -1.805 -1.337 1.582 2.321 -1.805 -1.271 1.499 2.222 -1.737 -1.288 1.516 2.205 -1.720 -1.288 1.516 2.205 -1.720 -1.291 1.521 2.197 -1.711 -1.291 1.521 2.197 -1.711 -1.642 1.862 2.187 -1.702 -1.659 1.879 2.170 -1.685 -1.659 1.879 2.170 -1.685 -1.661 1.886 2.163 -1.674 -1.661 1.886 2.163 -1.674 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 DIFFERENTIAL 1.8-V SSTL CLASS I -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 DIFFERENTIAL 1.8-V SSTL CLASS II -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.145 -1.241 -1.345 -1.296 -1.623 -1.238 1.336 1.825 1.454 2.064 1.579 2.293 1.518 2.173 1.847 2.110 1.459 2.086 DIFFERENTIAL 2.5-V SSTL CLASS I -1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.145 -1.241 -1.345 -1.296 -1.623 -1.238 1.336 1.825 1.454 2.064 1.579 2.293 1.518 2.173 1.847 2.110 1.459 2.086 DIFFERENTIAL 2.5-V SSTL CLASS II -1.422 -1.611 -1.789 -1.698 -1.625 -1.623 Table 1-67 lists the EP3SL110 column pins output timing parameters for differential I/O standards. Table 1-67. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 4) Parameter Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tco tco tco tco tco tco tco tco 3.100 1.308 3.096 1.304 3.100 1.308 3.096 1.304 3.330 1.480 3.333 1.483 3.330 1.480 3.333 1.483 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-113 Table 1-67. EP3SL110 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.100 1.308 3.096 1.304 3.127 1.335 3.117 1.325 3.117 1.325 3.110 1.318 3.109 1.317 3.131 1.339 3.121 1.329 3.116 1.324 3.114 1.322 3.106 1.314 3.107 1.315 3.106 1.314 3.330 1.480 3.333 1.483 3.363 1.513 3.353 1.503 3.353 1.503 3.347 1.497 3.345 1.495 3.367 1.517 3.356 1.506 3.352 1.502 3.350 1.500 3.341 1.491 3.343 1.493 3.340 1.490 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 4.758 5.157 5.670 5.531 5.815 5.280 5.792 5.656 5.889 1.956 2.056 2.272 2.283 2.310 2.161 2.379 2.389 2.297 4.748 5.146 5.660 5.521 5.805 5.269 5.782 5.646 5.879 1.946 2.045 2.262 2.273 2.300 2.150 2.369 2.379 2.287 4.751 5.150 5.664 5.525 5.809 5.274 5.787 5.651 5.884 1.949 2.049 2.266 2.277 2.304 2.155 2.374 2.384 2.292 4.744 5.144 5.658 5.519 5.803 5.267 5.781 5.645 5.878 1.942 2.043 2.260 2.271 2.298 2.148 2.368 2.378 2.286 4.741 5.141 5.655 5.516 5.800 5.264 5.777 5.641 5.874 1.939 2.040 2.257 2.268 2.295 2.145 2.364 2.374 2.282 4.762 5.161 5.674 5.535 5.819 5.284 5.797 5.661 5.894 1.960 2.060 2.276 2.287 2.314 2.165 2.384 2.394 2.302 4.741 5.138 5.649 5.510 5.794 5.260 5.770 5.634 5.867 1.939 2.037 2.251 2.262 2.289 2.141 2.357 2.367 2.275 4.741 5.138 5.650 5.511 5.795 5.261 5.772 5.636 5.869 1.939 2.037 2.252 2.263 2.290 2.142 2.359 2.369 2.277 4.740 5.137 5.648 5.509 5.793 5.260 5.771 5.635 5.868 1.938 2.036 2.250 2.261 2.288 2.141 2.358 2.368 2.276 4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858 1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266 4.736 5.134 5.647 5.508 5.792 5.258 5.770 5.634 5.867 1.934 2.033 2.249 2.260 2.287 2.139 2.357 2.367 2.275 4.719 5.115 5.625 5.486 5.770 5.237 5.746 5.610 5.843 1.917 2.014 2.227 2.238 2.265 2.118 2.333 2.343 2.251 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.5-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.5-V HSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-114 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-67. EP3SL110 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.118 1.326 3.114 1.322 3.104 1.312 3.102 1.310 3.102 1.310 3.106 1.314 3.132 1.340 3.118 1.326 3.106 1.314 3.106 1.314 3.102 1.310 3.106 1.314 3.107 1.315 3.353 1.503 3.350 1.500 3.339 1.489 3.337 1.487 3.338 1.488 3.341 1.491 3.370 1.520 3.356 1.506 3.343 1.493 3.343 1.493 3.339 1.489 3.341 1.491 3.343 1.493 4.737 5.133 5.643 5.504 5.788 5.256 5.765 5.629 5.862 1.935 2.032 2.245 2.256 2.283 2.137 2.352 2.362 2.270 4.738 5.135 5.647 5.508 5.792 5.258 5.769 5.633 5.866 1.936 2.034 2.249 2.260 2.287 2.139 2.356 2.366 2.274 4.727 5.124 5.635 5.496 5.780 5.247 5.757 5.621 5.854 1.925 2.023 2.237 2.248 2.275 2.128 2.344 2.354 2.262 4.725 5.121 5.633 5.494 5.778 5.245 5.755 5.619 5.852 1.923 2.020 2.235 2.246 2.273 2.126 2.342 2.352 2.260 4.728 5.126 5.638 5.499 5.783 5.249 5.761 5.625 5.858 1.926 2.025 2.240 2.251 2.278 2.130 2.348 2.358 2.266 4.725 5.121 5.632 5.493 5.777 5.244 5.754 5.618 5.851 1.923 2.020 2.234 2.245 2.272 2.125 2.341 2.351 2.259 4.770 5.169 5.682 5.543 5.827 5.292 5.804 5.668 5.901 1.968 2.068 2.284 2.295 2.322 2.173 2.391 2.401 2.309 4.758 5.158 5.672 5.533 5.817 5.282 5.795 5.659 5.892 1.956 2.057 2.274 2.285 2.312 2.163 2.382 2.392 2.300 4.741 5.140 5.654 5.515 5.799 5.264 5.777 5.641 5.874 1.939 2.039 2.256 2.267 2.294 2.145 2.364 2.374 2.282 4.744 5.144 5.658 5.519 5.803 5.268 5.782 5.646 5.879 1.942 2.043 2.260 2.271 2.298 2.149 2.369 2.379 2.287 4.737 5.136 5.651 5.512 5.796 5.261 5.774 5.638 5.871 1.935 2.035 2.253 2.264 2.291 2.142 2.361 2.371 2.279 4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858 1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266 4.738 5.137 5.650 5.511 5.795 5.260 5.773 5.637 5.870 1.936 2.036 2.252 2.263 2.290 2.141 2.360 2.370 2.278 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-115 Table 1-67. EP3SL110 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.135 1.343 3.124 1.332 3.119 1.327 3.105 1.313 3.103 1.311 3.107 1.315 3.107 1.315 3.123 1.331 3.123 1.331 3.113 1.321 3.106 1.314 3.373 1.523 3.361 1.511 3.357 1.507 3.342 1.492 3.340 1.490 3.342 1.492 3.343 1.493 3.360 1.510 3.360 1.510 3.350 1.500 3.342 1.492 4.769 5.167 5.680 5.541 5.825 5.291 5.802 5.666 5.899 1.967 2.066 2.282 2.293 2.320 2.172 2.389 2.399 2.307 4.757 5.155 5.668 5.529 5.813 5.279 5.790 5.654 5.887 1.955 2.054 2.270 2.281 2.308 2.160 2.377 2.387 2.295 4.757 5.156 5.669 5.530 5.814 5.280 5.792 5.656 5.889 1.955 2.055 2.271 2.282 2.309 2.161 2.379 2.389 2.297 4.739 5.137 5.650 5.511 5.795 5.261 5.774 5.638 5.871 1.937 2.036 2.252 2.263 2.290 2.142 2.361 2.371 2.279 4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276 4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263 4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276 4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 4.743 5.140 5.652 5.513 5.797 5.264 5.775 5.639 5.872 1.941 2.039 2.254 2.265 2.292 2.145 2.362 2.372 2.280 4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 8mA DIFFERENTIAL 2.5-V SSTL CLASS I GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-116 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-68 lists the EP3SL110 row pins output timing parameters for differential I/O standards. Table 1-68. EP3SL110 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.711 0.934 3.106 1.326 3.088 1.308 2.711 0.934 3.106 1.326 3.088 1.308 2.711 0.934 3.106 1.326 3.088 1.308 3.132 1.352 3.118 1.338 3.114 1.334 3.130 1.350 2.894 1.059 3.342 1.503 3.332 1.493 2.894 1.059 3.342 1.503 3.332 1.493 2.894 1.059 3.342 1.503 3.332 1.493 3.375 1.536 3.361 1.522 3.357 1.518 3.372 1.533 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.783 5.187 5.698 5.562 5.817 5.313 5.826 5.689 5.892 1.993 2.096 2.309 2.322 2.325 2.204 2.420 2.430 2.312 4.770 5.174 5.685 5.549 5.804 5.299 5.813 5.676 5.879 1.980 2.083 2.296 2.309 2.312 2.190 2.407 2.417 2.299 4.768 5.174 5.686 5.550 5.805 5.299 5.815 5.678 5.881 1.978 2.083 2.297 2.310 2.313 2.190 2.409 2.419 2.301 4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874 1.979 2.080 2.291 2.304 2.307 2.187 2.402 2.412 2.294 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I 4mA 6mA 8mA 4mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-117 Table 1-68. EP3SL110 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS I GCLK 6mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.119 1.339 3.116 1.336 3.127 1.347 3.117 1.337 3.103 1.323 3.100 1.320 3.097 1.317 3.098 1.318 3.147 1.367 3.123 1.343 3.106 1.326 3.151 1.371 3.136 1.356 3.362 1.523 3.359 1.520 3.369 1.530 3.360 1.521 3.346 1.507 3.342 1.503 3.340 1.501 3.340 1.501 3.393 1.554 3.369 1.530 3.350 1.511 3.396 1.557 3.381 1.542 4.765 5.167 5.677 5.541 5.796 5.293 5.805 5.668 5.871 1.975 2.076 2.288 2.301 2.304 2.184 2.399 2.409 2.291 4.763 5.165 5.675 5.539 5.794 5.291 5.804 5.667 5.870 1.973 2.074 2.286 2.299 2.302 2.182 2.398 2.408 2.290 4.764 5.166 5.674 5.538 5.793 5.291 5.802 5.665 5.868 1.974 2.075 2.285 2.298 2.301 2.182 2.396 2.406 2.288 4.762 5.164 5.673 5.537 5.792 5.290 5.802 5.665 5.868 1.972 2.073 2.284 2.297 2.300 2.181 2.396 2.406 2.288 4.747 5.149 5.659 5.523 5.778 5.275 5.787 5.650 5.853 1.957 2.058 2.270 2.283 2.286 2.166 2.381 2.391 2.273 4.743 5.145 5.655 5.519 5.774 5.271 5.783 5.646 5.849 1.953 2.054 2.266 2.279 2.282 2.162 2.377 2.387 2.269 4.744 5.148 5.658 5.522 5.777 5.274 5.787 5.650 5.853 1.954 2.057 2.269 2.282 2.285 2.165 2.381 2.391 2.273 4.734 5.136 5.645 5.509 5.764 5.261 5.773 5.636 5.839 1.944 2.045 2.256 2.269 2.272 2.152 2.367 2.377 2.259 4.805 5.209 5.721 5.585 5.840 5.335 5.849 5.712 5.915 2.015 2.118 2.332 2.345 2.348 2.226 2.443 2.453 2.335 4.787 5.192 5.704 5.568 5.823 5.318 5.834 5.697 5.900 1.997 2.101 2.315 2.328 2.331 2.209 2.428 2.438 2.320 4.765 5.170 5.682 5.546 5.801 5.296 5.812 5.675 5.878 1.975 2.079 2.293 2.306 2.309 2.187 2.406 2.416 2.298 4.805 5.209 5.720 5.584 5.839 5.335 5.849 5.712 5.915 2.015 2.118 2.331 2.344 2.347 2.226 2.443 2.453 2.335 4.791 5.194 5.705 5.569 5.824 5.320 5.834 5.697 5.900 2.001 2.103 2.316 2.329 2.332 2.211 2.428 2.438 2.320 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 4mA 6mA 8mA 10mA 12mA DIFFERENTIAL 1.8-V 16mA HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I 4mA 6mA 8mA 4mA 6mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-118 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-68. EP3SL110 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 1.8-V SSTL CLASS II DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.125 1.345 3.105 1.325 3.102 1.322 3.107 1.327 3.100 1.320 3.138 1.358 3.120 1.340 3.106 1.326 3.370 1.531 3.350 1.511 3.346 1.507 3.350 1.511 3.343 1.504 3.382 1.543 3.365 1.526 3.349 1.510 4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898 1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318 4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874 1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294 4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871 1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291 4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855 1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275 4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860 1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280 4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895 1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315 4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880 1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300 4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855 1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 10mA 12mA 8mA 16mA 8mA 12mA 16mA Table 1-69 and Table 1-70 list the EP3SL110 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-69 lists the EP3SL110 column pin delay adders when using the regional clock. Table 1-69. EP3SL110 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units 0.186 2.391 -0.374 -2.001 0.171 2.371 -0.162 -1.786 0.245 3.577 -0.226 -2.669 0.255 4.036 -0.233 -2.844 0.268 4.418 0.261 4.225 0.393 4.574 0.248 4.044 0.277 4.442 0.267 4.246 0.364 4.635 ns ns ns ns -0.244 -0.239 -0.367 -0.111 -0.123 -0.116 -0.296 -2.996 -2.879 -2.722 -2.699 -3.067 -2.798 -2.773 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-119 Table 1-70 lists the EP3SL110 row pin delay adders when using the regional clock. Table 1-70. EP3SL110 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units 0.086 0.075 -0.072 -0.063 0.109 0.075 -0.097 -0.065 0.158 0.117 -0.137 -0.097 0.16 0.123 -0.1 0.161 0.129 0.159 0.125 0.281 0.222 -0.24 0.137 0.113 -0.11 0.153 0.118 -0.09 0.153 0.114 0.285 0.226 ns ns ns ns -0.135 -0.116 -0.134 -0.104 -0.124 -0.244 -0.088 -0.201 -0.104 -0.101 -0.198 -0.088 EP3SL150 I/O Timing Parameters Table 1-71 through Table 1-74 list the maximum I/O timing parameters for EP3SL150 devices for single-ended I/O standards. Table 1-71 lists the EP3SL150 column pins input timing parameters for single-ended I/O standards. Table 1-71. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.986 1.119 -1.278 1.556 -0.986 1.119 -1.278 1.556 -0.997 1.130 -1.289 1.567 -0.997 1.130 -1.289 1.567 -0.992 1.125 -1.284 1.562 -0.964 1.093 -1.221 1.499 -0.964 1.093 -1.221 1.499 -0.975 1.104 -1.232 1.510 -0.975 1.104 -1.232 1.510 -0.970 1.099 -1.227 1.505 -1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106 1.584 2.175 1.584 2.175 1.583 2.174 1.583 2.174 1.592 2.183 1.767 2.439 1.767 2.439 1.769 2.441 1.769 2.441 1.781 2.453 2.027 2.697 2.027 2.697 2.026 2.696 2.026 2.696 2.045 2.715 1.996 2.598 1.996 2.598 1.995 2.597 1.995 2.597 2.014 2.616 2.327 3.034 2.327 3.034 2.326 3.033 2.326 3.033 2.345 3.052 1.767 2.439 1.767 2.439 1.769 2.441 1.769 2.441 1.781 2.453 2.027 2.697 2.027 2.697 2.026 2.696 2.026 2.696 2.045 2.715 1.996 2.598 1.996 2.598 1.995 2.597 1.995 2.597 2.014 2.616 2.327 3.034 2.327 3.034 2.326 3.033 2.326 3.033 2.345 3.052 -1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542 -1.402 -1.558 -1.797 -1.778 -2.106 -1.558 -1.797 -1.778 -2.106 -1.771 -1.984 -2.197 -2.123 -2.542 -1.984 -2.197 -2.123 -2.542 -1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105 -1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541 -1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105 -1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541 -1.410 -1.572 -1.815 -1.796 -2.124 -1.572 -1.815 -1.796 -2.124 -1.779 -1.998 -2.215 -2.141 -2.560 -1.998 -2.215 -2.141 -2.560 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-120 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-71. EP3SL150 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.8 V tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.014 1.149 -1.306 1.586 -1.004 1.139 -1.296 1.576 -0.952 1.087 -1.244 1.524 -0.923 1.058 -1.215 1.495 -0.923 1.058 -1.215 1.495 -0.917 1.052 -1.209 1.489 -0.917 1.052 -1.209 1.489 -0.906 1.041 -1.198 1.478 -0.906 1.041 -1.198 1.478 -0.992 1.123 -1.249 1.529 -0.982 1.113 -1.239 1.519 -0.930 1.061 -1.187 1.467 -0.901 1.032 -1.158 1.438 -0.901 1.032 -1.158 1.438 -0.895 1.026 -1.152 1.432 -0.895 1.026 -1.152 1.432 -0.884 1.015 -1.141 1.421 -0.884 1.015 -1.141 1.421 -1.450 -1.608 -1.813 -1.794 -2.122 -1.608 -1.813 -1.794 -2.122 1.632 2.223 1.609 2.200 1.532 2.123 1.504 2.095 1.504 2.095 1.491 2.082 1.491 2.082 1.479 2.070 1.479 2.070 1.817 2.489 1.785 2.457 1.686 2.358 1.670 2.342 1.670 2.342 1.659 2.331 1.659 2.331 1.648 2.320 1.648 2.320 2.043 2.713 1.973 2.643 1.817 2.487 1.819 2.489 1.819 2.489 1.813 2.483 1.813 2.483 1.794 2.464 1.794 2.464 2.012 2.614 1.942 2.544 1.786 2.388 1.788 2.390 1.788 2.390 1.782 2.384 1.782 2.384 1.763 2.365 1.763 2.365 2.343 3.050 2.273 2.980 2.117 2.824 2.119 2.826 2.119 2.826 2.112 2.819 2.112 2.819 2.093 2.800 2.093 2.800 1.817 2.489 1.785 2.457 1.686 2.358 1.670 2.342 1.670 2.342 1.659 2.331 1.659 2.331 1.648 2.320 1.648 2.320 2.043 2.713 1.973 2.643 1.817 2.487 1.819 2.489 1.819 2.489 1.813 2.483 1.813 2.483 1.794 2.464 1.794 2.464 2.012 2.614 1.942 2.544 1.786 2.388 1.788 2.390 1.788 2.390 1.782 2.384 1.782 2.384 1.763 2.365 1.763 2.365 2.343 3.050 2.273 2.980 2.117 2.824 2.119 2.826 2.119 2.826 2.112 2.819 2.112 2.819 2.093 2.800 2.093 2.800 -1.819 -2.034 -2.213 -2.139 -2.558 -2.034 -2.213 -2.139 -2.558 -1.427 -1.576 -1.743 -1.724 -2.052 -1.576 -1.743 -1.724 -2.052 -1.796 -2.002 -2.143 -2.069 -2.488 -2.002 -2.143 -2.069 -2.488 -1.350 -1.477 -1.587 -1.568 -1.896 -1.477 -1.587 -1.568 -1.896 -1.719 -1.903 -1.987 -1.913 -2.332 -1.903 -1.987 -1.913 -2.332 -1.322 -1.461 -1.589 -1.570 -1.898 -1.461 -1.589 -1.570 -1.898 -1.691 -1.887 -1.989 -1.915 -2.334 -1.887 -1.989 -1.915 -2.334 -1.322 -1.461 -1.589 -1.570 -1.898 -1.461 -1.589 -1.570 -1.898 -1.691 -1.887 -1.989 -1.915 -2.334 -1.887 -1.989 -1.915 -2.334 -1.309 -1.453 -1.586 -1.565 -1.896 -1.453 -1.586 -1.565 -1.896 -1.678 -1.879 -1.986 -1.910 -2.332 -1.879 -1.986 -1.910 -2.332 -1.309 -1.453 -1.586 -1.565 -1.896 -1.453 -1.586 -1.565 -1.896 -1.678 -1.879 -1.986 -1.910 -2.332 -1.879 -1.986 -1.910 -2.332 -1.298 -1.442 -1.567 -1.546 -1.877 -1.442 -1.567 -1.546 -1.877 -1.667 -1.868 -1.967 -1.891 -2.313 -1.868 -1.967 -1.891 -2.313 -1.298 -1.442 -1.567 -1.546 -1.877 -1.442 -1.567 -1.546 -1.877 -1.667 -1.868 -1.967 -1.891 -2.313 -1.868 -1.967 -1.891 -2.313 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-121 Table 1-71. EP3SL150 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.8-V HSTL CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.917 1.052 -1.209 1.489 -0.917 1.052 -1.209 1.489 -0.906 1.041 -1.198 1.478 -0.906 1.041 -1.198 1.478 -0.894 1.029 -1.186 1.466 -0.894 1.029 -1.186 1.466 -0.997 1.130 -1.289 1.567 -0.895 1.026 -1.152 1.432 -0.895 1.026 -1.152 1.432 -0.884 1.015 -1.141 1.421 -0.884 1.015 -1.141 1.421 -0.872 1.003 -1.129 1.409 -0.872 1.003 -1.129 1.409 -0.975 1.104 -1.232 1.510 -1.309 -1.453 -1.586 -1.565 -1.896 -1.453 -1.586 -1.565 -1.896 1.491 2.082 1.491 2.082 1.479 2.070 1.479 2.070 1.469 2.060 1.469 2.060 1.583 2.174 1.659 2.331 1.659 2.331 1.648 2.320 1.648 2.320 1.637 2.309 1.637 2.309 1.769 2.441 1.813 2.483 1.813 2.483 1.794 2.464 1.794 2.464 1.778 2.448 1.778 2.448 2.026 2.696 1.782 2.384 1.782 2.384 1.763 2.365 1.763 2.365 1.747 2.349 1.747 2.349 1.995 2.597 2.112 2.819 2.112 2.819 2.093 2.800 2.093 2.800 2.077 2.784 2.077 2.784 2.326 3.033 1.659 2.331 1.659 2.331 1.648 2.320 1.648 2.320 1.637 2.309 1.637 2.309 1.769 2.441 1.813 2.483 1.813 2.483 1.794 2.464 1.794 2.464 1.778 2.448 1.778 2.448 2.026 2.696 1.782 2.384 1.782 2.384 1.763 2.365 1.763 2.365 1.747 2.349 1.747 2.349 1.995 2.597 2.112 2.819 2.112 2.819 2.093 2.800 2.093 2.800 2.077 2.784 2.077 2.784 2.326 3.033 -1.678 -1.879 -1.986 -1.910 -2.332 -1.879 -1.986 -1.910 -2.332 -1.309 -1.453 -1.586 -1.565 -1.896 -1.453 -1.586 -1.565 -1.896 -1.678 -1.879 -1.986 -1.910 -2.332 -1.879 -1.986 -1.910 -2.332 -1.298 -1.442 -1.567 -1.546 -1.877 -1.442 -1.567 -1.546 -1.877 -1.667 -1.868 -1.967 -1.891 -2.313 -1.868 -1.967 -1.891 -2.313 -1.298 -1.442 -1.567 -1.546 -1.877 -1.442 -1.567 -1.546 -1.877 -1.667 -1.868 -1.967 -1.891 -2.313 -1.868 -1.967 -1.891 -2.313 -1.288 -1.431 -1.551 -1.530 -1.861 -1.431 -1.551 -1.530 -1.861 -1.657 -1.857 -1.951 -1.875 -2.297 -1.857 -1.951 -1.875 -2.297 -1.288 -1.431 -1.551 -1.530 -1.861 -1.431 -1.551 -1.530 -1.861 -1.657 -1.857 -1.951 -1.875 -2.297 -1.857 -1.951 -1.875 -2.297 -1.401 -1.560 -1.796 -1.777 -2.105 -1.560 -1.796 -1.777 -2.105 -1.770 -1.986 -2.196 -2.122 -2.541 -1.986 -2.196 -2.122 -2.541 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-122 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-72 lists the EP3SL150 row pins input timing parameters for single-ended I/O standards. Table 1-72. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.925 1.040 0.988 -0.737 -0.925 1.040 0.988 -0.737 -0.931 1.046 0.982 -0.731 -0.931 1.046 0.982 -0.731 -0.919 1.034 0.994 -0.743 -0.949 1.065 0.964 -0.712 -0.939 1.055 0.974 -0.722 -0.879 0.995 1.034 -0.782 -0.964 1.094 1.009 -0.741 -0.964 1.094 1.009 -0.741 -0.975 1.105 0.998 -0.730 -0.975 1.105 0.998 -0.730 -0.968 1.098 1.005 -0.737 -1.000 1.131 0.966 -0.698 -0.989 1.120 0.977 -0.709 -0.936 1.067 1.030 -0.762 -1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993 1.544 1.642 1.677 1.858 1.910 1.971 1.851 1.855 2.173 1.796 1.698 1.865 1.917 1.993 1.860 1.875 2.212 1.848 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS -1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363 -1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993 1.544 1.642 1.677 1.858 1.910 1.971 1.851 1.855 2.173 1.796 1.698 1.865 1.917 1.993 1.860 1.875 2.212 1.848 GCLK PLL GCLK -1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 1.541 1.645 1.678 1.857 1.913 1.968 1.854 1.852 2.176 1.793 1.697 1.866 1.922 1.988 1.865 1.870 2.217 1.843 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 1.541 1.645 1.678 1.857 1.913 1.968 1.854 1.852 2.176 1.793 1.697 1.866 1.922 1.988 1.865 1.870 2.217 1.843 GCLK PLL GCLK -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 -1.366 -1.484 -1.700 -1.651 -1.972 -1.488 -1.694 -1.649 -2.008 1.550 1.636 1.691 1.844 1.928 1.953 1.869 1.837 2.191 1.778 1.706 1.857 1.932 1.978 1.875 1.860 2.227 1.833 2.5 V GCLK PLL GCLK 1.8 V -1.235 -1.393 -1.453 -1.365 -1.296 -1.399 -1.467 -1.378 -1.348 -1.406 -1.530 -1.590 -1.662 -1.875 -1.521 -1.582 -1.663 -1.913 1.590 1.589 1.738 1.806 1.824 1.955 1.880 1.835 2.098 1.780 1.739 1.824 1.826 1.977 1.889 1.854 2.137 1.832 GCLK PLL GCLK 1.5 V -1.190 -1.356 -1.455 -1.362 -1.298 -1.366 -1.466 -1.372 -1.347 -1.382 -1.498 -1.522 -1.594 -1.807 -1.490 -1.517 -1.598 -1.848 1.566 1.613 1.706 1.838 1.756 2.023 1.812 1.903 2.030 1.848 1.708 1.855 1.761 2.042 1.824 1.919 2.072 1.897 GCLK PLL GCLK 1.2 V -1.214 -1.388 -1.523 -1.430 -1.366 -1.397 -1.531 -1.437 -1.412 -1.303 -1.397 -1.363 -1.435 -1.648 -1.394 -1.362 -1.443 -1.693 1.487 1.692 1.605 1.939 1.597 2.182 1.653 2.062 1.871 2.007 1.612 1.951 1.606 2.197 1.669 2.074 1.917 2.052 GCLK PLL -1.293 -1.489 -1.682 -1.589 -1.525 -1.493 -1.686 -1.592 -1.567 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-123 Table 1-72. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-2 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.862 0.978 1.051 -0.799 -0.862 0.978 1.051 -0.799 -0.853 0.969 1.060 -0.808 -0.853 0.969 1.060 -0.808 -0.839 0.955 1.074 -0.822 -0.853 0.969 1.060 -0.808 -0.853 0.969 1.060 -0.808 -0.839 0.955 1.074 -0.822 -0.839 0.955 1.074 -0.822 -0.910 1.041 1.063 -0.794 -0.910 1.041 1.063 -0.794 -0.901 1.032 1.065 -0.797 -0.901 1.032 1.065 -0.797 -0.889 1.020 1.077 -0.809 -0.901 1.032 1.065 -0.797 -0.901 1.032 1.065 -0.797 -0.889 1.020 1.077 -0.809 -0.889 1.020 1.077 -0.809 -1.280 -1.375 -1.480 -1.431 -1.752 -1.376 -1.477 -1.432 -1.791 1.464 1.722 1.582 1.953 1.708 2.173 1.649 2.057 1.971 1.998 1.594 1.969 1.715 2.195 1.658 2.077 2.010 2.050 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.321 -1.502 -1.673 -1.585 -1.516 -1.511 -1.684 -1.595 -1.565 -1.280 -1.375 -1.480 -1.431 -1.752 -1.376 -1.477 -1.432 -1.791 1.464 1.722 1.582 1.953 1.708 2.173 1.649 2.057 1.971 1.998 1.594 1.969 1.715 2.195 1.658 2.077 2.010 2.050 SSTL-2 CLASS II GCLK PLL GCLK -1.321 -1.502 -1.673 -1.585 -1.516 -1.511 -1.684 -1.595 -1.565 -1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688 1.449 1.730 1.576 1.966 1.592 2.187 1.646 2.068 1.865 2.011 1.578 1.983 1.599 2.204 1.660 2.082 1.908 2.059 SSTL-18 CLASS I GCLK PLL GCLK -1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578 -1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688 1.449 1.730 1.576 1.966 1.592 2.187 1.646 2.068 1.865 2.011 1.578 1.983 1.599 2.204 1.660 2.082 1.908 2.059 SSTL-18 CLASS II GCLK PLL GCLK -1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578 -1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671 1.435 1.745 1.566 1.976 1.574 2.205 1.628 2.086 1.847 2.029 1.567 1.994 1.582 2.221 1.643 2.099 1.891 2.076 SSTL-15 CLASS I GCLK PLL GCLK -1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595 -1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688 1.449 1.730 1.576 1.966 1.592 2.187 1.646 2.068 1.865 2.011 1.578 1.983 1.599 2.204 1.660 2.082 1.908 2.059 1.8-V HSTL CLASS I GCLK PLL GCLK -1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578 -1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688 1.449 1.730 1.576 1.966 1.592 2.187 1.646 2.068 1.865 2.011 1.578 1.983 1.599 2.204 1.660 2.082 1.908 2.059 1.8-V HSTL CLASS II GCLK PLL GCLK -1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578 -1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671 1.435 1.745 1.566 1.976 1.574 2.205 1.628 2.086 1.847 2.029 1.567 1.994 1.582 2.221 1.643 2.099 1.891 2.076 1.5-V HSTL CLASS I GCLK PLL GCLK -1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595 -1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671 1.435 1.745 1.566 1.976 1.574 2.205 1.628 2.086 1.847 2.029 1.567 1.994 1.582 2.221 1.643 2.099 1.891 2.076 1.5-V HSTL CLASS II GCLK PLL -1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-124 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-72. EP3SL150 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.2-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.830 0.946 1.083 -0.831 -0.830 0.946 1.083 -0.831 -0.931 1.046 0.982 -0.731 -0.931 1.046 0.982 -0.731 -0.877 1.008 1.089 -0.821 -0.877 1.008 1.089 -0.821 -0.975 1.105 0.998 -0.730 -0.975 1.105 0.998 -0.730 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 1.426 1.754 1.556 1.986 1.558 2.221 1.612 2.102 1.831 2.045 1.558 2.003 1.566 2.237 1.627 2.115 1.875 2.092 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 -1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 1.426 1.754 1.556 1.986 1.558 2.221 1.612 2.102 1.831 2.045 1.558 2.003 1.566 2.237 1.627 2.115 1.875 2.092 1.2-V HSTL CLASS II GCLK PLL GCLK -1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 1.541 1.645 1.678 1.857 1.913 1.968 1.854 1.852 2.176 1.793 1.697 1.866 1.922 1.988 1.865 1.870 2.217 1.843 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 -1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 1.541 1.645 1.678 1.857 1.913 1.968 1.854 1.852 2.176 1.793 1.697 1.866 1.922 1.988 1.865 1.870 2.217 1.843 GCLK PLL -1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358 Table 1-73 lists the EP3SL150 column pins output timing parameters for single-ended I/O standards. Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco 3.422 3.898 3.355 3.781 3.269 3.692 3.262 3.685 3.439 3.841 3.372 3.774 3.286 3.688 3.279 3.681 4.768 5.355 4.659 5.246 4.555 5.142 4.538 5.125 5.127 5.880 5.016 5.718 4.918 5.583 4.890 5.555 5.625 6.341 5.512 6.228 5.420 6.136 5.379 6.095 5.473 6.161 5.360 6.048 5.268 5.956 5.227 5.915 5.808 5.127 5.625 5.473 5.808 6.543 5.880 6.341 6.161 6.543 5.695 5.016 5.512 5.360 5.695 6.430 5.718 6.228 6.048 6.430 5.603 4.918 5.420 5.268 5.603 6.338 5.583 6.136 5.956 6.338 5.562 4.890 5.379 5.227 5.562 6.297 5.555 6.095 5.915 6.297 ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-125 Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.428 3.901 3.273 3.701 3.280 3.703 3.264 3.687 3.386 3.843 3.275 3.713 3.239 3.662 3.221 3.644 3.300 3.751 3.221 3.644 3.216 3.639 3.207 3.630 3.445 3.847 3.290 3.692 3.297 3.699 3.281 3.683 3.403 3.805 3.292 3.694 3.256 3.658 3.238 3.640 3.317 3.719 3.238 3.640 3.233 3.635 3.224 3.626 4.772 5.359 4.565 5.152 4.559 5.146 4.537 5.124 4.735 5.322 4.605 5.192 4.542 5.129 4.513 5.100 4.639 5.226 4.515 5.102 4.508 5.095 4.494 5.081 5.132 5.892 4.935 5.600 4.914 5.579 4.888 5.553 5.096 5.831 4.962 5.659 4.893 5.560 4.865 5.530 4.995 5.712 4.866 5.531 4.859 5.524 4.844 5.509 5.632 6.348 5.431 6.147 5.405 6.121 5.376 6.092 5.592 6.308 5.455 6.170 5.381 6.096 5.352 6.070 5.490 6.205 5.355 6.083 5.346 6.062 5.331 6.057 5.480 6.168 5.279 5.967 5.253 5.941 5.224 5.912 5.440 6.128 5.303 5.991 5.229 5.917 5.200 5.888 5.338 6.026 5.203 5.891 5.194 5.882 5.179 5.867 5.815 5.132 5.632 5.480 5.815 6.550 5.892 6.348 6.168 6.550 5.614 4.935 5.431 5.279 5.614 6.349 5.600 6.147 5.967 6.349 5.588 4.914 5.405 5.253 5.588 6.323 5.579 6.121 5.941 6.323 5.559 4.888 5.376 5.224 5.559 6.294 5.553 6.092 5.912 6.294 5.775 5.096 5.592 5.440 5.775 6.510 5.831 6.308 6.128 6.510 5.637 4.962 5.455 5.303 5.637 6.371 5.659 6.170 5.991 6.371 5.563 4.893 5.381 5.229 5.563 6.298 5.560 6.096 5.917 6.298 5.535 4.865 5.352 5.200 5.535 6.270 5.530 6.070 5.888 6.270 5.672 4.995 5.490 5.338 5.672 6.406 5.712 6.205 6.026 6.406 5.537 4.866 5.355 5.203 5.537 6.271 5.531 6.083 5.891 6.271 5.529 4.859 5.346 5.194 5.529 6.264 5.524 6.062 5.882 6.264 5.514 4.844 5.331 5.179 5.514 6.249 5.509 6.057 5.867 6.249 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA 4mA 8mA 3.0-V LVCMOS 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-126 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.422 3.898 3.322 3.773 3.278 3.701 3.240 3.663 3.613 4.161 3.432 3.920 3.350 3.802 3.330 3.753 3.267 3.690 3.249 3.672 3.439 3.841 3.339 3.741 3.295 3.697 3.257 3.659 3.630 4.032 3.449 3.851 3.367 3.769 3.347 3.749 3.284 3.686 3.266 3.668 4.846 5.433 4.727 5.314 4.640 5.227 4.601 5.188 5.167 5.754 4.888 5.475 4.781 5.368 4.723 5.310 4.662 5.249 4.641 5.228 5.222 5.991 5.096 5.807 5.006 5.671 4.963 5.628 5.582 6.474 5.273 6.068 5.158 5.878 5.105 5.780 5.030 5.695 5.008 5.673 5.737 6.452 5.605 6.320 5.509 6.225 5.466 6.182 6.141 6.857 5.794 6.509 5.683 6.399 5.617 6.333 5.536 6.252 5.513 6.229 5.585 6.273 5.453 6.141 5.357 6.045 5.314 6.002 5.989 6.677 5.642 6.330 5.531 6.219 5.465 6.153 5.384 6.072 5.361 6.049 5.919 5.222 5.737 5.585 5.919 6.654 5.991 6.452 6.273 6.654 5.787 5.096 5.605 5.453 5.787 6.521 5.807 6.320 6.141 6.521 5.692 5.006 5.509 5.357 5.692 6.427 5.671 6.225 6.045 6.427 5.649 4.963 5.466 5.314 5.649 6.384 5.628 6.182 6.002 6.384 6.324 5.582 6.141 5.989 6.324 7.059 6.474 6.857 6.677 7.059 5.976 5.273 5.794 5.642 5.976 6.710 6.068 6.509 6.330 6.710 5.866 5.158 5.683 5.531 5.866 6.601 5.878 6.399 6.219 6.601 5.800 5.105 5.617 5.465 5.800 6.535 5.780 6.333 6.153 6.535 5.719 5.030 5.536 5.384 5.719 6.454 5.695 6.252 6.072 6.454 5.696 5.008 5.513 5.361 5.696 6.431 5.673 6.229 6.049 6.431 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 2.5 V 12mA 16mA 2mA 4mA 6mA 1.8 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-127 Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.559 4.069 3.347 3.786 3.322 3.745 3.311 3.734 3.256 3.679 3.251 3.674 3.475 3.959 3.352 3.786 3.314 3.737 3.267 3.690 3.267 3.690 3.264 3.687 3.262 3.685 3.576 3.978 3.364 3.766 3.339 3.741 3.328 3.730 3.273 3.675 3.268 3.670 3.492 3.894 3.369 3.771 3.331 3.733 3.284 3.686 3.284 3.686 3.281 3.683 3.279 3.681 5.096 5.683 4.777 5.364 4.710 5.297 4.693 5.280 4.655 5.242 4.638 5.225 5.022 5.609 4.796 5.383 4.704 5.291 4.676 5.263 4.633 5.220 4.630 5.217 4.630 5.217 5.515 6.384 5.158 5.871 5.098 5.763 5.073 5.742 5.023 5.688 5.011 5.676 5.450 6.283 5.189 5.902 5.099 5.764 5.050 5.715 4.998 5.663 4.994 5.659 4.995 5.660 6.079 6.795 5.687 6.403 5.620 6.336 5.600 6.316 5.530 6.246 5.519 6.235 6.023 6.739 5.737 6.453 5.624 6.340 5.568 6.284 5.499 6.215 5.495 6.211 5.496 6.212 5.927 6.615 5.535 6.223 5.468 6.156 5.448 6.136 5.378 6.066 5.367 6.055 5.871 6.559 5.585 6.273 5.472 6.160 5.416 6.104 5.347 6.035 5.343 6.031 5.344 6.032 6.262 5.515 6.079 5.927 6.262 6.997 6.384 6.795 6.615 6.997 5.870 5.158 5.687 5.535 5.870 6.605 5.871 6.403 6.223 6.605 5.803 5.098 5.620 5.468 5.803 6.538 5.763 6.336 6.156 6.538 5.783 5.073 5.600 5.448 5.783 6.518 5.742 6.316 6.136 6.518 5.713 5.023 5.530 5.378 5.713 6.448 5.688 6.246 6.066 6.448 5.702 5.011 5.519 5.367 5.702 6.437 5.676 6.235 6.055 6.437 6.206 5.450 6.023 5.871 6.206 6.941 6.283 6.739 6.559 6.941 5.920 5.189 5.737 5.585 5.920 6.655 5.902 6.453 6.273 6.655 5.807 5.099 5.624 5.472 5.807 6.542 5.764 6.340 6.160 6.542 5.751 5.050 5.568 5.416 5.751 6.486 5.715 6.284 6.104 6.486 5.682 4.998 5.499 5.347 5.682 6.417 5.663 6.215 6.035 6.417 5.678 4.994 5.495 5.343 5.678 6.413 5.659 6.211 6.031 6.413 5.679 4.995 5.496 5.344 5.679 6.414 5.660 6.212 6.032 6.414 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.5 V 8mA 10mA 12mA 2mA 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-128 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock SSTL-2 CLASS II GCLK 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.253 3.676 3.274 3.697 3.270 3.693 3.259 3.682 3.248 3.671 3.248 3.671 3.254 3.677 3.257 3.680 3.278 3.701 3.264 3.687 3.253 3.676 3.252 3.675 3.249 3.672 3.270 3.672 3.291 3.693 3.287 3.689 3.276 3.678 3.265 3.667 3.265 3.667 3.271 3.673 3.274 3.676 3.295 3.697 3.281 3.683 3.270 3.672 3.269 3.671 3.266 3.668 4.615 5.202 4.645 5.232 4.643 5.230 4.633 5.220 4.620 5.207 4.620 5.207 4.619 5.206 4.627 5.214 4.654 5.241 4.644 5.231 4.630 5.217 4.633 5.220 4.628 5.215 4.980 5.645 5.012 5.677 5.010 5.675 5.000 5.665 4.987 5.652 4.987 5.652 4.984 5.649 4.994 5.659 5.023 5.688 5.013 5.678 4.999 5.664 5.003 5.668 4.997 5.662 5.481 6.197 5.515 6.231 5.513 6.229 5.504 6.220 5.491 6.207 5.491 6.207 5.486 6.202 5.498 6.214 5.528 6.244 5.519 6.235 5.505 6.221 5.509 6.225 5.503 6.219 5.329 6.017 5.363 6.051 5.361 6.049 5.352 6.040 5.339 6.027 5.339 6.027 5.334 6.022 5.346 6.034 5.376 6.064 5.367 6.055 5.353 6.041 5.357 6.045 5.351 6.039 5.664 4.980 5.481 5.329 5.664 6.399 5.645 6.197 6.017 6.399 5.698 5.012 5.515 5.363 5.698 6.433 5.677 6.231 6.051 6.433 5.696 5.010 5.513 5.361 5.696 6.431 5.675 6.229 6.049 6.431 5.687 5.000 5.504 5.352 5.687 6.422 5.665 6.220 6.040 6.422 5.674 4.987 5.491 5.339 5.674 6.409 5.652 6.207 6.027 6.409 5.674 4.987 5.491 5.339 5.674 6.409 5.652 6.207 6.027 6.409 5.669 4.984 5.486 5.334 5.669 6.404 5.649 6.202 6.022 6.404 5.681 4.994 5.498 5.346 5.681 6.416 5.659 6.214 6.034 6.416 5.711 5.023 5.528 5.376 5.711 6.446 5.688 6.244 6.064 6.446 5.702 5.013 5.519 5.367 5.702 6.437 5.678 6.235 6.055 6.437 5.688 4.999 5.505 5.353 5.688 6.423 5.664 6.221 6.041 6.423 5.692 5.003 5.509 5.357 5.692 6.427 5.668 6.225 6.045 6.427 5.686 4.997 5.503 5.351 5.686 6.421 5.662 6.219 6.039 6.421 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA 8mA SSTL-18 CLASS II 16mA 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-129 Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA SSTL-15 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.251 3.674 3.254 3.677 3.261 3.684 3.254 3.677 3.246 3.669 3.249 3.672 3.246 3.669 3.254 3.677 3.266 3.689 3.262 3.685 3.258 3.681 3.251 3.674 3.252 3.675 3.268 3.670 3.271 3.673 3.278 3.680 3.271 3.673 3.263 3.665 3.266 3.668 3.263 3.665 3.271 3.673 3.283 3.685 3.279 3.681 3.275 3.677 3.268 3.670 3.269 3.671 4.617 5.204 4.624 5.211 4.619 5.206 4.617 5.204 4.609 5.196 4.612 5.199 4.615 5.202 4.614 5.201 4.627 5.214 4.628 5.215 4.624 5.211 4.617 5.204 4.624 5.211 4.983 5.648 4.992 5.657 4.983 5.648 4.982 5.647 4.974 5.639 4.978 5.643 4.981 5.646 4.979 5.644 4.993 5.658 4.995 5.660 4.990 5.655 4.983 5.648 4.991 5.656 5.486 6.202 5.497 6.213 5.484 6.200 5.483 6.199 5.476 6.192 5.480 6.196 5.484 6.200 5.480 6.196 5.495 6.211 5.498 6.214 5.493 6.209 5.486 6.202 5.496 6.212 5.334 6.022 5.345 6.033 5.332 6.020 5.331 6.019 5.324 6.012 5.328 6.016 5.332 6.020 5.328 6.016 5.343 6.031 5.346 6.034 5.341 6.029 5.334 6.022 5.344 6.032 5.669 4.983 5.486 5.334 5.669 6.404 5.648 6.202 6.022 6.404 5.680 4.992 5.497 5.345 5.680 6.415 5.657 6.213 6.033 6.415 5.667 4.983 5.484 5.332 5.667 6.402 5.648 6.200 6.020 6.402 5.666 4.982 5.483 5.331 5.666 6.401 5.647 6.199 6.019 6.401 5.659 4.974 5.476 5.324 5.659 6.394 5.639 6.192 6.012 6.394 5.663 4.978 5.480 5.328 5.663 6.398 5.643 6.196 6.016 6.398 5.667 4.981 5.484 5.332 5.667 6.402 5.646 6.200 6.020 6.402 5.663 4.979 5.480 5.328 5.663 6.398 5.644 6.196 6.016 6.398 5.678 4.993 5.495 5.343 5.678 6.413 5.658 6.211 6.031 6.413 5.681 4.995 5.498 5.346 5.681 6.416 5.660 6.214 6.034 6.416 5.676 4.990 5.493 5.341 5.676 6.411 5.655 6.209 6.029 6.411 5.669 4.983 5.486 5.334 5.669 6.404 5.648 6.202 6.022 6.404 5.679 4.991 5.496 5.344 5.679 6.414 5.656 6.212 6.032 6.414 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-130 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-73. EP3SL150 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard 1.5-V HSTL CLASS II Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.250 3.673 3.269 3.692 3.261 3.684 3.262 3.685 3.251 3.674 3.251 3.674 3.272 3.695 3.375 3.798 3.375 3.798 3.267 3.669 3.286 3.688 3.278 3.680 3.279 3.681 3.268 3.670 3.268 3.670 3.289 3.691 3.392 3.794 3.392 3.794 4.605 5.192 4.641 5.228 4.632 5.219 4.640 5.227 4.627 5.214 4.627 5.214 4.643 5.230 4.688 5.275 4.688 5.275 4.969 5.634 5.010 5.675 5.001 5.666 5.010 5.675 4.996 5.661 4.996 5.661 5.011 5.676 5.045 5.710 5.045 5.710 5.470 6.186 5.516 6.232 5.507 6.223 5.516 6.232 5.502 6.218 5.503 6.219 5.516 6.233 5.541 6.264 5.541 6.264 5.318 6.006 5.364 6.052 5.355 6.043 5.364 6.052 5.350 6.038 5.351 6.039 5.364 6.052 5.389 6.077 5.389 6.077 5.653 4.969 5.470 5.318 5.653 6.388 5.634 6.186 6.006 6.388 5.699 5.010 5.516 5.364 5.699 6.434 5.675 6.232 6.052 6.434 5.690 5.001 5.507 5.355 5.690 6.425 5.666 6.223 6.043 6.425 5.699 5.010 5.516 5.364 5.699 6.434 5.675 6.232 6.052 6.434 5.685 4.996 5.502 5.350 5.685 6.420 5.661 6.218 6.038 6.420 5.686 4.996 5.503 5.351 5.686 6.421 5.661 6.219 6.039 6.421 5.699 5.011 5.516 5.364 5.699 6.434 5.676 6.233 6.052 6.434 5.724 5.045 5.541 5.389 5.724 6.459 5.710 6.264 6.077 6.459 5.724 5.045 5.541 5.389 5.724 6.459 5.710 6.264 6.077 6.459 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-131 Table 1-74 lists the EP3SL150 row pins output timing parameters for single-ended I/O standards. Table 1-74. EP3SL150 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.214 1.420 3.121 1.354 3.042 1.275 3.224 1.422 3.046 1.279 3.168 1.381 3.047 1.280 3.010 1.243 3.082 1.302 2.997 1.230 3.194 1.407 3.089 1.322 3.038 1.265 3.466 1.606 3.361 1.535 3.271 1.446 3.470 1.613 3.275 1.450 3.412 1.567 3.285 1.455 3.242 1.417 3.331 1.479 3.226 1.401 3.448 1.604 3.350 1.501 3.282 1.457 4.819 5.204 5.693 5.566 5.831 5.325 5.817 5.689 5.913 1.985 2.065 2.256 2.277 2.285 2.167 2.360 2.380 2.277 4.689 5.066 5.548 5.421 5.686 5.184 5.668 5.540 5.764 1.875 1.954 2.142 2.163 2.171 2.054 2.245 2.265 2.162 4.570 4.943 5.420 5.293 5.558 5.057 5.536 5.408 5.632 1.769 1.854 2.046 2.067 2.075 1.955 2.145 2.165 2.062 4.827 5.209 5.697 5.570 5.835 5.331 5.821 5.693 5.917 1.989 2.071 2.265 2.286 2.294 2.175 2.372 2.392 2.289 4.576 4.949 5.427 5.301 5.564 5.063 5.543 5.417 5.639 1.780 1.869 2.056 2.077 2.085 1.967 2.154 2.174 2.071 4.771 5.157 5.649 5.522 5.787 5.282 5.775 5.647 5.871 1.952 2.034 2.222 2.243 2.251 2.135 2.326 2.346 2.243 4.618 4.998 5.485 5.358 5.623 5.120 5.611 5.482 5.706 1.815 1.892 2.077 2.098 2.106 1.993 2.181 2.200 2.097 4.536 4.915 5.397 5.270 5.535 5.034 5.518 5.389 5.613 1.755 1.827 2.007 2.028 2.036 1.925 2.107 2.127 2.024 4.665 5.050 5.539 5.412 5.677 5.174 5.664 5.535 5.759 1.850 1.927 2.113 2.134 2.142 2.026 2.217 2.236 2.133 4.502 4.876 5.358 5.231 5.496 4.994 5.478 5.349 5.573 1.727 1.798 1.979 2.000 2.008 1.895 2.079 2.098 1.995 4.903 5.311 5.821 5.694 5.959 5.442 5.954 5.825 6.049 2.060 2.160 2.367 2.388 2.396 2.267 2.478 2.498 2.395 4.748 5.148 5.651 5.524 5.789 5.275 5.780 5.651 5.875 1.936 2.025 2.225 2.246 2.254 2.130 2.334 2.353 2.250 4.637 5.029 5.525 5.398 5.663 5.152 5.650 5.521 5.745 1.852 1.939 2.134 2.155 2.163 2.041 2.239 2.259 2.156 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVTTL 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-132 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-74. EP3SL150 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.431 1.655 3.206 1.430 3.141 1.365 3.081 1.327 3.342 1.566 3.100 1.343 3.073 1.316 3.064 1.297 3.285 1.509 3.105 1.348 3.036 1.269 3.031 1.264 3.022 1.255 3.699 1.850 3.497 1.648 3.395 1.546 3.321 1.508 3.617 1.768 3.359 1.525 3.312 1.499 3.303 1.488 3.542 1.693 3.353 1.529 3.270 1.445 3.266 1.441 3.255 1.430 5.291 5.740 6.296 6.169 6.434 5.882 6.438 6.310 6.534 2.491 2.527 2.770 2.796 2.799 2.776 2.888 2.913 2.805 4.964 5.371 5.891 5.764 6.029 5.517 6.032 5.903 6.127 2.164 2.201 2.410 2.436 2.439 2.411 2.527 2.551 2.443 4.811 5.221 5.732 5.605 5.870 5.349 5.859 5.731 5.955 2.011 2.096 2.310 2.336 2.339 2.243 2.421 2.446 2.338 4.734 5.127 5.635 5.508 5.773 5.254 5.765 5.637 5.861 1.937 2.043 2.244 2.270 2.273 2.148 2.349 2.374 2.266 5.201 5.653 6.224 6.097 6.362 5.789 6.362 6.234 6.458 2.401 2.454 2.707 2.733 2.736 2.683 2.823 2.848 2.740 4.796 5.216 5.733 5.606 5.871 5.343 5.858 5.730 5.954 1.996 2.096 2.313 2.339 2.342 2.237 2.422 2.447 2.339 4.723 5.120 5.627 5.502 5.765 5.245 5.753 5.625 5.849 1.923 2.035 2.244 2.270 2.273 2.139 2.349 2.374 2.266 4.701 5.102 5.608 5.483 5.746 5.227 5.731 5.606 5.827 1.905 2.010 2.225 2.251 2.254 2.121 2.330 2.355 2.247 5.111 5.567 6.149 6.022 6.287 5.701 6.278 6.150 6.374 2.311 2.386 2.646 2.672 2.675 2.595 2.754 2.779 2.671 4.818 5.244 5.774 5.647 5.912 5.368 5.900 5.772 5.996 2.018 2.124 2.361 2.387 2.390 2.262 2.466 2.491 2.383 4.620 5.004 5.495 5.369 5.631 5.123 5.614 5.488 5.708 1.845 1.930 2.124 2.145 2.153 2.028 2.225 2.245 2.142 4.617 5.002 5.493 5.367 5.628 5.122 5.613 5.487 5.706 1.842 1.928 2.122 2.143 2.151 2.027 2.224 2.244 2.141 4.602 4.986 5.476 5.350 5.611 5.105 5.595 5.469 5.688 1.827 1.912 2.105 2.126 2.134 2.010 2.206 2.226 2.123 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-133 Table 1-74. EP3SL150 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.042 1.276 3.027 1.271 3.016 1.260 2.992 1.249 2.992 1.249 3.002 1.257 2.996 1.258 3.038 1.279 3.015 1.265 2.998 1.254 3.277 1.452 3.263 1.447 3.251 1.436 3.228 1.425 3.227 1.424 3.236 1.431 3.231 1.434 3.273 1.455 3.251 1.441 3.234 1.429 4.629 5.031 5.512 5.397 5.647 5.135 5.631 5.516 5.724 1.856 1.947 2.139 2.165 2.168 2.041 2.240 2.265 2.157 4.626 5.030 5.511 5.396 5.646 5.133 5.629 5.514 5.722 1.854 1.946 2.138 2.164 2.167 2.039 2.238 2.263 2.155 4.609 5.020 5.501 5.386 5.636 5.116 5.620 5.505 5.713 1.844 1.936 2.128 2.154 2.157 2.030 2.229 2.254 2.146 4.593 5.007 5.488 5.373 5.623 5.101 5.608 5.493 5.701 1.831 1.923 2.115 2.141 2.144 2.018 2.217 2.242 2.134 4.592 5.007 5.488 5.373 5.623 5.100 5.608 5.493 5.701 1.831 1.923 2.115 2.141 2.144 2.017 2.217 2.242 2.134 4.590 5.004 5.483 5.368 5.618 5.095 5.602 5.487 5.695 1.830 1.920 2.110 2.136 2.139 2.013 2.211 2.236 2.128 4.589 5.012 5.493 5.378 5.628 5.097 5.613 5.498 5.706 1.836 1.928 2.120 2.146 2.149 2.022 2.222 2.247 2.139 4.640 5.042 5.526 5.410 5.664 5.148 5.644 5.528 5.740 1.865 1.958 2.152 2.178 2.181 2.051 2.252 2.277 2.169 4.622 5.032 5.515 5.400 5.650 5.132 5.634 5.519 5.727 1.854 1.948 2.142 2.168 2.171 2.042 2.243 2.268 2.160 4.605 5.019 5.502 5.387 5.637 5.114 5.621 5.506 5.714 1.841 1.935 2.129 2.155 2.158 2.029 2.230 2.255 2.147 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-134 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-74. EP3SL150 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.017 1.264 3.005 1.257 2.992 1.248 2.994 1.251 2.987 1.247 2.993 1.255 3.024 1.270 3.012 1.264 3.008 1.260 3.023 1.272 3.011 1.263 3.007 1.262 3.142 1.375 3.142 1.375 3.249 1.437 3.237 1.431 3.225 1.423 3.227 1.425 3.222 1.422 3.226 1.430 3.256 1.443 3.246 1.438 3.241 1.434 3.255 1.445 3.243 1.437 3.241 1.437 3.376 1.551 3.376 1.551 4.596 5.002 5.481 5.366 5.616 5.099 5.599 5.484 5.692 1.829 1.918 2.108 2.134 2.137 2.012 2.208 2.233 2.125 4.587 5.001 5.480 5.365 5.615 5.091 5.599 5.484 5.692 1.827 1.917 2.107 2.133 2.136 2.011 2.208 2.233 2.125 4.578 4.994 5.473 5.358 5.608 5.083 5.592 5.477 5.685 1.820 1.910 2.100 2.126 2.129 2.004 2.201 2.226 2.118 4.581 4.997 5.477 5.362 5.612 5.086 5.595 5.480 5.688 1.823 1.913 2.104 2.130 2.133 2.007 2.204 2.229 2.121 4.579 5.000 5.480 5.365 5.615 5.086 5.600 5.485 5.693 1.825 1.916 2.107 2.133 2.136 2.010 2.209 2.234 2.126 4.574 4.997 5.476 5.361 5.611 5.077 5.594 5.479 5.687 1.823 1.913 2.103 2.129 2.132 2.006 2.203 2.228 2.120 4.607 5.012 5.492 5.377 5.627 5.111 5.610 5.495 5.703 1.838 1.928 2.119 2.145 2.148 2.021 2.219 2.244 2.136 4.603 5.014 5.494 5.379 5.629 5.108 5.613 5.498 5.706 1.839 1.930 2.121 2.147 2.150 2.023 2.222 2.247 2.139 4.597 5.009 5.489 5.374 5.624 5.102 5.607 5.492 5.700 1.834 1.925 2.116 2.142 2.145 2.018 2.216 2.241 2.133 4.618 5.028 5.511 5.396 5.646 5.125 5.629 5.514 5.722 1.851 1.944 2.138 2.164 2.167 2.037 2.238 2.263 2.155 4.607 5.019 5.502 5.387 5.637 5.114 5.620 5.505 5.713 1.842 1.935 2.129 2.155 2.158 2.028 2.229 2.254 2.146 4.611 5.027 5.511 5.396 5.646 5.120 5.630 5.515 5.723 1.849 1.943 2.138 2.164 2.167 2.037 2.239 2.264 2.156 4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749 1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184 4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749 1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-135 Table 1-75 through Table 1-75 list the maximum I/O timing parameters for EP3SL150 devices for differential I/O standards. Table 1-75 lists the EP3SL150 column pins input timing parameters for differential I/O standards. Table 1-75. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK tsu th -0.978 1.104 0.967 -0.707 -0.978 1.104 0.967 -0.707 -0.978 1.104 0.967 -0.707 -0.794 0.913 1.151 -0.898 -0.794 0.913 1.151 -0.898 -0.802 0.921 1.143 -0.890 -0.802 0.921 1.143 -0.890 -0.814 0.933 1.131 -0.878 -1.006 1.152 1.001 -0.719 -1.006 1.152 1.001 -0.719 -1.006 1.152 1.001 -0.719 -0.829 0.967 1.178 -0.904 -0.829 0.967 1.178 -0.904 -0.841 0.979 1.166 -0.892 -0.841 0.979 1.166 -0.892 -0.852 0.990 1.155 -0.881 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632 1.371 1.885 1.387 2.230 1.564 2.404 1.502 2.293 1.860 2.197 1.361 2.284 1.634 2.556 1.471 2.353 1.898 2.249 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718 -1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786 1.416 1.808 1.546 2.031 1.677 2.245 1.610 2.139 1.964 2.048 1.554 2.049 1.684 2.266 1.621 2.155 2.007 2.095 DIFFERENTIAL 1.2-V HSTL CLASS I -1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609 -1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786 1.416 1.808 1.546 2.031 1.677 2.245 1.610 2.139 1.964 2.048 1.554 2.049 1.684 2.266 1.621 2.155 2.007 2.095 DIFFERENTIAL 1.2-V HSTL CLASS II -1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V HSTL CLASS I -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V HSTL CLASS II -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V HSTL CLASS I -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-136 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-75. EP3SL150 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.814 0.933 1.131 -0.878 -0.802 0.921 1.143 -0.890 -0.802 0.921 1.143 -0.890 -0.814 0.933 1.131 -0.878 -0.814 0.933 1.131 -0.878 -0.821 0.940 1.124 -0.871 -0.821 0.940 1.124 -0.871 -0.852 0.990 1.155 -0.881 -0.841 0.979 1.166 -0.892 -0.841 0.979 1.166 -0.892 -0.852 0.990 1.155 -0.881 -0.852 0.990 1.155 -0.881 -0.858 0.996 1.149 -0.875 -0.858 0.996 1.149 -0.875 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V SSTL CLASS I -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801 1.426 1.798 1.557 2.020 1.693 2.229 1.626 2.123 1.980 2.032 1.565 2.038 1.699 2.251 1.636 2.140 2.022 2.080 DIFFERENTIAL 1.5-V SSTL CLASS II -1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V SSTL CLASS I -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819 1.436 1.789 1.568 2.009 1.712 2.210 1.645 2.104 1.999 2.013 1.576 2.027 1.717 2.233 1.654 2.122 2.040 2.062 DIFFERENTIAL 1.8-V SSTL CLASS II -1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576 -1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 1.449 1.777 1.576 2.004 1.715 2.210 1.648 2.102 2.003 2.014 1.583 2.023 1.717 2.238 1.653 2.124 2.041 2.066 DIFFERENTIAL 2.5-V SSTL CLASS I -1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 -1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815 1.449 1.777 1.576 2.004 1.715 2.210 1.648 2.102 2.003 2.014 1.583 2.023 1.717 2.238 1.653 2.124 2.041 2.066 DIFFERENTIAL 2.5-V SSTL CLASS II -1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-137 Table 1-76 lists the EP3SL150 row pins input timing parameters for differential I/O standards. Table 1-76. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK LVDS GCLK PLL GCLK MINI-LVDS GCLK PLL GCLK RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.919 1.043 0.959 -0.698 -0.919 1.043 0.959 -0.698 -0.919 1.043 0.959 -0.698 -0.724 0.841 1.154 -0.900 -0.724 0.841 1.154 -0.900 -0.733 0.850 1.145 -0.891 -0.733 0.850 1.145 -0.891 -0.747 0.864 1.131 -0.877 -0.950 1.092 0.987 -0.708 -0.950 1.092 0.987 -0.708 -0.950 1.092 0.987 -0.708 -0.765 0.898 1.172 -0.902 -0.765 0.898 1.172 -0.902 -0.777 0.910 1.160 -0.890 -0.777 0.910 1.160 -0.890 -0.789 0.922 1.148 -0.878 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 1.358 2.597 1.303 2.470 1.711 2.387 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 1.358 2.597 1.303 2.470 1.711 2.387 -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853 -1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442 1.245 1.949 1.237 2.324 1.395 2.527 1.339 2.403 1.672 2.334 1.207 2.384 1.358 2.597 1.303 2.470 1.711 2.387 -1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853 -1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626 1.302 1.862 1.420 2.100 1.535 2.338 1.474 2.219 1.802 2.155 1.429 2.117 1.543 2.360 1.483 2.238 1.846 2.203 DIFFERENTIAL 1.2-V HSTL CLASS I -1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718 -1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626 1.302 1.862 1.420 2.100 1.535 2.338 1.474 2.219 1.802 2.155 1.429 2.117 1.543 2.360 1.483 2.238 1.846 2.203 DIFFERENTIAL 1.2-V HSTL CLASS II -1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 1.559 2.344 1.499 2.222 1.862 2.187 DIFFERENTIAL 1.5-V HSTL CLASS I -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 1.559 2.344 1.499 2.222 1.862 2.187 DIFFERENTIAL 1.5-V HSTL CLASS II -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 1.576 2.327 1.516 2.205 1.879 2.170 DIFFERENTIAL 1.8-V HSTL CLASS I -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-138 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-76. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK DIFFERENTIAL 1.8-V HSTL CLASS II GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.747 0.864 1.131 -0.877 -0.733 0.850 1.145 -0.891 -0.733 0.850 1.145 -0.891 -0.747 0.864 1.131 -0.877 -0.747 0.864 1.131 -0.877 -0.756 0.873 1.122 -0.868 -0.756 0.873 1.122 -0.868 -0.789 0.922 1.148 -0.878 -0.777 0.910 1.160 -0.890 -0.777 0.910 1.160 -0.890 -0.789 0.922 1.148 -0.878 -0.789 0.922 1.148 -0.878 -0.798 0.931 1.139 -0.869 -0.798 0.931 1.139 -0.869 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 1.576 2.327 1.516 2.205 1.879 2.170 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 1.559 2.344 1.499 2.222 1.862 2.187 DIFFERENTIAL 1.5-V SSTL CLASS I -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702 -1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642 1.311 1.853 1.430 2.090 1.551 2.322 1.490 2.203 1.818 2.139 1.438 2.108 1.559 2.344 1.499 2.222 1.862 2.187 DIFFERENTIAL 1.5-V SSTL CLASS II -1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 1.576 2.327 1.516 2.205 1.879 2.170 DIFFERENTIAL 1.8-V SSTL CLASS I -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 -1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659 1.321 1.840 1.440 2.080 1.569 2.304 1.508 2.185 1.836 2.121 1.449 2.097 1.576 2.327 1.516 2.205 1.879 2.170 DIFFERENTIAL 1.8-V SSTL CLASS II -1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685 -1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661 1.336 1.825 1.454 2.064 1.579 2.293 1.518 2.173 1.847 2.110 1.459 2.086 1.582 2.321 1.521 2.197 1.886 2.163 DIFFERENTIAL 2.5-V SSTL CLASS I -1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674 -1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661 1.336 1.825 1.454 2.064 1.579 2.293 1.518 2.173 1.847 2.110 1.459 2.086 1.582 2.321 1.521 2.197 1.886 2.163 DIFFERENTIAL 2.5-V SSTL CLASS II -1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-139 Table 1-77 lists the EP3SL150 column pins output timing parameters for differential I/O standards. Table 1-77. EP3SL150 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.100 1.308 3.096 1.304 3.100 1.308 3.096 1.304 3.100 1.308 3.096 1.304 3.127 1.335 3.117 1.325 3.117 1.325 3.110 1.318 3.109 1.317 3.131 1.339 3.330 1.480 3.333 1.483 3.330 1.480 3.333 1.483 3.330 1.480 3.333 1.483 3.363 1.513 3.353 1.503 3.353 1.503 3.347 1.497 3.345 1.495 3.367 1.517 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803 1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869 1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 4.758 5.157 5.670 5.531 5.815 5.280 5.792 5.656 5.889 1.956 2.056 2.272 2.283 2.310 2.161 2.379 2.389 2.297 4.748 5.146 5.660 5.521 5.805 5.269 5.782 5.646 5.879 1.946 2.045 2.262 2.273 2.300 2.150 2.369 2.379 2.287 4.751 5.150 5.664 5.525 5.809 5.274 5.787 5.651 5.884 1.949 2.049 2.266 2.277 2.304 2.155 2.374 2.384 2.292 4.744 5.144 5.658 5.519 5.803 5.267 5.781 5.645 5.878 1.942 2.043 2.260 2.271 2.298 2.148 2.368 2.378 2.286 4.741 5.141 5.655 5.516 5.800 5.264 5.777 5.641 5.874 1.939 2.040 2.257 2.268 2.295 2.145 2.364 2.374 2.282 4.762 5.161 5.674 5.535 5.819 5.284 5.797 5.661 5.894 1.960 2.060 2.276 2.287 2.314 2.165 2.384 2.394 2.302 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-140 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-77. EP3SL150 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.121 1.329 3.116 1.324 3.114 1.322 3.106 1.314 3.107 1.315 3.106 1.314 3.118 1.326 3.114 1.322 3.104 1.312 3.102 1.310 3.102 1.310 3.106 1.314 3.356 1.506 3.352 1.502 3.350 1.500 3.341 1.491 3.343 1.493 3.340 1.490 3.353 1.503 3.350 1.500 3.339 1.489 3.337 1.487 3.338 1.488 3.341 1.491 4.741 5.138 5.649 5.510 5.794 5.260 5.770 5.634 5.867 1.939 2.037 2.251 2.262 2.289 2.141 2.357 2.367 2.275 4.741 5.138 5.650 5.511 5.795 5.261 5.772 5.636 5.869 1.939 2.037 2.252 2.263 2.290 2.142 2.359 2.369 2.277 4.740 5.137 5.648 5.509 5.793 5.260 5.771 5.635 5.868 1.938 2.036 2.250 2.261 2.288 2.141 2.358 2.368 2.276 4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858 1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266 4.736 5.134 5.647 5.508 5.792 5.258 5.770 5.634 5.867 1.934 2.033 2.249 2.260 2.287 2.139 2.357 2.367 2.275 4.719 5.115 5.625 5.486 5.770 5.237 5.746 5.610 5.843 1.917 2.014 2.227 2.238 2.265 2.118 2.333 2.343 2.251 4.737 5.133 5.643 5.504 5.788 5.256 5.765 5.629 5.862 1.935 2.032 2.245 2.256 2.283 2.137 2.352 2.362 2.270 4.738 5.135 5.647 5.508 5.792 5.258 5.769 5.633 5.866 1.936 2.034 2.249 2.260 2.287 2.139 2.356 2.366 2.274 4.727 5.124 5.635 5.496 5.780 5.247 5.757 5.621 5.854 1.925 2.023 2.237 2.248 2.275 2.128 2.344 2.354 2.262 4.725 5.121 5.633 5.494 5.778 5.245 5.755 5.619 5.852 1.923 2.020 2.235 2.246 2.273 2.126 2.342 2.352 2.260 4.728 5.126 5.638 5.499 5.783 5.249 5.761 5.625 5.858 1.926 2.025 2.240 2.251 2.278 2.130 2.348 2.358 2.266 4.725 5.121 5.632 5.493 5.777 5.244 5.754 5.618 5.851 1.923 2.020 2.234 2.245 2.272 2.125 2.341 2.351 2.259 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-141 Table 1-77. EP3SL150 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.132 1.340 3.118 1.326 3.106 1.314 3.106 1.314 3.102 1.310 3.106 1.314 3.107 1.315 3.135 1.343 3.124 1.332 3.119 1.327 3.105 1.313 3.103 1.311 3.107 1.315 3.107 1.315 3.370 1.520 3.356 1.506 3.343 1.493 3.343 1.493 3.339 1.489 3.341 1.491 3.343 1.493 3.373 1.523 3.361 1.511 3.357 1.507 3.342 1.492 3.340 1.490 3.342 1.492 3.343 1.493 4.770 5.169 5.682 5.543 5.827 5.292 5.804 5.668 5.901 1.968 2.068 2.284 2.295 2.322 2.173 2.391 2.401 2.309 4.758 5.158 5.672 5.533 5.817 5.282 5.795 5.659 5.892 1.956 2.057 2.274 2.285 2.312 2.163 2.382 2.392 2.300 4.741 5.140 5.654 5.515 5.799 5.264 5.777 5.641 5.874 1.939 2.039 2.256 2.267 2.294 2.145 2.364 2.374 2.282 4.744 5.144 5.658 5.519 5.803 5.268 5.782 5.646 5.879 1.942 2.043 2.260 2.271 2.298 2.149 2.369 2.379 2.287 4.737 5.136 5.651 5.512 5.796 5.261 5.774 5.638 5.871 1.935 2.035 2.253 2.264 2.291 2.142 2.361 2.371 2.279 4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858 1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266 4.738 5.137 5.650 5.511 5.795 5.260 5.773 5.637 5.870 1.936 2.036 2.252 2.263 2.290 2.141 2.360 2.370 2.278 4.769 5.167 5.680 5.541 5.825 5.291 5.802 5.666 5.899 1.967 2.066 2.282 2.293 2.320 2.172 2.389 2.399 2.307 4.757 5.155 5.668 5.529 5.813 5.279 5.790 5.654 5.887 1.955 2.054 2.270 2.281 2.308 2.160 2.377 2.387 2.295 4.757 5.156 5.669 5.530 5.814 5.280 5.792 5.656 5.889 1.955 2.055 2.271 2.282 2.309 2.161 2.379 2.389 2.297 4.739 5.137 5.650 5.511 5.795 5.261 5.774 5.638 5.871 1.937 2.036 2.252 2.263 2.290 2.142 2.361 2.371 2.279 4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276 4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263 4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-142 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-77. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco 3.123 1.331 3.123 1.331 3.113 1.321 3.106 1.314 3.360 1.510 3.360 1.510 3.350 1.500 3.342 1.492 4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881 1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289 4.743 5.140 5.652 5.513 5.797 5.264 5.775 5.639 5.872 1.941 2.039 2.254 2.265 2.292 2.145 2.362 2.372 2.280 4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263 ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-143 Table 1-78 lists the EP3SL150 row pins output timing parameters for differential I/O standards. Table 1-78. EP3SL150 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.711 0.934 3.106 1.326 3.088 1.308 2.711 0.934 3.106 1.326 3.088 1.308 2.711 0.934 3.106 1.326 3.088 1.308 3.132 1.352 3.118 1.338 3.114 1.334 2.894 1.059 3.342 1.503 3.332 1.493 2.894 1.059 3.342 1.503 3.332 1.493 2.894 1.059 3.342 1.503 3.332 1.493 3.375 1.536 3.361 1.522 3.357 1.518 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035 1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459 4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802 1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283 4.783 5.187 5.698 5.562 5.817 5.313 5.826 5.689 5.892 1.993 2.096 2.309 2.322 2.325 2.204 2.420 2.430 2.312 4.770 5.174 5.685 5.549 5.804 5.299 5.813 5.676 5.879 1.980 2.083 2.296 2.309 2.312 2.190 2.407 2.417 2.299 4.768 5.174 5.686 5.550 5.805 5.299 5.815 5.678 5.881 1.978 2.083 2.297 2.310 2.313 2.190 2.409 2.419 2.301 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-144 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-78. EP3SL150 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA DIFFERENTIAL 1.8-V HSTL CLASS I tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.130 1.350 3.119 1.339 3.116 1.336 3.127 1.347 3.117 1.337 3.103 1.323 3.100 1.320 3.097 1.317 3.098 1.318 3.147 1.367 3.123 1.343 3.106 1.326 3.372 1.533 3.362 1.523 3.359 1.520 3.369 1.530 3.360 1.521 3.346 1.507 3.342 1.503 3.340 1.501 3.340 1.501 3.393 1.554 3.369 1.530 3.350 1.511 4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874 1.979 2.080 2.291 2.304 2.307 2.187 2.402 2.412 2.294 4.765 5.167 5.677 5.541 5.796 5.293 5.805 5.668 5.871 1.975 2.076 2.288 2.301 2.304 2.184 2.399 2.409 2.291 4.763 5.165 5.675 5.539 5.794 5.291 5.804 5.667 5.870 1.973 2.074 2.286 2.299 2.302 2.182 2.398 2.408 2.290 4.764 5.166 5.674 5.538 5.793 5.291 5.802 5.665 5.868 1.974 2.075 2.285 2.298 2.301 2.182 2.396 2.406 2.288 4.762 5.164 5.673 5.537 5.792 5.290 5.802 5.665 5.868 1.972 2.073 2.284 2.297 2.300 2.181 2.396 2.406 2.288 4.747 5.149 5.659 5.523 5.778 5.275 5.787 5.650 5.853 1.957 2.058 2.270 2.283 2.286 2.166 2.381 2.391 2.273 4.743 5.145 5.655 5.519 5.774 5.271 5.783 5.646 5.849 1.953 2.054 2.266 2.279 2.282 2.162 2.377 2.387 2.269 4.744 5.148 5.658 5.522 5.777 5.274 5.787 5.650 5.853 1.954 2.057 2.269 2.282 2.285 2.165 2.381 2.391 2.273 4.734 5.136 5.645 5.509 5.764 5.261 5.773 5.636 5.839 1.944 2.045 2.256 2.269 2.272 2.152 2.367 2.377 2.259 4.805 5.209 5.721 5.585 5.840 5.335 5.849 5.712 5.915 2.015 2.118 2.332 2.345 2.348 2.226 2.443 2.453 2.335 4.787 5.192 5.704 5.568 5.823 5.318 5.834 5.697 5.900 1.997 2.101 2.315 2.328 2.331 2.209 2.428 2.438 2.320 4.765 5.170 5.682 5.546 5.801 5.296 5.812 5.675 5.878 1.975 2.079 2.293 2.306 2.309 2.187 2.406 2.416 2.298 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL DIFFERENTIAL 1.5-V SSTL CLASS I Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-145 Table 1-78. EP3SL150 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 8mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.151 1.371 3.136 1.356 3.125 1.345 3.105 1.325 3.102 1.322 3.107 1.327 3.100 1.320 3.138 1.358 3.120 1.340 3.106 1.326 3.396 1.557 3.381 1.542 3.370 1.531 3.350 1.511 3.346 1.507 3.350 1.511 3.343 1.504 3.382 1.543 3.365 1.526 3.349 1.510 4.805 5.209 5.720 5.584 5.839 5.335 5.849 5.712 5.915 2.015 2.118 2.331 2.344 2.347 2.226 2.443 2.453 2.335 4.791 5.194 5.705 5.569 5.824 5.320 5.834 5.697 5.900 2.001 2.103 2.316 2.329 2.332 2.211 2.428 2.438 2.320 4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898 1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318 4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874 1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294 4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871 1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291 4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855 1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275 4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860 1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280 4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895 1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315 4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880 1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300 4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855 1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V SSTL CLASS I GCLK 16mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL DIFFERENTIAL 2.5-V SSTL CLASS I (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-146 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-79 and Table 1-80 list the EP3SL150 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-79 lists the EP3SL150 column pin delay adders when using the regional clock. Table 1-79. EP3SL150 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units 0.198 2.453 -0.374 -2.017 0.152 2.426 -0.152 -1.798 0.22 3.654 -2.68 0.258 4.098 -2.859 0.27 4.422 -0.248 -3.011 0.262 4.224 -0.227 -2.872 0.393 4.664 -0.367 -2.715 0.244 4.106 -0.11 -2.714 0.271 4.447 -0.127 -3.082 0.261 4.101 -0.106 -2.791 0.495 4.707 -0.303 -2.766 ns ns ns ns -0.216 -0.232 Table 1-80 lists the EP3SL150 row pin delay adders when using the regional clock. Table 1-80. EP3SL150 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.107 0.074 -0.093 -0.063 0.115 0.075 -0.103 -0.065 0.164 0.116 0.165 0.123 0.167 0.129 0.165 0.126 0.285 0.218 0.158 0.114 0.159 0.118 0.158 0.114 0.29 0.223 ns ns ns ns -0.137 -0.136 -0.133 -0.134 -0.257 -0.125 -0.121 -0.122 -0.261 -0.097 -0.102 -0.103 -0.102 -0.198 -0.088 -0.089 -0.088 -0.202 EP3SL200 I/O Timing Parameters Table 1-81 through Table 1-84 list the maximum I/O timing parameters for EP3SL200 devices for single-ended I/O standards. Table 1-81 lists the EP3SL200 column pins input timing parameters for single-ended I/O standards. Table 1-81. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th -1.137 1.285 -1.465 1.778 -1.137 1.285 -1.465 1.778 -1.173 1.319 -1.465 1.778 -1.173 1.319 -1.465 1.778 -1.810 -1.775 -2.002 -1.934 -2.482 -1.775 2.032 2.727 2.032 2.727 2.008 2.776 2.008 2.776 2.259 3.113 2.259 3.113 2.177 3.000 2.177 3.000 2.724 3.543 2.724 3.543 2.008 2.776 2.008 2.776 -2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.002 2.259 -2.558 3.113 -2.002 2.259 -2.558 3.113 -1.934 2.177 -2.477 3.000 -1.934 2.177 -2.477 3.000 -2.482 2.724 -2.997 3.543 -2.482 2.724 -2.997 3.543 ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-147 Table 1-81. EP3SL200 Column Pins Input Timing Parameters (Part 2 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.148 1.296 -1.476 1.789 -1.148 1.296 -1.476 1.789 -1.143 1.291 -1.471 1.784 -1.163 1.313 -1.493 1.808 -1.153 1.303 -1.483 1.798 -1.101 1.251 -1.431 1.746 -1.072 1.222 -1.402 1.717 -1.072 1.222 -1.402 1.717 -1.066 1.216 -1.396 1.711 -1.184 1.330 -1.476 1.789 -1.184 1.330 -1.476 1.789 -1.179 1.325 -1.471 1.784 -1.201 1.349 -1.493 1.808 -1.191 1.339 -1.483 1.798 -1.139 1.287 -1.431 1.746 -1.110 1.258 -1.402 1.717 -1.110 1.258 -1.402 1.717 -1.104 1.252 -1.396 1.711 -1.809 -1.777 -2.001 -1.933 -2.481 -1.777 2.031 2.726 2.031 2.726 2.040 2.735 2.080 2.775 2.057 2.752 1.980 2.675 1.952 2.647 1.952 2.647 1.939 2.634 2.010 2.778 2.010 2.778 2.022 2.790 2.058 2.826 2.026 2.794 1.927 2.695 1.911 2.679 1.911 2.679 1.903 2.668 2.258 3.112 2.258 3.112 2.277 3.131 2.275 3.129 2.205 3.059 2.049 2.903 2.051 2.905 2.051 2.905 2.048 2.899 2.176 2.999 2.176 2.999 2.195 3.018 2.193 3.016 2.123 2.946 1.967 2.790 1.969 2.792 1.969 2.792 1.966 2.786 2.723 3.542 2.723 3.542 2.742 3.561 2.740 3.559 2.670 3.489 2.514 3.333 2.516 3.335 2.516 3.335 2.509 3.328 2.010 2.778 2.010 2.778 2.022 2.790 2.058 2.826 2.026 2.794 1.927 2.695 1.911 2.679 1.911 2.679 1.903 2.668 -2.237 -2.273 -2.557 -2.476 -2.996 -2.273 -1.809 -1.777 -2.001 -1.933 -2.481 -1.777 -2.237 -2.273 -2.557 -2.476 -2.996 -2.273 -1.818 -1.789 -2.020 -1.952 -2.500 -1.789 -2.246 -2.285 -2.576 -2.495 -3.015 -2.285 -1.858 -1.825 -2.018 -1.950 -2.498 -1.825 -2.286 -2.321 -2.574 -2.493 -3.013 -2.321 -1.835 -1.793 -1.948 -1.880 -2.428 -1.793 -2.263 -2.289 -2.504 -2.423 -2.943 -2.289 -1.758 -1.694 -1.792 -1.724 -2.272 -1.694 -2.186 -2.190 -2.348 -2.267 -2.787 -2.190 -1.730 -1.678 -1.794 -1.726 -2.274 -1.678 -2.158 -2.174 -2.350 -2.269 -2.789 -2.174 -1.730 -1.678 -1.794 -1.726 -2.274 -1.678 -2.158 -2.174 -2.350 -2.269 -2.789 -2.174 -1.717 -1.673 -1.794 -1.724 -2.272 -1.673 -2.145 -2.166 -2.347 -2.264 -2.787 -2.166 -2.001 2.258 -2.557 3.112 -2.001 2.258 -2.557 3.112 -2.020 2.277 -2.576 3.131 -2.018 2.275 -2.574 3.129 -1.948 2.205 -2.504 3.059 -1.792 2.049 -2.348 2.903 -1.794 2.051 -2.350 2.905 -1.794 2.051 -2.350 2.905 -1.794 2.048 -2.347 2.899 -1.933 2.176 -2.476 2.999 -1.933 2.176 -2.476 2.999 -1.952 2.195 -2.495 3.018 -1.950 2.193 -2.493 3.016 -1.880 2.123 -2.423 2.946 -1.724 1.967 -2.267 2.790 -1.726 1.969 -2.269 2.792 -1.726 1.969 -2.269 2.792 -1.724 1.966 -2.264 2.786 -2.481 2.723 -2.996 3.542 -2.481 2.723 -2.996 3.542 -2.500 2.742 -3.015 3.561 -2.498 2.740 -3.013 3.559 -2.428 2.670 -2.943 3.489 -2.272 2.514 -2.787 3.333 -2.274 2.516 -2.789 3.335 -2.274 2.516 -2.789 3.335 -2.272 2.509 -2.787 3.328 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-148 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-81. EP3SL200 Column Pins Input Timing Parameters (Part 3 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-18 CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.066 1.216 -1.396 1.711 -1.055 1.205 -1.385 1.700 -1.055 1.205 -1.385 1.700 -1.066 1.216 -1.396 1.711 -1.066 1.216 -1.396 1.711 -1.055 1.205 -1.385 1.700 -1.055 1.205 -1.385 1.700 -1.043 1.193 -1.373 1.688 -1.043 1.193 -1.373 1.688 -1.104 1.252 -1.396 1.711 -1.093 1.241 -1.385 1.700 -1.093 1.241 -1.385 1.700 -1.104 1.252 -1.396 1.711 -1.104 1.252 -1.396 1.711 -1.093 1.241 -1.385 1.700 -1.093 1.241 -1.385 1.700 -1.081 1.229 -1.373 1.688 -1.081 1.229 -1.373 1.688 -1.717 -1.673 -1.794 -1.724 -2.272 -1.673 1.939 2.634 1.927 2.622 1.927 2.622 1.939 2.634 1.939 2.634 1.927 2.622 1.927 2.622 1.917 2.612 1.917 2.612 1.903 2.668 1.892 2.657 1.892 2.657 1.903 2.668 1.903 2.668 1.892 2.657 1.892 2.657 1.881 2.646 1.881 2.646 2.048 2.899 2.029 2.880 2.029 2.880 2.048 2.899 2.048 2.899 2.029 2.880 2.029 2.880 2.013 2.864 2.013 2.864 1.966 2.786 1.947 2.767 1.947 2.767 1.966 2.786 1.966 2.786 1.947 2.767 1.947 2.767 1.931 2.751 1.931 2.751 2.509 3.328 2.490 3.309 2.490 3.309 2.509 3.328 2.509 3.328 2.490 3.309 2.490 3.309 2.474 3.293 2.474 3.293 1.903 2.668 1.892 2.657 1.892 2.657 1.903 2.668 1.903 2.668 1.892 2.657 1.892 2.657 1.881 2.646 1.881 2.646 -2.145 -2.166 -2.347 -2.264 -2.787 -2.166 -1.706 -1.662 -1.775 -1.705 -2.253 -1.662 -2.134 -2.155 -2.328 -2.245 -2.768 -2.155 -1.706 -1.662 -1.775 -1.705 -2.253 -1.662 -2.134 -2.155 -2.328 -2.245 -2.768 -2.155 -1.717 -1.673 -1.794 -1.724 -2.272 -1.673 -2.145 -2.166 -2.347 -2.264 -2.787 -2.166 -1.717 -1.673 -1.794 -1.724 -2.272 -1.673 -2.145 -2.166 -2.347 -2.264 -2.787 -2.166 -1.706 -1.662 -1.775 -1.705 -2.253 -1.662 -2.134 -2.155 -2.328 -2.245 -2.768 -2.155 -1.706 -1.662 -1.775 -1.705 -2.253 -1.662 -2.134 -2.155 -2.328 -2.245 -2.768 -2.155 -1.696 -1.651 -1.759 -1.689 -2.237 -1.651 -2.124 -2.144 -2.312 -2.229 -2.752 -2.144 -1.696 -1.651 -1.759 -1.689 -2.237 -1.651 -2.124 -2.144 -2.312 -2.229 -2.752 -2.144 -1.794 2.048 -2.347 2.899 -1.775 2.029 -2.328 2.880 -1.775 2.029 -2.328 2.880 -1.794 2.048 -2.347 2.899 -1.794 2.048 -2.347 2.899 -1.775 2.029 -2.328 2.880 -1.775 2.029 -2.328 2.880 -1.759 2.013 -2.312 2.864 -1.759 2.013 -2.312 2.864 -1.724 1.966 -2.264 2.786 -1.705 1.947 -2.245 2.767 -1.705 1.947 -2.245 2.767 -1.724 1.966 -2.264 2.786 -1.724 1.966 -2.264 2.786 -1.705 1.947 -2.245 2.767 -1.705 1.947 -2.245 2.767 -1.689 1.931 -2.229 2.751 -1.689 1.931 -2.229 2.751 -2.272 2.509 -2.787 3.328 -2.253 2.490 -2.768 3.309 -2.253 2.490 -2.768 3.309 -2.272 2.509 -2.787 3.328 -2.272 2.509 -2.787 3.328 -2.253 2.490 -2.768 3.309 -2.253 2.490 -2.768 3.309 -2.237 2.474 -2.752 3.293 -2.237 2.474 -2.752 3.293 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-149 Table 1-81. EP3SL200 Column Pins Input Timing Parameters (Part 4 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V PCI-X tsu th tsu th -1.148 1.296 -1.476 1.789 -1.184 1.330 -1.476 1.789 -1.809 -1.777 -2.001 -1.933 -2.481 -1.777 2.031 2.726 2.010 2.778 2.258 3.112 2.176 2.999 2.723 3.542 2.010 2.778 -2.237 -2.273 -2.557 -2.476 -2.996 -2.273 -2.001 2.258 -2.557 3.112 -1.933 2.176 -2.476 2.999 -2.481 2.723 -2.996 3.542 ns ns ns ns GCLK PLL Table 1-82 lists the EP3SL200 row pins input timing parameters for single-ended I/O standards. Table 1-82. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.298 1.432 0.915 -0.638 -1.298 1.432 0.915 -0.638 -1.304 1.438 0.909 -0.632 -1.304 1.438 0.909 -0.632 -1.292 1.426 0.921 -0.644 -1.322 0.891 1.457 -1.312 -1.321 1.473 0.938 -0.643 -1.321 1.473 0.938 -0.643 -1.332 1.484 0.927 -0.632 -1.332 1.484 0.927 -0.632 -1.325 1.477 0.934 -0.639 -1.354 0.902 1.507 -1.343 -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 1.671 2.210 1.862 2.223 1.969 2.633 1.850 2.541 1.775 2.966 1.751 2.384 1.869 2.665 1.850 2.541 1.775 2.966 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 1.671 2.210 2.207 1.674 2.207 2.216 1.665 2.216 1.625 2.254 1.625 1.649 2.230 1.728 1.862 2.223 2.224 1.861 2.224 2.237 1.848 2.237 1.722 2.297 1.722 1.754 2.265 1.855 1.969 2.633 2.636 1.966 2.636 2.651 1.951 2.651 1.945 2.649 1.945 2.013 2.581 2.172 1.850 2.541 2.544 1.847 2.544 2.559 1.832 2.559 1.834 2.557 1.834 1.902 2.489 2.061 1.775 2.966 2.969 1.772 2.969 2.984 1.757 2.984 1.742 2.982 1.742 1.810 2.914 1.969 1.751 2.384 2.383 1.752 2.383 2.392 1.743 2.392 1.710 2.425 1.710 1.741 2.394 1.837 1.869 2.665 2.670 1.864 2.670 2.680 1.854 2.680 1.853 2.681 1.853 1.918 2.616 2.073 1.850 2.541 2.544 1.847 2.544 2.559 1.832 2.559 1.834 2.557 1.834 1.902 2.489 2.061 1.775 2.966 2.969 1.772 2.969 2.984 1.757 2.984 1.742 2.982 1.742 1.810 2.914 1.969 3.3-V LVCMOS GCLK PLL GCLK -1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715 -1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS -1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730 GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V -2.017 -2.051 -2.384 -2.307 -2.728 -2.173 -2.404 -2.307 -2.728 GCLK PLL -1.993 -2.019 -2.316 -2.239 -2.660 -2.142 -2.339 -2.239 -2.660 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-150 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-82. EP3SL200 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5 V tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 0.901 1.447 -1.252 0.961 1.387 -1.235 0.978 1.370 -1.235 0.978 1.370 -1.226 0.987 1.361 -1.226 0.987 1.361 -1.212 1.001 1.347 -1.226 0.987 1.361 -1.226 0.987 1.361 -1.212 1.001 1.347 -1.212 1.001 1.347 -1.203 1.010 1.338 -1.203 0.913 1.496 -1.290 0.966 1.443 -1.266 0.992 1.419 -1.266 0.992 1.419 -1.255 1.001 1.408 -1.255 1.001 1.408 -1.243 1.013 1.396 -1.255 1.001 1.408 -1.255 1.001 1.408 -1.243 1.013 1.396 -1.243 1.013 1.396 -1.231 1.025 1.384 -1.231 2.151 1.751 2.130 1.766 2.113 -1.876 1.766 2.113 1.766 2.113 2.164 1.957 2.128 2.422 2.171 2.431 2.330 2.052 2.339 2.755 1.977 2.764 2.298 1.855 2.280 2.461 2.071 2.463 2.330 2.052 2.339 2.755 1.977 2.764 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.914 -1.918 -2.157 -2.080 -2.501 -2.046 -2.184 -2.080 -2.501 GCLK PLL GCLK 1.2 V -1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497 2.137 1.882 1.882 2.415 2.174 2.174 2.323 2.064 2.064 2.747 1.973 1.973 2.264 1.869 1.869 2.451 2.080 2.080 2.323 2.064 2.064 2.747 1.973 1.973 GCLK PLL GCLK SSTL-2 CLASS I -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441 2.137 1.882 2.415 2.174 2.323 2.064 2.747 1.973 2.264 1.869 2.451 2.080 2.323 2.064 2.747 1.973 GCLK PLL GCLK -1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497 SSTL-2 CLASS II -1.876 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441 -1.302 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479 -1.863 2.101 1.766 2.113 1.766 2.113 -1.876 -1.302 2.101 1.781 -1.302 -1.311 2.092 1.790 -1.311 -1.311 2.127 1.892 1.892 2.397 2.192 2.192 2.305 2.082 2.082 2.729 1.991 1.991 2.253 1.880 1.880 2.434 2.097 2.097 2.305 2.082 2.082 2.729 1.991 1.991 GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497 2.137 1.882 2.415 2.174 2.323 2.064 2.747 1.973 2.264 1.869 2.451 2.080 2.323 2.064 2.747 1.973 -1.876 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479 SSTL-18 CLASS II GCLK PLL GCLK -1.863 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497 2.137 1.882 1.892 2.415 2.174 2.192 2.323 2.064 2.082 2.747 1.973 1.991 2.264 1.869 1.880 2.451 2.080 2.097 2.323 2.064 2.082 2.747 1.973 1.991 SSTL-15 CLASS I GCLK PLL GCLK -1.863 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441 -1.854 -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479 2.127 1.892 1.902 2.397 2.192 2.208 2.305 2.082 2.098 2.729 1.991 2.007 2.253 1.880 1.889 2.434 2.097 2.113 2.305 2.082 2.098 2.729 1.991 2.007 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL -1.854 -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-151 Table 1-82. EP3SL200 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.010 1.338 -1.304 1.438 0.909 -0.632 -1.304 1.438 0.909 -0.632 -1.298 1.432 0.915 -0.638 -1.298 1.432 0.915 -0.638 -1.304 1.438 0.909 -0.632 -1.304 1.438 1.025 1.384 -1.332 1.484 0.927 -0.632 -1.332 1.484 0.927 -0.632 -1.321 1.473 0.938 -0.643 -1.321 1.473 0.938 -0.643 -1.332 1.484 0.927 -0.632 -1.332 1.484 -1.969 -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475 1.674 2.207 -1.969 1.674 2.207 2.207 2.207 2.207 2.207 1.671 2.210 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463 2.117 1.902 2.381 2.208 2.289 2.098 2.713 2.007 2.244 1.889 2.418 2.113 2.289 2.098 2.713 2.007 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463 2.117 1.902 2.381 2.208 2.289 2.098 2.713 2.007 2.244 1.889 2.418 2.113 2.289 2.098 2.713 2.007 1.5-V HSTL CLASS II GCLK PLL GCLK -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463 1.862 2.223 1.969 2.633 1.850 2.541 1.775 2.966 1.751 2.384 1.869 2.665 1.850 2.541 1.775 2.966 1.2-V HSTL CLASS I GCLK PLL GCLK -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 1.2-V HSTL CLASS II -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 -1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712 1.671 2.210 2.207 1.674 2.207 2.216 1.862 2.223 2.224 1.861 2.224 2.237 1.969 2.633 2.636 1.966 2.636 2.651 1.850 2.541 2.544 1.847 2.544 2.559 1.775 2.966 2.969 1.772 2.969 2.984 1.751 2.384 2.383 1.752 2.383 2.392 1.869 2.665 2.670 1.864 2.670 2.680 1.850 2.541 2.544 1.847 2.544 2.559 1.775 2.966 2.969 1.772 2.969 2.984 GCLK PLL GCLK 3.0-V PCI -1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715 -1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715 GCLK PLL GCLK 3.0-V PCI-X GCLK PLL -1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-152 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-83 lists the EP3SL200 column pins output timing parameters for single-ended I/O standards. Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA 3.3-V LVTTL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.677 4.076 3.610 4.009 3.524 3.923 3.517 3.916 3.683 4.082 3.528 3.927 3.535 3.934 3.519 3.918 3.641 4.040 3.530 3.929 3.494 3.893 3.476 3.875 3.677 4.076 3.610 4.009 3.524 3.923 3.517 3.916 3.683 4.082 3.528 3.927 3.535 3.934 3.519 3.918 3.641 4.040 3.530 3.929 3.494 3.893 3.476 3.875 5.302 5.492 5.937 6.132 5.193 5.381 5.828 6.021 5.089 5.282 5.724 5.922 5.072 5.254 5.707 5.894 5.306 5.497 5.941 6.137 5.099 5.299 5.734 5.939 5.093 5.278 5.728 5.918 5.071 5.253 5.706 5.893 5.269 5.460 5.904 6.100 5.139 5.326 5.774 5.966 5.076 5.257 5.711 5.897 5.047 5.229 5.682 5.869 5.997 6.701 5.884 6.588 5.792 6.496 5.751 6.455 6.004 6.708 5.803 6.507 5.777 6.481 5.748 6.452 5.964 6.668 5.826 6.531 5.752 6.457 5.724 6.428 5.854 6.529 5.741 6.416 5.649 6.324 5.608 6.283 5.861 6.536 5.660 6.335 5.634 6.309 5.605 6.280 5.821 6.496 5.684 6.360 5.610 6.286 5.581 6.256 6.259 5.492 5.997 5.854 6.259 7.016 6.132 6.701 6.529 7.016 6.146 5.381 5.884 5.741 6.146 6.903 6.021 6.588 6.416 6.903 6.054 5.282 5.792 5.649 6.054 6.811 5.922 6.496 6.324 6.811 6.013 5.254 5.751 5.608 6.013 6.770 5.894 6.455 6.283 6.770 6.266 5.497 6.004 5.861 6.266 7.023 6.137 6.708 6.536 7.023 6.065 5.299 5.803 5.660 6.065 6.822 5.939 6.507 6.335 6.822 6.039 5.278 5.777 5.634 6.039 6.796 5.918 6.481 6.309 6.796 6.010 5.253 5.748 5.605 6.010 6.767 5.893 6.452 6.280 6.767 6.226 5.460 5.964 5.821 6.226 6.983 6.100 6.668 6.496 6.983 6.088 5.326 5.826 5.684 6.088 6.845 5.966 6.531 6.360 6.845 6.014 5.257 5.752 5.610 6.014 6.771 5.897 6.457 6.286 6.771 5.986 5.229 5.724 5.581 5.986 6.743 5.869 6.428 6.256 6.743 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-153 Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA 3.0-V LVCMOS tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.555 3.954 3.476 3.875 3.471 3.870 3.462 3.861 3.677 4.076 3.577 3.976 3.533 3.932 3.495 3.894 3.555 3.954 3.476 3.875 3.471 3.870 3.462 3.861 3.677 4.076 3.577 3.976 3.533 3.932 3.495 3.894 5.173 5.360 5.808 6.000 5.049 5.231 5.684 5.871 5.042 5.224 5.677 5.864 5.028 5.209 5.663 5.849 5.380 5.587 6.015 6.227 5.261 5.461 5.896 6.101 5.174 5.370 5.809 6.010 5.135 5.328 5.770 5.968 5.861 6.566 5.726 6.431 5.718 6.422 5.703 6.407 6.108 6.813 5.976 6.681 5.881 6.585 5.838 6.542 5.719 6.395 5.584 6.260 5.575 6.250 5.560 6.235 5.966 6.642 5.834 6.510 5.738 6.413 5.695 6.370 6.123 5.360 5.861 5.719 6.123 6.880 6.000 6.566 6.395 6.880 5.988 5.231 5.726 5.584 5.988 6.745 5.871 6.431 6.260 6.745 5.980 5.224 5.718 5.575 5.980 6.737 5.864 6.422 6.250 6.737 5.965 5.209 5.703 5.560 5.965 6.722 5.849 6.407 6.235 6.722 6.370 5.587 6.108 5.966 6.370 7.127 6.227 6.813 6.642 7.127 6.238 5.461 5.976 5.834 6.238 6.995 6.101 6.681 6.510 6.995 6.143 5.370 5.881 5.738 6.143 6.900 6.010 6.585 6.413 6.900 6.100 5.328 5.838 5.695 6.100 6.857 5.968 6.542 6.370 6.857 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-154 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.8 V tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.868 4.267 3.687 4.086 3.605 4.004 3.585 3.984 3.522 3.921 3.504 3.903 3.814 4.213 3.602 4.001 3.577 3.976 3.566 3.965 3.511 3.910 3.506 3.905 3.868 4.267 3.687 4.086 3.605 4.004 3.585 3.984 3.522 3.921 3.504 3.903 3.814 4.213 3.602 4.001 3.577 3.976 3.566 3.965 3.511 3.910 3.506 3.905 5.701 5.947 6.336 6.587 5.422 5.638 6.057 6.278 5.315 5.523 5.950 6.163 5.257 5.469 5.892 6.109 5.196 5.394 5.831 6.034 5.175 5.373 5.810 6.013 5.630 5.879 6.265 6.519 5.311 5.523 5.946 6.163 5.244 5.463 5.879 6.103 5.227 5.438 5.862 6.078 5.189 5.387 5.824 6.027 5.172 5.376 5.807 6.016 6.513 7.217 6.165 6.870 6.055 6.759 5.989 6.693 5.908 6.612 5.885 6.589 6.451 7.155 6.059 6.763 5.992 6.696 5.972 6.676 5.902 6.606 5.891 6.595 6.370 7.045 6.023 6.699 5.912 6.587 5.846 6.521 5.765 6.440 5.742 6.417 6.308 6.983 5.916 6.591 5.849 6.524 5.829 6.504 5.759 6.434 5.748 6.423 6.775 5.947 6.513 6.370 6.775 7.532 6.587 7.217 7.045 7.532 6.427 5.638 6.165 6.023 6.427 7.184 6.278 6.870 6.699 7.184 6.317 5.523 6.055 5.912 6.317 7.074 6.163 6.759 6.587 7.074 6.251 5.469 5.989 5.846 6.251 7.008 6.109 6.693 6.521 7.008 6.170 5.394 5.908 5.765 6.170 6.927 6.034 6.612 6.440 6.927 6.147 5.373 5.885 5.742 6.147 6.904 6.013 6.589 6.417 6.904 6.713 5.879 6.451 6.308 6.713 7.470 6.519 7.155 6.983 7.470 6.321 5.523 6.059 5.916 6.321 7.078 6.163 6.763 6.591 7.078 6.254 5.463 5.992 5.849 6.254 7.011 6.103 6.696 6.524 7.011 6.234 5.438 5.972 5.829 6.234 6.991 6.078 6.676 6.504 6.991 6.164 5.387 5.902 5.759 6.164 6.921 6.027 6.606 6.434 6.921 6.153 5.376 5.891 5.748 6.153 6.910 6.016 6.595 6.423 6.910 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-155 Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA 1.2 V tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.730 4.129 3.607 4.006 3.569 3.968 3.522 3.921 3.522 3.921 3.519 3.918 3.517 3.916 3.508 3.907 3.529 3.928 3.525 3.924 3.514 3.913 3.503 3.902 3.503 3.902 3.730 4.129 3.607 4.006 3.569 3.968 3.522 3.921 3.522 3.921 3.519 3.918 3.517 3.916 3.508 3.907 3.529 3.928 3.525 3.924 3.514 3.913 3.503 3.902 3.503 3.902 5.556 5.815 6.191 6.455 5.330 5.553 5.965 6.193 5.238 5.464 5.873 6.104 5.210 5.415 5.845 6.055 5.167 5.362 5.802 6.002 5.164 5.359 5.799 5.999 5.164 5.360 5.799 6.000 5.149 5.344 5.784 5.984 5.179 5.376 5.814 6.016 5.177 5.374 5.812 6.014 5.167 5.365 5.802 6.005 5.154 5.352 5.789 5.992 5.154 5.352 5.789 5.992 6.395 7.099 6.109 6.813 5.996 6.700 5.940 6.644 5.871 6.575 5.867 6.571 5.868 6.572 5.853 6.557 5.887 6.591 5.885 6.589 5.876 6.580 5.863 6.567 5.863 6.567 6.252 6.927 5.966 6.641 5.853 6.528 5.797 6.472 5.728 6.403 5.724 6.399 5.725 6.400 5.710 6.385 5.744 6.419 5.742 6.417 5.733 6.408 5.720 6.395 5.720 6.395 6.657 5.815 6.395 6.252 6.657 7.414 6.455 7.099 6.927 7.414 6.371 5.553 6.109 5.966 6.371 7.128 6.193 6.813 6.641 7.128 6.258 5.464 5.996 5.853 6.258 7.015 6.104 6.700 6.528 7.015 6.202 5.415 5.940 5.797 6.202 6.959 6.055 6.644 6.472 6.959 6.133 5.362 5.871 5.728 6.133 6.890 6.002 6.575 6.403 6.890 6.129 5.359 5.867 5.724 6.129 6.886 5.999 6.571 6.399 6.886 6.130 5.360 5.868 5.725 6.130 6.887 6.000 6.572 6.400 6.887 6.115 5.344 5.853 5.710 6.115 6.872 5.984 6.557 6.385 6.872 6.149 5.376 5.887 5.744 6.149 6.906 6.016 6.591 6.419 6.906 6.147 5.374 5.885 5.742 6.147 6.904 6.014 6.589 6.417 6.904 6.138 5.365 5.876 5.733 6.138 6.895 6.005 6.580 6.408 6.895 6.125 5.352 5.863 5.720 6.125 6.882 5.992 6.567 6.395 6.882 6.125 5.352 5.863 5.720 6.125 6.882 5.992 6.567 6.395 6.882 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-156 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA SSTL-18 CLASS II tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.509 3.908 3.512 3.911 3.533 3.932 3.519 3.918 3.508 3.907 3.507 3.906 3.504 3.903 3.506 3.905 3.509 3.908 3.509 3.908 3.512 3.911 3.533 3.932 3.519 3.918 3.508 3.907 3.507 3.906 3.504 3.903 3.506 3.905 3.509 3.908 5.153 5.349 5.788 5.989 5.161 5.358 5.796 5.998 5.188 5.388 5.823 6.028 5.178 5.378 5.813 6.018 5.164 5.364 5.799 6.004 5.167 5.367 5.802 6.007 5.162 5.362 5.797 6.002 5.151 5.348 5.786 5.988 5.158 5.357 5.793 5.997 5.858 6.562 5.870 6.574 5.900 6.604 5.891 6.595 5.877 6.581 5.881 6.585 5.875 6.579 5.858 6.562 5.869 6.573 5.715 6.390 5.727 6.402 5.757 6.432 5.748 6.423 5.734 6.409 5.738 6.413 5.732 6.407 5.715 6.390 5.726 6.401 6.120 5.349 5.858 5.715 6.120 6.877 5.989 6.562 6.390 6.877 6.132 5.358 5.870 5.727 6.132 6.889 5.998 6.574 6.402 6.889 6.162 5.388 5.900 5.757 6.162 6.919 6.028 6.604 6.432 6.919 6.153 5.378 5.891 5.748 6.153 6.910 6.018 6.595 6.423 6.910 6.139 5.364 5.877 5.734 6.139 6.896 6.004 6.581 6.409 6.896 6.143 5.367 5.881 5.738 6.143 6.900 6.007 6.585 6.413 6.900 6.137 5.362 5.875 5.732 6.137 6.894 6.002 6.579 6.407 6.894 6.120 5.348 5.858 5.715 6.120 6.877 5.988 6.562 6.390 6.877 6.131 5.357 5.869 5.726 6.131 6.888 5.997 6.573 6.401 6.888 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 16mA 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-157 Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.516 3.915 3.509 3.908 3.501 3.900 3.504 3.903 3.501 3.900 3.509 3.908 3.521 3.920 3.517 3.916 3.513 3.912 3.506 3.905 3.507 3.906 3.505 3.904 3.516 3.915 3.509 3.908 3.501 3.900 3.504 3.903 3.501 3.900 3.509 3.908 3.521 3.920 3.517 3.916 3.513 3.912 3.506 3.905 3.507 3.906 3.505 3.904 5.153 5.348 5.788 5.988 5.151 5.346 5.786 5.986 5.143 5.339 5.778 5.979 5.146 5.342 5.781 5.982 5.149 5.346 5.784 5.986 5.148 5.343 5.783 5.983 5.161 5.358 5.796 5.998 5.162 5.359 5.797 5.999 5.158 5.355 5.793 5.995 5.151 5.348 5.786 5.988 5.158 5.356 5.793 5.996 5.139 5.334 5.774 5.974 5.856 6.560 5.855 6.559 5.848 6.552 5.852 6.556 5.856 6.560 5.852 6.556 5.867 6.571 5.870 6.574 5.865 6.569 5.858 6.562 5.868 6.572 5.842 6.546 5.713 6.388 5.712 6.387 5.705 6.380 5.709 6.384 5.713 6.388 5.709 6.384 5.724 6.399 5.727 6.402 5.722 6.397 5.715 6.390 5.725 6.400 5.699 6.374 6.118 5.348 5.856 5.713 6.118 6.875 5.988 6.560 6.388 6.875 6.117 5.346 5.855 5.712 6.117 6.874 5.986 6.559 6.387 6.874 6.110 5.339 5.848 5.705 6.110 6.867 5.979 6.552 6.380 6.867 6.114 5.342 5.852 5.709 6.114 6.871 5.982 6.556 6.384 6.871 6.118 5.346 5.856 5.713 6.118 6.875 5.986 6.560 6.388 6.875 6.114 5.343 5.852 5.709 6.114 6.871 5.983 6.556 6.384 6.871 6.129 5.358 5.867 5.724 6.129 6.886 5.998 6.571 6.399 6.886 6.132 5.359 5.870 5.727 6.132 6.889 5.999 6.574 6.402 6.889 6.127 5.355 5.865 5.722 6.127 6.884 5.995 6.569 6.397 6.884 6.120 5.348 5.858 5.715 6.120 6.877 5.988 6.562 6.390 6.877 6.130 5.356 5.868 5.725 6.130 6.887 5.996 6.572 6.400 6.887 6.104 5.334 5.842 5.699 6.104 6.861 5.974 6.546 6.374 6.861 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-158 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-83. EP3SL200 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 3.0-V PCI tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.524 3.923 3.516 3.915 3.517 3.916 3.506 3.905 3.506 3.905 3.527 3.926 3.630 4.029 3.630 4.029 3.524 3.923 3.516 3.915 3.517 3.916 3.506 3.905 3.506 3.905 3.527 3.926 3.630 4.029 3.630 4.029 5.175 5.375 5.810 6.015 5.166 5.366 5.801 6.006 5.174 5.374 5.809 6.014 5.161 5.361 5.796 6.001 5.161 5.361 5.796 6.001 5.177 5.376 5.812 6.016 5.222 5.410 5.857 6.050 5.222 5.410 5.857 6.050 5.888 6.592 5.879 6.583 5.888 6.592 5.874 6.578 5.875 6.579 5.888 6.592 5.913 6.617 5.913 6.617 5.745 6.420 5.736 6.411 5.745 6.420 5.731 6.406 5.732 6.407 5.745 6.420 5.770 6.445 5.770 6.445 6.150 5.375 5.888 5.745 6.150 6.907 6.015 6.592 6.420 6.907 6.141 5.366 5.879 5.736 6.141 6.898 6.006 6.583 6.411 6.898 6.150 5.374 5.888 5.745 6.150 6.907 6.014 6.592 6.420 6.907 6.136 5.361 5.874 5.731 6.136 6.893 6.001 6.578 6.406 6.893 6.137 5.361 5.875 5.732 6.137 6.894 6.001 6.579 6.407 6.894 6.150 5.376 5.888 5.745 6.150 6.907 6.016 6.592 6.420 6.907 6.175 5.410 5.913 5.770 6.175 6.932 6.050 6.617 6.445 6.932 6.175 5.410 5.913 5.770 6.175 6.932 6.050 6.617 6.445 6.932 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 1.2-V HSTL CLASS II -- GCLK PLL GCLK GCLK PLL 3.0-V PCI-X -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-159 Table 1-84 lists the EP3SL200 row pins output timing parameters for single-ended I/O standards. Table 1-84. EP3SL200 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.639 1.551 3.548 1.468 3.469 1.389 3.649 1.561 3.473 1.393 3.593 1.505 3.474 1.394 3.437 1.357 3.507 1.419 3.424 1.344 3.619 1.531 3.516 1.436 3.463 1.379 3.902 1.768 3.813 1.663 3.724 1.560 3.906 1.772 3.728 1.564 3.848 1.714 3.733 1.587 3.695 1.536 3.767 1.633 3.679 1.515 3.884 1.750 3.785 1.651 3.735 1.575 5.663 5.916 6.397 6.238 6.709 6.053 6.634 6.238 6.709 2.210 2.317 2.505 2.518 2.444 2.409 2.649 2.518 2.444 5.533 5.778 6.283 6.124 6.565 5.912 6.485 6.124 6.565 2.080 2.179 2.361 2.374 2.300 2.268 2.500 2.374 2.300 5.414 5.655 6.187 6.028 6.437 5.785 6.353 6.028 6.437 1.961 2.056 2.233 2.246 2.172 2.147 2.368 2.246 2.172 5.671 5.921 6.406 6.247 6.714 6.059 6.639 6.247 6.714 2.218 2.322 2.510 2.523 2.449 2.415 2.654 2.523 2.449 5.420 5.661 6.197 6.038 6.443 5.794 6.360 6.038 6.443 1.967 2.062 2.239 2.252 2.178 2.159 2.375 2.252 2.178 5.615 5.869 6.363 6.204 6.666 6.010 6.592 6.204 6.666 2.162 2.270 2.462 2.475 2.401 2.366 2.607 2.475 2.401 5.463 5.710 6.218 6.059 6.502 5.848 6.428 6.059 6.502 2.010 2.111 2.298 2.311 2.237 2.204 2.443 2.311 2.237 5.395 5.627 6.148 5.989 6.414 5.762 6.335 5.989 6.414 1.928 2.028 2.210 2.223 2.149 2.118 2.350 2.223 2.149 5.510 5.762 6.254 6.095 6.555 5.902 6.481 6.095 6.555 2.057 2.163 2.351 2.364 2.290 2.258 2.496 2.364 2.290 5.368 5.588 6.120 5.961 6.375 5.722 6.295 5.961 6.375 1.893 1.989 2.171 2.184 2.110 2.087 2.310 2.184 2.110 5.748 6.023 6.508 6.349 6.838 6.170 6.771 6.349 6.838 2.295 2.424 2.634 2.647 2.573 2.526 2.786 2.647 2.573 5.593 5.860 6.366 6.207 6.668 6.003 6.597 6.207 6.668 2.140 2.261 2.464 2.477 2.403 2.359 2.612 2.477 2.403 5.492 5.741 6.275 6.116 6.542 5.880 6.467 6.116 6.542 2.029 2.142 2.338 2.351 2.277 2.236 2.482 2.351 2.277 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVTTL 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-160 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-84. EP3SL200 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.863 1.795 3.638 1.570 3.573 1.505 3.521 1.445 3.774 1.706 3.537 1.464 3.510 1.437 3.496 1.428 3.717 1.649 3.542 1.469 3.463 1.383 3.458 1.378 3.449 1.369 4.170 2.018 3.968 1.816 3.866 1.714 3.792 1.640 4.088 1.936 3.831 1.679 3.783 1.631 3.774 1.622 4.013 1.861 3.824 1.672 3.723 1.561 3.719 1.555 3.708 1.544 6.174 6.451 7.093 6.933 7.278 6.617 7.250 6.933 7.278 2.703 2.852 3.121 3.130 3.066 2.995 3.095 3.130 3.066 5.848 6.083 6.688 6.528 6.873 6.252 6.844 6.528 6.873 2.377 2.484 2.716 2.725 2.661 2.630 2.734 2.725 2.661 5.694 5.933 6.529 6.369 6.714 6.084 6.671 6.369 6.714 2.223 2.334 2.557 2.566 2.502 2.462 2.628 2.566 2.502 5.617 5.840 6.433 6.273 6.618 5.989 6.577 6.273 6.618 2.146 2.241 2.461 2.470 2.406 2.367 2.556 2.470 2.406 6.084 6.365 7.021 6.861 7.206 6.524 7.174 6.861 7.206 2.613 2.766 3.049 3.058 2.994 2.902 3.030 3.058 2.994 5.679 5.928 6.530 6.370 6.715 6.078 6.670 6.370 6.715 2.208 2.329 2.558 2.567 2.503 2.456 2.629 2.567 2.503 5.606 5.832 6.424 6.264 6.609 5.980 6.565 6.264 6.609 2.135 2.233 2.452 2.461 2.397 2.358 2.556 2.461 2.397 5.584 5.814 6.405 6.245 6.590 5.962 6.543 6.245 6.590 2.113 2.215 2.433 2.442 2.378 2.340 2.537 2.442 2.378 5.994 6.279 6.946 6.786 7.131 6.436 7.090 6.786 7.131 2.523 2.680 2.974 2.983 2.919 2.814 2.961 2.983 2.919 5.701 5.956 6.571 6.411 6.756 6.103 6.712 6.411 6.756 2.230 2.357 2.599 2.608 2.544 2.481 2.673 2.608 2.544 5.485 5.713 6.265 6.106 6.510 5.855 6.429 6.106 6.510 2.006 2.114 2.306 2.319 2.245 2.220 2.444 2.319 2.245 5.482 5.705 6.263 6.104 6.502 5.854 6.422 6.104 6.502 1.999 2.106 2.298 2.311 2.237 2.219 2.437 2.311 2.237 5.467 5.680 6.246 6.087 6.475 5.837 6.395 6.087 6.475 1.984 2.081 2.271 2.284 2.210 2.202 2.413 2.284 2.210 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-161 Table 1-84. EP3SL200 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.474 1.406 3.465 1.391 3.454 1.380 3.443 1.363 3.443 1.363 3.451 1.371 3.452 1.372 3.473 1.402 3.459 1.379 3.448 1.368 3.748 1.596 3.734 1.582 3.722 1.570 3.699 1.547 3.698 1.546 3.707 1.555 3.702 1.550 3.744 1.592 3.722 1.570 3.705 1.553 5.512 5.727 6.306 6.146 6.491 5.870 6.440 6.146 6.491 2.041 2.128 2.334 2.343 2.279 2.248 2.447 2.343 2.279 5.509 5.725 6.304 6.144 6.489 5.868 6.438 6.144 6.489 2.038 2.126 2.332 2.341 2.277 2.246 2.445 2.341 2.277 5.492 5.708 6.287 6.127 6.472 5.857 6.422 6.127 6.472 2.021 2.109 2.315 2.324 2.260 2.229 2.436 2.324 2.260 5.476 5.692 6.272 6.112 6.457 5.845 6.407 6.112 6.457 2.005 2.093 2.300 2.309 2.245 2.214 2.424 2.309 2.245 5.475 5.691 6.271 6.111 6.456 5.844 6.406 6.111 6.456 2.004 2.092 2.299 2.308 2.244 2.213 2.424 2.308 2.244 5.473 5.687 6.265 6.105 6.450 5.840 6.399 6.105 6.450 2.002 2.088 2.293 2.302 2.238 2.208 2.418 2.302 2.238 5.472 5.688 6.267 6.107 6.458 5.849 6.408 6.107 6.458 2.001 2.093 2.295 2.304 2.240 2.214 2.429 2.304 2.240 5.523 5.741 6.323 6.163 6.508 5.883 6.456 6.163 6.508 2.052 2.142 2.351 2.360 2.296 2.261 2.459 2.360 2.296 5.505 5.724 6.306 6.146 6.491 5.869 6.440 6.146 6.491 2.034 2.125 2.334 2.343 2.279 2.245 2.450 2.343 2.279 5.488 5.706 6.288 6.128 6.473 5.856 6.423 6.128 6.473 2.017 2.107 2.316 2.325 2.261 2.227 2.437 2.325 2.261 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-162 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-84. EP3SL200 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.458 1.381 3.451 1.371 3.442 1.362 3.445 1.365 3.441 1.361 3.449 1.369 3.464 1.388 3.458 1.378 3.454 1.374 3.466 1.387 3.457 1.377 3.456 1.376 3.569 1.489 3.569 1.489 3.720 1.568 3.708 1.556 3.696 1.544 3.698 1.546 3.693 1.541 3.697 1.545 3.727 1.575 3.717 1.565 3.712 1.560 3.726 1.574 3.714 1.562 3.712 1.560 3.829 1.665 3.829 1.665 5.479 5.692 6.268 6.108 6.453 5.839 6.402 6.108 6.453 2.008 2.093 2.296 2.305 2.241 2.212 2.415 2.305 2.241 5.470 5.684 6.260 6.100 6.445 5.838 6.395 6.100 6.445 1.999 2.085 2.288 2.297 2.233 2.204 2.415 2.297 2.233 5.462 5.675 6.252 6.092 6.438 5.831 6.387 6.092 6.438 1.991 2.076 2.280 2.289 2.225 2.196 2.408 2.289 2.225 5.464 5.678 6.255 6.095 6.442 5.834 6.390 6.095 6.442 1.993 2.079 2.283 2.292 2.228 2.199 2.411 2.292 2.228 5.462 5.677 6.255 6.095 6.445 5.837 6.395 6.095 6.445 1.991 2.081 2.283 2.292 2.228 2.202 2.416 2.292 2.228 5.457 5.669 6.246 6.086 6.441 5.833 6.389 6.086 6.441 1.986 2.078 2.274 2.283 2.219 2.198 2.410 2.283 2.219 5.490 5.705 6.283 6.123 6.468 5.848 6.416 6.123 6.468 2.019 2.106 2.311 2.320 2.256 2.224 2.426 2.320 2.256 5.486 5.701 6.279 6.119 6.464 5.850 6.413 6.119 6.464 2.015 2.102 2.307 2.316 2.252 2.221 2.429 2.316 2.252 5.480 5.695 6.273 6.113 6.458 5.845 6.407 6.113 6.458 2.009 2.096 2.301 2.310 2.246 2.215 2.423 2.310 2.246 5.501 5.719 6.301 6.141 6.486 5.864 6.433 6.141 6.486 2.030 2.120 2.329 2.338 2.274 2.238 2.445 2.338 2.274 5.490 5.707 6.289 6.129 6.474 5.855 6.422 6.129 6.474 2.019 2.108 2.317 2.326 2.262 2.227 2.436 2.326 2.262 5.494 5.712 6.295 6.135 6.480 5.864 6.429 6.135 6.480 2.023 2.113 2.323 2.332 2.268 2.233 2.446 2.332 2.268 5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519 2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267 5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519 2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-163 Table 1-85 through Table 1-88 list the maximum I/O timing parameters for EP3SL200 devices for differential I/O standards. Table 1-85 lists the EP3SL200 column pins input timing parameters for differential I/O standards. Table 1-85. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -1.153 1.289 1.103 -0.824 -1.153 1.289 1.103 -0.824 -1.161 1.297 1.095 -0.816 -1.161 1.297 1.095 -0.816 -1.173 1.309 1.083 -0.804 -1.173 1.309 1.083 -0.804 -1.161 1.297 1.095 -0.816 -1.161 1.297 1.095 -0.816 -1.221 1.376 1.122 -0.821 -1.221 1.376 1.122 -0.821 -1.233 1.388 1.110 -0.809 -1.233 1.388 1.110 -0.809 -1.244 1.399 1.099 -0.798 -1.244 1.399 1.099 -0.798 -1.233 1.388 1.110 -0.809 -1.233 1.388 1.110 -0.809 -1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.114 1.882 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.114 1.882 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.124 1.872 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.124 1.872 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.2-V HSTL CLASS I -1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.133 1.863 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.2-V HSTL CLASS II -1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.133 1.863 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.5-V HSTL CLASS I -1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.124 1.872 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.5-V HSTL CLASS II -1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.124 1.872 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.8-V HSTL CLASS I -1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-164 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-85. EP3SL200 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.173 1.309 1.083 -0.804 -1.173 1.309 1.083 -0.804 -1.180 1.316 1.076 -0.797 -1.180 1.316 1.076 -0.797 -1.153 1.289 1.103 -0.824 -1.153 1.289 1.103 -0.824 -1.161 1.297 1.095 -0.816 -1.244 1.399 1.099 -0.798 -1.244 1.399 1.099 -0.798 -1.250 1.405 1.093 -0.792 -1.250 1.405 1.093 -0.792 -1.221 1.376 1.122 -0.821 -1.221 1.376 1.122 -0.821 -1.233 1.388 1.110 -0.809 -1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.133 1.863 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.133 1.863 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.5-V SSTL CLASS I -1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 2.146 1.851 2.180 1.959 2.368 2.172 2.275 2.062 2.750 2.062 2.206 1.972 2.388 2.189 2.275 2.062 2.750 2.062 DIFFERENTIAL 1.5-V SSTL CLASS II -1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 -1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 2.146 1.851 2.180 1.959 2.368 2.172 2.275 2.062 2.750 2.062 2.206 1.972 2.388 2.189 2.275 2.062 2.750 2.062 DIFFERENTIAL 1.8-V SSTL CLASS I -1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 -1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.114 1.882 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 DIFFERENTIAL 1.8-V SSTL CLASS II -1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.114 1.882 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 DIFFERENTIAL 2.5-V SSTL CLASS I -1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.124 1.872 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 2.5-V SSTL CLASS II -1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-165 Table 1-86 lists the EP3SL200 row pins input timing parameters for differential I/O standards. Table 1-86. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK LVDS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.332 1.476 0.869 -0.581 -1.332 1.476 0.869 -0.581 -1.332 1.476 0.869 -0.581 -1.137 1.274 1.064 -0.783 -1.137 1.274 1.064 -0.783 -1.146 1.283 1.055 -0.774 -1.146 1.283 1.055 -0.774 -1.401 1.563 0.886 -0.578 -1.401 1.563 0.886 -0.578 -1.401 1.563 0.886 -0.578 -1.216 1.369 1.071 -0.772 -1.216 1.369 1.071 -0.772 -1.228 1.381 1.059 -0.760 -1.228 1.381 1.059 -0.760 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK MINI-LVDS -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 GCLK PLL GCLK RSDS -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 2.088 1.866 2.122 1.981 2.297 2.216 2.206 2.098 2.656 2.118 2.156 1.985 2.330 2.221 2.206 2.098 2.656 2.118 DIFFERENTIAL 1.2-V HSTL CLASS I -1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 -1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 2.088 1.866 2.122 1.981 2.297 2.216 2.206 2.098 2.656 2.118 2.156 1.985 2.330 2.221 2.206 2.098 2.656 2.118 -1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 DIFFERENTIAL 1.5-V HSTL CLASS I -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-166 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-86. EP3SL200 Row Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.160 1.297 1.041 -0.760 -1.160 1.297 1.041 -0.760 -1.146 1.283 1.055 -0.774 -1.146 1.283 1.055 -0.774 -1.160 1.297 1.041 -0.760 -1.160 1.297 1.041 -0.760 -1.169 1.306 1.032 -0.751 -1.169 1.306 1.032 -0.751 -1.240 1.393 1.047 -0.748 -1.240 1.393 1.047 -0.748 -1.228 1.381 1.059 -0.760 -1.228 1.381 1.059 -0.760 -1.240 1.393 1.047 -0.748 -1.240 1.393 1.047 -0.748 -1.249 1.402 1.038 -0.739 -1.249 1.402 1.038 -0.739 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS I -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 DIFFERENTIAL 1.5-V SSTL CLASS I -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 DIFFERENTIAL 1.8-V SSTL CLASS I -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 2.121 1.829 2.156 1.945 2.341 2.171 2.250 2.052 2.701 2.073 2.186 1.954 2.369 2.182 2.250 2.052 2.701 2.073 DIFFERENTIAL 2.5-V SSTL CLASS I -1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 -1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 2.121 1.829 2.156 1.945 2.341 2.171 2.250 2.052 2.701 2.073 2.186 1.954 2.369 2.182 2.250 2.052 2.701 2.073 -1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-167 Table 1-87 lists the EP3SL200 column pins output timing parameters for differential I/O standards. Table 1-87. EP3SL200 Column Pins output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.479 3.475 3.479 3.475 3.479 3.475 3.506 3.496 3.496 3.489 3.488 3.510 3.500 3.495 3.493 3.485 3.486 3.485 3.497 3.493 3.483 3.481 3.481 3.485 3.750 3.753 3.750 3.753 3.750 3.753 3.783 3.773 3.773 3.767 3.765 3.787 3.776 3.772 3.770 3.761 3.763 3.760 3.773 3.770 3.759 3.757 3.758 3.761 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 5.567 5.779 6.344 6.180 6.587 5.923 6.487 6.180 6.587 5.570 5.783 6.348 6.184 6.591 5.928 6.492 6.184 6.591 5.563 5.777 6.342 6.178 6.585 5.921 6.486 6.178 6.585 5.560 5.774 6.339 6.175 6.582 5.918 6.482 6.175 6.582 5.581 5.794 6.358 6.194 6.601 5.938 6.502 6.194 6.601 5.560 5.771 6.333 6.169 6.576 5.914 6.475 6.169 6.576 5.560 5.771 6.334 6.170 6.577 5.915 6.477 6.170 6.577 5.559 5.770 6.332 6.168 6.575 5.914 6.476 6.168 6.575 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.555 5.767 6.331 6.167 6.574 5.912 6.475 6.167 6.574 5.538 5.748 6.309 6.145 6.552 5.891 6.451 6.145 6.552 5.556 5.766 6.327 6.163 6.570 5.910 6.470 6.163 6.570 5.557 5.768 6.331 6.167 6.574 5.912 6.474 6.167 6.574 5.546 5.757 6.319 6.155 6.562 5.901 6.462 6.155 6.562 5.544 5.754 6.317 6.153 6.560 5.899 6.460 6.153 6.560 5.547 5.759 6.322 6.158 6.565 5.903 6.466 6.158 6.565 5.544 5.754 6.316 6.152 6.559 5.898 6.459 6.152 6.559 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-168 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-87. EP3SL200 Column Pins output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.511 3.497 3.485 3.485 3.481 3.485 3.486 3.514 3.503 3.498 3.484 3.482 3.486 3.486 3.502 3.502 3.492 3.485 3.479 3.475 3.479 3.475 3.479 3.475 3.790 3.776 3.763 3.763 3.759 3.761 3.763 3.793 3.781 3.777 3.762 3.760 3.762 3.763 3.780 3.780 3.770 3.762 3.750 3.753 3.750 3.753 3.750 3.753 5.589 5.802 6.366 6.202 6.609 5.946 6.509 6.202 6.609 5.577 5.791 6.356 6.192 6.599 5.936 6.500 6.192 6.599 5.560 5.773 6.338 6.174 6.581 5.918 6.482 6.174 6.581 5.563 5.777 6.342 6.178 6.585 5.922 6.487 6.178 6.585 5.556 5.769 6.335 6.171 6.578 5.915 6.479 6.171 6.578 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.557 5.770 6.334 6.170 6.577 5.914 6.478 6.170 6.577 5.588 5.800 6.364 6.200 6.607 5.945 6.507 6.200 6.607 5.576 5.788 6.352 6.188 6.595 5.933 6.495 6.188 6.595 5.576 5.789 6.353 6.189 6.596 5.934 6.497 6.189 6.596 5.558 5.770 6.334 6.170 6.577 5.915 6.479 6.170 6.577 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.562 5.773 6.336 6.172 6.579 5.918 6.480 6.172 6.579 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-169 Table 1-87. EP3SL200 Column Pins output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.506 3.496 3.496 3.489 3.488 3.510 3.500 3.495 3.493 3.485 3.486 3.485 3.497 3.493 3.483 3.481 3.481 3.485 3.511 3.497 3.485 3.485 3.481 3.485 3.486 3.514 3.503 3.498 3.783 3.773 3.773 3.767 3.765 3.787 3.776 3.772 3.770 3.761 3.763 3.760 3.773 3.770 3.759 3.757 3.758 3.761 3.790 3.776 3.763 3.763 3.759 3.761 3.763 3.793 3.781 3.777 5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 5.567 5.779 6.344 6.180 6.587 5.923 6.487 6.180 6.587 5.570 5.783 6.348 6.184 6.591 5.928 6.492 6.184 6.591 5.563 5.777 6.342 6.178 6.585 5.921 6.486 6.178 6.585 5.560 5.774 6.339 6.175 6.582 5.918 6.482 6.175 6.582 5.581 5.794 6.358 6.194 6.601 5.938 6.502 6.194 6.601 5.560 5.771 6.333 6.169 6.576 5.914 6.475 6.169 6.576 5.560 5.771 6.334 6.170 6.577 5.915 6.477 6.170 6.577 5.559 5.770 6.332 6.168 6.575 5.914 6.476 6.168 6.575 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.555 5.767 6.331 6.167 6.574 5.912 6.475 6.167 6.574 5.538 5.748 6.309 6.145 6.552 5.891 6.451 6.145 6.552 5.556 5.766 6.327 6.163 6.570 5.910 6.470 6.163 6.570 5.557 5.768 6.331 6.167 6.574 5.912 6.474 6.167 6.574 5.546 5.757 6.319 6.155 6.562 5.901 6.462 6.155 6.562 5.544 5.754 6.317 6.153 6.560 5.899 6.460 6.153 6.560 5.547 5.759 6.322 6.158 6.565 5.903 6.466 6.158 6.565 5.544 5.754 6.316 6.152 6.559 5.898 6.459 6.152 6.559 5.589 5.802 6.366 6.202 6.609 5.946 6.509 6.202 6.609 5.577 5.791 6.356 6.192 6.599 5.936 6.500 6.192 6.599 5.560 5.773 6.338 6.174 6.581 5.918 6.482 6.174 6.581 5.563 5.777 6.342 6.178 6.585 5.922 6.487 6.178 6.585 5.556 5.769 6.335 6.171 6.578 5.915 6.479 6.171 6.578 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.557 5.770 6.334 6.170 6.577 5.914 6.478 6.170 6.577 5.588 5.800 6.364 6.200 6.607 5.945 6.507 6.200 6.607 5.576 5.788 6.352 6.188 6.595 5.933 6.495 6.188 6.595 5.576 5.789 6.353 6.189 6.596 5.934 6.497 6.189 6.596 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-170 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-87. EP3SL200 Column Pins output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco 3.484 3.482 3.486 3.486 3.502 3.502 3.492 3.485 3.762 3.760 3.762 3.763 3.780 3.780 3.770 3.762 5.558 5.770 6.334 6.170 6.577 5.915 6.479 6.170 6.577 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.562 5.773 6.336 6.172 6.579 5.918 6.480 6.172 6.579 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-171 Table 1-88 lists the EP3SL200 row pins output timing parameters for differential I/O standards. Table 1-88. EP3SL200 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.152 3.536 3.518 3.152 3.536 3.518 3.152 3.536 3.518 3.562 3.548 3.544 3.560 3.549 3.546 3.557 3.547 3.533 3.530 3.527 3.528 3.577 3.553 3.535 3.376 3.812 3.802 3.376 3.812 3.802 3.376 3.812 3.802 3.845 3.831 3.827 3.842 3.832 3.829 3.839 3.830 3.816 3.812 3.810 3.810 3.863 3.839 3.820 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 5.657 5.871 6.443 6.276 6.655 6.023 6.597 6.276 6.655 5.642 5.856 6.429 6.262 6.641 6.008 6.582 6.262 6.641 5.638 5.852 6.425 6.258 6.637 6.004 6.578 6.258 6.637 5.639 5.855 6.428 6.261 6.640 6.007 6.582 6.261 6.640 5.629 5.843 6.415 6.248 6.627 5.994 6.568 6.248 6.627 5.700 5.916 6.491 6.324 6.703 6.068 6.644 6.324 6.703 5.682 5.899 6.474 6.307 6.686 6.051 6.629 6.307 6.686 5.660 5.877 6.452 6.285 6.664 6.029 6.607 6.285 6.664 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-172 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-88. EP3SL200 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.581 3.566 3.555 3.535 3.532 3.537 3.530 3.568 3.550 3.536 3.152 3.536 3.518 3.152 3.536 3.518 3.152 3.536 3.518 3.562 3.548 3.544 3.560 3.549 3.866 3.851 3.840 3.820 3.816 3.820 3.813 3.852 3.835 3.819 3.376 3.812 3.802 3.376 3.812 3.802 3.376 3.812 3.802 3.845 3.831 3.827 3.842 3.832 5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 5.686 5.901 6.475 6.308 6.687 6.053 6.629 6.308 6.687 5.681 5.898 6.472 6.305 6.684 6.050 6.627 6.305 6.684 5.658 5.874 6.449 6.282 6.661 6.027 6.603 6.282 6.661 5.654 5.871 6.445 6.278 6.657 6.023 6.600 6.278 6.657 5.645 5.859 6.431 6.264 6.643 6.010 6.584 6.264 6.643 5.644 5.860 6.434 6.267 6.646 6.013 6.589 6.267 6.646 5.682 5.897 6.470 6.303 6.682 6.049 6.624 6.303 6.682 5.667 5.882 6.455 6.288 6.667 6.034 6.609 6.288 6.667 5.644 5.858 6.430 6.263 6.642 6.010 6.584 6.263 6.642 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA 8mA DIFFERENTIAL 1.8-V HSTL CLASS I 10mA 12mA 16mA 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-173 Table 1-88. EP3SL200 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.546 3.557 3.547 3.533 3.530 3.527 3.528 3.577 3.553 3.535 3.581 3.566 3.555 3.535 3.532 3.537 3.530 3.568 3.550 3.536 3.829 3.839 3.830 3.816 3.812 3.810 3.810 3.863 3.839 3.820 3.866 3.851 3.840 3.820 3.816 3.820 3.813 3.852 3.835 3.819 5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 5.657 5.871 6.443 6.276 6.655 6.023 6.597 6.276 6.655 5.642 5.856 6.429 6.262 6.641 6.008 6.582 6.262 6.641 5.638 5.852 6.425 6.258 6.637 6.004 6.578 6.258 6.637 5.639 5.855 6.428 6.261 6.640 6.007 6.582 6.261 6.640 5.629 5.843 6.415 6.248 6.627 5.994 6.568 6.248 6.627 5.700 5.916 6.491 6.324 6.703 6.068 6.644 6.324 6.703 5.682 5.899 6.474 6.307 6.686 6.051 6.629 6.307 6.686 5.660 5.877 6.452 6.285 6.664 6.029 6.607 6.285 6.664 5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 5.686 5.901 6.475 6.308 6.687 6.053 6.629 6.308 6.687 5.681 5.898 6.472 6.305 6.684 6.050 6.627 6.305 6.684 5.658 5.874 6.449 6.282 6.661 6.027 6.603 6.282 6.661 5.654 5.871 6.445 6.278 6.657 6.023 6.600 6.278 6.657 5.645 5.859 6.431 6.264 6.643 6.010 6.584 6.264 6.643 5.644 5.860 6.434 6.267 6.646 6.013 6.589 6.267 6.646 5.682 5.897 6.470 6.303 6.682 6.049 6.624 6.303 6.682 5.667 5.882 6.455 6.288 6.667 6.034 6.609 6.288 6.667 5.644 5.858 6.430 6.263 6.642 6.010 6.584 6.263 6.642 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS I 10mA 12mA 8mA 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V SSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-174 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-89 and Table 1-90 list the EP3SL200 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-89 lists the EP3SL200 column pin delay adders when using the regional clock. Table 1-89. EP3SL200 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.204 0.036 -0.211 1.904 0.235 0.046 -0.234 1.965 0.378 0.078 -0.332 3.193 0.378 0.078 -0.328 3.323 0.403 -0.34 3.688 0.392 0.509 0.387 0.085 3.351 0.411 0.392 0.509 ns ns ns ns -0.047 -0.038 -0.036 3.496 3.804 -0.046 -0.038 -0.036 3.716 3.496 3.804 -0.334 -0.464 -0.327 -0.339 -0.334 -0.464 Table 1-90 lists the EP3SL200 row pin delay adders when using the regional clock. Table 1-90. EP3SL200 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.272 0.14 -0.278 -0.15 0.301 0.149 -0.306 -0.15 0.446 0.226 0.424 0.216 0.473 0.235 0.46 0.226 -0.472 -0.243 0.547 0.306 -0.592 -0.322 0.454 0.232 -0.464 -0.243 0.481 0.254 0.46 0.226 0.547 0.306 -0.592 -0.322 ns ns ns ns -0.418 -0.434 -0.486 -0.227 -0.233 -0.254 -0.493 -0.472 -0.258 -0.243 EP3SL340 I/O Timing Parameters Table 1-91 through Table 1-94 list the maximum I/O timing parameters for EP3SL340 devices for single-ended I/O standards. Table 1-91 lists the EP3SL340 column pins input timing parameters for single-ended I/O standards. Table 1-91. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th -1.345 1.486 -1.691 1.996 -1.345 1.486 -1.691 1.996 -1.335 1.476 -1.691 1.996 -1.335 1.476 -1.691 1.996 -2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542 2.232 3.031 2.232 3.031 2.284 3.081 2.284 3.081 2.574 3.434 2.574 3.434 2.476 3.313 2.476 3.313 2.783 3.912 2.783 3.912 2.284 3.081 2.284 3.081 2.574 3.434 2.574 3.434 2.476 3.313 2.476 3.313 2.783 3.912 2.783 3.912 -2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373 -2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542 -2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373 ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-175 Table 1-91. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.356 1.497 -1.702 2.007 -1.356 1.497 -1.702 2.007 -1.351 1.492 -1.697 2.002 -1.373 1.516 -1.719 2.026 -1.363 1.506 -1.709 2.016 -1.311 1.454 -1.657 1.964 -1.282 1.425 -1.628 1.935 -1.282 1.425 -1.628 1.935 -1.276 1.419 -1.622 1.929 -1.346 1.487 -1.702 2.007 -1.346 1.487 -1.702 2.007 -1.341 1.482 -1.697 2.002 -1.363 1.506 -1.719 2.026 -1.353 1.496 -1.709 2.016 -1.301 1.444 -1.657 1.964 -1.272 1.415 -1.628 1.935 -1.272 1.415 -1.628 1.935 -1.266 1.409 -1.622 1.929 -2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541 2.231 3.030 2.231 3.030 2.240 3.039 2.280 3.079 2.257 3.056 2.180 2.979 2.152 2.951 2.152 2.951 2.139 2.938 2.286 3.083 2.286 3.083 2.298 3.095 2.334 3.131 2.302 3.099 2.203 3.000 2.187 2.984 2.187 2.984 2.176 2.973 2.573 3.433 2.573 3.433 2.592 3.452 2.590 3.450 2.520 3.380 2.364 3.224 2.366 3.226 2.366 3.226 2.360 3.220 2.475 3.312 2.475 3.312 2.494 3.331 2.492 3.329 2.422 3.259 2.266 3.103 2.268 3.105 2.268 3.105 2.262 3.099 2.782 3.911 2.782 3.911 2.801 3.930 2.799 3.928 2.729 3.858 2.573 3.702 2.575 3.704 2.575 3.704 2.571 3.697 2.286 3.083 2.286 3.083 2.298 3.095 2.334 3.131 2.302 3.099 2.203 3.000 2.187 2.984 2.187 2.984 2.176 2.973 2.573 3.433 2.573 3.433 2.592 3.452 2.590 3.450 2.520 3.380 2.364 3.224 2.366 3.226 2.366 3.226 2.360 3.220 2.475 3.312 2.475 3.312 2.494 3.331 2.492 3.329 2.422 3.259 2.266 3.103 2.268 3.105 2.268 3.105 2.262 3.099 2.782 3.911 2.782 3.911 2.801 3.930 2.799 3.928 2.729 3.858 2.573 3.702 2.575 3.704 2.575 3.704 2.571 3.697 -2.553 -2.587 -2.889 -2.798 -3.372 -2.587 -2.889 -2.798 -3.372 -2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541 -2.553 -2.587 -2.889 -2.798 -3.372 -2.587 -2.889 -2.798 -3.372 -2.025 -2.075 -2.348 -2.263 -2.560 -2.075 -2.348 -2.263 -2.560 -2.562 -2.599 -2.908 -2.817 -3.391 -2.599 -2.908 -2.817 -3.391 -2.065 -2.111 -2.346 -2.261 -2.558 -2.111 -2.346 -2.261 -2.558 -2.602 -2.635 -2.906 -2.815 -3.389 -2.635 -2.906 -2.815 -3.389 -2.042 -2.079 -2.276 -2.191 -2.488 -2.079 -2.276 -2.191 -2.488 -2.579 -2.603 -2.836 -2.745 -3.319 -2.603 -2.836 -2.745 -3.319 -1.965 -1.980 -2.120 -2.035 -2.332 -1.980 -2.120 -2.035 -2.332 -2.502 -2.504 -2.680 -2.589 -3.163 -2.504 -2.680 -2.589 -3.163 -1.937 -1.964 -2.122 -2.037 -2.334 -1.964 -2.122 -2.037 -2.334 -2.474 -2.488 -2.682 -2.591 -3.165 -2.488 -2.682 -2.591 -3.165 -1.937 -1.964 -2.122 -2.037 -2.334 -1.964 -2.122 -2.037 -2.334 -2.474 -2.488 -2.682 -2.591 -3.165 -2.488 -2.682 -2.591 -3.165 -1.924 -1.956 -2.119 -2.032 -2.335 -1.956 -2.119 -2.032 -2.335 -2.461 -2.480 -2.679 -2.586 -3.163 -2.480 -2.679 -2.586 -3.163 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-176 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-91. EP3SL340 Column Pins Input Timing Parameters (Part 3 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-18 CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.397 1.530 0.785 -0.510 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -1.354 1.508 0.779 -0.485 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 SSTL-15 CLASS I GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.8-V HSTL CLASS I GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.8-V HSTL CLASS II GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.5-V HSTL CLASS I GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.5-V HSTL CLASS II GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.2-V HSTL CLASS I GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 1.2-V HSTL CLASS II GCLK PLL GCLK -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 -2.096 -2.121 -2.299 -2.366 -2.766 -2.321 -2.476 -2.366 -2.766 2.327 1.380 2.361 1.479 2.563 1.654 2.611 1.670 3.023 1.679 2.566 1.480 2.745 1.660 2.611 1.670 3.023 1.679 3.0-V PCI GCLK PLL -0.912 -0.992 -1.113 -1.156 -1.144 -0.982 -1.107 -1.156 -1.144 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-177 Table 1-91. EP3SL340 Column Pins Input Timing Parameters (Part 4 of 4) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V PCI-X tsu th tsu th -1.356 1.497 -1.702 2.007 -1.346 1.487 -1.702 2.007 -2.016 -2.063 -2.329 -2.244 -2.541 -2.063 -2.329 -2.244 -2.541 2.231 3.030 2.286 3.083 2.573 3.433 2.475 3.312 2.782 3.911 2.286 3.083 2.573 3.433 2.475 3.312 2.782 3.911 -2.553 -2.587 -2.889 -2.798 -3.372 -2.587 -2.889 -2.798 -3.372 ns ns ns ns GCLK PLL Table 1-92 lists the EP3SL340 row pins input timing parameters for single-ended I/O standards. Table 1-92. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.239 1.362 0.879 -0.615 -1.239 1.362 0.879 -0.615 -1.245 1.368 0.873 -0.609 -1.245 1.368 0.873 -0.609 -1.233 1.356 0.885 -0.621 -1.251 1.377 0.827 -0.562 -1.296 1.435 0.945 -0.660 -1.296 1.435 0.945 -0.660 -1.307 1.446 0.934 -0.649 -1.307 1.446 0.934 -0.649 -1.300 1.439 0.941 -0.656 -1.343 1.482 0.910 -0.624 -1.925 -1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522 2.137 1.670 2.177 1.687 2.442 1.786 2.366 1.680 2.822 1.689 2.205 1.689 2.456 1.807 2.382 1.695 2.763 1.746 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS -1.216 -1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231 -1.925 -1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522 2.137 1.670 2.177 1.687 2.442 1.786 2.366 1.680 2.822 1.689 2.205 1.689 2.456 1.807 2.382 1.695 2.763 1.746 GCLK PLL GCLK -1.216 -1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231 -1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527 2.134 1.673 2.178 1.686 2.445 1.783 2.369 1.677 2.825 1.686 2.204 1.690 2.461 1.802 2.387 1.690 2.768 1.741 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS -1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226 -1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527 2.134 1.673 2.178 1.686 2.445 1.783 2.369 1.677 2.825 1.686 2.204 1.690 2.461 1.802 2.387 1.690 2.768 1.741 GCLK PLL GCLK -1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226 -1.931 -1.970 -2.217 -2.153 -2.605 -1.981 -2.219 -2.157 -2.537 2.143 1.664 2.191 1.673 2.460 1.768 2.384 1.662 2.840 1.671 2.213 1.681 2.471 1.792 2.397 1.680 2.778 1.731 2.5 V GCLK PLL GCLK 1.8 V -1.210 -1.203 -1.245 -1.170 -1.160 -1.200 -1.258 -1.178 -1.216 -1.980 -1.995 -2.204 -2.138 -2.582 -2.003 -2.208 -2.153 -2.621 2.193 1.624 2.216 1.634 2.447 1.857 2.369 1.742 2.817 1.565 2.234 1.620 2.461 1.886 2.393 1.762 2.859 1.619 GCLK PLL -1.170 -1.164 -1.330 -1.246 -1.060 -1.140 -1.347 -1.255 -1.107 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-178 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-92. EP3SL340 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5 V tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.241 1.367 0.837 -0.572 -1.181 1.307 0.897 -0.632 -1.176 1.300 0.942 -0.677 -1.176 1.300 0.942 -0.677 -1.155 1.281 0.923 -0.658 -1.155 1.281 0.923 -0.658 -1.141 1.267 0.937 -0.672 -1.155 1.281 0.923 -0.658 -1.155 1.281 0.923 -0.658 -1.332 1.471 0.921 -0.635 -1.279 1.418 0.974 -0.688 -1.242 1.382 1.000 -0.714 -1.242 1.382 1.000 -0.714 -1.244 1.383 1.009 -0.723 -1.244 1.383 1.009 -0.723 -1.232 1.371 1.021 -0.735 -1.244 1.383 1.009 -0.723 -1.244 1.383 1.009 -0.723 -1.956 -1.963 -2.136 -2.070 -2.514 -1.972 -2.143 -2.088 -2.556 2.169 1.648 2.184 1.666 2.379 1.925 2.301 1.810 2.749 1.633 2.203 1.651 2.396 1.951 2.328 1.827 2.794 1.684 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.2 V -1.194 -1.196 -1.398 -1.314 -1.128 -1.171 -1.412 -1.320 -1.172 -1.877 -1.862 -1.977 -1.911 -2.355 -1.876 -1.988 -1.933 -2.401 2.090 1.727 2.083 1.767 2.220 2.084 2.142 1.969 2.590 1.792 2.107 1.747 2.241 2.106 2.173 1.982 2.639 1.839 GCLK PLL GCLK SSTL-2 CLASS I -1.273 -1.297 -1.557 -1.473 -1.287 -1.267 -1.567 -1.475 -1.327 -1.845 -1.861 -1.997 -1.933 -2.385 -1.869 -2.002 -1.940 -2.320 2.057 1.750 2.082 1.782 2.240 1.988 2.164 1.882 2.620 1.891 2.101 1.793 2.254 2.009 2.180 1.897 2.561 1.948 GCLK PLL GCLK -1.296 -1.312 -1.465 -1.390 -1.380 -1.312 -1.475 -1.395 -1.433 -1.845 -1.861 -1.997 -1.933 -2.385 -1.869 -2.002 -1.940 -2.320 2.057 1.750 2.082 1.782 2.240 1.988 2.164 1.882 2.620 1.891 2.101 1.793 2.254 2.009 2.180 1.897 2.561 1.948 SSTL-2 CLASS II GCLK PLL GCLK -1.296 -1.312 -1.465 -1.390 -1.380 -1.312 -1.475 -1.395 -1.433 -1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394 2.052 1.765 2.054 1.794 2.213 2.086 2.135 1.972 2.582 1.796 2.073 1.779 2.231 2.110 2.164 1.988 2.628 1.846 SSTL-18 CLASS I GCLK PLL GCLK -1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338 -1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394 2.052 1.765 2.054 1.794 2.213 2.086 2.135 1.972 2.582 1.796 2.073 1.779 2.231 2.110 2.164 1.988 2.628 1.846 SSTL-18 CLASS II GCLK PLL GCLK -1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338 -1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377 2.038 1.778 2.044 1.804 2.195 2.104 2.117 1.990 2.564 1.814 2.062 1.790 2.214 2.127 2.147 2.005 2.611 1.863 SSTL-15 CLASS I GCLK PLL GCLK -1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355 -1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394 2.052 1.765 2.054 1.794 2.213 2.086 2.135 1.972 2.582 1.796 2.073 1.779 2.231 2.110 2.164 1.988 2.628 1.846 1.8-V HSTL CLASS I GCLK PLL GCLK -1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338 -1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394 2.052 1.765 2.054 1.794 2.213 2.086 2.135 1.972 2.582 1.796 2.073 1.779 2.231 2.110 2.164 1.988 2.628 1.846 1.8-V HSTL CLASS II GCLK PLL -1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-179 Table 1-92. EP3SL340 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.141 1.267 0.937 -0.672 -1.141 1.267 0.937 -0.672 -1.132 1.258 0.946 -0.681 -1.132 1.258 0.946 -0.681 -1.245 1.368 0.873 -0.609 -1.245 1.368 0.873 -0.609 -1.232 1.371 1.021 -0.735 -1.232 1.371 1.021 -0.735 -1.220 1.359 1.033 -0.747 -1.220 1.359 1.033 -0.747 -1.307 1.446 0.934 -0.649 -1.307 1.446 0.934 -0.649 -1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377 2.038 1.778 2.044 1.804 2.195 2.104 2.117 1.990 2.564 1.814 2.062 1.790 2.214 2.127 2.147 2.005 2.611 1.863 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355 -1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377 2.038 1.778 2.044 1.804 2.195 2.104 2.117 1.990 2.564 1.814 2.062 1.790 2.214 2.127 2.147 2.005 2.611 1.863 1.5-V HSTL CLASS II GCLK PLL GCLK -1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355 -1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361 2.029 1.787 2.034 1.814 2.179 2.120 2.101 2.006 2.548 1.830 2.053 1.799 2.198 2.143 2.131 2.021 2.595 1.879 1.2-V HSTL CLASS I GCLK PLL GCLK -1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371 -1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361 2.029 1.787 2.034 1.814 2.179 2.120 2.101 2.006 2.548 1.830 2.053 1.799 2.198 2.143 2.131 2.021 2.595 1.879 1.2-V HSTL CLASS II GCLK PLL GCLK -1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371 -1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527 2.134 1.673 2.178 1.686 2.445 1.783 2.369 1.677 2.825 1.686 2.204 1.690 2.461 1.802 2.387 1.690 2.768 1.741 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X -1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226 -1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527 2.134 1.673 2.178 1.686 2.445 1.783 2.369 1.677 2.825 1.686 2.204 1.690 2.461 1.802 2.387 1.690 2.768 1.741 GCLK PLL -1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-180 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-93 lists the EP3SL340 column pins output timing parameters for single-ended I/O standards. Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.705 4.269 3.638 4.202 3.552 4.116 3.545 4.110 3.711 4.275 3.556 4.120 3.563 4.127 3.547 4.111 3.669 4.232 3.558 4.125 3.522 4.087 3.504 4.068 3.705 4.269 3.638 4.202 3.552 4.116 3.545 4.110 3.711 4.275 3.556 4.120 3.563 4.127 3.547 4.111 3.669 4.232 3.558 4.125 3.522 4.087 3.504 4.068 5.372 6.214 5.263 6.105 5.160 6.001 5.143 5.985 5.377 6.218 5.170 6.012 5.164 6.006 5.141 5.983 5.339 6.181 5.209 6.053 5.146 5.987 5.117 5.959 5.559 6.409 5.448 6.298 5.350 6.200 5.322 6.172 5.564 6.414 5.367 6.217 5.346 6.196 5.320 6.171 5.528 6.377 5.394 6.246 5.325 6.174 5.297 6.147 6.083 6.992 5.970 6.879 5.878 6.789 5.837 6.747 6.090 7.000 5.889 6.799 5.863 6.775 5.834 6.746 6.050 6.983 5.912 6.867 5.838 6.803 5.810 6.780 5.935 6.812 5.822 6.699 5.730 6.609 5.689 6.567 5.942 6.820 5.741 6.619 5.715 6.595 5.686 6.566 5.902 6.803 5.765 6.688 5.691 6.624 5.662 6.601 6.364 5.559 6.083 5.935 6.364 7.355 6.409 6.992 6.812 7.355 6.251 5.448 5.970 5.822 6.251 7.242 6.298 6.879 6.699 7.242 6.159 5.350 5.878 5.730 6.159 7.152 6.200 6.789 6.609 7.152 6.118 5.322 5.837 5.689 6.118 7.110 6.172 6.747 6.567 7.110 6.371 5.564 6.090 5.942 6.371 7.363 6.414 7.000 6.820 7.363 6.170 5.367 5.889 5.741 6.170 7.162 6.217 6.799 6.619 7.162 6.144 5.346 5.863 5.715 6.144 7.138 6.196 6.775 6.595 7.138 6.115 5.320 5.834 5.686 6.115 7.109 6.171 6.746 6.566 7.109 6.331 5.528 6.050 5.902 6.331 7.346 6.377 6.983 6.803 7.346 6.193 5.394 5.912 5.765 6.193 7.229 6.246 6.867 6.688 7.229 6.119 5.325 5.838 5.691 6.119 7.165 6.174 6.803 6.624 7.165 6.091 5.297 5.810 5.662 6.091 7.142 6.147 6.780 6.601 7.142 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-181 Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.583 4.149 3.504 4.070 3.499 4.063 3.490 4.054 3.705 4.269 3.605 4.172 3.561 4.127 3.523 4.088 3.583 4.149 3.504 4.070 3.499 4.063 3.490 4.054 3.705 4.269 3.605 4.172 3.561 4.127 3.523 4.088 5.243 6.087 5.120 5.963 5.112 5.955 5.098 5.940 5.450 6.293 5.331 6.174 5.244 6.087 5.205 6.048 5.427 6.279 5.298 6.149 5.291 6.142 5.276 6.126 5.654 6.504 5.528 6.379 5.438 6.288 5.395 6.246 5.947 6.903 5.812 6.793 5.804 6.761 5.789 6.767 6.194 7.111 6.062 6.987 5.967 6.909 5.924 6.852 5.800 6.724 5.665 6.614 5.656 6.581 5.641 6.588 6.047 6.932 5.915 6.808 5.819 6.730 5.776 6.673 6.228 5.427 5.947 5.800 6.228 7.265 6.279 6.903 6.724 7.265 6.093 5.298 5.812 5.665 6.093 7.155 6.149 6.793 6.614 7.155 6.085 5.291 5.804 5.656 6.085 7.124 6.142 6.761 6.581 7.124 6.070 5.276 5.789 5.641 6.070 7.129 6.126 6.767 6.588 7.129 6.475 5.654 6.194 6.047 6.475 7.473 6.504 7.111 6.932 7.473 6.343 5.528 6.062 5.915 6.343 7.349 6.379 6.987 6.808 7.349 6.248 5.438 5.967 5.819 6.248 7.271 6.288 6.909 6.730 7.271 6.205 5.395 5.924 5.776 6.205 7.214 6.246 6.852 6.673 7.214 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-182 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.896 4.460 3.715 4.282 3.633 4.197 3.613 4.177 3.550 4.114 3.532 4.097 3.842 4.406 3.630 4.194 3.605 4.170 3.594 4.158 3.539 4.103 3.534 4.097 3.896 4.460 3.715 4.282 3.633 4.197 3.613 4.177 3.550 4.114 3.532 4.097 3.842 4.406 3.630 4.194 3.605 4.170 3.594 4.158 3.539 4.103 3.534 4.097 5.772 6.613 5.493 6.336 5.386 6.227 5.327 6.169 5.266 6.109 5.246 6.088 5.700 6.542 5.381 6.223 5.314 6.156 5.297 6.140 5.259 6.101 5.243 6.084 6.014 6.863 5.705 6.556 5.590 6.440 5.537 6.386 5.462 6.312 5.440 6.291 5.947 6.796 5.590 6.439 5.530 6.381 5.505 6.356 5.455 6.305 5.443 6.292 6.599 7.507 6.251 7.177 6.141 7.064 6.075 6.987 5.994 6.918 5.971 6.885 6.537 7.452 6.145 7.066 6.078 6.989 6.058 6.972 5.988 6.909 5.977 6.888 6.451 7.327 6.104 6.998 5.993 6.884 5.927 6.807 5.846 6.738 5.823 6.705 6.389 7.272 5.997 6.886 5.930 6.809 5.910 6.792 5.840 6.729 5.829 6.708 6.880 6.014 6.599 6.451 6.880 7.870 6.863 7.507 7.327 7.870 6.532 5.705 6.251 6.104 6.532 7.539 6.556 7.177 6.998 7.539 6.422 5.590 6.141 5.993 6.422 7.427 6.440 7.064 6.884 7.427 6.356 5.537 6.075 5.927 6.356 7.350 6.386 6.987 6.807 7.350 6.275 5.462 5.994 5.846 6.275 7.281 6.312 6.918 6.738 7.281 6.252 5.440 5.971 5.823 6.252 7.248 6.291 6.885 6.705 7.248 6.818 5.947 6.537 6.389 6.818 7.815 6.796 7.452 7.272 7.815 6.426 5.590 6.145 5.997 6.426 7.429 6.439 7.066 6.886 7.429 6.359 5.530 6.078 5.930 6.359 7.352 6.381 6.989 6.809 7.352 6.339 5.505 6.058 5.910 6.339 7.335 6.356 6.972 6.792 7.335 6.269 5.455 5.988 5.840 6.269 7.272 6.305 6.909 6.729 7.272 6.258 5.443 5.977 5.829 6.258 7.251 6.292 6.888 6.708 7.251 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-183 Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.758 4.322 3.635 4.200 3.597 4.162 3.550 4.113 3.550 4.114 3.547 4.111 3.545 4.110 3.536 4.101 3.557 4.121 3.553 4.117 3.542 4.107 3.531 4.095 3.531 4.095 3.758 4.322 3.635 4.200 3.597 4.162 3.550 4.113 3.550 4.114 3.547 4.111 3.545 4.110 3.536 4.101 3.557 4.121 3.553 4.117 3.542 4.107 3.531 4.095 3.531 4.095 5.626 6.468 5.401 6.243 5.308 6.150 5.280 6.121 5.237 6.078 5.234 6.075 5.234 6.075 5.220 6.062 5.249 6.090 5.247 6.088 5.237 6.079 5.225 6.066 5.224 6.066 5.882 6.731 5.621 6.471 5.531 6.381 5.482 6.331 5.430 6.278 5.426 6.274 5.427 6.275 5.412 6.261 5.444 6.292 5.442 6.290 5.432 6.281 5.419 6.268 5.419 6.268 6.481 7.392 6.195 7.107 6.082 6.993 6.026 6.946 5.957 6.903 5.953 6.899 5.954 6.899 5.939 6.883 5.973 6.923 5.971 6.920 5.962 6.919 5.949 6.894 5.949 6.892 6.333 7.212 6.047 6.927 5.934 6.813 5.878 6.766 5.809 6.723 5.805 6.720 5.806 6.719 5.791 6.703 5.825 6.744 5.823 6.740 5.814 6.740 5.801 6.715 5.801 6.712 6.762 5.882 6.481 6.333 6.762 7.755 6.731 7.392 7.212 7.755 6.476 5.621 6.195 6.047 6.476 7.470 6.471 7.107 6.927 7.470 6.363 5.531 6.082 5.934 6.363 7.356 6.381 6.993 6.813 7.356 6.307 5.482 6.026 5.878 6.307 7.309 6.331 6.946 6.766 7.309 6.238 5.430 5.957 5.809 6.238 7.266 6.278 6.903 6.723 7.266 6.234 5.426 5.953 5.805 6.234 7.261 6.274 6.899 6.720 7.261 6.235 5.427 5.954 5.806 6.235 7.262 6.275 6.899 6.719 7.262 6.220 5.412 5.939 5.791 6.220 7.246 6.261 6.883 6.703 7.246 6.254 5.444 5.973 5.825 6.254 7.285 6.292 6.923 6.744 7.285 6.252 5.442 5.971 5.823 6.252 7.283 6.290 6.920 6.740 7.283 6.243 5.432 5.962 5.814 6.243 7.281 6.281 6.919 6.740 7.281 6.230 5.419 5.949 5.801 6.230 7.256 6.268 6.894 6.715 7.256 6.230 5.419 5.949 5.801 6.230 7.255 6.268 6.892 6.712 7.255 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-184 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 8mA SSTL-18 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.537 4.102 3.540 4.104 3.561 4.124 3.547 4.112 3.536 4.100 3.535 4.099 3.532 4.096 3.534 4.098 3.537 4.101 3.537 4.102 3.540 4.104 3.561 4.124 3.547 4.112 3.536 4.100 3.535 4.099 3.532 4.096 3.534 4.098 3.537 4.101 5.223 6.065 5.231 6.072 5.259 6.100 5.248 6.090 5.235 6.076 5.238 6.078 5.232 6.073 5.221 6.063 5.228 6.070 5.416 6.265 5.426 6.274 5.455 6.303 5.445 6.294 5.431 6.280 5.435 6.283 5.429 6.277 5.415 6.264 5.424 6.272 5.944 6.895 5.956 6.918 5.986 6.937 5.977 6.923 5.963 6.908 5.967 6.905 5.961 6.899 5.944 6.896 5.955 6.920 5.796 6.715 5.808 6.738 5.838 6.757 5.829 6.743 5.815 6.728 5.819 6.726 5.813 6.719 5.796 6.716 5.807 6.740 6.225 5.416 5.944 5.796 6.225 7.258 6.265 6.895 6.715 7.258 6.237 5.426 5.956 5.808 6.237 7.281 6.274 6.918 6.738 7.281 6.267 5.455 5.986 5.838 6.267 7.300 6.303 6.937 6.757 7.300 6.258 5.445 5.977 5.829 6.258 7.286 6.294 6.923 6.743 7.286 6.244 5.431 5.963 5.815 6.244 7.271 6.280 6.908 6.728 7.271 6.248 5.435 5.967 5.819 6.248 7.268 6.283 6.905 6.726 7.268 6.242 5.429 5.961 5.813 6.242 7.262 6.277 6.899 6.719 7.262 6.225 5.415 5.944 5.796 6.225 7.259 6.264 6.896 6.716 7.259 6.236 5.424 5.955 5.807 6.236 7.283 6.272 6.920 6.740 7.283 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-185 Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.544 4.108 3.537 4.102 3.529 4.094 3.532 4.096 3.529 4.093 3.537 4.101 3.549 4.113 3.545 4.109 3.541 4.105 3.534 4.098 3.535 4.098 3.533 4.096 3.544 4.108 3.537 4.102 3.529 4.094 3.532 4.096 3.529 4.093 3.537 4.101 3.549 4.113 3.545 4.109 3.541 4.105 3.534 4.098 3.535 4.098 3.533 4.096 5.223 6.064 5.221 6.063 5.214 6.055 5.217 6.058 5.219 6.060 5.218 6.059 5.232 6.072 5.233 6.075 5.228 6.070 5.221 6.063 5.228 6.069 5.209 6.050 5.415 6.263 5.414 6.263 5.406 6.255 5.410 6.258 5.413 6.261 5.411 6.259 5.425 6.273 5.427 6.276 5.422 6.271 5.415 6.264 5.423 6.271 5.401 6.249 5.942 6.897 5.941 6.903 5.934 6.885 5.938 6.887 5.942 6.895 5.938 6.898 5.953 6.910 5.956 6.907 5.951 6.902 5.944 6.896 5.954 6.900 5.928 6.884 5.794 6.717 5.793 6.724 5.786 6.706 5.790 6.707 5.794 6.716 5.790 6.718 5.805 6.730 5.808 6.727 5.803 6.722 5.796 6.716 5.806 6.721 5.780 6.704 6.223 5.415 5.942 5.794 6.223 7.260 6.263 6.897 6.717 7.260 6.222 5.414 5.941 5.793 6.222 7.265 6.263 6.903 6.724 7.265 6.215 5.406 5.934 5.786 6.215 7.247 6.255 6.885 6.706 7.247 6.219 5.410 5.938 5.790 6.219 7.250 6.258 6.887 6.707 7.250 6.223 5.413 5.942 5.794 6.223 7.257 6.261 6.895 6.716 7.257 6.219 5.411 5.938 5.790 6.219 7.261 6.259 6.898 6.718 7.261 6.234 5.425 5.953 5.805 6.234 7.273 6.273 6.910 6.730 7.273 6.237 5.427 5.956 5.808 6.237 7.270 6.276 6.907 6.727 7.270 6.232 5.422 5.951 5.803 6.232 7.265 6.271 6.902 6.722 7.265 6.225 5.415 5.944 5.796 6.225 7.259 6.264 6.896 6.716 7.259 6.235 5.423 5.954 5.806 6.235 7.262 6.271 6.900 6.721 7.262 6.209 5.401 5.928 5.780 6.209 7.247 6.249 6.884 6.704 7.247 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-186 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-93. EP3SL340 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.552 4.117 3.544 4.108 3.545 4.108 3.534 4.098 3.534 4.098 3.555 4.119 3.658 4.222 3.658 4.222 3.552 4.117 3.544 4.108 3.545 4.108 3.534 4.098 3.534 4.098 3.555 4.119 3.658 4.222 3.658 4.222 5.246 6.087 5.237 6.078 5.244 6.085 5.231 6.072 5.231 6.073 5.247 6.089 5.292 6.134 5.292 6.134 5.442 6.291 5.433 6.282 5.442 6.290 5.428 6.276 5.428 6.277 5.443 6.292 5.477 6.328 5.477 6.328 5.974 6.929 5.965 6.917 5.974 6.920 5.960 6.915 5.961 6.906 5.974 6.943 5.999 6.974 5.999 6.974 5.826 6.749 5.817 6.737 5.826 6.740 5.812 6.736 5.813 6.727 5.826 6.763 5.851 6.794 5.851 6.794 6.255 5.442 5.974 5.826 6.255 7.292 6.291 6.929 6.749 7.292 6.246 5.433 5.965 5.817 6.246 7.280 6.282 6.917 6.737 7.280 6.255 5.442 5.974 5.826 6.255 7.283 6.290 6.920 6.740 7.283 6.241 5.428 5.960 5.812 6.241 7.277 6.276 6.915 6.736 7.277 6.242 5.428 5.961 5.813 6.242 7.269 6.277 6.906 6.727 7.269 6.255 5.443 5.974 5.826 6.255 7.306 6.292 6.943 6.763 7.306 6.280 5.477 5.999 5.851 6.280 7.337 6.328 6.974 6.794 7.337 6.280 5.477 5.999 5.851 6.280 7.337 6.328 6.974 6.794 7.337 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-187 Table 1-94 lists the EP3SL340 row pins output timing parameters for single-ended I/O standards. Table 1-94. EP3SL340 Row Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.479 1.562 3.413 1.496 3.334 1.417 3.481 1.564 3.338 1.421 3.440 1.523 3.339 1.422 3.302 1.385 3.361 1.444 3.289 1.372 3.466 1.549 3.381 1.464 3.324 1.407 3.781 1.782 3.681 1.677 3.592 1.575 3.785 1.786 3.596 1.579 3.727 1.728 3.601 1.601 3.563 1.550 3.646 1.647 3.547 1.530 3.763 1.764 3.665 1.666 3.603 1.589 5.469 2.243 5.339 2.113 5.220 1.994 5.477 2.251 5.226 2.000 5.421 2.195 5.269 2.043 5.188 1.961 5.316 2.090 5.161 1.926 5.554 2.328 5.399 2.173 5.288 2.062 5.657 6.238 6.095 6.481 5.741 6.370 6.120 6.565 2.285 2.559 2.570 2.578 2.386 2.666 2.671 2.594 5.519 6.093 5.950 6.336 5.628 6.221 6.005 6.416 2.174 2.414 2.425 2.433 2.273 2.517 2.522 2.445 5.398 5.965 5.822 6.208 5.529 6.089 5.905 6.284 2.074 2.286 2.297 2.305 2.174 2.385 2.390 2.313 5.662 6.242 6.099 6.485 5.749 6.374 6.132 6.569 2.291 2.563 2.574 2.582 2.394 2.670 2.675 2.598 5.413 5.971 5.828 6.214 5.541 6.096 5.914 6.291 2.089 2.292 2.303 2.311 2.186 2.392 2.397 2.320 5.610 6.194 6.051 6.437 5.709 6.328 6.086 6.523 2.254 2.515 2.526 2.534 2.354 2.624 2.629 2.552 5.451 6.030 5.887 6.273 5.567 6.164 5.940 6.358 2.112 2.351 2.362 2.370 2.212 2.460 2.464 2.387 5.371 5.942 5.799 6.185 5.499 6.071 5.867 6.265 2.047 2.263 2.274 2.282 2.144 2.367 2.371 2.294 5.503 6.084 5.941 6.327 5.600 6.217 5.976 6.411 2.147 2.405 2.416 2.424 2.245 2.513 2.517 2.440 5.342 5.903 5.760 6.146 5.469 6.031 5.838 6.225 2.018 2.224 2.235 2.243 2.114 2.327 2.331 2.254 5.764 6.366 6.223 6.609 5.841 6.507 6.238 6.701 2.380 2.687 2.698 2.706 2.486 2.803 2.807 2.730 5.601 6.196 6.053 6.439 5.704 6.333 6.093 6.527 2.245 2.517 2.528 2.536 2.349 2.629 2.633 2.556 5.483 6.070 5.927 6.313 5.615 6.203 5.999 6.397 2.159 2.391 2.402 2.410 2.260 2.499 2.503 2.426 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVTTL 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-188 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-94. EP3SL340 Row Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.692 1.785 3.519 1.562 3.444 1.495 3.426 1.469 3.634 1.696 3.442 1.485 3.415 1.458 3.396 1.439 3.564 1.639 3.447 1.490 3.328 1.411 3.323 1.406 3.314 1.397 3.942 1.925 3.756 1.739 3.674 1.657 3.654 1.637 3.885 1.868 3.671 1.654 3.645 1.628 3.634 1.617 3.798 1.781 3.675 1.658 3.591 1.575 3.587 1.570 3.576 1.559 5.817 2.574 5.527 2.284 5.427 2.184 5.370 2.127 5.745 2.502 5.423 2.180 5.355 2.112 5.338 2.095 5.666 2.423 5.440 2.197 5.278 2.039 5.275 2.032 5.260 2.017 6.193 6.841 6.698 7.084 6.248 6.991 6.682 7.186 2.860 3.162 3.173 3.192 2.985 3.287 3.292 3.203 5.824 6.436 6.293 6.679 5.922 6.585 6.320 6.779 2.491 2.757 2.768 2.787 2.620 2.881 2.885 2.796 5.674 6.277 6.134 6.520 5.808 6.412 6.215 6.607 2.341 2.598 2.609 2.628 2.452 2.708 2.713 2.624 5.595 6.180 6.037 6.423 5.752 6.318 6.143 6.513 2.259 2.501 2.512 2.531 2.361 2.614 2.619 2.530 6.106 6.769 6.626 7.012 6.169 6.915 6.617 7.110 2.773 3.090 3.101 3.120 2.892 3.211 3.216 3.127 5.669 6.278 6.135 6.521 5.805 6.411 6.216 6.606 2.336 2.599 2.610 2.629 2.446 2.707 2.712 2.623 5.587 6.172 6.029 6.415 5.745 6.306 6.143 6.501 2.251 2.493 2.504 2.523 2.354 2.602 2.607 2.518 5.562 6.153 6.010 6.396 5.721 6.284 6.124 6.479 2.226 2.474 2.485 2.504 2.330 2.580 2.585 2.496 6.020 6.694 6.551 6.937 6.100 6.831 6.548 7.026 2.687 3.015 3.026 3.045 2.804 3.127 3.132 3.043 5.697 6.319 6.176 6.562 5.834 6.453 6.260 6.648 2.364 2.640 2.651 2.670 2.471 2.749 2.754 2.665 5.474 6.038 5.895 6.281 5.602 6.165 5.985 6.360 2.150 2.359 2.370 2.378 2.247 2.461 2.466 2.389 5.472 6.030 5.887 6.273 5.601 6.158 5.984 6.353 2.148 2.351 2.362 2.370 2.246 2.454 2.459 2.382 5.456 6.003 5.860 6.246 5.584 6.131 5.966 6.326 2.132 2.324 2.335 2.343 2.229 2.427 2.432 2.355 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-189 Table 1-94. EP3SL340 Row Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.375 1.418 3.370 1.413 3.359 1.402 3.348 1.391 3.348 1.391 3.356 1.399 3.357 1.400 3.378 1.421 3.364 1.407 3.353 1.396 3.598 1.581 3.593 1.576 3.582 1.565 3.571 1.554 3.570 1.553 3.577 1.560 3.580 1.563 3.601 1.584 3.587 1.570 3.575 1.558 5.289 2.046 5.287 2.044 5.277 2.034 5.264 2.021 5.264 2.021 5.263 2.020 5.269 2.026 5.298 2.055 5.287 2.044 5.274 2.031 5.499 6.054 5.911 6.297 5.651 6.181 6.034 6.376 2.163 2.375 2.386 2.405 2.260 2.477 2.482 2.393 5.498 6.052 5.909 6.295 5.649 6.179 6.032 6.374 2.162 2.373 2.384 2.403 2.258 2.475 2.480 2.391 5.488 6.035 5.895 6.278 5.640 6.163 6.023 6.358 2.152 2.356 2.367 2.386 2.249 2.459 2.464 2.375 5.475 6.020 5.882 6.263 5.628 6.148 6.011 6.343 2.139 2.341 2.352 2.371 2.237 2.444 2.449 2.360 5.475 6.019 5.882 6.262 5.627 6.147 6.011 6.342 2.139 2.340 2.351 2.370 2.236 2.443 2.448 2.359 5.472 6.013 5.877 6.256 5.623 6.140 6.005 6.335 2.136 2.334 2.345 2.364 2.232 2.436 2.441 2.352 5.480 6.015 5.887 6.258 5.632 6.144 6.016 6.339 2.144 2.336 2.347 2.366 2.241 2.440 2.445 2.356 5.510 6.071 5.928 6.314 5.661 6.197 6.046 6.392 2.174 2.392 2.403 2.422 2.270 2.493 2.498 2.409 5.500 6.054 5.911 6.297 5.652 6.181 6.037 6.376 2.164 2.375 2.386 2.405 2.261 2.477 2.482 2.393 5.487 6.036 5.896 6.279 5.639 6.164 6.024 6.359 2.151 2.357 2.368 2.387 2.248 2.460 2.465 2.376 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-190 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-94. EP3SL340 Row Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.363 1.406 3.356 1.399 3.347 1.390 3.350 1.393 3.346 1.389 3.354 1.397 3.369 1.412 3.363 1.406 3.359 1.402 3.371 1.414 3.362 1.405 3.361 1.404 3.434 1.517 3.434 1.517 3.583 1.566 3.577 1.560 3.569 1.552 3.571 1.554 3.568 1.551 3.576 1.559 3.589 1.572 3.584 1.567 3.580 1.563 3.591 1.574 3.583 1.566 3.583 1.566 3.697 1.680 3.697 1.680 5.262 2.019 5.260 2.017 5.253 2.010 5.256 2.013 5.258 2.015 5.256 2.013 5.271 2.028 5.272 2.029 5.267 2.024 5.284 2.041 5.275 2.032 5.282 2.039 5.330 2.087 5.330 2.087 5.470 6.016 5.875 6.259 5.622 6.143 6.002 6.338 2.134 2.337 2.348 2.367 2.231 2.439 2.444 2.355 5.469 6.008 5.874 6.251 5.621 6.136 6.002 6.331 2.133 2.329 2.340 2.359 2.230 2.432 2.437 2.348 5.462 6.000 5.867 6.243 5.614 6.128 5.995 6.323 2.126 2.321 2.332 2.351 2.223 2.424 2.429 2.340 5.465 6.003 5.871 6.246 5.617 6.131 5.998 6.326 2.129 2.324 2.335 2.354 2.226 2.427 2.432 2.343 5.468 6.003 5.874 6.246 5.620 6.132 6.003 6.327 2.132 2.324 2.335 2.354 2.229 2.428 2.433 2.344 5.465 5.994 5.870 6.237 5.616 6.121 5.997 6.316 2.129 2.315 2.326 2.345 2.225 2.417 2.422 2.333 5.480 6.031 5.888 6.274 5.631 6.157 6.013 6.352 2.144 2.352 2.363 2.382 2.240 2.453 2.458 2.369 5.482 6.027 5.888 6.270 5.633 6.154 6.016 6.349 2.146 2.348 2.359 2.378 2.242 2.450 2.455 2.366 5.477 6.021 5.883 6.264 5.628 6.148 6.010 6.343 2.141 2.342 2.353 2.372 2.237 2.444 2.449 2.360 5.496 6.049 5.906 6.292 5.647 6.174 6.032 6.369 2.160 2.370 2.381 2.400 2.256 2.470 2.475 2.386 5.487 6.037 5.896 6.280 5.638 6.163 6.023 6.358 2.151 2.358 2.369 2.388 2.247 2.459 2.464 2.375 5.495 6.043 5.905 6.286 5.647 6.170 6.033 6.365 2.159 2.364 2.375 2.394 2.256 2.466 2.471 2.382 5.520 6.047 5.904 6.299 5.650 6.177 6.027 6.372 2.196 2.378 2.386 2.387 2.295 2.482 2.493 2.401 5.520 6.047 5.904 6.299 5.650 6.177 6.027 6.372 2.196 2.378 2.386 2.387 2.295 2.482 2.493 2.401 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-191 Table 1-95 through Table 1-98 list the maximum I/O timing parameters for EP3SL340 devices for differential I/O standards. Table 1-95 lists the EP3SL340 column pins input timing parameters for differential I/O standards. Table 1-95. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -1.278 1.414 0.857 -0.582 -1.278 1.414 0.857 -0.582 -1.278 1.414 0.857 -0.582 -1.094 1.223 1.041 -0.773 -1.094 1.223 1.041 -0.773 -1.102 1.231 1.033 -0.765 -1.102 1.231 1.033 -0.765 -1.114 1.243 1.021 -0.753 -1.335 1.489 0.885 -0.589 -1.335 1.489 0.885 -0.589 -1.335 1.489 0.885 -0.589 -1.158 1.304 1.062 -0.774 -1.158 1.304 1.062 -0.774 -1.170 1.316 1.050 -0.762 -1.170 1.316 1.050 -0.762 -1.181 1.327 1.039 -0.751 -1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242 1.926 1.872 1.873 2.050 2.080 2.211 2.002 2.107 2.485 1.975 1.857 2.104 2.327 2.409 1.981 2.165 2.527 2.031 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474 -1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242 1.926 1.872 1.873 2.050 2.080 2.211 2.002 2.107 2.485 1.975 1.857 2.104 2.327 2.409 1.981 2.165 2.527 2.031 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474 -1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242 1.926 1.872 1.873 2.050 2.080 2.211 2.002 2.107 2.485 1.975 1.857 2.104 2.327 2.409 1.981 2.165 2.527 2.031 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474 -1.787 -1.806 -1.947 -1.875 -2.353 -1.815 -1.953 -1.887 -2.396 2.006 1.759 2.032 1.851 2.193 2.052 2.110 1.953 2.589 1.826 2.050 1.869 2.208 2.073 2.131 1.967 2.636 1.877 DIFFERENTIAL 1.2-V HSTL CLASS I -1.302 -1.378 -1.527 -1.457 -1.319 -1.386 -1.537 -1.462 -1.365 -1.787 -1.806 -1.947 -1.875 -2.353 -1.815 -1.953 -1.887 -2.396 2.006 1.759 2.032 1.851 2.193 2.052 2.110 1.953 2.589 1.826 2.050 1.869 2.208 2.073 2.131 1.967 2.636 1.877 DIFFERENTIAL 1.2-V HSTL CLASS II -1.302 -1.378 -1.527 -1.457 -1.319 -1.386 -1.537 -1.462 -1.365 -1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411 2.016 1.749 2.043 1.840 2.209 2.036 2.126 1.937 2.605 1.810 2.061 1.858 2.223 2.058 2.146 1.952 2.651 1.862 DIFFERENTIAL 1.5-V HSTL CLASS I -1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350 -1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411 2.016 1.749 2.043 1.840 2.209 2.036 2.126 1.937 2.605 1.810 2.061 1.858 2.223 2.058 2.146 1.952 2.651 1.862 DIFFERENTIAL 1.5-V HSTL CLASS II -1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350 -1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429 2.025 1.740 2.054 1.829 2.228 2.017 2.145 1.918 2.624 1.791 2.072 1.847 2.241 2.040 2.164 1.934 2.669 1.844 DIFFERENTIAL 1.8-V HSTL CLASS I -1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-192 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-95. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.114 1.243 1.021 -0.753 -1.102 1.231 1.033 -0.765 -1.102 1.231 1.033 -0.765 -1.114 1.243 1.021 -0.753 -1.114 1.243 1.021 -0.753 -1.121 1.250 1.014 -0.746 -1.121 1.250 1.014 -0.746 -1.181 1.327 1.039 -0.751 -1.170 1.316 1.050 -0.762 -1.170 1.316 1.050 -0.762 -1.181 1.327 1.039 -0.751 -1.181 1.327 1.039 -0.751 -1.187 1.333 1.033 -0.745 -1.187 1.333 1.033 -0.745 -1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429 2.025 1.740 2.054 1.829 2.228 2.017 2.145 1.918 2.624 1.791 2.072 1.847 2.241 2.040 2.164 1.934 2.669 1.844 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332 -1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411 2.016 1.749 2.043 1.840 2.209 2.036 2.126 1.937 2.605 1.810 2.061 1.858 2.223 2.058 2.146 1.952 2.651 1.862 DIFFERENTIAL 1.5-V SSTL CLASS I -1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350 -1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411 2.016 1.749 2.043 1.840 2.209 2.036 2.126 1.937 2.605 1.810 2.061 1.858 2.223 2.058 2.146 1.952 2.651 1.862 DIFFERENTIAL 1.5-V SSTL CLASS II -1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350 -1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429 2.025 1.740 2.054 1.829 2.228 2.017 2.145 1.918 2.624 1.791 2.072 1.847 2.241 2.040 2.164 1.934 2.669 1.844 DIFFERENTIAL 1.8-V SSTL CLASS I -1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332 -1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429 2.025 1.740 2.054 1.829 2.228 2.017 2.145 1.918 2.624 1.791 2.072 1.847 2.241 2.040 2.164 1.934 2.669 1.844 DIFFERENTIAL 1.8-V SSTL CLASS II -1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332 -1.818 -1.833 -1.982 -1.912 -2.387 -1.841 -1.981 -1.918 -2.425 2.038 1.728 2.062 1.824 2.231 2.017 2.148 1.916 2.628 1.792 2.079 1.843 2.241 2.045 2.163 1.936 2.670 1.848 DIFFERENTIAL 2.5-V SSTL CLASS I -1.270 -1.348 -1.489 -1.419 -1.280 -1.357 -1.504 -1.430 -1.331 -1.818 -1.833 -1.982 -1.912 -2.387 -1.841 -1.981 -1.918 -2.425 2.038 1.728 2.062 1.824 2.231 2.017 2.148 1.916 2.628 1.792 2.079 1.843 2.241 2.045 2.163 1.936 2.670 1.848 DIFFERENTIAL 2.5-V SSTL CLASS II -1.270 -1.348 -1.489 -1.419 -1.280 -1.357 -1.504 -1.430 -1.331 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-193 Table 1-96 lists the EP3SL340 row pins input timing parameters for differential I/O standards. Table 1-96. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK LVDS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.246 1.380 0.822 -0.548 -1.246 1.380 0.822 -0.548 -1.246 1.380 0.822 -0.548 -1.051 1.178 1.007 -0.740 -1.051 1.178 1.007 -0.740 -1.060 1.187 0.998 -0.731 -1.060 1.187 0.998 -0.731 -1.074 1.201 0.984 -0.717 -1.308 1.458 0.846 -0.552 -1.308 1.458 0.846 -0.552 -1.308 1.458 0.846 -0.552 -1.123 1.264 1.021 -0.736 -1.123 1.264 1.021 -0.736 -1.135 1.276 1.009 -0.724 -1.135 1.276 1.009 -0.724 -1.147 1.288 0.997 -0.712 -1.577 1.832 1.911 -1.422 -1.577 1.832 1.911 -1.422 -1.577 1.832 1.911 -1.422 -1.707 1.926 1.776 -1.321 -1.707 1.926 1.776 -1.321 -1.716 1.935 1.767 -1.312 -1.716 1.935 1.767 -1.312 -1.725 1.944 1.754 -1.300 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087 1.758 2.121 1.950 2.309 1.878 2.193 2.332 2.091 1.738 2.181 1.920 2.377 1.853 2.260 2.374 2.149 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK MINI-LVDS -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087 1.758 2.121 1.950 2.309 1.878 2.193 2.332 2.091 1.738 2.181 1.920 2.377 1.853 2.260 2.374 2.149 GCLK PLL GCLK RSDS -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087 1.758 2.121 1.950 2.309 1.878 2.193 2.332 2.091 1.738 2.181 1.920 2.377 1.853 2.260 2.374 2.149 GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.8-V HSTL CLASS I -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588 -1.717 -1.845 -1.779 -2.225 -1.727 -1.852 -1.790 -2.271 1.941 1.887 2.090 2.110 2.013 1.999 2.462 1.902 1.960 1.904 2.105 2.130 2.033 2.018 2.509 1.955 DIFFERENTIAL 1.2-V HSTL CLASS I -1.415 -1.586 -1.505 -1.396 -1.423 -1.595 -1.512 -1.443 -1.717 -1.845 -1.779 -2.225 -1.727 -1.852 -1.790 -2.271 1.941 1.887 2.090 2.110 2.013 1.999 2.462 1.902 1.960 1.904 2.105 2.130 2.033 2.018 2.509 1.955 -1.415 -1.586 -1.505 -1.396 -1.423 -1.595 -1.512 -1.443 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287 1.951 1.877 2.106 2.094 2.029 1.983 2.478 1.886 1.969 1.895 2.121 2.114 2.049 2.002 2.525 1.939 DIFFERENTIAL 1.5-V HSTL CLASS I -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287 1.951 1.877 2.106 2.094 2.029 1.983 2.478 1.886 1.969 1.895 2.121 2.114 2.049 2.002 2.525 1.939 -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304 1.961 1.867 2.124 2.076 2.047 1.965 2.496 1.868 1.980 1.884 2.138 2.097 2.066 1.985 2.542 1.922 GCLK GCLK PLL -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-194 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-96. EP3SL340 Row Pins Input Timing Parameters (Part 2 of 2) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.8-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.074 1.201 0.984 -0.717 -1.060 1.187 0.998 -0.731 -1.060 1.187 0.998 -0.731 -1.074 1.201 0.984 -0.717 -1.074 1.201 0.984 -0.717 -1.083 1.210 0.985 -0.718 -1.083 1.210 0.985 -0.718 -1.147 1.288 0.997 -0.712 -1.135 1.276 1.009 -0.724 -1.135 1.276 1.009 -0.724 -1.147 1.288 0.997 -0.712 -1.147 1.288 0.997 -0.712 -1.156 1.297 0.998 -0.713 -1.156 1.297 0.998 -0.713 -1.725 1.944 1.754 -1.300 -1.716 1.935 1.767 -1.312 -1.716 1.935 1.767 -1.312 -1.725 1.944 1.754 -1.300 -1.725 1.944 1.754 -1.300 -1.739 1.959 1.749 -1.295 -1.739 1.959 1.749 -1.295 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304 1.961 1.867 2.124 2.076 2.047 1.965 2.496 1.868 1.980 1.884 2.138 2.097 2.066 1.985 2.542 1.922 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287 1.951 1.877 2.106 2.094 2.029 1.983 2.478 1.886 1.969 1.895 2.121 2.114 2.049 2.002 2.525 1.939 DIFFERENTIAL 1.5-V SSTL CLASS I -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287 1.951 1.877 2.106 2.094 2.029 1.983 2.478 1.886 1.969 1.895 2.121 2.114 2.049 2.002 2.525 1.939 DIFFERENTIAL 1.5-V SSTL CLASS II -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304 1.961 1.867 2.124 2.076 2.047 1.965 2.496 1.868 1.980 1.884 2.138 2.097 2.066 1.985 2.542 1.922 DIFFERENTIAL 1.8-V SSTL CLASS I -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304 1.961 1.867 2.124 2.076 2.047 1.965 2.496 1.868 1.980 1.884 2.138 2.097 2.066 1.985 2.542 1.922 DIFFERENTIAL 1.8-V SSTL CLASS II -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410 -1.748 -1.886 -1.821 -2.265 -1.754 -1.886 -1.826 -2.306 1.975 1.861 2.134 2.075 2.057 1.963 2.507 1.867 1.990 1.883 2.144 2.101 2.071 1.987 2.549 1.925 DIFFERENTIAL 2.5-V SSTL CLASS I -1.387 -1.548 -1.467 -1.357 -1.399 -1.563 -1.480 -1.409 -1.748 -1.886 -1.821 -2.265 -1.754 -1.886 -1.826 -2.306 1.975 1.861 2.134 2.075 2.057 1.963 2.507 1.867 1.990 1.883 2.144 2.101 2.071 1.987 2.549 1.925 -1.387 -1.548 -1.467 -1.357 -1.399 -1.563 -1.480 -1.409 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-195 Table 1-97 lists the EP3SL340 column pins output timing parameters for differential I/O standards. Table 1-97. EP3SL340 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.438 1.427 3.434 1.423 3.438 1.427 3.434 1.423 3.438 1.427 3.434 1.423 3.465 1.454 3.455 1.444 3.455 1.444 3.448 1.437 3.447 1.436 3.469 1.458 3.700 1.606 3.703 1.609 3.700 1.606 3.703 1.609 3.700 1.606 3.703 1.609 3.733 1.639 3.723 1.629 3.723 1.629 3.717 1.623 3.715 1.621 3.737 1.643 5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475 2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459 5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541 2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525 5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475 2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459 5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541 2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525 5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475 2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459 5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541 2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525 5.486 5.685 6.227 6.075 6.483 5.819 6.360 6.208 6.561 2.160 2.259 2.490 2.491 2.559 2.367 2.597 2.600 2.545 5.476 5.674 6.217 6.065 6.473 5.808 6.350 6.198 6.551 2.150 2.248 2.480 2.481 2.549 2.356 2.587 2.590 2.535 5.479 5.678 6.221 6.069 6.477 5.813 6.355 6.203 6.556 2.153 2.252 2.484 2.485 2.553 2.361 2.592 2.595 2.540 5.472 5.672 6.215 6.063 6.471 5.806 6.349 6.197 6.550 2.146 2.246 2.478 2.479 2.547 2.354 2.586 2.589 2.534 5.469 5.669 6.212 6.060 6.468 5.803 6.345 6.193 6.546 2.143 2.243 2.475 2.476 2.544 2.351 2.582 2.585 2.530 5.490 5.689 6.231 6.079 6.487 5.823 6.365 6.213 6.566 2.164 2.263 2.494 2.495 2.563 2.371 2.602 2.605 2.550 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.2-V HSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-196 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-97. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.459 1.448 3.454 1.443 3.452 1.441 3.444 1.433 3.445 1.434 3.444 1.433 3.456 1.445 3.452 1.441 3.442 1.431 3.440 1.429 3.440 1.429 3.444 1.433 3.726 1.632 3.722 1.628 3.720 1.626 3.711 1.617 3.713 1.619 3.710 1.616 3.723 1.629 3.720 1.626 3.709 1.615 3.707 1.613 3.708 1.614 3.711 1.617 5.469 5.666 6.206 6.054 6.462 5.799 6.338 6.186 6.539 2.143 2.240 2.469 2.470 2.538 2.347 2.575 2.578 2.523 5.469 5.666 6.207 6.055 6.463 5.800 6.340 6.188 6.541 2.143 2.240 2.470 2.471 2.539 2.348 2.577 2.580 2.525 5.468 5.665 6.205 6.053 6.461 5.799 6.339 6.187 6.540 2.142 2.239 2.468 2.469 2.537 2.347 2.576 2.579 2.524 5.458 5.655 6.196 6.044 6.452 5.789 6.329 6.177 6.530 2.132 2.229 2.459 2.460 2.528 2.337 2.566 2.569 2.514 5.464 5.662 6.204 6.052 6.460 5.797 6.338 6.186 6.539 2.138 2.236 2.467 2.468 2.536 2.345 2.575 2.578 2.523 5.447 5.643 6.182 6.030 6.438 5.776 6.314 6.162 6.515 2.121 2.217 2.445 2.446 2.514 2.324 2.551 2.554 2.499 5.465 5.661 6.200 6.048 6.456 5.795 6.333 6.181 6.534 2.139 2.235 2.463 2.464 2.532 2.343 2.570 2.573 2.518 5.466 5.663 6.204 6.052 6.460 5.797 6.337 6.185 6.538 2.140 2.237 2.467 2.468 2.536 2.345 2.574 2.577 2.522 5.455 5.652 6.192 6.040 6.448 5.786 6.325 6.173 6.526 2.129 2.226 2.455 2.456 2.524 2.334 2.562 2.565 2.510 5.453 5.649 6.190 6.038 6.446 5.784 6.323 6.171 6.524 2.127 2.223 2.453 2.454 2.522 2.332 2.560 2.563 2.508 5.456 5.654 6.195 6.043 6.451 5.788 6.329 6.177 6.530 2.130 2.228 2.458 2.459 2.527 2.336 2.566 2.569 2.514 5.453 5.649 6.189 6.037 6.445 5.783 6.322 6.170 6.523 2.127 2.223 2.452 2.453 2.521 2.331 2.559 2.562 2.507 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-197 Table 1-97. EP3SL340 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.470 1.459 3.456 1.445 3.444 1.433 3.444 1.433 3.440 1.429 3.444 1.433 3.445 1.434 3.473 1.462 3.462 1.451 3.457 1.446 3.443 1.432 3.441 1.430 3.445 1.434 3.445 1.434 3.740 1.646 3.726 1.632 3.713 1.619 3.713 1.619 3.709 1.615 3.711 1.617 3.713 1.619 3.743 1.649 3.731 1.637 3.727 1.633 3.712 1.618 3.710 1.616 3.712 1.618 3.713 1.619 5.498 5.697 6.239 6.087 6.495 5.831 6.372 6.220 6.573 2.172 2.271 2.502 2.503 2.571 2.379 2.609 2.612 2.557 5.486 5.686 6.229 6.077 6.485 5.821 6.363 6.211 6.564 2.160 2.260 2.492 2.493 2.561 2.369 2.600 2.603 2.548 5.469 5.668 6.211 6.059 6.467 5.803 6.345 6.193 6.546 2.143 2.242 2.474 2.475 2.543 2.351 2.582 2.585 2.530 5.472 5.672 6.215 6.063 6.471 5.807 6.350 6.198 6.551 2.146 2.246 2.478 2.479 2.547 2.355 2.587 2.590 2.535 5.465 5.664 6.208 6.056 6.464 5.800 6.342 6.190 6.543 2.139 2.238 2.471 2.472 2.540 2.348 2.579 2.582 2.527 5.458 5.655 6.196 6.044 6.452 5.789 6.329 6.177 6.530 2.132 2.229 2.459 2.460 2.528 2.337 2.566 2.569 2.514 5.466 5.665 6.207 6.055 6.463 5.799 6.341 6.189 6.542 2.140 2.239 2.470 2.471 2.539 2.347 2.578 2.581 2.526 5.497 5.695 6.237 6.085 6.493 5.830 6.370 6.218 6.571 2.171 2.269 2.500 2.501 2.569 2.378 2.607 2.610 2.555 5.485 5.683 6.225 6.073 6.481 5.818 6.358 6.206 6.559 2.159 2.257 2.488 2.489 2.557 2.366 2.595 2.598 2.543 5.485 5.684 6.226 6.074 6.482 5.819 6.360 6.208 6.561 2.159 2.258 2.489 2.490 2.558 2.367 2.597 2.600 2.545 5.467 5.665 6.207 6.055 6.463 5.800 6.342 6.190 6.543 2.141 2.239 2.470 2.471 2.539 2.348 2.579 2.582 2.527 5.465 5.663 6.205 6.053 6.461 5.798 6.339 6.187 6.540 2.139 2.237 2.468 2.469 2.537 2.346 2.576 2.579 2.524 5.457 5.653 6.193 6.041 6.449 5.787 6.326 6.174 6.527 2.131 2.227 2.456 2.457 2.525 2.335 2.563 2.566 2.511 5.465 5.663 6.205 6.053 6.461 5.798 6.339 6.187 6.540 2.139 2.237 2.468 2.469 2.537 2.346 2.576 2.579 2.524 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-198 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-97. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco 3.461 1.450 3.461 1.450 3.451 1.440 3.444 1.433 3.730 1.636 3.730 1.636 3.720 1.626 3.712 1.618 5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553 2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537 5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553 2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537 5.471 5.668 6.209 6.057 6.465 5.803 6.343 6.191 6.544 2.145 2.242 2.472 2.473 2.541 2.351 2.580 2.583 2.528 5.457 5.653 6.193 6.041 6.449 5.787 6.326 6.174 6.527 2.131 2.227 2.456 2.457 2.525 2.335 2.563 2.566 2.511 ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS I DIFFERENTIAL 2.5-V SSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-199 Table 1-98 lists the EP3SL340 row pins output timing parameters for differential I/O standards. Table 1-98. EP3SL340 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.022 1.063 3.414 1.455 3.396 1.437 3.022 1.063 3.414 1.455 3.396 1.437 3.022 1.063 3.414 1.455 3.396 1.437 3.440 1.491 3.426 1.477 3.422 1.473 3.234 1.193 3.678 1.637 3.668 1.627 3.234 1.193 3.678 1.637 3.668 1.627 3.234 1.193 3.678 1.637 3.668 1.627 3.711 1.680 3.697 1.666 3.693 1.662 4.714 1.445 5.396 2.127 5.434 2.165 4.714 1.445 5.396 2.127 5.434 2.165 4.714 1.445 5.396 2.127 5.434 2.165 5.470 2.211 5.457 2.198 5.455 2.196 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528 5.668 6.212 6.059 6.436 5.806 6.345 6.195 6.515 2.307 2.538 2.542 2.579 2.418 2.649 2.651 2.567 5.655 6.199 6.046 6.423 5.792 6.332 6.182 6.502 2.294 2.525 2.529 2.566 2.404 2.636 2.638 2.554 5.655 6.200 6.047 6.424 5.792 6.334 6.184 6.504 2.294 2.526 2.530 2.567 2.404 2.638 2.640 2.556 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-200 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-98. EP3SL340 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.438 1.489 3.427 1.478 3.424 1.475 3.435 1.486 3.425 1.476 3.411 1.462 3.408 1.459 3.405 1.456 3.406 1.457 3.455 1.506 3.431 1.482 3.414 1.465 3.708 1.677 3.698 1.667 3.695 1.664 3.705 1.674 3.696 1.665 3.682 1.651 3.678 1.647 3.676 1.645 3.676 1.645 3.729 1.698 3.705 1.674 3.686 1.655 5.456 2.197 5.452 2.193 5.450 2.191 5.451 2.192 5.449 2.190 5.434 2.175 5.430 2.171 5.431 2.172 5.421 2.162 5.492 2.233 5.474 2.215 5.452 2.193 5.652 6.194 6.041 6.418 5.789 6.327 6.177 6.497 2.291 2.520 2.524 2.561 2.401 2.631 2.633 2.549 5.648 6.191 6.038 6.415 5.786 6.324 6.174 6.494 2.287 2.517 2.521 2.558 2.398 2.628 2.630 2.546 5.646 6.189 6.036 6.413 5.784 6.323 6.173 6.493 2.285 2.515 2.519 2.556 2.396 2.627 2.629 2.545 5.647 6.188 6.035 6.412 5.784 6.321 6.171 6.491 2.286 2.514 2.518 2.555 2.396 2.625 2.627 2.543 5.645 6.187 6.034 6.411 5.783 6.321 6.171 6.491 2.284 2.513 2.517 2.554 2.395 2.625 2.627 2.543 5.630 6.173 6.020 6.397 5.768 6.306 6.156 6.476 2.269 2.499 2.503 2.540 2.380 2.610 2.612 2.528 5.626 6.169 6.016 6.393 5.764 6.302 6.152 6.472 2.265 2.495 2.499 2.536 2.376 2.606 2.608 2.524 5.629 6.172 6.019 6.396 5.767 6.306 6.156 6.476 2.268 2.498 2.502 2.539 2.379 2.610 2.612 2.528 5.617 6.159 6.006 6.383 5.754 6.292 6.142 6.462 2.256 2.485 2.489 2.526 2.366 2.596 2.598 2.514 5.690 6.235 6.082 6.459 5.828 6.368 6.218 6.538 2.329 2.561 2.565 2.602 2.440 2.672 2.674 2.590 5.673 6.218 6.065 6.442 5.811 6.353 6.203 6.523 2.312 2.544 2.548 2.585 2.423 2.657 2.659 2.575 5.651 6.196 6.043 6.420 5.789 6.331 6.181 6.501 2.290 2.522 2.526 2.563 2.401 2.635 2.637 2.553 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA DIFFERENTIAL 1.8-V HSTL CLASS I 8mA 10mA 12mA DIFFERENTIAL 1.8-V HSTL CLASS II 16mA 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-201 Table 1-98. EP3SL340 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.459 1.510 3.444 1.495 3.433 1.484 3.413 1.464 3.410 1.461 3.415 1.466 3.408 1.459 3.446 1.487 3.428 1.469 3.414 1.455 3.732 1.701 3.717 1.686 3.706 1.675 3.686 1.655 3.682 1.651 3.686 1.655 3.679 1.648 3.718 1.677 3.701 1.660 3.685 1.644 5.492 2.233 5.478 2.219 5.473 2.214 5.450 2.191 5.446 2.187 5.437 2.178 5.436 2.177 5.474 2.205 5.459 2.190 5.436 2.167 5.690 6.234 6.081 6.458 5.828 6.368 6.218 6.538 2.329 2.560 2.564 2.601 2.440 2.672 2.674 2.590 5.675 6.219 6.066 6.443 5.813 6.353 6.203 6.523 2.314 2.545 2.549 2.586 2.425 2.657 2.659 2.575 5.672 6.216 6.063 6.440 5.810 6.351 6.201 6.521 2.311 2.542 2.546 2.583 2.422 2.655 2.657 2.573 5.648 6.193 6.040 6.417 5.787 6.327 6.177 6.497 2.287 2.519 2.523 2.560 2.399 2.631 2.633 2.549 5.645 6.189 6.036 6.413 5.783 6.324 6.174 6.494 2.284 2.515 2.519 2.556 2.395 2.628 2.630 2.546 5.633 6.175 6.022 6.399 5.770 6.308 6.158 6.478 2.272 2.501 2.505 2.542 2.382 2.612 2.614 2.530 5.634 6.178 6.025 6.402 5.773 6.313 6.163 6.483 2.273 2.504 2.508 2.545 2.385 2.617 2.619 2.535 5.671 6.214 6.061 6.438 5.809 6.348 6.198 6.518 2.300 2.530 2.534 2.571 2.411 2.642 2.644 2.560 5.656 6.199 6.046 6.423 5.794 6.333 6.183 6.503 2.285 2.515 2.519 2.556 2.396 2.627 2.629 2.545 5.632 6.174 6.021 6.398 5.770 6.308 6.158 6.478 2.261 2.490 2.494 2.531 2.372 2.602 2.604 2.520 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA DIFFERENTIAL 1.8-V SSTL CLASS I 8mA 10mA 12mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS II 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V SSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-202 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-99 and Table 1-100 list the EP3SL340 regional (RCLK) clock adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-99 lists the EP3SL340 column pin delay adders when using the regional clock. Table 1-99. EP3SL340 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units 0.318 2.716 -0.341 -2.36 0.171 2.739 -0.107 -2.128 0.255 4.379 -0.18 0.247 4.508 0.257 4.926 0.244 4.717 0.369 5.376 0.37 4.508 -0.03 0.253 4.94 0.232 4.89 0.336 5.434 ns ns ns ns -0.169 -0.171 -0.167 -0.362 -0.043 -0.034 -0.287 -3.344 -3.384 -3.571 -3.487 -3.545 -3.246 -3.636 -3.357 -3.544 Table 1-100 lists the EP3SL340 row pin delay adders when using the regional clock. Table 1-100. EP3SL340 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units 0.075 0.157 -0.052 -0.157 0.079 0.151 -0.066 -0.139 0.133 0.262 0.124 0.274 0.125 0.306 0.124 0.288 0.307 0.464 0.117 0.268 0.116 0.291 0.117 0.278 0.31 0.46 ns ns ns ns -0.107 -0.098 -0.127 -0.129 -0.282 -0.082 -0.118 -0.085 -0.285 -0.232 -0.248 -0.272 -0.259 -0.422 -0.252 -0.256 -0.244 -0.444 EP3SE50 I/O Timing Parameters Table 1-101 through Table 1-104 list the maximum I/O timing parameters for EP3SE50 devices for single-ended I/O standards. Table 1-101 lists the EP3SE50 column pins input timing parameters for single-ended I/O standards. Table 1-101. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th -0.743 0.870 -1.037 1.290 -0.743 0.870 -1.037 1.290 -0.742 0.869 -1.037 1.290 -0.742 0.869 -1.037 1.290 -1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605 1.241 1.836 1.241 1.836 1.366 2.009 1.366 2.009 1.595 2.292 1.595 2.292 1.538 2.207 1.538 2.207 1.815 2.484 1.815 2.484 1.366 2.009 1.366 2.009 1.595 2.292 1.595 2.292 1.538 2.207 1.538 2.207 1.815 2.484 1.815 2.484 -1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038 -1.063 -1.165 -1.374 -1.329 -1.605 -1.165 -1.374 -1.329 -1.605 -1.466 -1.593 -1.830 -1.772 -2.038 -1.593 -1.830 -1.772 -2.038 ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-203 Table 1-101. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.754 0.881 -1.048 1.301 -0.754 0.881 -1.048 1.301 -0.749 0.876 -1.043 1.296 -0.769 0.898 -1.065 1.320 -0.759 0.888 -1.055 1.310 -0.707 0.836 -1.003 1.258 -0.678 0.807 -0.974 1.229 -0.678 0.807 -0.974 1.229 -0.672 0.801 -0.968 1.223 -0.753 0.880 -1.048 1.301 -0.753 0.880 -1.048 1.301 -0.748 0.875 -1.043 1.296 -0.768 0.897 -1.065 1.320 -0.758 0.887 -1.055 1.310 -0.706 0.835 -1.003 1.258 -0.677 0.806 -0.974 1.229 -0.677 0.806 -0.974 1.229 -0.671 0.800 -0.968 1.223 -1.062 -1.167 -1.373 -1.328 -1.604 -1.167 -1.373 -1.328 -1.604 1.240 1.835 1.240 1.835 1.249 1.844 1.289 1.884 1.266 1.861 1.189 1.784 1.161 1.756 1.161 1.756 1.148 1.743 1.368 2.011 1.368 2.011 1.380 2.023 1.416 2.059 1.384 2.027 1.285 1.928 1.269 1.912 1.269 1.912 1.261 1.901 1.594 2.291 1.594 2.291 1.613 2.310 1.611 2.308 1.541 2.238 1.385 2.082 1.387 2.084 1.387 2.084 1.384 2.078 1.537 2.206 1.537 2.206 1.556 2.225 1.554 2.223 1.484 2.153 1.328 1.997 1.330 1.999 1.330 1.999 1.327 1.993 1.814 2.483 1.814 2.483 1.833 2.502 1.831 2.500 1.761 2.430 1.605 2.274 1.607 2.276 1.607 2.276 1.603 2.269 1.368 2.011 1.368 2.011 1.380 2.023 1.416 2.059 1.384 2.027 1.285 1.928 1.269 1.912 1.269 1.912 1.261 1.901 1.594 2.291 1.594 2.291 1.613 2.310 1.611 2.308 1.541 2.238 1.385 2.082 1.387 2.084 1.387 2.084 1.384 2.078 1.537 2.206 1.537 2.206 1.556 2.225 1.554 2.223 1.484 2.153 1.328 1.997 1.330 1.999 1.330 1.999 1.327 1.993 1.814 2.483 1.814 2.483 1.833 2.502 1.831 2.500 1.761 2.430 1.605 2.274 1.607 2.276 1.607 2.276 1.603 2.269 -1.465 -1.595 -1.829 -1.771 -2.037 -1.595 -1.829 -1.771 -2.037 -1.062 -1.167 -1.373 -1.328 -1.604 -1.167 -1.373 -1.328 -1.604 -1.465 -1.595 -1.829 -1.771 -2.037 -1.595 -1.829 -1.771 -2.037 -1.071 -1.179 -1.392 -1.347 -1.623 -1.179 -1.392 -1.347 -1.623 -1.474 -1.607 -1.848 -1.790 -2.056 -1.607 -1.848 -1.790 -2.056 -1.111 -1.215 -1.390 -1.345 -1.621 -1.215 -1.390 -1.345 -1.621 -1.514 -1.643 -1.846 -1.788 -2.054 -1.643 -1.846 -1.788 -2.054 -1.088 -1.183 -1.320 -1.275 -1.551 -1.183 -1.320 -1.275 -1.551 -1.491 -1.611 -1.776 -1.718 -1.984 -1.611 -1.776 -1.718 -1.984 -1.011 -1.084 -1.164 -1.119 -1.395 -1.084 -1.164 -1.119 -1.395 -1.414 -1.512 -1.620 -1.562 -1.828 -1.512 -1.620 -1.562 -1.828 -0.983 -1.068 -1.166 -1.121 -1.397 -1.068 -1.166 -1.121 -1.397 -1.386 -1.496 -1.622 -1.564 -1.830 -1.496 -1.622 -1.564 -1.830 -0.983 -1.068 -1.166 -1.121 -1.397 -1.068 -1.166 -1.121 -1.397 -1.386 -1.496 -1.622 -1.564 -1.830 -1.496 -1.622 -1.564 -1.830 -0.971 -1.063 -1.166 -1.119 -1.398 -1.063 -1.166 -1.119 -1.398 -1.373 -1.488 -1.619 -1.559 -1.828 -1.488 -1.619 -1.559 -1.828 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-204 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-101. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-18 CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.672 0.801 -0.968 1.223 -0.661 0.790 -0.957 1.212 -0.661 0.790 -0.957 1.212 -0.672 0.801 -0.968 1.223 -0.672 0.801 -0.968 1.223 -0.661 0.790 -0.957 1.212 -0.661 0.790 -0.957 1.212 -0.649 0.778 -0.945 1.200 -0.649 0.778 -0.945 1.200 -0.671 0.800 -0.968 1.223 -0.660 0.789 -0.957 1.212 -0.660 0.789 -0.957 1.212 -0.671 0.800 -0.968 1.223 -0.671 0.800 -0.968 1.223 -0.660 0.789 -0.957 1.212 -0.660 0.789 -0.957 1.212 -0.648 0.777 -0.945 1.200 -0.648 0.777 -0.945 1.200 -0.971 -1.063 -1.166 -1.119 -1.398 -1.063 -1.166 -1.119 -1.398 1.148 1.743 1.138 1.731 1.138 1.731 1.148 1.743 1.148 1.743 1.138 1.731 1.138 1.731 1.128 1.721 1.128 1.721 1.261 1.901 1.250 1.890 1.250 1.890 1.261 1.901 1.261 1.901 1.250 1.890 1.250 1.890 1.239 1.879 1.239 1.879 1.384 2.078 1.365 2.059 1.365 2.059 1.384 2.078 1.384 2.078 1.365 2.059 1.365 2.059 1.349 2.043 1.349 2.043 1.327 1.993 1.308 1.974 1.308 1.974 1.327 1.993 1.327 1.993 1.308 1.974 1.308 1.974 1.292 1.958 1.292 1.958 1.603 2.269 1.584 2.250 1.584 2.250 1.603 2.269 1.603 2.269 1.584 2.250 1.584 2.250 1.568 2.234 1.568 2.234 1.261 1.901 1.250 1.890 1.250 1.890 1.261 1.901 1.261 1.901 1.250 1.890 1.250 1.890 1.239 1.879 1.239 1.879 1.384 2.078 1.365 2.059 1.365 2.059 1.384 2.078 1.384 2.078 1.365 2.059 1.365 2.059 1.349 2.043 1.349 2.043 1.327 1.993 1.308 1.974 1.308 1.974 1.327 1.993 1.327 1.993 1.308 1.974 1.308 1.974 1.292 1.958 1.292 1.958 1.603 2.269 1.584 2.250 1.584 2.250 1.603 2.269 1.603 2.269 1.584 2.250 1.584 2.250 1.568 2.234 1.568 2.234 -1.373 -1.488 -1.619 -1.559 -1.828 -1.488 -1.619 -1.559 -1.828 -0.962 -1.052 -1.147 -1.100 -1.379 -1.052 -1.147 -1.100 -1.379 -1.362 -1.477 -1.600 -1.540 -1.809 -1.477 -1.600 -1.540 -1.809 -0.962 -1.052 -1.147 -1.100 -1.379 -1.052 -1.147 -1.100 -1.379 -1.362 -1.477 -1.600 -1.540 -1.809 -1.477 -1.600 -1.540 -1.809 -0.971 -1.063 -1.166 -1.119 -1.398 -1.063 -1.166 -1.119 -1.398 -1.373 -1.488 -1.619 -1.559 -1.828 -1.488 -1.619 -1.559 -1.828 -0.971 -1.063 -1.166 -1.119 -1.398 -1.063 -1.166 -1.119 -1.398 -1.373 -1.488 -1.619 -1.559 -1.828 -1.488 -1.619 -1.559 -1.828 -0.962 -1.052 -1.147 -1.100 -1.379 -1.052 -1.147 -1.100 -1.379 -1.362 -1.477 -1.600 -1.540 -1.809 -1.477 -1.600 -1.540 -1.809 -0.962 -1.052 -1.147 -1.100 -1.379 -1.052 -1.147 -1.100 -1.379 -1.362 -1.477 -1.600 -1.540 -1.809 -1.477 -1.600 -1.540 -1.809 -0.952 -1.041 -1.131 -1.084 -1.363 -1.041 -1.131 -1.084 -1.363 -1.352 -1.466 -1.584 -1.524 -1.793 -1.466 -1.584 -1.524 -1.793 -0.952 -1.041 -1.131 -1.084 -1.363 -1.041 -1.131 -1.084 -1.363 -1.352 -1.466 -1.584 -1.524 -1.793 -1.466 -1.584 -1.524 -1.793 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-205 Table 1-101. EP3SE50 Column Pins Input Timing Parameters (Part 4 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V | PCI-X tsu th tsu th -0.754 0.881 -1.048 1.301 -0.753 0.880 -1.048 1.301 -1.062 -1.167 -1.373 -1.328 -1.604 -1.167 -1.373 -1.328 -1.604 1.240 1.835 1.368 2.011 1.594 2.291 1.537 2.206 1.814 2.483 1.368 2.011 1.594 2.291 1.537 2.206 1.814 2.483 -1.465 -1.595 -1.829 -1.771 -2.037 -1.595 -1.829 -1.771 -2.037 ns ns ns ns GCLK PLL Table 1-102 lists the EP3SE50 row pins input timing parameters for single-ended I/O standards. Table 1-102. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.896 1.009 0.952 -0.703 -0.896 1.009 0.952 -0.703 -0.902 1.015 0.946 -0.697 -0.902 1.015 0.946 -0.697 -0.890 1.003 0.958 -0.709 -0.869 0.890 0.986 -0.859 -0.926 1.052 0.960 -0.700 -0.926 1.052 0.960 -0.700 -0.937 1.063 0.949 -0.689 -0.937 1.063 0.949 -0.689 -0.930 1.056 0.956 -0.696 -0.907 0.886 1.035 -0.896 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 1.597 1.494 1.816 1.640 1.931 1.888 1.813 1.819 1.843 2.111 1.809 1.667 1.936 1.903 1.818 1.836 1.895 2.144 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 1.597 1.494 1.491 1.600 1.491 1.500 1.591 1.500 1.510 1.458 1.510 1.534 1.434 1.613 1.816 1.640 1.641 1.815 1.641 1.654 1.802 1.654 1.730 1.596 1.730 1.762 1.564 1.863 1.931 1.888 1.891 1.928 1.891 1.906 1.913 1.906 1.876 1.807 1.876 1.944 1.739 2.103 1.813 1.819 1.822 1.810 1.822 1.837 1.795 1.837 1.758 1.742 1.758 1.826 1.674 1.985 1.843 2.111 2.114 1.840 2.114 2.129 1.825 2.129 1.788 2.015 1.788 1.856 1.947 2.015 1.809 1.667 1.666 1.810 1.666 1.675 1.801 1.675 1.729 1.614 1.729 1.760 1.583 1.856 1.936 1.903 1.908 1.931 1.908 1.918 1.921 1.918 1.881 1.817 1.881 1.946 1.752 2.101 1.818 1.836 1.841 1.813 1.841 1.851 1.803 1.851 1.762 1.754 1.762 1.827 1.689 1.982 1.895 2.144 2.149 1.890 2.149 2.159 1.880 2.159 1.840 2.048 1.840 1.905 1.983 2.060 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 -1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942 -1.272 -1.388 -1.573 -1.523 -1.797 -1.395 -1.573 -1.526 -1.829 -1.248 -1.356 -1.505 -1.455 -1.729 -1.364 -1.508 -1.461 -1.764 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-206 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-102. EP3SE50 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 0.900 0.976 -0.799 0.960 0.916 -0.833 1.015 0.947 -0.833 1.015 0.947 -0.773 0.986 0.890 -0.773 0.986 0.890 -0.759 1.000 0.876 -0.773 0.986 0.890 -0.773 0.986 0.890 -0.759 1.000 0.876 -0.759 1.000 0.876 -0.750 1.009 0.867 -0.750 0.897 1.024 -0.843 0.950 0.971 -0.872 1.014 0.999 -0.872 1.014 0.999 -0.808 0.985 0.936 -0.808 0.985 0.936 -0.796 0.997 0.924 -0.808 0.985 0.936 -0.808 0.985 0.936 -0.796 0.997 0.924 -0.796 0.997 0.924 -0.784 1.009 0.912 -0.784 1.355 1.677 1.414 1.651 1.317 -1.131 1.651 1.317 1.651 1.317 1.463 1.911 1.545 1.580 2.133 1.686 1.515 2.015 1.617 1.788 2.045 1.909 1.487 1.913 1.563 1.597 2.138 1.701 1.534 2.020 1.634 1.828 2.097 1.942 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.169 -1.255 -1.346 -1.296 -1.570 -1.268 -1.353 -1.306 -1.609 -1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 1.436 1.890 1.890 1.575 2.108 2.108 1.510 1.991 1.991 1.782 2.019 2.019 1.455 1.888 1.888 1.590 2.108 2.108 1.527 1.990 1.990 1.819 2.067 2.067 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 1.436 1.890 1.575 2.108 1.510 1.991 1.782 2.019 1.455 1.888 1.590 2.108 1.527 1.990 1.819 2.067 -1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 -1.131 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 -1.267 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 -1.118 1.305 1.651 1.317 1.651 1.317 -1.131 -1.267 1.305 1.666 -1.267 -1.276 1.296 1.675 -1.276 -1.276 1.426 1.900 1.900 1.557 2.126 2.126 1.492 2.009 2.009 1.764 2.037 2.037 1.444 1.899 1.899 1.573 2.125 2.125 1.510 2.007 2.007 1.802 2.084 2.084 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 1.436 1.890 1.575 2.108 1.510 1.991 1.782 2.019 1.455 1.888 1.590 2.108 1.527 1.990 1.819 2.067 -1.131 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 -1.118 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 1.436 1.890 1.900 1.575 2.108 2.126 1.510 1.991 2.009 1.782 2.019 2.037 1.455 1.888 1.899 1.590 2.108 2.125 1.527 1.990 2.007 1.819 2.067 2.084 -1.118 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 -1.109 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 1.426 1.900 1.910 1.557 2.126 2.142 1.492 2.009 2.025 1.764 2.037 2.053 1.444 1.899 1.908 1.573 2.125 2.141 1.510 2.007 2.023 1.802 2.084 2.100 -1.109 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-207 Table 1-102. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.009 0.867 -0.902 1.015 0.946 -0.697 -0.902 1.015 0.946 -0.697 -0.896 1.009 0.952 -0.703 -0.896 1.009 0.952 -0.703 -0.902 1.015 0.946 -0.697 -0.902 1.015 1.009 0.912 -0.937 1.063 0.949 -0.689 -0.937 1.063 0.949 -0.689 -0.926 1.052 0.960 -0.700 -0.926 1.052 0.960 -0.700 -0.937 1.063 0.949 -0.689 -0.937 1.063 -1.308 -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622 1.600 1.491 -1.308 1.600 1.491 1.491 1.491 1.491 1.491 1.597 1.494 -1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571 1.416 1.910 1.541 2.142 1.476 2.025 1.748 2.053 1.435 1.908 1.557 2.141 1.494 2.023 1.786 2.100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622 -1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571 1.416 1.910 1.541 2.142 1.476 2.025 1.748 2.053 1.435 1.908 1.557 2.141 1.494 2.023 1.786 2.100 -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622 -1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571 1.816 1.640 1.931 1.888 1.813 1.819 1.843 2.111 1.809 1.667 1.936 1.903 1.818 1.836 1.895 2.144 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 -1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 1.597 1.494 1.491 1.600 1.491 1.500 1.816 1.640 1.641 1.815 1.641 1.654 1.931 1.888 1.891 1.928 1.891 1.906 1.813 1.819 1.822 1.810 1.822 1.837 1.843 2.111 2.114 1.840 2.114 2.129 1.809 1.667 1.666 1.810 1.666 1.675 1.936 1.903 1.908 1.931 1.908 1.918 1.818 1.836 1.841 1.813 1.841 1.851 1.895 2.144 2.149 1.890 2.149 2.159 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 -1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 -1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-208 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-103 lists the EP3SE50 column pins output timing parameters for single-ended I/O standards. Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA 3.3-V LVTTL 12mA GCLK PLL GCLK GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA 3.3-V LVCMOS 12mA GCLK PLL GCLK GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA 3.0-V LVTTL 12mA GCLK PLL GCLK GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.293 3.550 3.176 3.483 3.081 3.397 3.041 3.390 3.296 3.556 3.096 3.401 3.059 3.408 3.043 3.392 3.238 3.514 3.108 3.403 3.033 3.367 3.000 3.349 3.293 3.524 3.176 3.457 3.081 3.371 3.051 3.364 3.296 3.530 3.096 3.375 3.069 3.382 3.053 3.366 3.238 3.488 3.108 3.377 3.033 3.341 3.010 3.323 4.559 4.903 4.405 4.794 4.268 4.691 4.243 4.674 4.563 4.908 4.273 4.701 4.236 4.695 4.212 4.672 4.508 4.870 4.339 4.740 4.250 4.677 4.188 4.648 4.925 5.402 5.329 5.819 4.763 5.232 5.218 5.706 4.620 5.080 5.120 5.614 4.596 5.055 5.092 5.573 4.937 5.416 5.334 5.826 4.625 5.086 5.137 5.625 4.594 5.055 5.116 5.599 4.553 5.025 5.090 5.570 4.876 5.367 5.298 5.786 4.704 5.205 5.164 5.648 4.605 5.103 5.095 5.574 4.536 5.053 5.067 5.546 5.282 5.674 5.112 5.561 4.960 5.469 4.935 5.428 5.296 5.681 4.966 5.480 4.935 5.454 4.904 5.425 5.247 5.641 5.086 5.504 4.984 5.430 4.934 5.401 5.365 5.973 5.252 5.860 5.162 5.768 5.120 5.727 5.373 5.980 5.172 5.779 5.148 5.753 5.119 5.724 5.356 5.940 5.239 5.801 5.175 5.728 5.152 5.700 4.925 5.402 5.329 5.819 4.763 5.232 5.218 5.706 4.620 5.080 5.120 5.614 4.596 5.055 5.092 5.573 4.937 5.416 5.334 5.826 4.625 5.086 5.137 5.625 4.594 5.055 5.116 5.599 4.553 5.025 5.090 5.570 4.876 5.367 5.298 5.786 4.704 5.205 5.164 5.648 4.605 5.103 5.095 5.574 4.536 5.053 5.067 5.546 5.282 5.674 5.112 5.561 4.960 5.469 4.935 5.428 5.296 5.681 4.966 5.480 4.935 5.454 4.904 5.425 5.247 5.641 5.086 5.504 4.984 5.430 4.934 5.401 5.365 5.973 5.252 5.860 5.162 5.768 5.120 5.727 5.373 5.980 5.172 5.779 5.148 5.753 5.119 5.724 5.356 5.940 5.239 5.801 5.175 5.728 5.152 5.700 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-209 Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 2 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA 3.0-V LVCMOS 12mA GCLK PLL GCLK GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA 2.5 V 12mA GCLK PLL GCLK GCLK PLL GCLK 16mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.8 V 8mA GCLK PLL GCLK GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.146 3.428 3.009 3.349 2.995 3.344 2.986 3.335 3.293 3.550 3.168 3.450 3.068 3.406 3.041 3.368 3.556 3.741 3.315 3.560 3.197 3.478 3.143 3.458 3.075 3.395 3.051 3.377 3.146 3.402 3.010 3.323 3.005 3.318 2.996 3.309 3.293 3.524 3.168 3.424 3.068 3.380 3.041 3.342 3.556 3.715 3.315 3.534 3.197 3.452 3.143 3.432 3.075 3.369 3.051 3.351 4.397 4.774 4.202 4.651 4.183 4.643 4.169 4.629 4.651 4.981 4.478 4.862 4.349 4.775 4.280 4.736 5.088 5.303 4.728 5.024 4.538 4.917 4.438 4.858 4.342 4.797 4.317 4.777 4.757 5.259 5.197 5.683 4.558 5.077 5.068 5.548 4.524 5.009 5.061 5.540 4.509 5.007 5.046 5.525 5.036 5.541 5.424 5.930 4.852 5.344 5.298 5.798 4.716 5.204 5.208 5.703 4.649 5.154 5.165 5.660 5.519 6.078 5.784 6.335 5.113 5.617 5.475 5.987 4.923 5.443 5.360 5.877 4.825 5.331 5.307 5.811 4.727 5.217 5.232 5.730 4.680 5.179 5.210 5.707 5.140 5.539 4.958 5.404 4.889 5.395 4.888 5.380 5.422 5.786 5.225 5.654 5.085 5.558 5.035 5.515 5.958 6.190 5.498 5.843 5.323 5.732 5.211 5.666 5.097 5.585 5.059 5.562 5.275 5.836 5.165 5.701 5.134 5.694 5.139 5.679 5.483 6.084 5.359 5.951 5.281 5.857 5.224 5.814 5.880 6.489 5.549 6.140 5.437 6.031 5.360 5.965 5.291 5.884 5.258 5.861 4.757 5.259 5.197 5.683 4.558 5.077 5.068 5.548 4.524 5.009 5.061 5.540 4.509 5.007 5.046 5.525 5.036 5.541 5.424 5.930 4.852 5.344 5.298 5.798 4.716 5.204 5.208 5.703 4.649 5.154 5.165 5.660 5.519 6.078 5.784 6.335 5.113 5.617 5.475 5.987 4.923 5.443 5.360 5.877 4.825 5.331 5.307 5.811 4.727 5.217 5.232 5.730 4.680 5.179 5.210 5.707 5.140 5.539 4.958 5.404 4.889 5.395 4.888 5.380 5.422 5.786 5.225 5.654 5.085 5.558 5.035 5.515 5.958 6.190 5.498 5.843 5.323 5.732 5.211 5.666 5.097 5.585 5.059 5.562 5.275 5.836 5.165 5.701 5.134 5.694 5.139 5.679 5.483 6.084 5.359 5.951 5.281 5.857 5.224 5.814 5.880 6.489 5.549 6.140 5.437 6.031 5.360 5.965 5.291 5.884 5.258 5.861 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-210 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 3 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.5 V 8mA GCLK PLL GCLK GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.2 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.464 3.687 3.181 3.475 3.103 3.450 3.093 3.439 3.063 3.384 3.030 3.379 3.354 3.603 3.181 3.480 3.094 3.442 3.070 3.395 3.058 3.395 3.055 3.392 3.043 3.390 3.032 3.381 3.464 3.661 3.181 3.449 3.111 3.424 3.100 3.413 3.063 3.358 3.040 3.353 3.354 3.577 3.181 3.454 3.103 3.416 3.070 3.369 3.058 3.369 3.055 3.366 3.051 3.364 3.042 3.355 4.981 5.231 4.527 4.912 4.427 4.845 4.409 4.828 4.330 4.790 4.314 4.774 4.868 5.157 4.546 4.932 4.419 4.839 4.351 4.811 4.312 4.768 4.305 4.765 4.305 4.765 4.291 4.751 5.429 5.995 5.717 6.273 4.916 5.439 5.360 5.881 4.808 5.322 5.300 5.814 4.787 5.290 5.275 5.794 4.709 5.208 5.225 5.724 4.676 5.168 5.213 5.713 5.328 5.915 5.652 6.217 4.947 5.486 5.391 5.931 4.806 5.331 5.301 5.818 4.746 5.240 5.252 5.762 4.677 5.188 5.200 5.693 4.670 5.193 5.196 5.689 4.666 5.174 5.197 5.690 4.644 5.140 5.182 5.675 5.875 6.128 5.319 5.736 5.202 5.669 5.170 5.649 5.088 5.579 5.047 5.568 5.795 6.072 5.366 5.786 5.211 5.673 5.120 5.617 5.068 5.548 5.074 5.544 5.054 5.545 5.020 5.530 5.825 6.427 5.439 6.035 5.362 5.968 5.345 5.948 5.282 5.878 5.261 5.867 5.765 6.371 5.480 6.085 5.366 5.972 5.319 5.916 5.276 5.847 5.271 5.843 5.272 5.844 5.256 5.829 5.429 5.995 5.717 6.273 4.916 5.439 5.360 5.881 4.808 5.322 5.300 5.814 4.787 5.290 5.275 5.794 4.709 5.208 5.225 5.724 4.676 5.168 5.213 5.713 5.328 5.915 5.652 6.217 4.947 5.486 5.391 5.931 4.806 5.331 5.301 5.818 4.746 5.240 5.252 5.762 4.677 5.188 5.200 5.693 4.670 5.193 5.196 5.689 4.666 5.174 5.197 5.690 4.644 5.140 5.182 5.675 5.875 6.128 5.319 5.736 5.202 5.669 5.170 5.649 5.088 5.579 5.047 5.568 5.795 6.072 5.366 5.786 5.211 5.673 5.120 5.617 5.068 5.548 5.074 5.544 5.054 5.545 5.020 5.530 5.825 6.427 5.439 6.035 5.362 5.968 5.345 5.948 5.282 5.878 5.261 5.867 5.765 6.371 5.480 6.085 5.366 5.972 5.319 5.916 5.276 5.847 5.271 5.843 5.272 5.844 5.256 5.829 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-2 CLASS I SSTL-2 CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-211 Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 4 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 8mA SSTL-18 CLASS II 16mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 8mA SSTL-15 CLASS II 16mA GCLK PLL GCLK GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.074 3.402 3.057 3.398 3.045 3.387 3.027 3.376 3.027 3.376 3.033 3.382 3.036 3.385 3.068 3.406 3.043 3.392 3.032 3.381 3.031 3.380 3.028 3.377 3.030 3.379 3.033 3.382 3.074 3.376 3.059 3.372 3.048 3.361 3.037 3.350 3.037 3.350 3.043 3.356 3.046 3.359 3.068 3.380 3.053 3.366 3.042 3.355 3.041 3.354 3.038 3.351 3.040 3.353 3.043 3.356 4.324 4.780 4.321 4.778 4.308 4.768 4.296 4.756 4.295 4.755 4.294 4.754 4.302 4.762 4.338 4.790 4.319 4.779 4.306 4.766 4.309 4.769 4.303 4.763 4.292 4.752 4.299 4.759 4.692 5.215 5.214 5.709 4.689 5.205 5.212 5.707 4.669 5.197 5.202 5.698 4.652 5.159 5.189 5.685 4.652 5.159 5.189 5.685 4.649 5.159 5.186 5.680 4.658 5.164 5.196 5.692 4.709 5.230 5.225 5.722 4.688 5.204 5.215 5.713 4.667 5.180 5.201 5.699 4.667 5.169 5.205 5.703 4.662 5.159 5.199 5.697 4.648 5.159 5.185 5.680 4.657 5.165 5.194 5.691 5.096 5.564 5.085 5.562 5.078 5.553 5.039 5.540 5.039 5.540 5.039 5.535 5.044 5.547 5.110 5.577 5.084 5.568 5.060 5.554 5.049 5.558 5.039 5.552 5.039 5.535 5.045 5.546 5.295 5.863 5.293 5.861 5.291 5.852 5.266 5.839 5.265 5.839 5.268 5.834 5.291 5.846 5.310 5.876 5.296 5.867 5.281 5.853 5.278 5.857 5.272 5.851 5.269 5.834 5.293 5.845 4.692 5.215 5.214 5.709 4.689 5.205 5.212 5.707 4.669 5.197 5.202 5.698 4.652 5.159 5.189 5.685 4.652 5.159 5.189 5.685 4.649 5.159 5.186 5.680 4.658 5.164 5.196 5.692 4.709 5.230 5.225 5.722 4.688 5.204 5.215 5.713 4.667 5.180 5.201 5.699 4.667 5.169 5.205 5.703 4.662 5.159 5.199 5.697 4.648 5.159 5.185 5.680 4.657 5.165 5.194 5.691 5.096 5.564 5.085 5.562 5.078 5.553 5.039 5.540 5.039 5.540 5.039 5.535 5.044 5.547 5.110 5.577 5.084 5.568 5.060 5.554 5.049 5.558 5.039 5.552 5.039 5.535 5.045 5.546 5.295 5.863 5.293 5.861 5.291 5.852 5.266 5.839 5.265 5.839 5.268 5.834 5.291 5.846 5.310 5.876 5.296 5.867 5.281 5.853 5.278 5.857 5.272 5.851 5.269 5.834 5.293 5.845 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS I SSTL-15 CLASS I (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-212 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 5 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.042 3.389 3.033 3.382 3.025 3.374 3.028 3.377 3.025 3.374 3.033 3.382 3.048 3.394 3.041 3.390 3.037 3.386 3.030 3.379 3.031 3.380 3.029 3.378 3.050 3.363 3.043 3.356 3.035 3.348 3.038 3.351 3.035 3.348 3.043 3.356 3.055 3.368 3.051 3.364 3.047 3.360 3.040 3.353 3.041 3.354 3.039 3.352 4.294 4.754 4.292 4.752 4.285 4.745 4.288 4.748 4.290 4.750 4.289 4.749 4.303 4.763 4.304 4.764 4.299 4.759 4.292 4.752 4.299 4.759 4.280 4.740 4.654 5.173 5.185 5.678 4.646 5.169 5.184 5.677 4.639 5.142 5.176 5.670 4.642 5.145 5.180 5.674 4.646 5.144 5.183 5.678 4.643 5.141 5.181 5.674 4.667 5.189 5.195 5.689 4.662 5.178 5.197 5.692 4.655 5.172 5.192 5.687 4.648 5.159 5.185 5.680 4.656 5.155 5.193 5.690 4.634 5.134 5.171 5.664 5.053 5.533 5.050 5.532 5.023 5.525 5.025 5.529 5.025 5.533 5.021 5.529 5.069 5.544 5.058 5.547 5.052 5.542 5.039 5.535 5.035 5.545 5.014 5.519 5.270 5.832 5.275 5.831 5.257 5.824 5.260 5.828 5.267 5.832 5.271 5.828 5.283 5.843 5.280 5.846 5.275 5.841 5.269 5.834 5.272 5.844 5.257 5.818 4.654 5.173 5.185 5.678 4.646 5.169 5.184 5.677 4.639 5.142 5.176 5.670 4.642 5.145 5.180 5.674 4.646 5.144 5.183 5.678 4.643 5.141 5.181 5.674 4.667 5.189 5.195 5.689 4.662 5.178 5.197 5.692 4.655 5.172 5.192 5.687 4.648 5.159 5.185 5.680 4.656 5.155 5.193 5.690 4.634 5.134 5.171 5.664 5.053 5.533 5.050 5.532 5.023 5.525 5.025 5.529 5.025 5.533 5.021 5.529 5.069 5.544 5.058 5.547 5.052 5.542 5.039 5.535 5.035 5.545 5.014 5.519 5.270 5.832 5.275 5.831 5.257 5.824 5.260 5.828 5.267 5.832 5.271 5.828 5.283 5.843 5.280 5.846 5.275 5.841 5.269 5.834 5.272 5.844 5.257 5.818 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8-V HSTL CLASS I 1.8-V HSTL CLASS II 1.5-V HSTL CLASS I 1.5-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-213 Table 1-103. EP3SE50 Column Pins Output Timing Parameters (Part 6 of 6) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 3.0-V PCI -- GCLK PLL GCLK -- GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.048 3.397 3.040 3.389 3.041 3.390 3.030 3.379 3.030 3.379 3.061 3.400 3.154 3.503 3.154 3.503 3.058 3.371 3.050 3.363 3.051 3.364 3.040 3.353 3.040 3.353 3.061 3.374 3.164 3.477 3.164 3.477 4.317 4.777 4.308 4.768 4.315 4.775 4.302 4.762 4.302 4.762 4.318 4.778 4.363 4.823 4.363 4.823 4.683 5.208 5.212 5.710 4.668 5.191 5.203 5.701 4.674 5.187 5.212 5.710 4.661 5.164 5.198 5.696 4.661 5.165 5.198 5.697 4.685 5.243 5.213 5.710 4.710 5.218 5.247 5.735 4.710 5.218 5.247 5.735 5.088 5.565 5.071 5.556 5.067 5.565 5.044 5.551 5.045 5.552 5.123 5.565 5.098 5.590 5.098 5.590 5.302 5.864 5.290 5.855 5.293 5.864 5.287 5.850 5.279 5.851 5.316 5.864 5.347 5.889 5.347 5.889 4.683 5.208 5.212 5.710 4.668 5.191 5.203 5.701 4.674 5.187 5.212 5.710 4.661 5.164 5.198 5.696 4.661 5.165 5.198 5.697 4.685 5.243 5.213 5.710 4.710 5.218 5.247 5.735 4.710 5.218 5.247 5.735 5.088 5.565 5.071 5.556 5.067 5.565 5.044 5.551 5.045 5.552 5.123 5.565 5.098 5.590 5.098 5.590 5.302 5.864 5.290 5.855 5.293 5.864 5.287 5.850 5.279 5.851 5.316 5.864 5.347 5.889 5.347 5.889 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 1.2-V HSTL CLASS II 3.0-V PCI-X Table 1-104 lists the EP3SE50 row pins output timing parameters for single-ended I/O standards. Table 1-104. EP3SE50 Row Pins Output Timing Parameters (Part 1 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL tco tco tco tco tco tco 3.161 1.488 3.095 1.395 3.016 1.314 3.395 1.692 3.324 1.587 3.235 1.493 4.722 5.117 5.622 5.486 5.755 5.247 5.754 5.618 5.832 2.101 2.185 2.381 2.400 2.349 2.304 2.505 2.523 2.344 4.612 5.005 5.508 5.372 5.611 5.134 5.638 5.502 5.683 1.971 2.047 2.237 2.256 2.205 2.163 2.356 2.374 2.195 4.506 4.905 5.412 5.276 5.483 5.035 5.539 5.403 5.551 1.852 1.924 2.109 2.128 2.077 2.036 2.224 2.242 2.063 ns ns ns ns ns ns 3.3-V LVTTL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-214 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-104. EP3SE50 Row Pins Output Timing Parameters (Part 2 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.163 1.498 3.020 1.318 3.122 1.442 3.021 1.319 2.984 1.282 3.043 1.356 2.971 1.269 3.148 1.468 3.063 1.361 3.006 1.312 3.405 1.650 3.180 1.477 3.115 1.402 3.055 1.384 3.402 1.696 3.239 1.497 3.356 1.638 3.244 1.511 3.206 1.464 3.268 1.557 3.190 1.448 3.393 1.674 3.290 1.575 3.246 1.504 3.663 1.863 3.461 1.677 3.359 1.595 3.285 1.575 4.726 5.122 5.631 5.495 5.760 5.255 5.766 5.630 5.837 2.109 2.190 2.386 2.405 2.354 2.310 2.510 2.528 2.349 4.517 4.920 5.422 5.286 5.489 5.047 5.548 5.412 5.558 1.858 1.930 2.115 2.134 2.083 2.042 2.231 2.249 2.070 4.689 5.085 5.588 5.452 5.712 5.215 5.720 5.584 5.790 2.053 2.138 2.338 2.357 2.306 2.261 2.463 2.481 2.302 4.552 4.943 5.443 5.307 5.548 5.073 5.575 5.438 5.625 1.900 1.979 2.174 2.193 2.142 2.099 2.299 2.316 2.137 4.492 4.878 5.373 5.237 5.460 5.005 5.501 5.365 5.532 1.818 1.896 2.086 2.105 2.054 2.013 2.206 2.223 2.044 4.587 4.978 5.479 5.343 5.601 5.107 5.611 5.474 5.678 1.947 2.031 2.227 2.246 2.195 2.153 2.352 2.369 2.190 4.464 4.849 5.345 5.209 5.421 4.975 5.473 5.336 5.492 1.783 1.857 2.047 2.066 2.015 1.973 2.166 2.183 2.004 4.797 5.211 5.733 5.597 5.884 5.347 5.872 5.736 5.968 2.185 2.292 2.510 2.529 2.478 2.421 2.642 2.659 2.480 4.673 5.076 5.591 5.455 5.714 5.210 5.728 5.591 5.794 2.030 2.129 2.340 2.359 2.308 2.254 2.468 2.485 2.306 4.589 4.990 5.500 5.364 5.588 5.121 5.633 5.497 5.664 1.919 2.010 2.214 2.233 2.182 2.131 2.338 2.355 2.176 5.253 5.717 6.292 6.156 6.368 5.867 6.444 6.308 6.461 2.459 2.597 2.849 2.868 2.787 2.729 2.984 3.002 2.793 4.926 5.349 5.887 5.751 5.963 5.502 6.038 5.901 6.054 2.168 2.271 2.489 2.508 2.427 2.403 2.623 2.640 2.431 4.773 5.199 5.728 5.592 5.804 5.334 5.865 5.729 5.882 2.069 2.166 2.388 2.407 2.326 2.289 2.517 2.535 2.326 4.696 5.106 5.632 5.496 5.708 5.239 5.771 5.635 5.788 2.012 2.113 2.323 2.342 2.261 2.233 2.445 2.463 2.254 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 4mA 3.0-V LVCMOS 8mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-215 Table 1-104. EP3SE50 Row Pins Output Timing Parameters (Part 3 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA GCLK PLL GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.316 1.592 3.074 1.400 3.047 1.373 3.038 1.354 3.259 1.522 3.079 1.405 3.010 1.308 3.005 1.303 2.996 1.294 3.016 1.333 3.001 1.328 2.990 1.317 2.966 1.306 2.966 1.306 3.581 1.806 3.324 1.592 3.276 1.566 3.267 1.555 3.506 1.719 3.317 1.596 3.234 1.492 3.230 1.488 3.219 1.477 3.241 1.519 3.227 1.514 3.215 1.503 3.192 1.492 3.191 1.491 5.163 5.631 6.220 6.084 6.296 5.774 6.368 6.232 6.385 2.387 2.524 2.786 2.805 2.724 2.650 2.919 2.937 2.728 4.758 5.194 5.729 5.593 5.805 5.328 5.864 5.728 5.881 2.065 2.166 2.392 2.411 2.330 2.286 2.518 2.536 2.327 4.685 5.098 5.623 5.487 5.699 5.230 5.759 5.623 5.776 1.996 2.105 2.323 2.342 2.261 2.226 2.445 2.463 2.254 4.663 5.080 5.604 5.468 5.680 5.212 5.737 5.601 5.754 1.980 2.081 2.304 2.323 2.242 2.202 2.426 2.444 2.235 5.073 5.545 6.145 6.009 6.221 5.686 6.284 6.148 6.301 2.308 2.456 2.725 2.744 2.663 2.582 2.850 2.868 2.659 4.780 5.222 5.770 5.634 5.846 5.353 5.906 5.770 5.923 2.082 2.194 2.440 2.459 2.378 2.315 2.562 2.580 2.371 4.582 4.981 5.490 5.354 5.556 5.108 5.619 5.483 5.627 1.899 1.984 2.183 2.202 2.150 2.100 2.301 2.318 2.139 4.579 4.979 5.488 5.352 5.548 5.107 5.618 5.482 5.620 1.896 1.982 2.181 2.200 2.142 2.099 2.300 2.317 2.132 4.564 4.963 5.471 5.335 5.521 5.090 5.600 5.464 5.593 1.881 1.966 2.164 2.183 2.115 2.082 2.282 2.299 2.105 4.591 4.993 5.505 5.369 5.581 5.120 5.634 5.498 5.651 1.931 2.017 2.218 2.237 2.156 2.132 2.336 2.354 2.145 4.588 4.991 5.503 5.367 5.579 5.118 5.632 5.496 5.649 1.929 2.016 2.217 2.236 2.155 2.130 2.334 2.352 2.143 4.571 4.974 5.486 5.350 5.562 5.101 5.616 5.480 5.633 1.919 2.006 2.207 2.226 2.145 2.121 2.325 2.343 2.134 4.555 4.958 5.471 5.335 5.547 5.086 5.601 5.465 5.618 1.906 1.993 2.194 2.213 2.132 2.109 2.313 2.331 2.122 4.554 4.957 5.470 5.334 5.546 5.085 5.600 5.464 5.617 1.906 1.993 2.194 2.213 2.132 2.108 2.313 2.331 2.122 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 V 1.2 V SSTL-2 CLASS I 12mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK SSTL-18 CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-216 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-104. EP3SE50 Row Pins Output Timing Parameters (Part 4 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 8mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.976 1.314 2.975 1.315 3.012 1.336 2.989 1.322 2.972 1.311 2.991 1.321 2.979 1.314 2.966 1.305 2.968 1.308 2.964 1.304 2.972 1.312 2.998 1.327 2.986 1.321 2.982 1.317 3.200 1.498 3.198 1.501 3.237 1.522 3.215 1.508 3.198 1.496 3.213 1.504 3.201 1.498 3.189 1.490 3.191 1.492 3.186 1.489 3.194 1.497 3.220 1.510 3.210 1.505 3.205 1.501 4.552 4.953 5.464 5.328 5.540 5.080 5.593 5.457 5.610 1.905 1.990 2.189 2.208 2.127 2.104 2.307 2.325 2.116 4.551 4.954 5.466 5.330 5.542 5.082 5.597 5.461 5.614 1.911 1.998 2.199 2.218 2.137 2.113 2.318 2.336 2.127 4.602 5.007 5.522 5.386 5.598 5.133 5.650 5.514 5.667 1.940 2.028 2.231 2.250 2.169 2.142 2.348 2.366 2.157 4.584 4.990 5.505 5.369 5.581 5.117 5.634 5.498 5.651 1.929 2.018 2.221 2.240 2.159 2.133 2.339 2.357 2.148 4.567 4.972 5.487 5.351 5.563 5.099 5.617 5.481 5.634 1.916 2.005 2.208 2.227 2.146 2.120 2.326 2.344 2.135 4.558 4.958 5.467 5.331 5.543 5.084 5.596 5.460 5.613 1.904 1.988 2.187 2.206 2.125 2.103 2.304 2.322 2.113 4.549 4.950 5.459 5.323 5.535 5.076 5.589 5.453 5.606 1.902 1.987 2.186 2.205 2.124 2.102 2.304 2.322 2.113 4.541 4.941 5.451 5.315 5.527 5.068 5.581 5.445 5.598 1.895 1.980 2.179 2.198 2.117 2.095 2.297 2.315 2.106 4.543 4.944 5.454 5.318 5.530 5.071 5.584 5.448 5.601 1.898 1.983 2.183 2.202 2.121 2.098 2.300 2.318 2.109 4.541 4.943 5.454 5.318 5.530 5.071 5.585 5.449 5.602 1.900 1.986 2.186 2.205 2.124 2.101 2.305 2.323 2.114 4.536 4.935 5.445 5.309 5.521 5.062 5.574 5.438 5.591 1.898 1.983 2.182 2.201 2.120 2.097 2.299 2.317 2.108 4.569 4.971 5.482 5.346 5.558 5.096 5.610 5.474 5.627 1.913 1.998 2.198 2.217 2.136 2.112 2.315 2.333 2.124 4.565 4.967 5.478 5.342 5.554 5.093 5.607 5.471 5.624 1.914 2.000 2.200 2.219 2.138 2.114 2.318 2.336 2.127 4.559 4.961 5.472 5.336 5.548 5.087 5.601 5.465 5.618 1.909 1.995 2.195 2.214 2.133 2.109 2.312 2.330 2.121 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS II 16mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 1.8-V HSTL CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 1.8-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 1.5-V HSTL CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-217 Table 1-104. EP3SE50 Row Pins Output Timing Parameters (Part 5 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco 2.997 1.329 2.985 1.320 2.982 1.319 3.116 1.414 3.116 1.414 3.219 1.512 3.207 1.504 3.205 1.504 3.340 1.598 3.340 1.598 4.580 4.985 5.500 5.364 5.576 5.110 5.627 5.491 5.644 1.926 2.014 2.217 2.236 2.155 2.128 2.334 2.352 2.143 4.569 4.973 5.488 5.352 5.564 5.099 5.616 5.480 5.633 1.917 2.005 2.208 2.227 2.146 2.119 2.325 2.343 2.134 4.573 4.978 5.494 5.358 5.570 5.105 5.623 5.487 5.640 1.924 2.013 2.217 2.236 2.155 2.128 2.335 2.353 2.144 4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651 1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151 4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651 1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151 ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Table 1-115 through Table 1-108 list the maximum I/O timing parameters for EP3SE50 devices for differential I/O standards. Table 1-105 lists the EP3SE50 column pins input timing parameters for differential I/O standards. Table 1-105. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -0.730 0.848 1.120 -0.867 -0.730 0.848 1.120 -0.867 -0.738 0.856 1.112 -0.859 -0.738 0.856 1.112 -0.859 -0.751 0.884 1.138 -0.870 -0.751 0.884 1.138 -0.870 -0.763 0.896 1.126 -0.858 -0.763 0.896 1.126 -0.858 -1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 1.299 1.796 1.436 2.027 1.571 2.253 1.501 2.141 1.798 2.145 1.446 2.036 1.583 2.262 1.516 2.145 1.835 2.193 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 -1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 1.299 1.796 1.436 2.027 1.571 2.253 1.501 2.141 1.798 2.145 1.446 2.036 1.583 2.262 1.516 2.145 1.835 2.193 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 -1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 1.309 1.786 1.447 2.016 1.587 2.237 1.517 2.125 1.814 2.129 1.457 2.025 1.598 2.247 1.531 2.130 1.850 2.178 RSDS GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th -1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 -1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 1.309 1.786 1.447 2.016 1.587 2.237 1.517 2.125 1.814 2.129 1.457 2.025 1.598 2.247 1.531 2.130 1.850 2.178 DIFFERENTIAL 1.2-V HSTL CLASS I -1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-218 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-105. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.2-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.750 0.868 1.100 -0.847 -0.750 0.868 1.100 -0.847 -0.738 0.856 1.112 -0.859 -0.738 0.856 1.112 -0.859 -0.750 0.868 1.100 -0.847 -0.750 0.868 1.100 -0.847 -0.757 0.875 1.093 -0.840 -0.757 0.875 1.093 -0.840 -0.730 0.848 1.120 -0.867 -0.774 0.907 1.115 -0.847 -0.774 0.907 1.115 -0.847 -0.763 0.896 1.126 -0.858 -0.763 0.896 1.126 -0.858 -0.774 0.907 1.115 -0.847 -0.774 0.907 1.115 -0.847 -0.780 0.913 1.109 -0.841 -0.780 0.913 1.109 -0.841 -0.751 0.884 1.138 -0.870 -1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 1.319 1.777 1.458 2.005 1.606 2.218 1.536 2.106 1.833 2.110 1.468 2.014 1.616 2.229 1.549 2.112 1.868 2.160 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 -1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 1.319 1.777 1.458 2.005 1.606 2.218 1.536 2.106 1.833 2.110 1.468 2.014 1.616 2.229 1.549 2.112 1.868 2.160 DIFFERENTIAL 1.5-V HSTL CLASS I -1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 -1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 1.309 1.786 1.447 2.016 1.587 2.237 1.517 2.125 1.814 2.129 1.457 2.025 1.598 2.247 1.531 2.130 1.850 2.178 DIFFERENTIAL 1.5-V HSTL CLASS II -1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 -1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 1.309 1.786 1.447 2.016 1.587 2.237 1.517 2.125 1.814 2.129 1.457 2.025 1.598 2.247 1.531 2.130 1.850 2.178 DIFFERENTIAL 1.8-V HSTL CLASS I -1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 -1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 1.319 1.777 1.458 2.005 1.606 2.218 1.536 2.106 1.833 2.110 1.468 2.014 1.616 2.229 1.549 2.112 1.868 2.160 DIFFERENTIAL 1.8-V HSTL CLASS II -1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 -1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 1.319 1.777 1.458 2.005 1.606 2.218 1.536 2.106 1.833 2.110 1.468 2.014 1.616 2.229 1.549 2.112 1.868 2.160 DIFFERENTIAL 1.5-V SSTL CLASS I -1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 -1.145 -1.255 -1.376 -1.321 -1.615 -1.256 -1.372 -1.321 -1.646 1.332 1.765 1.466 2.000 1.609 2.218 1.539 2.104 1.837 2.111 1.475 2.010 1.616 2.234 1.548 2.114 1.869 2.164 DIFFERENTIAL 1.5-V SSTL CLASS II -1.364 -1.548 -1.714 -1.631 -1.627 -1.551 -1.721 -1.633 -1.676 -1.145 -1.255 -1.376 -1.321 -1.615 -1.256 -1.372 -1.321 -1.646 1.332 1.765 1.466 2.000 1.609 2.218 1.539 2.104 1.837 2.111 1.475 2.010 1.616 2.234 1.548 2.114 1.869 2.164 DIFFERENTIAL 1.8-V SSTL CLASS I -1.364 -1.548 -1.714 -1.631 -1.627 -1.551 -1.721 -1.633 -1.676 -1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 1.299 1.796 1.436 2.027 1.571 2.253 1.501 2.141 1.798 2.145 1.446 2.036 1.583 2.262 1.516 2.145 1.835 2.193 DIFFERENTIAL 1.8-V SSTL CLASS II -1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-219 Table 1-105. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th -0.730 0.848 1.120 -0.867 -0.738 0.856 1.112 -0.859 -0.751 0.884 1.138 -0.870 -0.763 0.896 1.126 -0.858 -1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 1.299 1.796 1.436 2.027 1.571 2.253 1.501 2.141 1.798 2.145 1.446 2.036 1.583 2.262 1.516 2.145 1.835 2.193 ns ns ns ns ns ns ns ns -1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 -1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 1.309 1.786 1.447 2.016 1.587 2.237 1.517 2.125 1.814 2.129 1.457 2.025 1.598 2.247 1.531 2.130 1.850 2.178 DIFFERENTIAL 2.5-V SSTL CLASS II -1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 Table 1-106 lists the EP3SE50 row pins input timing parameters for differential I/O standards. Table 1-106. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -0.925 1.048 0.886 -0.626 -0.925 1.048 0.886 -0.626 -0.925 1.048 0.886 -0.626 -0.740 0.856 1.081 -0.828 -0.740 0.856 1.081 -0.828 -0.948 1.086 0.901 -0.628 -0.948 1.086 0.901 -0.628 -0.948 1.086 0.901 -0.628 -0.773 0.902 1.086 -0.822 -0.773 0.902 1.086 -0.822 -1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 1.223 1.866 1.219 2.244 1.381 2.450 1.322 2.324 1.601 2.344 1.199 2.289 1.353 2.502 1.296 2.376 1.634 2.396 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 -1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 1.223 1.866 1.219 2.244 1.381 2.450 1.322 2.324 1.601 2.344 1.199 2.289 1.353 2.502 1.296 2.376 1.634 2.396 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 -1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 1.223 1.866 1.219 2.244 1.381 2.450 1.322 2.324 1.601 2.344 1.199 2.289 1.353 2.502 1.296 2.376 1.634 2.396 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th -1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 -1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 1.288 1.779 1.408 2.020 1.531 2.261 1.467 2.140 1.741 2.165 1.427 2.022 1.548 2.265 1.486 2.144 1.779 2.212 DIFFERENTIAL 1.2-V HSTL CLASS I -1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 -1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 1.288 1.779 1.408 2.020 1.531 2.261 1.467 2.140 1.741 2.165 1.427 2.022 1.548 2.265 1.486 2.144 1.779 2.212 DIFFERENTIAL 1.2-V HSTL CLASS II -1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-220 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-106. EP3SE50 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.5-V HSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.749 0.865 1.072 -0.819 -0.749 0.865 1.072 -0.819 -0.763 0.879 1.058 -0.805 -0.763 0.879 1.058 -0.805 -0.749 0.865 1.072 -0.819 -0.749 0.865 1.072 -0.819 -0.763 0.879 1.058 -0.805 -0.763 0.879 1.058 -0.805 -0.762 0.878 1.049 -0.796 -0.785 0.914 1.074 -0.810 -0.785 0.914 1.074 -0.810 -0.797 0.926 1.062 -0.798 -0.797 0.926 1.062 -0.798 -0.785 0.914 1.074 -0.810 -0.785 0.914 1.074 -0.810 -0.797 0.926 1.062 -0.798 -0.797 0.926 1.062 -0.798 -0.796 0.925 1.053 -0.789 -1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 1.297 1.770 1.418 2.010 1.547 2.245 1.483 2.124 1.757 2.149 1.436 2.013 1.564 2.249 1.502 2.128 1.795 2.196 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 -1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 1.297 1.770 1.418 2.010 1.547 2.245 1.483 2.124 1.757 2.149 1.436 2.013 1.564 2.249 1.502 2.128 1.795 2.196 DIFFERENTIAL 1.5-V HSTL CLASS II -1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 -1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 1.309 1.757 1.428 2.000 1.565 2.227 1.501 2.106 1.775 2.131 1.447 2.002 1.581 2.232 1.519 2.111 1.812 2.179 DIFFERENTIAL 1.8-V HSTL CLASS I -1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 -1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 1.309 1.757 1.428 2.000 1.565 2.227 1.501 2.106 1.775 2.131 1.447 2.002 1.581 2.232 1.519 2.111 1.812 2.179 DIFFERENTIAL 1.8-V HSTL CLASS II -1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 -1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 1.297 1.770 1.418 2.010 1.547 2.245 1.483 2.124 1.757 2.149 1.436 2.013 1.564 2.249 1.502 2.128 1.795 2.196 DIFFERENTIAL 1.5-V SSTL CLASS I -1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 -1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 1.297 1.770 1.418 2.010 1.547 2.245 1.483 2.124 1.757 2.149 1.436 2.013 1.564 2.249 1.502 2.128 1.795 2.196 DIFFERENTIAL 1.5-V SSTL CLASS II -1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 -1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 1.309 1.757 1.428 2.000 1.565 2.227 1.501 2.106 1.775 2.131 1.447 2.002 1.581 2.232 1.519 2.111 1.812 2.179 DIFFERENTIAL 1.8-V SSTL CLASS I -1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 -1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 1.309 1.757 1.428 2.000 1.565 2.227 1.501 2.106 1.775 2.131 1.447 2.002 1.581 2.232 1.519 2.111 1.812 2.179 DIFFERENTIAL 1.8-V SSTL CLASS II -1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 -1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593 1.314 1.742 1.436 1.984 1.569 2.216 1.505 2.094 1.780 2.120 1.451 1.991 1.580 2.226 1.518 2.103 1.813 2.172 DIFFERENTIAL 2.5-V SSTL CLASS I -1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-221 Table 1-106. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS II GCLK GCLK PLL tsu th tsu th -0.762 0.878 1.049 -0.796 -0.796 0.925 1.053 -0.789 -1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593 1.314 1.742 1.436 1.984 1.569 2.216 1.505 2.094 1.780 2.120 1.451 1.991 1.580 2.226 1.518 2.103 1.813 2.172 ns ns ns ns -1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688 Table 1-107 lists the EP3SE50 column pins output timing parameters for differential I/O standards. Table 1-107. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco 3.058 3.054 3.058 3.054 3.058 3.054 3.085 3.075 3.075 3.068 3.067 3.089 3.277 3.280 3.277 3.280 3.277 3.280 3.310 3.300 3.300 3.294 3.292 3.314 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.681 5.092 5.611 5.469 5.698 5.220 5.740 5.600 5.766 4.671 5.081 5.601 5.459 5.688 5.209 5.730 5.590 5.756 4.674 5.085 5.605 5.463 5.692 5.214 5.735 5.595 5.761 4.667 5.079 5.599 5.457 5.686 5.207 5.729 5.589 5.755 4.664 5.076 5.596 5.454 5.683 5.204 5.725 5.585 5.751 4.685 5.096 5.615 5.473 5.702 5.224 5.745 5.605 5.771 ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-222 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-107. EP3SE50 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.079 3.074 3.072 3.064 3.065 3.064 3.076 3.072 3.062 3.060 3.060 3.064 3.090 3.076 3.064 3.064 3.060 3.064 3.065 3.093 3.082 3.077 3.063 3.061 3.303 3.299 3.297 3.288 3.290 3.287 3.300 3.297 3.286 3.284 3.285 3.288 3.317 3.303 3.290 3.290 3.286 3.288 3.290 3.320 3.308 3.304 3.289 3.287 4.664 5.073 5.590 5.448 5.677 5.200 5.718 5.578 5.744 4.664 5.073 5.591 5.449 5.678 5.201 5.720 5.580 5.746 4.663 5.072 5.589 5.447 5.676 5.200 5.719 5.579 5.745 4.653 5.062 5.580 5.438 5.667 5.190 5.709 5.569 5.735 4.659 5.069 5.588 5.446 5.675 5.198 5.718 5.578 5.744 4.642 5.050 5.566 5.424 5.653 5.177 5.694 5.554 5.720 4.660 5.068 5.584 5.442 5.671 5.196 5.713 5.573 5.739 4.661 5.070 5.588 5.446 5.675 5.198 5.717 5.577 5.743 4.650 5.059 5.576 5.434 5.663 5.187 5.705 5.565 5.731 4.648 5.056 5.574 5.432 5.661 5.185 5.703 5.563 5.729 4.651 5.061 5.579 5.437 5.666 5.189 5.709 5.569 5.735 4.648 5.056 5.573 5.431 5.660 5.184 5.702 5.562 5.728 4.693 5.104 5.623 5.481 5.710 5.232 5.752 5.612 5.778 4.681 5.093 5.613 5.471 5.700 5.222 5.743 5.603 5.769 4.664 5.075 5.595 5.453 5.682 5.204 5.725 5.585 5.751 4.667 5.079 5.599 5.457 5.686 5.208 5.730 5.590 5.756 4.660 5.071 5.592 5.450 5.679 5.201 5.722 5.582 5.748 4.653 5.062 5.580 5.438 5.667 5.190 5.709 5.569 5.735 4.661 5.072 5.591 5.449 5.678 5.200 5.721 5.581 5.747 4.692 5.102 5.621 5.479 5.708 5.231 5.750 5.610 5.776 4.680 5.090 5.609 5.467 5.696 5.219 5.738 5.598 5.764 4.680 5.091 5.610 5.468 5.697 5.220 5.740 5.600 5.766 4.662 5.072 5.591 5.449 5.678 5.201 5.722 5.582 5.748 4.660 5.070 5.589 5.447 5.676 5.199 5.719 5.579 5.745 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-223 Table 1-107. EP3SE50 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.065 3.065 3.081 3.081 3.071 3.064 3.058 3.054 3.058 3.054 3.058 3.054 3.085 3.075 3.075 3.068 3.067 3.089 3.079 3.074 3.072 3.064 3.065 3.064 3.076 3.072 3.289 3.290 3.307 3.307 3.297 3.289 3.277 3.280 3.277 3.280 3.277 3.280 3.310 3.300 3.300 3.294 3.292 3.314 3.303 3.299 3.297 3.288 3.290 3.287 3.300 3.297 4.652 5.060 5.577 5.435 5.664 5.188 5.706 5.566 5.732 4.660 5.070 5.589 5.447 5.676 5.199 5.719 5.579 5.745 4.676 5.085 5.603 5.461 5.690 5.214 5.732 5.592 5.758 4.676 5.085 5.603 5.461 5.690 5.214 5.732 5.592 5.758 4.666 5.075 5.593 5.451 5.680 5.204 5.723 5.583 5.749 4.652 5.060 5.577 5.435 5.664 5.188 5.706 5.566 5.732 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 4.681 5.092 5.611 5.469 5.698 5.220 5.740 5.600 5.766 4.671 5.081 5.601 5.459 5.688 5.209 5.730 5.590 5.756 4.674 5.085 5.605 5.463 5.692 5.214 5.735 5.595 5.761 4.667 5.079 5.599 5.457 5.686 5.207 5.729 5.589 5.755 4.664 5.076 5.596 5.454 5.683 5.204 5.725 5.585 5.751 4.685 5.096 5.615 5.473 5.702 5.224 5.745 5.605 5.771 4.664 5.073 5.590 5.448 5.677 5.200 5.718 5.578 5.744 4.664 5.073 5.591 5.449 5.678 5.201 5.720 5.580 5.746 4.663 5.072 5.589 5.447 5.676 5.200 5.719 5.579 5.745 4.653 5.062 5.580 5.438 5.667 5.190 5.709 5.569 5.735 4.659 5.069 5.588 5.446 5.675 5.198 5.718 5.578 5.744 4.642 5.050 5.566 5.424 5.653 5.177 5.694 5.554 5.720 4.660 5.068 5.584 5.442 5.671 5.196 5.713 5.573 5.739 4.661 5.070 5.588 5.446 5.675 5.198 5.717 5.577 5.743 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-224 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-107. EP3SE50 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.062 3.060 3.060 3.064 3.090 3.076 3.064 3.064 3.060 3.064 3.065 3.093 3.082 3.077 3.063 3.061 3.065 3.065 3.081 3.081 3.071 3.064 3.286 3.284 3.285 3.288 3.317 3.303 3.290 3.290 3.286 3.288 3.290 3.320 3.308 3.304 3.289 3.287 3.289 3.290 3.307 3.307 3.297 3.289 4.650 5.059 5.576 5.434 5.663 5.187 5.705 5.565 5.731 4.648 5.056 5.574 5.432 5.661 5.185 5.703 5.563 5.729 4.651 5.061 5.579 5.437 5.666 5.189 5.709 5.569 5.735 4.648 5.056 5.573 5.431 5.660 5.184 5.702 5.562 5.728 4.693 5.104 5.623 5.481 5.710 5.232 5.752 5.612 5.778 4.681 5.093 5.613 5.471 5.700 5.222 5.743 5.603 5.769 4.664 5.075 5.595 5.453 5.682 5.204 5.725 5.585 5.751 4.667 5.079 5.599 5.457 5.686 5.208 5.730 5.590 5.756 4.660 5.071 5.592 5.450 5.679 5.201 5.722 5.582 5.748 4.653 5.062 5.580 5.438 5.667 5.190 5.709 5.569 5.735 4.661 5.072 5.591 5.449 5.678 5.200 5.721 5.581 5.747 4.692 5.102 5.621 5.479 5.708 5.231 5.750 5.610 5.776 4.680 5.090 5.609 5.467 5.696 5.219 5.738 5.598 5.764 4.680 5.091 5.610 5.468 5.697 5.220 5.740 5.600 5.766 4.662 5.072 5.591 5.449 5.678 5.201 5.722 5.582 5.748 4.660 5.070 5.589 5.447 5.676 5.199 5.719 5.579 5.745 4.652 5.060 5.577 5.435 5.664 5.188 5.706 5.566 5.732 4.660 5.070 5.589 5.447 5.676 5.199 5.719 5.579 5.745 4.676 5.085 5.603 5.461 5.690 5.214 5.732 5.592 5.758 4.676 5.085 5.603 5.461 5.690 5.214 5.732 5.592 5.758 4.666 5.075 5.593 5.451 5.680 5.204 5.723 5.583 5.749 4.652 5.060 5.577 5.435 5.664 5.188 5.706 5.566 5.732 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 8mA DIFFERENTIAL 2.5-V SSTL CLASS I GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-225 Table 1-108 lists the EP3SE50 row pins output timing parameters for differential I/O standards. Table 1-108. EP3SE50 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.674 3.068 3.050 2.674 3.068 3.050 2.674 3.068 3.050 3.104 3.090 3.086 3.102 3.091 3.088 3.099 3.089 3.075 3.072 3.069 3.070 3.119 3.095 3.077 2.849 3.295 3.285 2.849 3.295 3.285 2.849 3.295 3.285 3.338 3.324 3.320 3.335 3.325 3.322 3.332 3.323 3.309 3.305 3.303 3.303 3.356 3.332 3.313 3.990 4.657 4.695 3.990 4.657 4.695 3.990 4.657 4.695 4.741 4.728 4.726 4.727 4.723 4.721 4.722 4.720 4.705 4.701 4.702 4.692 4.763 4.745 4.723 4.359 4.834 5.068 5.588 5.114 5.642 4.359 4.834 5.068 5.588 5.114 5.642 4.359 4.834 5.068 5.588 5.114 5.642 5.158 5.685 5.145 5.672 5.145 5.673 5.142 5.667 5.138 5.664 5.136 5.662 5.137 5.661 5.135 5.660 5.120 5.646 5.116 5.642 5.119 5.645 5.107 5.632 5.180 5.708 5.163 5.691 5.141 5.669 4.699 5.445 5.499 4.699 5.445 5.499 4.699 5.445 5.499 5.542 5.529 5.530 5.524 5.521 5.519 5.518 5.517 5.503 5.499 5.502 5.489 5.565 5.548 5.526 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 5.745 5.294 5.824 5.679 5.815 5.732 5.280 5.811 5.666 5.802 5.733 5.280 5.813 5.668 5.804 5.727 5.277 5.806 5.661 5.797 5.724 5.274 5.803 5.658 5.794 5.722 5.272 5.802 5.657 5.793 5.721 5.271 5.800 5.655 5.791 5.720 5.271 5.800 5.655 5.791 5.706 5.256 5.785 5.640 5.776 5.702 5.252 5.781 5.636 5.772 5.705 5.255 5.785 5.640 5.776 5.692 5.242 5.771 5.626 5.762 5.768 5.316 5.847 5.702 5.838 5.751 5.299 5.832 5.687 5.823 5.729 5.277 5.810 5.665 5.801 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-226 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-108. EP3SE50 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.123 3.108 3.097 3.077 3.074 3.079 3.072 3.100 3.082 3.068 2.674 3.068 3.050 2.674 3.068 3.050 2.674 3.068 3.050 3.104 3.090 3.086 3.102 3.091 3.359 3.344 3.333 3.313 3.309 3.313 3.306 3.335 3.318 3.302 2.849 3.295 3.285 2.849 3.295 3.285 2.849 3.295 3.285 3.338 3.324 3.320 3.335 3.325 4.763 4.749 4.744 4.721 4.717 4.708 4.707 4.735 4.720 4.697 3.990 4.657 4.695 3.990 4.657 4.695 3.990 4.657 4.695 4.741 4.728 4.726 4.727 4.723 5.180 5.707 5.165 5.692 5.162 5.689 5.138 5.666 5.135 5.662 5.123 5.648 5.124 5.651 5.151 5.677 5.136 5.662 5.112 5.637 4.359 4.834 5.068 5.588 5.114 5.642 4.359 4.834 5.068 5.588 5.114 5.642 4.359 4.834 5.068 5.588 5.114 5.642 5.158 5.685 5.145 5.672 5.145 5.673 5.142 5.667 5.138 5.664 5.564 5.549 5.546 5.523 5.519 5.505 5.508 5.534 5.519 5.494 4.699 5.445 5.499 4.699 5.445 5.499 4.699 5.445 5.499 5.542 5.529 5.530 5.524 5.521 5.767 5.316 5.847 5.702 5.838 5.752 5.301 5.832 5.687 5.823 5.749 5.298 5.830 5.685 5.821 5.726 5.275 5.806 5.661 5.797 5.722 5.271 5.803 5.658 5.794 5.708 5.258 5.787 5.642 5.778 5.711 5.261 5.792 5.647 5.783 5.737 5.287 5.817 5.672 5.808 5.722 5.272 5.802 5.657 5.793 5.697 5.248 5.777 5.632 5.768 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 4.910 4.467 4.945 4.809 4.961 5.648 5.200 5.724 5.579 5.715 5.702 5.251 5.785 5.640 5.776 5.745 5.294 5.824 5.679 5.815 5.732 5.280 5.811 5.666 5.802 5.733 5.280 5.813 5.668 5.804 5.727 5.277 5.806 5.661 5.797 5.724 5.274 5.803 5.658 5.794 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA DIFFERENTIAL 1.8-V HSTL CLASS I 8mA 10mA 12mA DIFFERENTIAL 1.8-V HSTL CLASS II 16mA 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-227 Table 1-108. EP3SE50 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.088 3.099 3.089 3.075 3.072 3.069 3.070 3.119 3.095 3.077 3.123 3.108 3.097 3.077 3.074 3.079 3.072 3.100 3.082 3.068 3.322 3.332 3.323 3.309 3.305 3.303 3.303 3.356 3.332 3.313 3.359 3.344 3.333 3.313 3.309 3.313 3.306 3.335 3.318 3.302 4.721 4.722 4.720 4.705 4.701 4.702 4.692 4.763 4.745 4.723 4.763 4.749 4.744 4.721 4.717 4.708 4.707 4.735 4.720 4.697 5.136 5.662 5.137 5.661 5.135 5.660 5.120 5.646 5.116 5.642 5.119 5.645 5.107 5.632 5.180 5.708 5.163 5.691 5.141 5.669 5.180 5.707 5.165 5.692 5.162 5.689 5.138 5.666 5.135 5.662 5.123 5.648 5.124 5.651 5.151 5.677 5.136 5.662 5.112 5.637 5.519 5.518 5.517 5.503 5.499 5.502 5.489 5.565 5.548 5.526 5.564 5.549 5.546 5.523 5.519 5.505 5.508 5.534 5.519 5.494 5.722 5.272 5.802 5.657 5.793 5.721 5.271 5.800 5.655 5.791 5.720 5.271 5.800 5.655 5.791 5.706 5.256 5.785 5.640 5.776 5.702 5.252 5.781 5.636 5.772 5.705 5.255 5.785 5.640 5.776 5.692 5.242 5.771 5.626 5.762 5.768 5.316 5.847 5.702 5.838 5.751 5.299 5.832 5.687 5.823 5.729 5.277 5.810 5.665 5.801 5.767 5.316 5.847 5.702 5.838 5.752 5.301 5.832 5.687 5.823 5.749 5.298 5.830 5.685 5.821 5.726 5.275 5.806 5.661 5.797 5.722 5.271 5.803 5.658 5.794 5.708 5.258 5.787 5.642 5.778 5.711 5.261 5.792 5.647 5.783 5.737 5.287 5.817 5.672 5.808 5.722 5.272 5.802 5.657 5.793 5.697 5.248 5.777 5.632 5.768 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA DIFFERENTIAL 1.8-V SSTL CLASS I 8mA 10mA 12mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS II 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V SSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-228 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-109 and Table 1-110 list the EP3SE50 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-109 lists the EP3SE50 column pin delay adders when using the regional clock in Stratix III devices. Table 1-109. EP3SE50 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units 0.152 -0.001 -0.116 1.647 0.164 -0.001 -0.119 1.684 0.22 -0.003 -0.134 2.61 0.237 -0.004 -0.136 2.926 0.25 -0.004 -0.17 3.238 0.244 -0.004 -0.171 3.084 0.31 -0.006 -0.249 3.298 0.24 -0.003 -0.131 2.943 0.254 -0.004 -0.13 3.254 0.246 -0.004 -0.13 3.098 0.312 -0.006 -0.216 3.374 ns ns ns ns Table 1-110 lists the EP3SE50 row pin delay adders when using the regional clock in Stratix III devices. Table 1-110. EP3SE50 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units 0.113 0.13 -0.116 -0.137 0.125 0.14 -0.129 -0.143 0.182 0.213 0.197 0.241 0.212 0.267 0.205 0.255 0.274 0.385 -0.28 0.201 0.244 0.215 0.27 0.21 0.256 0.275 0.386 ns ns ns ns -0.186 -0.202 -0.218 -0.209 -0.206 -0.221 -0.214 -0.283 -0.193 -0.214 -0.236 -0.225 -0.295 -0.215 -0.237 -0.226 -0.297 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-229 EP3SE80 I/O Timing Parameters Table 1-111 through Table 1-114 list the maximum I/O timing parameters for EP3SE80 devices for single-ended I/O standards. Table 1-111 lists the EP3SE80 column pins input timing parameters for single-ended I/O standards. Table 1-111. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.054 1.195 -1.307 1.605 -1.054 1.195 -1.307 1.605 -1.065 1.206 -1.318 1.616 -1.065 1.206 -1.318 1.616 -1.060 1.201 -1.313 1.611 -1.082 1.225 -1.335 1.635 -1.072 1.215 -1.325 1.625 -1.020 1.163 -1.273 1.573 -1.054 1.195 -1.307 1.605 -1.054 1.195 -1.307 1.605 -1.065 1.206 -1.318 1.616 -1.065 1.206 -1.318 1.616 -1.060 1.201 -1.313 1.611 -1.082 1.225 -1.335 1.635 -1.072 1.215 -1.325 1.625 -1.020 1.163 -1.273 1.573 -1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173 1.704 2.302 1.704 2.302 1.703 2.301 1.703 2.301 1.712 2.310 1.752 2.350 1.729 2.327 1.652 2.250 1.861 2.513 1.861 2.513 1.863 2.515 1.863 2.515 1.875 2.527 1.911 2.563 1.879 2.531 1.780 2.432 2.117 2.858 2.117 2.858 2.116 2.857 2.116 2.857 2.135 2.876 2.133 2.874 2.063 2.804 1.907 2.648 2.050 2.721 2.050 2.721 2.049 2.720 2.049 2.720 2.068 2.739 2.066 2.737 1.996 2.667 1.840 2.511 2.409 3.186 2.409 3.186 2.408 3.185 2.408 3.185 2.427 3.204 2.425 3.202 2.355 3.132 2.199 2.976 1.861 2.513 1.861 2.513 1.863 2.515 1.863 2.515 1.875 2.527 1.911 2.563 1.879 2.531 1.780 2.432 2.117 2.858 2.117 2.858 2.116 2.857 2.116 2.857 2.135 2.876 2.133 2.874 2.063 2.804 1.907 2.648 2.050 2.721 2.050 2.721 2.049 2.720 2.049 2.720 2.068 2.739 2.066 2.737 1.996 2.667 1.840 2.511 2.409 3.186 2.409 3.186 2.408 3.185 2.408 3.185 2.427 3.204 2.425 3.202 2.355 3.132 2.199 2.976 -1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661 -1.505 -1.636 -1.872 -1.819 -2.173 -1.636 -1.872 -1.819 -2.173 -1.870 -2.028 -2.321 -2.214 -2.661 -2.028 -2.321 -2.214 -2.661 -1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172 -1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660 -1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172 -1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660 -1.513 -1.650 -1.890 -1.837 -2.191 -1.650 -1.890 -1.837 -2.191 -1.878 -2.042 -2.339 -2.232 -2.679 -2.042 -2.339 -2.232 -2.679 -1.553 -1.686 -1.888 -1.835 -2.189 -1.686 -1.888 -1.835 -2.189 -1.918 -2.078 -2.337 -2.230 -2.677 -2.078 -2.337 -2.230 -2.677 -1.530 -1.654 -1.818 -1.765 -2.119 -1.654 -1.818 -1.765 -2.119 -1.895 -2.046 -2.267 -2.160 -2.607 -2.046 -2.267 -2.160 -2.607 -1.453 -1.555 -1.662 -1.609 -1.963 -1.555 -1.662 -1.609 -1.963 -1.818 -1.947 -2.111 -2.004 -2.451 -1.947 -2.111 -2.004 -2.451 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-230 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-111. EP3SE80 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-2 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.991 1.134 -1.244 1.544 -0.991 1.134 -1.244 1.544 -0.985 1.128 -1.238 1.538 -0.985 1.128 -1.238 1.538 -0.974 1.117 -1.227 1.527 -0.974 1.117 -1.227 1.527 -0.985 1.128 -1.238 1.538 -0.985 1.128 -1.238 1.538 -0.974 1.117 -1.227 1.527 -0.991 1.134 -1.244 1.544 -0.991 1.134 -1.244 1.544 -0.985 1.128 -1.238 1.538 -0.985 1.128 -1.238 1.538 -0.974 1.117 -1.227 1.527 -0.974 1.117 -1.227 1.527 -0.985 1.128 -1.238 1.538 -0.985 1.128 -1.238 1.538 -0.974 1.117 -1.227 1.527 -1.425 -1.539 -1.664 -1.611 -1.965 -1.539 -1.664 -1.611 -1.965 1.624 2.222 1.624 2.222 1.611 2.209 1.611 2.209 1.599 2.197 1.599 2.197 1.611 2.209 1.611 2.209 1.599 2.197 1.764 2.416 1.764 2.416 1.753 2.405 1.753 2.405 1.742 2.394 1.742 2.394 1.753 2.405 1.753 2.405 1.742 2.394 1.909 2.650 1.909 2.650 1.903 2.644 1.903 2.644 1.884 2.625 1.884 2.625 1.903 2.644 1.903 2.644 1.884 2.625 1.842 2.513 1.842 2.513 1.836 2.507 1.836 2.507 1.817 2.488 1.817 2.488 1.836 2.507 1.836 2.507 1.817 2.488 2.201 2.978 2.201 2.978 2.194 2.971 2.194 2.971 2.175 2.952 2.175 2.952 2.194 2.971 2.194 2.971 2.175 2.952 1.764 2.416 1.764 2.416 1.753 2.405 1.753 2.405 1.742 2.394 1.742 2.394 1.753 2.405 1.753 2.405 1.742 2.394 1.909 2.650 1.909 2.650 1.903 2.644 1.903 2.644 1.884 2.625 1.884 2.625 1.903 2.644 1.903 2.644 1.884 2.625 1.842 2.513 1.842 2.513 1.836 2.507 1.836 2.507 1.817 2.488 1.817 2.488 1.836 2.507 1.836 2.507 1.817 2.488 2.201 2.978 2.201 2.978 2.194 2.971 2.194 2.971 2.175 2.952 2.175 2.952 2.194 2.971 2.194 2.971 2.175 2.952 -1.790 -1.931 -2.113 -2.006 -2.453 -1.931 -2.113 -2.006 -2.453 -1.425 -1.539 -1.664 -1.611 -1.965 -1.539 -1.664 -1.611 -1.965 -1.790 -1.931 -2.113 -2.006 -2.453 -1.931 -2.113 -2.006 -2.453 -1.412 -1.531 -1.661 -1.606 -1.963 -1.531 -1.661 -1.606 -1.963 -1.777 -1.923 -2.110 -2.001 -2.451 -1.923 -2.110 -2.001 -2.451 -1.412 -1.531 -1.661 -1.606 -1.963 -1.531 -1.661 -1.606 -1.963 -1.777 -1.923 -2.110 -2.001 -2.451 -1.923 -2.110 -2.001 -2.451 -1.401 -1.520 -1.642 -1.587 -1.944 -1.520 -1.642 -1.587 -1.944 -1.766 -1.912 -2.091 -1.982 -2.432 -1.912 -2.091 -1.982 -2.432 -1.401 -1.520 -1.642 -1.587 -1.944 -1.520 -1.642 -1.587 -1.944 -1.766 -1.912 -2.091 -1.982 -2.432 -1.912 -2.091 -1.982 -2.432 -1.412 -1.531 -1.661 -1.606 -1.963 -1.531 -1.661 -1.606 -1.963 -1.777 -1.923 -2.110 -2.001 -2.451 -1.923 -2.110 -2.001 -2.451 -1.412 -1.531 -1.661 -1.606 -1.963 -1.531 -1.661 -1.606 -1.963 -1.777 -1.923 -2.110 -2.001 -2.451 -1.923 -2.110 -2.001 -2.451 -1.401 -1.520 -1.642 -1.587 -1.944 -1.520 -1.642 -1.587 -1.944 -1.766 -1.912 -2.091 -1.982 -2.432 -1.912 -2.091 -1.982 -2.432 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-231 Table 1-111. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.2-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.974 1.117 -1.227 1.527 -0.962 1.105 -1.215 1.515 -0.962 1.105 -1.215 1.515 -1.065 1.206 -1.318 1.616 -0.974 1.117 -1.227 1.527 -0.962 1.105 -1.215 1.515 -0.962 1.105 -1.215 1.515 -1.065 1.206 -1.318 1.616 -1.401 -1.520 -1.642 -1.587 -1.944 -1.520 -1.642 -1.587 -1.944 1.599 2.197 1.589 2.187 1.589 2.187 1.703 2.301 1.742 2.394 1.731 2.383 1.731 2.383 1.863 2.515 1.884 2.625 1.868 2.609 1.868 2.609 2.116 2.857 1.817 2.488 1.801 2.472 1.801 2.472 2.049 2.720 2.175 2.952 2.159 2.936 2.159 2.936 2.408 3.185 1.742 2.394 1.731 2.383 1.731 2.383 1.863 2.515 1.884 2.625 1.868 2.609 1.868 2.609 2.116 2.857 1.817 2.488 1.801 2.472 1.801 2.472 2.049 2.720 2.175 2.952 2.159 2.936 2.159 2.936 2.408 3.185 -1.766 -1.912 -2.091 -1.982 -2.432 -1.912 -2.091 -1.982 -2.432 -1.391 -1.509 -1.626 -1.571 -1.928 -1.509 -1.626 -1.571 -1.928 -1.756 -1.901 -2.075 -1.966 -2.416 -1.901 -2.075 -1.966 -2.416 -1.391 -1.509 -1.626 -1.571 -1.928 -1.509 -1.626 -1.571 -1.928 -1.756 -1.901 -2.075 -1.966 -2.416 -1.901 -2.075 -1.966 -2.416 -1.504 -1.638 -1.871 -1.818 -2.172 -1.638 -1.871 -1.818 -2.172 -1.869 -2.030 -2.320 -2.213 -2.660 -2.030 -2.320 -2.213 -2.660 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL Table 1-112 lists the EP3SE80 row pins input timing parameters for single-ended I/O standards. Table 1-112. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th -0.922 1.045 1.087 -0.825 -0.922 1.045 1.087 -0.825 -0.928 1.051 1.081 -0.819 -0.964 1.103 1.110 -0.830 -0.964 1.103 1.110 -0.830 -0.975 1.114 1.099 -0.819 -1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929 1.566 1.770 1.703 2.000 1.842 1.985 1.878 2.004 2.128 1.799 1.725 2.012 1.950 2.003 1.890 2.024 2.168 1.850 ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS -1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349 -1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929 1.566 1.770 1.703 2.000 1.842 1.985 1.878 2.004 2.128 1.799 1.725 2.012 1.950 2.003 1.890 2.024 2.168 1.850 GCLK PLL GCLK -1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349 -1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934 1.563 1.773 1.704 1.999 1.845 1.982 1.881 2.001 2.131 1.796 1.724 2.013 1.955 1.998 1.895 2.019 2.173 1.845 3.0-V LVTTL GCLK PLL -1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-232 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-112. EP3SE80 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVCMOS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.928 1.051 1.081 -0.819 -0.916 1.039 1.093 -0.831 -0.973 1.097 0.974 -0.714 -0.963 1.087 0.984 -0.724 -0.903 1.027 1.044 -0.784 -0.859 0.983 1.151 -0.888 -0.859 0.983 1.151 -0.888 -0.877 1.001 1.070 -0.810 -0.877 1.001 1.070 -0.810 -0.975 1.114 1.099 -0.819 -0.968 1.107 1.106 -0.826 -1.027 1.167 0.984 -0.705 -1.016 1.156 0.995 -0.716 -0.963 1.103 1.048 -0.769 -0.910 1.050 1.165 -0.884 -0.910 1.050 1.165 -0.884 -0.928 1.068 1.083 -0.804 -0.928 1.068 1.083 -0.804 -1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934 1.563 1.773 1.704 1.999 1.845 1.982 1.881 2.001 2.131 1.796 1.724 2.013 1.955 1.998 1.895 2.019 2.173 1.845 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344 -1.375 -1.495 -1.613 -1.665 -1.908 -1.500 -1.712 -1.664 -1.944 1.572 1.764 1.717 1.986 1.860 1.967 1.896 1.986 2.146 1.781 1.733 2.004 1.965 1.988 1.905 2.009 2.183 1.835 2.5 V GCLK PLL GCLK 1.8 V -1.347 -1.518 -1.452 -1.495 -1.282 -1.525 -1.462 -1.508 -1.334 -1.441 -1.555 -1.741 -1.689 -1.906 -1.560 -1.739 -1.691 -1.945 1.638 1.606 1.777 1.824 1.984 1.969 1.920 1.854 2.144 1.783 1.792 1.837 1.992 1.987 1.931 1.870 2.184 1.834 GCLK PLL GCLK 1.5 V -1.192 -1.359 -1.454 -1.366 -1.284 -1.362 -1.461 -1.373 -1.333 -1.417 -1.523 -1.673 -1.621 -1.838 -1.529 -1.674 -1.626 -1.880 1.614 1.630 1.745 1.856 1.916 2.037 1.852 1.922 2.076 1.851 1.761 1.868 1.927 2.052 1.866 1.935 2.119 1.899 GCLK PLL GCLK 1.2 V -1.216 -1.391 -1.522 -1.434 -1.352 -1.393 -1.526 -1.438 -1.398 -1.338 -1.422 -1.514 -1.462 -1.679 -1.433 -1.519 -1.471 -1.725 1.535 1.709 1.644 1.957 1.757 2.196 1.693 2.081 1.917 2.010 1.665 1.964 1.772 2.207 1.711 2.090 1.964 2.054 GCLK PLL GCLK SSTL-2 CLASS I -1.295 -1.492 -1.681 -1.593 -1.511 -1.489 -1.681 -1.593 -1.553 -1.289 -1.386 -1.393 -1.445 -1.688 -1.388 -1.495 -1.447 -1.727 1.486 1.850 1.608 2.095 1.640 2.187 1.676 2.206 1.926 2.001 1.621 2.116 1.748 2.205 1.688 2.226 1.966 2.052 GCLK PLL GCLK -1.433 -1.627 -1.672 -1.715 -1.502 -1.637 -1.679 -1.725 -1.551 -1.289 -1.386 -1.393 -1.445 -1.688 -1.388 -1.495 -1.447 -1.727 1.486 1.850 1.608 2.095 1.640 2.187 1.676 2.206 1.926 2.001 1.621 2.116 1.748 2.205 1.688 2.226 1.966 2.052 SSTL-2 CLASS II GCLK PLL GCLK -1.433 -1.627 -1.672 -1.715 -1.502 -1.637 -1.679 -1.725 -1.551 -1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720 1.497 1.747 1.615 1.984 1.750 2.201 1.686 2.087 1.911 2.014 1.631 1.996 1.762 2.214 1.702 2.098 1.955 2.061 SSTL-18 CLASS I GCLK PLL GCLK -1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564 -1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720 1.497 1.747 1.615 1.984 1.750 2.201 1.686 2.087 1.911 2.014 1.631 1.996 1.762 2.214 1.702 2.098 1.955 2.061 SSTL-18 CLASS II GCLK PLL -1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-233 Table 1-112. EP3SE80 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-15 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.863 0.987 1.084 -0.824 -0.877 1.001 1.070 -0.810 -0.877 1.001 1.070 -0.810 -0.863 0.987 1.084 -0.824 -0.863 0.987 1.084 -0.824 -0.854 0.978 1.093 -0.833 -0.854 0.978 1.093 -0.833 -0.928 1.051 1.081 -0.819 -0.928 1.051 1.081 -0.819 -0.916 1.056 1.095 -0.816 -0.928 1.068 1.083 -0.804 -0.928 1.068 1.083 -0.804 -0.916 1.056 1.095 -0.816 -0.916 1.056 1.095 -0.816 -0.904 1.044 1.107 -0.828 -0.904 1.044 1.107 -0.828 -0.975 1.114 1.099 -0.819 -0.975 1.114 1.099 -0.819 -1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703 1.483 1.762 1.605 1.994 1.732 2.219 1.668 2.105 1.893 2.032 1.620 2.007 1.745 2.231 1.685 2.115 1.938 2.078 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581 -1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720 1.497 1.747 1.615 1.984 1.750 2.201 1.686 2.087 1.911 2.014 1.631 1.996 1.762 2.214 1.702 2.098 1.955 2.061 1.8-V HSTL CLASS I GCLK PLL GCLK -1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564 -1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720 1.497 1.747 1.615 1.984 1.750 2.201 1.686 2.087 1.911 2.014 1.631 1.996 1.762 2.214 1.702 2.098 1.955 2.061 1.8-V HSTL CLASS II GCLK PLL GCLK -1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564 -1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703 1.483 1.762 1.605 1.994 1.732 2.219 1.668 2.105 1.893 2.032 1.620 2.007 1.745 2.231 1.685 2.115 1.938 2.078 1.5-V HSTL CLASS I GCLK PLL GCLK -1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581 -1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703 1.483 1.762 1.605 1.994 1.732 2.219 1.668 2.105 1.893 2.032 1.620 2.007 1.745 2.231 1.685 2.115 1.938 2.078 1.5-V HSTL CLASS II GCLK PLL GCLK -1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581 -1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687 1.474 1.771 1.595 2.004 1.716 2.235 1.652 2.121 1.877 2.048 1.611 2.016 1.729 2.247 1.669 2.131 1.922 2.094 1.2-V HSTL CLASS I GCLK PLL GCLK -1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597 -1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687 1.474 1.771 1.595 2.004 1.716 2.235 1.652 2.121 1.877 2.048 1.611 2.016 1.729 2.247 1.669 2.131 1.922 2.094 1.2-V HSTL CLASS II GCLK PLL GCLK -1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597 -1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934 1.563 1.773 1.704 1.999 1.845 1.982 1.881 2.001 2.131 1.796 1.724 2.013 1.955 1.998 1.895 2.019 2.173 1.845 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X -1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344 -1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934 1.563 1.773 1.704 1.999 1.845 1.982 1.881 2.001 2.131 1.796 1.724 2.013 1.955 1.998 1.895 2.019 2.173 1.845 GCLK PLL -1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-234 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-113 lists the EP3SE80 column pins output timing parameters for single-ended I/O standards. Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.559 3.859 3.442 3.792 3.347 3.706 3.302 3.699 3.562 3.865 3.362 3.710 3.305 3.717 3.285 3.701 3.504 3.823 3.374 3.712 3.299 3.676 3.262 3.658 3.559 3.865 3.442 3.798 3.347 3.712 3.302 3.705 3.562 3.871 3.362 3.716 3.305 3.723 3.285 3.707 3.504 3.829 3.374 3.718 3.299 3.682 3.262 3.664 4.935 5.323 5.638 5.693 5.865 5.323 5.638 5.693 5.865 5.394 5.826 6.396 6.210 6.631 5.826 6.396 6.210 6.631 4.781 5.161 5.525 5.523 5.752 5.161 5.525 5.523 5.752 5.285 5.715 6.283 6.097 6.518 5.715 6.283 6.097 6.518 4.644 5.018 5.433 5.371 5.660 5.018 5.433 5.371 5.660 5.181 5.616 6.191 6.005 6.426 5.616 6.191 6.005 6.426 4.619 4.994 5.392 5.346 5.619 4.994 5.392 5.346 5.619 5.164 5.588 6.150 5.964 6.385 5.588 6.150 5.964 6.385 4.939 5.335 5.645 5.707 5.872 5.335 5.645 5.707 5.872 5.398 5.831 6.403 6.217 6.638 5.831 6.403 6.217 6.638 4.649 5.023 5.444 5.377 5.671 5.023 5.444 5.377 5.671 5.191 5.633 6.202 6.016 6.437 5.633 6.202 6.016 6.437 4.612 4.992 5.418 5.346 5.645 4.992 5.418 5.346 5.645 5.185 5.612 6.176 5.990 6.411 5.612 6.176 5.990 6.411 4.558 4.934 5.389 5.289 5.616 4.934 5.389 5.289 5.616 5.163 5.587 6.147 5.961 6.382 5.587 6.147 5.961 6.382 4.884 5.274 5.605 5.658 5.832 5.274 5.605 5.658 5.832 5.361 5.794 6.363 6.177 6.598 5.794 6.363 6.177 6.598 4.715 5.102 5.468 5.497 5.693 5.102 5.468 5.497 5.693 5.231 5.660 6.225 6.041 6.459 5.660 6.225 6.041 6.459 4.626 5.003 5.394 5.395 5.620 5.003 5.394 5.395 5.620 5.168 5.591 6.151 5.967 6.386 5.591 6.151 5.967 6.386 4.561 4.934 5.365 5.345 5.592 4.934 5.365 5.345 5.592 5.139 5.563 6.123 5.937 6.358 5.563 6.123 5.937 6.358 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-235 Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.412 3.737 3.275 3.658 3.245 3.653 3.223 3.644 3.559 3.859 3.434 3.759 3.334 3.715 3.307 3.677 3.412 3.743 3.275 3.664 3.245 3.659 3.224 3.650 3.559 3.865 3.434 3.765 3.334 3.721 3.307 3.683 4.773 5.155 5.503 5.551 5.728 5.155 5.503 5.551 5.728 5.265 5.694 6.260 6.076 6.494 5.694 6.260 6.076 6.494 4.578 4.956 5.368 5.369 5.593 4.956 5.368 5.369 5.593 5.141 5.565 6.125 5.941 6.359 5.565 6.125 5.941 6.359 4.532 4.904 5.359 5.300 5.586 4.904 5.359 5.300 5.586 5.134 5.558 6.117 5.931 6.352 5.558 6.117 5.931 6.352 4.510 4.883 5.344 5.299 5.571 4.883 5.344 5.299 5.571 5.120 5.543 6.102 5.916 6.337 5.543 6.102 5.916 6.337 5.027 5.434 5.750 5.833 5.976 5.434 5.750 5.833 5.976 5.472 5.921 6.507 6.323 6.742 5.921 6.507 6.323 6.742 4.854 5.250 5.618 5.636 5.843 5.250 5.618 5.636 5.843 5.353 5.795 6.375 6.191 6.609 5.795 6.375 6.191 6.609 4.725 5.114 5.522 5.496 5.749 5.114 5.522 5.496 5.749 5.266 5.704 6.280 6.094 6.515 5.704 6.280 6.094 6.515 4.656 5.047 5.479 5.446 5.706 5.047 5.479 5.446 5.706 5.227 5.662 6.237 6.051 6.472 5.662 6.237 6.051 6.472 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-236 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.822 4.050 3.581 3.869 3.463 3.787 3.409 3.767 3.341 3.704 3.317 3.686 3.730 3.996 3.447 3.784 3.369 3.759 3.359 3.748 3.329 3.693 3.280 3.688 3.822 4.056 3.581 3.875 3.463 3.793 3.409 3.773 3.341 3.710 3.317 3.692 3.730 4.002 3.447 3.790 3.369 3.765 3.359 3.754 3.329 3.699 3.280 3.694 5.464 5.917 6.154 6.369 6.381 5.917 6.154 6.369 6.381 5.793 6.281 6.912 6.726 7.147 6.281 6.912 6.726 7.147 5.104 5.511 5.807 5.909 6.032 5.511 5.807 5.909 6.032 5.514 5.972 6.564 6.380 6.798 5.972 6.564 6.380 6.798 4.914 5.321 5.696 5.734 5.923 5.321 5.696 5.734 5.923 5.407 5.857 6.454 6.268 6.689 5.857 6.454 6.268 6.689 4.814 5.223 5.630 5.622 5.857 5.223 5.630 5.622 5.857 5.349 5.803 6.388 6.202 6.623 5.803 6.388 6.202 6.623 4.718 5.125 5.549 5.508 5.776 5.125 5.549 5.508 5.776 5.288 5.728 6.307 6.121 6.542 5.728 6.307 6.121 6.542 4.685 5.078 5.526 5.470 5.753 5.078 5.526 5.470 5.753 5.267 5.707 6.284 6.098 6.519 5.707 6.284 6.098 6.519 5.357 5.827 6.092 6.286 6.319 5.827 6.092 6.286 6.319 5.722 6.213 6.850 6.664 7.085 6.213 6.850 6.664 7.085 4.903 5.314 5.700 5.730 5.927 5.314 5.700 5.730 5.927 5.403 5.857 6.458 6.272 6.693 5.857 6.458 6.272 6.693 4.803 5.206 5.633 5.613 5.860 5.206 5.633 5.613 5.860 5.336 5.797 6.391 6.205 6.626 5.797 6.391 6.205 6.626 4.785 5.185 5.613 5.581 5.840 5.185 5.613 5.581 5.840 5.319 5.772 6.371 6.185 6.606 5.772 6.371 6.185 6.606 4.701 5.107 5.543 5.499 5.770 5.107 5.543 5.499 5.770 5.281 5.721 6.301 6.115 6.536 5.721 6.301 6.115 6.536 4.679 5.072 5.532 5.457 5.759 5.072 5.532 5.457 5.759 5.264 5.710 6.290 6.104 6.525 5.710 6.290 6.104 6.525 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-237 Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.620 3.912 3.447 3.789 3.360 3.751 3.336 3.704 3.324 3.704 3.321 3.701 3.309 3.699 3.286 3.690 3.340 3.711 3.323 3.707 3.311 3.696 3.282 3.685 3.281 3.685 3.620 3.918 3.447 3.795 3.360 3.757 3.336 3.710 3.324 3.710 3.321 3.707 3.309 3.705 3.286 3.696 3.340 3.717 3.323 3.713 3.311 3.702 3.282 3.691 3.281 3.691 5.244 5.726 6.036 6.206 6.263 5.726 6.036 6.206 6.263 5.648 6.149 6.794 6.608 7.029 6.149 6.794 6.608 7.029 4.922 5.345 5.750 5.777 5.977 5.345 5.750 5.777 5.977 5.422 5.887 6.508 6.322 6.743 5.887 6.508 6.322 6.743 4.795 5.204 5.637 5.622 5.864 5.204 5.637 5.622 5.864 5.330 5.798 6.395 6.209 6.630 5.798 6.395 6.209 6.630 4.726 5.144 5.581 5.531 5.808 5.144 5.581 5.531 5.808 5.302 5.749 6.339 6.153 6.574 5.749 6.339 6.153 6.574 4.688 5.075 5.512 5.479 5.739 5.075 5.512 5.479 5.739 5.259 5.696 6.270 6.084 6.505 5.696 6.270 6.084 6.505 4.681 5.068 5.508 5.485 5.735 5.068 5.508 5.485 5.735 5.256 5.693 6.266 6.080 6.501 5.693 6.266 6.080 6.501 4.677 5.064 5.509 5.465 5.736 5.064 5.509 5.465 5.736 5.256 5.694 6.267 6.081 6.502 5.694 6.267 6.081 6.502 4.647 5.033 5.494 5.431 5.721 5.033 5.494 5.431 5.721 5.241 5.678 6.252 6.066 6.487 5.678 6.252 6.066 6.487 4.700 5.090 5.528 5.507 5.755 5.090 5.528 5.507 5.755 5.271 5.710 6.286 6.100 6.521 5.710 6.286 6.100 6.521 4.697 5.087 5.526 5.496 5.753 5.087 5.526 5.496 5.753 5.269 5.708 6.284 6.098 6.519 5.708 6.284 6.098 6.519 4.677 5.067 5.517 5.489 5.744 5.067 5.517 5.489 5.744 5.259 5.699 6.275 6.089 6.510 5.699 6.275 6.089 6.510 4.659 5.049 5.504 5.450 5.731 5.049 5.504 5.450 5.731 5.246 5.686 6.262 6.076 6.497 5.686 6.262 6.076 6.497 4.659 5.049 5.504 5.450 5.731 5.049 5.504 5.450 5.731 5.246 5.686 6.262 6.076 6.497 5.686 6.262 6.076 6.497 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-238 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 8mA SSTL-18 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.290 3.691 3.279 3.694 3.334 3.715 3.309 3.701 3.289 3.690 3.280 3.689 3.275 3.686 3.284 3.688 3.274 3.691 3.290 3.697 3.279 3.700 3.334 3.721 3.309 3.707 3.289 3.696 3.280 3.695 3.275 3.692 3.284 3.694 3.274 3.697 4.656 5.044 5.499 5.450 5.726 5.044 5.499 5.450 5.726 5.245 5.683 6.257 6.071 6.492 5.683 6.257 6.071 6.492 4.649 5.039 5.511 5.455 5.738 5.039 5.511 5.455 5.738 5.253 5.692 6.269 6.083 6.504 5.692 6.269 6.083 6.504 4.714 5.107 5.541 5.521 5.768 5.107 5.541 5.521 5.768 5.280 5.722 6.299 6.113 6.534 5.722 6.299 6.113 6.534 4.693 5.086 5.532 5.495 5.759 5.086 5.532 5.495 5.759 5.270 5.712 6.290 6.104 6.525 5.712 6.290 6.104 6.525 4.672 5.065 5.518 5.471 5.745 5.065 5.518 5.471 5.745 5.256 5.698 6.276 6.090 6.511 5.698 6.276 6.090 6.511 4.666 5.059 5.522 5.460 5.749 5.059 5.522 5.460 5.749 5.259 5.701 6.280 6.094 6.515 5.701 6.280 6.094 6.515 4.659 5.051 5.516 5.450 5.743 5.051 5.516 5.450 5.743 5.254 5.696 6.274 6.088 6.509 5.696 6.274 6.088 6.509 4.652 5.042 5.499 5.450 5.726 5.042 5.499 5.450 5.726 5.243 5.682 6.257 6.071 6.492 5.682 6.257 6.071 6.492 4.646 5.036 5.510 5.456 5.737 5.036 5.510 5.456 5.737 5.250 5.691 6.268 6.082 6.503 5.691 6.268 6.082 6.503 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-239 Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.308 3.698 3.294 3.691 3.278 3.683 3.279 3.686 3.271 3.683 3.274 3.691 3.314 3.703 3.302 3.699 3.296 3.695 3.284 3.688 3.279 3.689 3.275 3.687 3.308 3.704 3.294 3.697 3.278 3.689 3.279 3.692 3.271 3.689 3.274 3.697 3.314 3.709 3.302 3.705 3.296 3.701 3.284 3.694 3.279 3.695 3.275 3.693 4.665 5.052 5.497 5.464 5.724 5.052 5.497 5.464 5.724 5.245 5.682 6.255 6.069 6.490 5.682 6.255 6.069 6.490 4.652 5.040 5.496 5.461 5.723 5.040 5.496 5.461 5.723 5.243 5.680 6.254 6.068 6.489 5.680 6.254 6.068 6.489 4.642 5.029 5.489 5.434 5.716 5.029 5.489 5.434 5.716 5.235 5.673 6.247 6.061 6.482 5.673 6.247 6.061 6.482 4.644 5.032 5.493 5.436 5.720 5.032 5.493 5.436 5.720 5.238 5.676 6.251 6.065 6.486 5.676 6.251 6.065 6.486 4.640 5.028 5.497 5.436 5.724 5.028 5.497 5.436 5.724 5.241 5.680 6.255 6.069 6.490 5.680 6.255 6.069 6.490 4.631 5.018 5.493 5.432 5.720 5.018 5.493 5.432 5.720 5.240 5.677 6.251 6.065 6.486 5.677 6.251 6.065 6.486 4.676 5.065 5.508 5.480 5.735 5.065 5.508 5.480 5.735 5.253 5.692 6.266 6.080 6.501 5.692 6.266 6.080 6.501 4.670 5.060 5.511 5.469 5.738 5.060 5.511 5.469 5.738 5.254 5.693 6.269 6.083 6.504 5.693 6.269 6.083 6.504 4.664 5.053 5.506 5.463 5.733 5.053 5.506 5.463 5.733 5.250 5.689 6.264 6.078 6.499 5.689 6.264 6.078 6.499 4.652 5.042 5.499 5.450 5.726 5.042 5.499 5.450 5.726 5.243 5.682 6.257 6.071 6.492 5.682 6.257 6.071 6.492 4.653 5.043 5.509 5.446 5.736 5.043 5.509 5.446 5.736 5.250 5.690 6.267 6.081 6.502 5.690 6.267 6.081 6.502 4.629 5.015 5.483 5.425 5.710 5.015 5.483 5.425 5.710 5.231 5.668 6.241 6.055 6.476 5.668 6.241 6.055 6.476 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-240 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-113. EP3SE80 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.312 3.706 3.298 3.698 3.292 3.699 3.277 3.688 3.277 3.688 3.327 3.709 3.395 3.812 3.395 3.812 3.312 3.712 3.298 3.704 3.292 3.705 3.277 3.694 3.277 3.694 3.327 3.715 3.395 3.818 3.395 3.818 4.688 5.081 5.529 5.499 5.756 5.081 5.529 5.499 5.756 5.267 5.709 6.287 6.101 6.522 5.709 6.287 6.101 6.522 4.674 5.066 5.520 5.482 5.747 5.066 5.520 5.482 5.747 5.258 5.700 6.278 6.092 6.513 5.700 6.278 6.092 6.513 4.675 5.068 5.529 5.478 5.756 5.068 5.529 5.478 5.756 5.266 5.708 6.287 6.101 6.522 5.708 6.287 6.101 6.522 4.657 5.049 5.515 5.455 5.742 5.049 5.515 5.455 5.742 5.253 5.695 6.273 6.087 6.508 5.695 6.273 6.087 6.508 4.657 5.049 5.516 5.456 5.743 5.049 5.516 5.456 5.743 5.253 5.695 6.274 6.088 6.509 5.695 6.274 6.088 6.509 4.692 5.083 5.529 5.534 5.756 5.083 5.529 5.534 5.756 5.269 5.710 6.287 6.101 6.522 5.710 6.287 6.101 6.522 4.701 5.080 5.554 5.509 5.781 5.080 5.554 5.509 5.781 5.314 5.744 6.312 6.126 6.547 5.744 6.312 6.126 6.547 4.701 5.080 5.554 5.509 5.781 5.080 5.554 5.509 5.781 5.314 5.744 6.312 6.126 6.547 5.744 6.312 6.126 6.547 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Table 1-114 lists the EP3SE80 row pins output timing parameters for single-ended I/O standards. Table 1-114. EP3SE80 Row Pins Output Timing Parameters (Part 1 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL tco tco tco tco tco tco 3.238 1.439 3.156 1.346 3.077 1.247 3.493 1.634 3.399 1.529 3.310 1.423 4.856 5.245 5.757 5.609 5.907 5.368 5.891 5.735 5.990 2.039 2.121 2.343 2.334 2.309 2.226 2.430 2.441 2.301 4.726 5.107 5.612 5.464 5.762 5.227 5.742 5.586 5.841 1.909 1.983 2.198 2.189 2.195 2.085 2.281 2.292 2.186 4.607 4.984 5.484 5.348 5.634 5.107 5.610 5.468 5.709 1.790 1.860 2.070 2.061 2.099 1.958 2.149 2.160 2.086 ns ns ns ns ns ns 3.3-V LVTTL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-241 Table 1-114. EP3SE80 Row Pins Output Timing Parameters (Part 2 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.248 1.449 3.081 1.251 3.192 1.393 3.082 1.268 3.045 1.229 3.106 1.307 3.032 1.207 3.218 1.419 3.124 1.309 3.067 1.263 3.451 1.652 3.229 1.427 3.161 1.362 3.136 1.315 3.497 1.638 3.314 1.429 3.439 1.580 3.319 1.453 3.281 1.402 3.358 1.499 3.265 1.380 3.475 1.616 3.377 1.518 3.321 1.441 3.722 1.862 3.520 1.660 3.418 1.558 3.379 1.497 4.864 5.250 5.761 5.613 5.911 5.374 5.895 5.739 5.994 2.047 2.126 2.347 2.338 2.318 2.232 2.434 2.445 2.313 4.613 4.999 5.490 5.358 5.640 5.119 5.617 5.477 5.716 1.796 1.866 2.076 2.067 2.109 1.964 2.156 2.167 2.095 4.808 5.198 5.713 5.565 5.863 5.325 5.849 5.693 5.948 1.991 2.074 2.299 2.290 2.275 2.183 2.388 2.399 2.267 4.655 5.039 5.549 5.401 5.699 5.163 5.685 5.528 5.783 1.838 1.915 2.135 2.126 2.130 2.021 2.224 2.234 2.121 4.582 4.957 5.461 5.313 5.611 5.077 5.592 5.435 5.690 1.756 1.832 2.047 2.038 2.060 1.935 2.131 2.141 2.048 4.702 5.091 5.603 5.455 5.753 5.217 5.738 5.581 5.836 1.885 1.967 2.189 2.180 2.166 2.075 2.277 2.287 2.157 4.554 4.928 5.422 5.281 5.572 5.047 5.552 5.401 5.650 1.721 1.793 2.008 1.999 2.032 1.895 2.091 2.101 2.019 4.940 5.352 5.885 5.737 6.035 5.485 6.028 5.871 6.126 2.123 2.228 2.471 2.462 2.420 2.343 2.567 2.577 2.419 4.785 5.189 5.715 5.567 5.865 5.318 5.854 5.697 5.952 1.968 2.065 2.301 2.292 2.278 2.176 2.393 2.403 2.274 4.679 5.070 5.589 5.441 5.739 5.195 5.724 5.567 5.822 1.857 1.946 2.175 2.166 2.187 2.053 2.263 2.273 2.180 5.326 5.781 6.360 6.212 6.510 5.922 6.504 6.356 6.611 2.507 2.657 2.761 2.937 2.944 2.780 2.883 3.062 2.957 4.999 5.412 5.955 5.807 6.105 5.557 6.098 5.949 6.204 2.180 2.288 2.401 2.532 2.539 2.415 2.522 2.655 2.550 4.846 5.262 5.796 5.648 5.946 5.389 5.925 5.777 6.032 2.027 2.138 2.301 2.373 2.380 2.247 2.416 2.483 2.378 4.770 5.176 5.699 5.552 5.849 5.300 5.831 5.683 5.938 1.950 2.044 2.235 2.276 2.297 2.152 2.344 2.389 2.290 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-242 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-114. EP3SE80 Row Pins Output Timing Parameters (Part 3 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.362 1.563 3.152 1.331 3.125 1.304 3.106 1.285 3.305 1.506 3.157 1.336 3.071 1.248 3.066 1.236 3.057 1.220 3.085 1.264 3.080 1.259 3.069 1.248 3.058 1.237 3.058 1.237 3.640 1.780 3.396 1.522 3.370 1.488 3.359 1.477 3.565 1.705 3.400 1.518 3.309 1.427 3.305 1.415 3.294 1.397 3.323 1.441 3.318 1.436 3.307 1.425 3.296 1.414 3.295 1.413 5.236 5.694 6.288 6.140 6.438 5.829 6.428 6.280 6.535 2.417 2.570 2.698 2.865 2.872 2.687 2.818 2.986 2.881 4.831 5.257 5.797 5.649 5.947 5.383 5.924 5.776 6.031 2.012 2.133 2.304 2.374 2.381 2.241 2.417 2.482 2.377 4.758 5.168 5.691 5.552 5.841 5.293 5.819 5.677 5.926 1.939 2.037 2.235 2.268 2.297 2.143 2.344 2.377 2.290 4.738 5.143 5.672 5.533 5.822 5.269 5.797 5.658 5.904 1.917 2.019 2.216 2.249 2.278 2.125 2.325 2.355 2.271 5.146 5.608 6.213 6.065 6.363 5.741 6.344 6.196 6.451 2.327 2.484 2.637 2.790 2.797 2.599 2.749 2.902 2.797 4.853 5.285 5.838 5.690 5.988 5.408 5.966 5.818 6.073 2.034 2.161 2.352 2.415 2.422 2.266 2.461 2.524 2.419 4.672 5.060 5.557 5.426 5.707 5.180 5.686 5.548 5.785 1.835 1.918 2.143 2.134 2.177 2.020 2.225 2.236 2.166 4.669 5.058 5.549 5.424 5.699 5.179 5.679 5.547 5.778 1.827 1.910 2.135 2.126 2.175 2.012 2.218 2.229 2.165 4.654 5.042 5.522 5.407 5.672 5.162 5.652 5.529 5.751 1.802 1.885 2.108 2.099 2.158 1.986 2.191 2.202 2.147 4.689 5.080 5.578 5.447 5.724 5.199 5.698 5.568 5.802 1.849 1.934 2.130 2.151 2.192 2.035 2.235 2.254 2.181 4.687 5.079 5.577 5.446 5.723 5.197 5.696 5.566 5.800 1.847 1.933 2.129 2.150 2.191 2.033 2.233 2.252 2.179 4.677 5.069 5.567 5.436 5.713 5.188 5.687 5.557 5.791 1.837 1.923 2.119 2.140 2.181 2.024 2.224 2.243 2.170 4.664 5.056 5.554 5.423 5.700 5.176 5.675 5.545 5.779 1.824 1.910 2.106 2.127 2.168 2.012 2.212 2.231 2.158 4.664 5.056 5.554 5.423 5.700 5.175 5.675 5.545 5.779 1.824 1.910 2.106 2.127 2.168 2.011 2.212 2.231 2.158 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK SSTL-18 CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-243 Table 1-114. EP3SE80 Row Pins Output Timing Parameters (Part 4 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.066 1.245 3.067 1.246 3.088 1.267 3.074 1.253 3.063 1.242 3.073 1.252 3.066 1.245 3.057 1.236 3.060 1.239 3.056 1.235 3.064 1.243 3.079 1.258 3.073 1.252 3.069 1.248 3.302 1.420 3.305 1.423 3.326 1.444 3.312 1.430 3.300 1.418 3.308 1.426 3.302 1.420 3.294 1.412 3.296 1.414 3.293 1.411 3.301 1.419 3.314 1.432 3.309 1.427 3.305 1.423 4.663 5.053 5.549 5.418 5.695 5.171 5.669 5.539 5.773 1.823 1.907 2.101 2.122 2.163 2.007 2.206 2.225 2.152 4.669 5.061 5.559 5.428 5.705 5.180 5.680 5.550 5.784 1.829 1.915 2.111 2.132 2.173 2.016 2.217 2.236 2.163 4.698 5.091 5.591 5.460 5.740 5.209 5.710 5.580 5.817 1.858 1.946 2.143 2.167 2.205 2.046 2.247 2.268 2.193 4.687 5.081 5.581 5.450 5.727 5.200 5.701 5.571 5.805 1.847 1.935 2.133 2.154 2.195 2.036 2.238 2.257 2.184 4.674 5.068 5.568 5.437 5.714 5.187 5.688 5.558 5.792 1.834 1.922 2.120 2.141 2.182 2.023 2.225 2.244 2.171 4.662 5.051 5.547 5.416 5.693 5.170 5.666 5.536 5.770 1.822 1.905 2.099 2.120 2.161 2.006 2.203 2.222 2.149 4.660 5.050 5.546 5.415 5.692 5.169 5.666 5.536 5.770 1.820 1.904 2.098 2.119 2.160 2.005 2.203 2.222 2.149 4.653 5.043 5.539 5.408 5.685 5.162 5.659 5.529 5.763 1.813 1.897 2.091 2.112 2.153 1.998 2.196 2.215 2.142 4.656 5.046 5.543 5.412 5.689 5.165 5.662 5.532 5.766 1.816 1.900 2.095 2.116 2.157 2.001 2.199 2.218 2.145 4.658 5.049 5.546 5.415 5.692 5.168 5.667 5.537 5.771 1.818 1.903 2.098 2.119 2.160 2.004 2.204 2.223 2.150 4.656 5.046 5.542 5.411 5.688 5.164 5.661 5.531 5.765 1.816 1.900 2.094 2.115 2.156 2.000 2.198 2.217 2.144 4.671 5.061 5.558 5.427 5.704 5.179 5.677 5.547 5.781 1.831 1.915 2.110 2.131 2.172 2.015 2.214 2.233 2.160 4.672 5.063 5.560 5.429 5.706 5.181 5.680 5.550 5.784 1.832 1.917 2.112 2.133 2.174 2.017 2.217 2.236 2.163 4.667 5.058 5.555 5.424 5.701 5.176 5.674 5.544 5.778 1.827 1.912 2.107 2.128 2.169 2.012 2.211 2.230 2.157 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.8-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 1.8-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA 1.5-V HSTL CLASS I GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-244 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-114. EP3SE80 Row Pins Output Timing Parameters (Part 5 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco 3.081 1.260 3.072 1.251 3.071 1.250 3.177 1.333 3.177 1.333 3.316 1.434 3.308 1.426 3.308 1.426 3.415 1.510 3.415 1.510 4.684 5.077 5.577 5.446 5.723 5.195 5.696 5.566 5.800 1.844 1.931 2.129 2.150 2.191 2.031 2.233 2.252 2.179 4.675 5.068 5.568 5.437 5.714 5.186 5.687 5.557 5.791 1.835 1.922 2.120 2.141 2.182 2.022 2.224 2.243 2.170 4.682 5.076 5.577 5.446 5.723 5.195 5.697 5.567 5.801 1.842 1.930 2.129 2.150 2.191 2.031 2.234 2.253 2.180 4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810 1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208 4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810 1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208 ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Table 1-115 through Table 1-118 list the maximum I/O timing parameters for EP3SE80 devices for differential I/O standards. Table 1-115 lists the EP3SE80 column pins input timing parameters for differential I/O standards. Table 1-115. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK tsu th -0.997 1.133 0.960 -0.691 -0.997 1.133 0.960 -0.691 -0.997 1.133 0.960 -0.691 -0.813 0.942 1.144 -0.882 -1.029 1.184 0.994 -0.701 -1.029 1.184 0.994 -0.701 -1.029 1.184 0.994 -0.701 -0.852 0.999 1.171 -0.886 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL tsu th tsu -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 MINI-LVDS GCLK GCLK PLL th tsu th tsu th -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 RSDS GCLK tsu th -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837 1.460 1.802 1.595 2.025 1.731 2.242 1.659 2.134 2.031 2.045 1.604 2.042 1.739 2.260 1.674 2.147 2.075 2.091 DIFFERENTIAL 1.2-V HSTL CLASS I GCLK GCLK PLL tsu th tsu th -1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-245 Table 1-115. EP3SE80 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.2-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.813 0.942 1.144 -0.882 -0.821 0.950 1.136 -0.874 -0.821 0.950 1.136 -0.874 -0.833 0.962 1.124 -0.862 -0.833 0.962 1.124 -0.862 -0.821 0.950 1.136 -0.874 -0.821 0.950 1.136 -0.874 -0.833 0.962 1.124 -0.862 -0.833 0.962 1.124 -0.862 -0.852 0.999 1.171 -0.886 -0.864 1.011 1.159 -0.874 -0.864 1.011 1.159 -0.874 -0.875 1.022 1.148 -0.863 -0.875 1.022 1.148 -0.863 -0.864 1.011 1.159 -0.874 -0.864 1.011 1.159 -0.874 -0.875 1.022 1.148 -0.863 -0.875 1.022 1.148 -0.863 -1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837 1.460 1.802 1.595 2.025 1.731 2.242 1.659 2.134 2.031 2.045 1.604 2.042 1.739 2.260 1.674 2.147 2.075 2.091 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V HSTL CLASS I -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V HSTL CLASS II -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V HSTL CLASS I -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V HSTL CLASS II -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V SSTL CLASS I -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V SSTL CLASS II -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V SSTL CLASS I -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V SSTL CLASS II -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-246 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-115. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th -0.840 0.969 1.117 -0.855 -0.840 0.969 1.117 -0.855 -0.881 1.028 1.142 -0.857 -0.881 1.028 1.142 -0.857 -1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 1.493 1.771 1.625 1.998 1.769 2.207 1.697 2.097 2.070 2.011 1.633 2.016 1.772 2.232 1.706 2.116 2.109 2.062 ns ns ns ns ns ns ns ns -1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 -1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 1.493 1.771 1.625 1.998 1.769 2.207 1.697 2.097 2.070 2.011 1.633 2.016 1.772 2.232 1.706 2.116 2.109 2.062 DIFFERENTIAL 2.5-V SSTL CLASS II -1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 Table 1-116 lists the EP3SE80 row pins input timing parameters for differential I/O standards. Table 1-116. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -0.944 1.077 0.961 -0.691 -0.944 1.077 0.961 -0.691 -0.944 1.077 0.961 -0.691 -0.749 0.875 1.156 -0.893 -0.749 0.875 1.156 -0.893 -0.979 1.130 0.989 -0.700 -0.979 1.130 0.989 -0.700 -0.979 1.130 0.989 -0.700 -0.794 0.936 1.174 -0.894 -0.794 0.936 1.174 -0.894 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 1.345 1.864 1.468 2.104 1.587 2.344 1.524 2.224 1.867 2.163 1.479 2.120 1.597 2.362 1.535 2.240 1.912 2.210 DIFFERENTIAL 1.2-V HSTL CLASS I -1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 -1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 1.345 1.864 1.468 2.104 1.587 2.344 1.524 2.224 1.867 2.163 1.479 2.120 1.597 2.362 1.535 2.240 1.912 2.210 DIFFERENTIAL 1.2-V HSTL CLASS II -1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-247 Table 1-116. EP3SE80 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.5-V HSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.758 0.884 1.147 -0.884 -0.758 0.884 1.147 -0.884 -0.772 0.898 1.133 -0.870 -0.772 0.898 1.133 -0.870 -0.758 0.884 1.147 -0.884 -0.758 0.884 1.147 -0.884 -0.772 0.898 1.133 -0.870 -0.772 0.898 1.133 -0.870 -0.781 0.907 1.124 -0.861 -0.806 0.948 1.162 -0.882 -0.806 0.948 1.162 -0.882 -0.818 0.960 1.150 -0.870 -0.818 0.960 1.150 -0.870 -0.806 0.948 1.162 -0.882 -0.806 0.948 1.162 -0.882 -0.818 0.960 1.150 -0.870 -0.818 0.960 1.150 -0.870 -0.827 0.969 1.141 -0.861 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V HSTL CLASS II -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V HSTL CLASS I -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V HSTL CLASS II -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V SSTL CLASS I -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V SSTL CLASS II -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V SSTL CLASS I -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V SSTL CLASS II -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 1.379 1.827 1.502 2.068 1.631 2.299 1.568 2.178 1.912 2.118 1.509 2.089 1.636 2.323 1.573 2.199 1.952 2.170 DIFFERENTIAL 2.5-V SSTL CLASS I -1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-248 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-116. EP3SE80 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS II GCLK GCLK PLL tsu th tsu th -0.781 0.907 1.124 -0.861 -0.827 0.969 1.141 -0.861 -1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 1.379 1.827 1.502 2.068 1.631 2.299 1.568 2.178 1.912 2.118 1.509 2.089 1.636 2.323 1.573 2.199 1.952 2.170 ns ns ns ns -1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 Table 1-117 lists the EP3SE80 column pins output timing parameters for differential I/O standards. Table 1-117. EP3SE80 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco 3.152 1.328 3.148 1.324 3.152 1.328 3.148 1.324 3.152 1.328 3.148 1.324 3.387 1.502 3.390 1.505 3.387 1.502 3.390 1.505 3.387 1.502 3.390 1.505 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-249 Table 1-117. EP3SE80 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.179 1.355 3.169 1.345 3.169 1.345 3.162 1.338 3.161 1.337 3.183 1.359 3.173 1.349 3.168 1.344 3.166 1.342 3.158 1.334 3.159 1.335 3.158 1.334 3.420 1.535 3.410 1.525 3.410 1.525 3.404 1.519 3.402 1.517 3.424 1.539 3.413 1.528 3.409 1.524 3.407 1.522 3.398 1.513 3.400 1.515 3.397 1.512 4.828 5.233 5.750 5.610 5.910 5.358 5.875 5.736 5.985 1.984 2.084 2.298 2.309 2.335 2.190 2.407 2.417 2.323 4.818 5.222 5.740 5.600 5.900 5.347 5.865 5.726 5.975 1.974 2.073 2.288 2.299 2.325 2.179 2.397 2.407 2.313 4.821 5.226 5.744 5.604 5.904 5.352 5.870 5.731 5.980 1.977 2.077 2.292 2.303 2.329 2.184 2.402 2.412 2.318 4.814 5.220 5.738 5.598 5.898 5.345 5.864 5.725 5.974 1.970 2.071 2.286 2.297 2.323 2.177 2.396 2.406 2.312 4.811 5.217 5.735 5.595 5.895 5.342 5.860 5.721 5.970 1.967 2.068 2.283 2.294 2.320 2.174 2.392 2.402 2.308 4.832 5.237 5.754 5.614 5.914 5.362 5.880 5.741 5.990 1.988 2.088 2.302 2.313 2.339 2.194 2.412 2.422 2.328 4.811 5.214 5.729 5.589 5.889 5.338 5.853 5.714 5.963 1.967 2.065 2.277 2.288 2.314 2.170 2.385 2.395 2.301 4.811 5.214 5.730 5.590 5.890 5.339 5.855 5.716 5.965 1.967 2.065 2.278 2.289 2.315 2.171 2.387 2.397 2.303 4.810 5.213 5.728 5.588 5.888 5.338 5.854 5.715 5.964 1.966 2.064 2.276 2.287 2.313 2.170 2.386 2.396 2.302 4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954 1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292 4.806 5.210 5.727 5.587 5.887 5.336 5.853 5.714 5.963 1.962 2.061 2.275 2.286 2.312 2.168 2.385 2.395 2.301 4.789 5.191 5.705 5.565 5.865 5.315 5.829 5.690 5.939 1.945 2.042 2.253 2.264 2.290 2.147 2.361 2.371 2.277 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-250 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-117. EP3SE80 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.170 1.346 3.166 1.342 3.156 1.332 3.154 1.330 3.154 1.330 3.158 1.334 3.184 1.360 3.170 1.346 3.158 1.334 3.158 1.334 3.154 1.330 3.158 1.334 3.159 1.335 3.410 1.525 3.407 1.522 3.396 1.511 3.394 1.509 3.395 1.510 3.398 1.513 3.427 1.542 3.413 1.528 3.400 1.515 3.400 1.515 3.396 1.511 3.398 1.513 3.400 1.515 4.807 5.209 5.723 5.583 5.883 5.334 5.848 5.709 5.958 1.963 2.060 2.271 2.282 2.308 2.166 2.380 2.390 2.296 4.808 5.211 5.727 5.587 5.887 5.336 5.852 5.713 5.962 1.964 2.062 2.275 2.286 2.312 2.168 2.384 2.394 2.300 4.797 5.200 5.715 5.575 5.875 5.325 5.840 5.701 5.950 1.953 2.051 2.263 2.274 2.300 2.157 2.372 2.382 2.288 4.795 5.197 5.713 5.573 5.873 5.323 5.838 5.699 5.948 1.951 2.048 2.261 2.272 2.298 2.155 2.370 2.380 2.286 4.798 5.202 5.718 5.578 5.878 5.327 5.844 5.705 5.954 1.954 2.053 2.266 2.277 2.303 2.159 2.376 2.386 2.292 4.795 5.197 5.712 5.572 5.872 5.322 5.837 5.698 5.947 1.951 2.048 2.260 2.271 2.297 2.154 2.369 2.379 2.285 4.840 5.245 5.762 5.622 5.922 5.370 5.887 5.748 5.997 1.996 2.096 2.310 2.321 2.347 2.202 2.419 2.429 2.335 4.828 5.234 5.752 5.612 5.912 5.360 5.878 5.739 5.988 1.984 2.085 2.300 2.311 2.337 2.192 2.410 2.420 2.326 4.811 5.216 5.734 5.594 5.894 5.342 5.860 5.721 5.970 1.967 2.067 2.282 2.293 2.319 2.174 2.392 2.402 2.308 4.814 5.220 5.738 5.598 5.898 5.346 5.865 5.726 5.975 1.970 2.071 2.286 2.297 2.323 2.178 2.397 2.407 2.313 4.807 5.212 5.731 5.591 5.891 5.339 5.857 5.718 5.967 1.963 2.063 2.279 2.290 2.316 2.171 2.389 2.399 2.305 4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954 1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292 4.808 5.213 5.730 5.590 5.890 5.338 5.856 5.717 5.966 1.964 2.064 2.278 2.289 2.315 2.170 2.388 2.398 2.304 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-251 Table 1-117. EP3SE80 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL = 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.187 1.363 3.176 1.352 3.171 1.347 3.157 1.333 3.155 1.331 3.159 1.335 3.159 1.335 3.175 1.351 3.175 1.351 3.165 1.341 3.158 1.334 3.430 1.545 3.418 1.533 3.414 1.529 3.399 1.514 3.397 1.512 3.399 1.514 3.400 1.515 3.417 1.532 3.417 1.532 3.407 1.522 3.399 1.514 4.839 5.243 5.760 5.620 5.920 5.369 5.885 5.746 5.995 1.995 2.094 2.308 2.319 2.345 2.201 2.417 2.427 2.333 4.827 5.231 5.748 5.608 5.908 5.357 5.873 5.734 5.983 1.983 2.082 2.296 2.307 2.333 2.189 2.405 2.415 2.321 4.827 5.232 5.749 5.609 5.909 5.358 5.875 5.736 5.985 1.983 2.083 2.297 2.308 2.334 2.190 2.407 2.417 2.323 4.809 5.213 5.730 5.590 5.890 5.339 5.857 5.718 5.967 1.965 2.064 2.278 2.289 2.315 2.171 2.389 2.399 2.305 4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302 4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289 4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302 4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977 1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315 4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977 1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315 4.813 5.216 5.732 5.592 5.892 5.342 5.858 5.719 5.968 1.969 2.067 2.280 2.291 2.317 2.174 2.390 2.400 2.306 4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 8mA DIFFERENTIAL 2.5-V SSTL CLASS I GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 2.5-V SSTL CLASS II 16mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-252 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-118 lists the EP3SE80 row pins output timing parameters for differential I/O standards. Table 1-118. EP3SE80 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.744 0.931 3.136 1.333 3.118 1.315 2.744 0.931 3.136 1.333 3.118 1.315 2.744 0.931 3.136 1.333 3.118 1.315 3.162 1.359 3.148 1.345 3.144 1.341 2.932 1.057 3.376 1.511 3.366 1.501 2.932 1.057 3.376 1.511 3.366 1.501 2.932 1.057 3.376 1.511 3.366 1.501 3.409 1.544 3.395 1.530 3.391 1.526 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.828 5.236 5.751 5.613 5.884 5.365 5.880 5.742 5.961 2.004 2.106 2.318 2.332 2.330 2.217 2.433 2.442 2.319 4.815 5.223 5.738 5.600 5.871 5.351 5.867 5.729 5.948 1.991 2.093 2.305 2.319 2.317 2.203 2.420 2.429 2.306 4.813 5.223 5.739 5.601 5.872 5.351 5.869 5.731 5.950 1.989 2.093 2.306 2.320 2.318 2.203 2.422 2.431 2.308 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-253 Table 1-118. EP3SE80 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.160 1.357 3.149 1.346 3.146 1.343 3.157 1.354 3.147 1.344 3.133 1.330 3.130 1.327 3.127 1.324 3.128 1.325 3.177 1.374 3.153 1.350 3.136 1.333 3.406 1.541 3.396 1.531 3.393 1.528 3.403 1.538 3.394 1.529 3.380 1.515 3.376 1.511 3.374 1.509 3.374 1.509 3.427 1.562 3.403 1.538 3.384 1.519 4.814 5.220 5.733 5.595 5.866 5.348 5.862 5.724 5.943 1.990 2.090 2.300 2.314 2.312 2.200 2.415 2.424 2.301 4.810 5.216 5.730 5.592 5.863 5.345 5.859 5.721 5.940 1.986 2.086 2.297 2.311 2.309 2.197 2.412 2.421 2.298 4.808 5.214 5.728 5.590 5.861 5.343 5.858 5.720 5.939 1.984 2.084 2.295 2.309 2.307 2.195 2.411 2.420 2.297 4.809 5.215 5.727 5.589 5.860 5.343 5.856 5.718 5.937 1.985 2.085 2.294 2.308 2.306 2.195 2.409 2.418 2.295 4.807 5.213 5.726 5.588 5.859 5.342 5.856 5.718 5.937 1.983 2.083 2.293 2.307 2.305 2.194 2.409 2.418 2.295 4.792 5.198 5.712 5.574 5.845 5.327 5.841 5.703 5.922 1.968 2.068 2.279 2.293 2.291 2.179 2.394 2.403 2.280 4.788 5.194 5.708 5.570 5.841 5.323 5.837 5.699 5.918 1.964 2.064 2.275 2.289 2.287 2.175 2.390 2.399 2.276 4.789 5.197 5.711 5.573 5.844 5.326 5.841 5.703 5.922 1.965 2.067 2.278 2.292 2.290 2.178 2.394 2.403 2.280 4.779 5.185 5.698 5.560 5.831 5.313 5.827 5.689 5.908 1.955 2.055 2.265 2.279 2.277 2.165 2.380 2.389 2.266 4.850 5.258 5.774 5.636 5.907 5.387 5.903 5.765 5.984 2.026 2.128 2.341 2.355 2.353 2.239 2.456 2.465 2.342 4.832 5.241 5.757 5.619 5.890 5.370 5.888 5.750 5.969 2.008 2.111 2.324 2.338 2.336 2.222 2.441 2.450 2.327 4.810 5.219 5.735 5.597 5.868 5.348 5.866 5.728 5.947 1.986 2.089 2.302 2.316 2.314 2.200 2.419 2.428 2.305 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA 8mA DIFFERENTIAL 1.8-V HSTL CLASS I 10mA 12mA 16mA 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-254 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-118. EP3SE80 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.181 1.378 3.166 1.363 3.155 1.352 3.135 1.332 3.132 1.329 3.137 1.334 3.130 1.327 3.168 1.365 3.150 1.347 3.136 1.333 3.430 1.565 3.415 1.550 3.404 1.539 3.384 1.519 3.380 1.515 3.384 1.519 3.377 1.512 3.416 1.551 3.399 1.534 3.383 1.518 4.850 5.258 5.773 5.635 5.906 5.387 5.903 5.765 5.984 2.026 2.128 2.340 2.354 2.352 2.239 2.456 2.465 2.342 4.836 5.243 5.758 5.620 5.891 5.372 5.888 5.750 5.969 2.012 2.113 2.325 2.339 2.337 2.224 2.441 2.450 2.327 4.831 5.240 5.755 5.617 5.888 5.369 5.886 5.748 5.967 2.007 2.110 2.322 2.336 2.334 2.221 2.439 2.448 2.325 4.808 5.216 5.732 5.594 5.865 5.346 5.862 5.724 5.943 1.984 2.086 2.299 2.313 2.311 2.198 2.415 2.424 2.301 4.804 5.213 5.728 5.590 5.861 5.342 5.859 5.721 5.940 1.980 2.083 2.295 2.309 2.307 2.194 2.412 2.421 2.298 4.795 5.201 5.714 5.576 5.847 5.329 5.843 5.705 5.924 1.971 2.071 2.281 2.295 2.293 2.181 2.396 2.405 2.282 4.794 5.202 5.717 5.579 5.850 5.332 5.848 5.710 5.929 1.970 2.072 2.284 2.298 2.296 2.184 2.401 2.410 2.287 4.832 5.239 5.753 5.615 5.886 5.368 5.883 5.745 5.964 2.008 2.109 2.320 2.334 2.332 2.220 2.436 2.445 2.322 4.817 5.224 5.738 5.600 5.871 5.353 5.868 5.730 5.949 1.993 2.094 2.305 2.319 2.317 2.205 2.421 2.430 2.307 4.794 5.200 5.713 5.575 5.846 5.329 5.843 5.705 5.924 1.970 2.070 2.280 2.294 2.292 2.181 2.396 2.405 2.282 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA DIFFERENTIAL 1.8-V SSTL CLASS I 8mA 10mA 12mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS II 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V SSTL CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-255 Table 1-119 and Table 1-120 list the EP3SE80 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-119 lists the EP3SE80 column pin delay adders when using the regional clock. Table 1-119. EP3SE80 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.251 1.895 -0.069 -1.545 0.187 1.982 0.253 -1.367 0.308 2.923 0.551 0.239 3.16 0.865 0.389 3.601 0.693 0.103 4.28 0.176 4.913 0.199 3.261 1.06 0.102 4.491 0.135 0.099 4.295 0.066 0.172 4.833 -0.046 ns ns ns ns -0.059 -0.119 -1.715 -1.587 -1.976 -3.145 -3.116 -1.541 -3.343 -3.027 -3.123 Table 1-120 lists the EP3SE80 row pin delay adders when using the regional clock. Table 1-120. EP3SE80 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.014 0.116 0.004 -0.089 0.014 0.122 0.003 -0.089 0.018 0.192 0.029 0.005 0.206 0.042 -0.022 0.231 0.056 0.0 0.217 0.039 0.052 0.367 -0.021 -0.004 -0.014 -0.008 0.198 0.047 0.223 0.061 0.21 0.049 0.056 0.371 -0.025 ns ns ns ns -0.145 -0.161 -0.197 -0.169 -0.332 -0.151 -0.186 -0.157 -0.333 EP3SE110 I/O Timing Parameters Table 1-121 through Table 1-124 list the maximum I/O timing parameters for EP3SE110 for single-ended I/O standards. Table 1-121 lists the EP3SE110 column pins input timing parameters for single-ended I/O standards. Table 1-121. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th -1.030 1.172 -1.297 1.600 -1.030 1.172 -1.297 1.600 -1.006 1.144 -1.267 1.565 -1.006 1.144 -1.267 1.565 -1.454 1.648 -1.831 2.262 -1.454 1.648 -1.831 2.262 -1.613 1.838 -2.023 2.514 -1.613 1.838 -2.023 2.514 -1.847 -1.786 -2.148 -1.613 -1.847 -1.786 -2.148 2.093 2.793 2.093 2.793 2.017 2.689 2.017 2.689 2.385 3.180 2.385 3.180 1.838 2.514 1.838 2.514 2.093 2.793 2.093 2.793 2.017 2.689 2.017 2.689 2.385 3.180 2.385 3.180 -2.261 -2.187 -2.655 -2.023 -2.261 -2.187 -2.655 -1.847 -1.786 -2.148 -1.613 -1.847 -1.786 -2.148 -2.261 -2.187 -2.655 -2.023 -2.261 -2.187 -2.655 ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-256 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-121. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 3.0-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.041 1.183 -1.308 1.611 -1.041 1.183 -1.308 1.611 -1.036 1.178 -1.303 1.606 -1.058 1.202 -1.325 1.630 -1.048 1.192 -1.315 1.620 -0.996 1.140 -1.263 1.568 -0.967 1.111 -1.234 1.539 -0.967 1.111 -1.234 1.539 -0.961 1.105 -1.228 1.533 -1.017 1.155 -1.278 1.576 -1.017 1.155 -1.278 1.576 -1.012 1.150 -1.273 1.571 -1.034 1.174 -1.295 1.595 -1.024 1.164 -1.285 1.585 -0.972 1.112 -1.233 1.533 -0.943 1.083 -1.204 1.504 -0.943 1.083 -1.204 1.504 -0.937 1.077 -1.198 1.498 -1.453 1.647 -1.830 2.261 -1.453 1.647 -1.830 2.261 -1.462 1.656 -1.839 2.270 -1.502 1.696 -1.879 2.310 -1.479 1.673 -1.856 2.287 -1.402 1.596 -1.779 2.210 -1.374 1.568 -1.751 2.182 -1.374 1.568 -1.751 2.182 -1.361 1.555 -1.738 2.169 -1.615 1.840 -2.025 2.516 -1.615 1.840 -2.025 2.516 -1.627 1.852 -2.037 2.528 -1.663 1.888 -2.073 2.564 -1.631 1.856 -2.041 2.532 -1.532 1.757 -1.942 2.433 -1.516 1.741 -1.926 2.417 -1.516 1.741 -1.926 2.417 -1.508 1.730 -1.918 2.406 -1.846 -1.785 -2.147 -1.615 -1.846 -1.785 -2.147 2.092 2.792 2.092 2.792 2.111 2.811 2.109 2.809 2.039 2.739 1.883 2.583 1.885 2.585 1.885 2.585 1.879 2.579 2.016 2.688 2.016 2.688 2.035 2.707 2.033 2.705 1.963 2.635 1.807 2.479 1.809 2.481 1.809 2.481 1.803 2.475 2.384 3.179 2.384 3.179 2.403 3.198 2.401 3.196 2.331 3.126 2.175 2.970 2.177 2.972 2.177 2.972 2.170 2.965 1.840 2.516 1.840 2.516 1.852 2.528 1.888 2.564 1.856 2.532 1.757 2.433 1.741 2.417 1.741 2.417 1.730 2.406 2.092 2.792 2.092 2.792 2.111 2.811 2.109 2.809 2.039 2.739 1.883 2.583 1.885 2.585 1.885 2.585 1.879 2.579 2.016 2.688 2.016 2.688 2.035 2.707 2.033 2.705 1.963 2.635 1.807 2.479 1.809 2.481 1.809 2.481 1.803 2.475 2.384 3.179 2.384 3.179 2.403 3.198 2.401 3.196 2.331 3.126 2.175 2.970 2.177 2.972 2.177 2.972 2.170 2.965 -2.260 -2.186 -2.654 -2.025 -2.260 -2.186 -2.654 -1.846 -1.785 -2.147 -1.615 -1.846 -1.785 -2.147 -2.260 -2.186 -2.654 -2.025 -2.260 -2.186 -2.654 -1.865 -1.804 -2.166 -1.627 -1.865 -1.804 -2.166 -2.279 -2.205 -2.673 -2.037 -2.279 -2.205 -2.673 -1.863 -1.802 -2.164 -1.663 -1.863 -1.802 -2.164 -2.277 -2.203 -2.671 -2.073 -2.277 -2.203 -2.671 -1.793 -1.732 -2.094 -1.631 -1.793 -1.732 -2.094 -2.207 -2.133 -2.601 -2.041 -2.207 -2.133 -2.601 -1.637 -1.576 -1.938 -1.532 -1.637 -1.576 -1.938 -2.051 -1.977 -2.445 -1.942 -2.051 -1.977 -2.445 -1.639 -1.578 -1.940 -1.516 -1.639 -1.578 -1.940 -2.053 -1.979 -2.447 -1.926 -2.053 -1.979 -2.447 -1.639 -1.578 -1.940 -1.516 -1.639 -1.578 -1.940 -2.053 -1.979 -2.447 -1.926 -2.053 -1.979 -2.447 -1.636 -1.573 -1.938 -1.508 -1.636 -1.573 -1.938 -2.050 -1.974 -2.445 -1.918 -2.050 -1.974 -2.445 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL GCLK SSTL-2 CLASS I GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-257 Table 1-121. EP3SE110 Column Pins Input Timing Parameters (Part 3 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK SSTL-18 CLASS II tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.961 1.105 -1.228 1.533 -0.950 1.094 -1.217 1.522 -0.950 1.094 -1.217 1.522 -0.961 1.105 -1.228 1.533 -0.961 1.105 -1.228 1.533 -0.950 1.094 -1.217 1.522 -0.950 1.094 -1.217 1.522 -0.938 1.082 -1.205 1.510 -0.938 1.082 -1.205 1.510 -0.937 1.077 -1.198 1.498 -0.926 1.066 -1.187 1.487 -0.926 1.066 -1.187 1.487 -0.937 1.077 -1.198 1.498 -0.937 1.077 -1.198 1.498 -0.926 1.066 -1.187 1.487 -0.926 1.066 -1.187 1.487 -0.914 1.054 -1.175 1.475 -0.914 1.054 -1.175 1.475 -1.361 1.555 -1.738 2.169 -1.350 1.543 -1.727 2.157 -1.350 1.543 -1.727 2.157 -1.361 1.555 -1.738 2.169 -1.361 1.555 -1.738 2.169 -1.350 1.543 -1.727 2.157 -1.350 1.543 -1.727 2.157 -1.340 1.533 -1.717 2.147 -1.340 1.533 -1.717 2.147 -1.508 1.730 -1.918 2.406 -1.497 1.719 -1.907 2.395 -1.497 1.719 -1.907 2.395 -1.508 1.730 -1.918 2.406 -1.508 1.730 -1.918 2.406 -1.497 1.719 -1.907 2.395 -1.497 1.719 -1.907 2.395 -1.486 1.708 -1.896 2.384 -1.486 1.708 -1.896 2.384 -1.636 -1.573 -1.938 -1.508 -1.636 -1.573 -1.938 1.879 2.579 1.860 2.560 1.860 2.560 1.879 2.579 1.879 2.579 1.860 2.560 1.860 2.560 1.844 2.544 1.844 2.544 1.803 2.475 1.784 2.456 1.784 2.456 1.803 2.475 1.803 2.475 1.784 2.456 1.784 2.456 1.768 2.440 1.768 2.440 2.170 2.965 2.151 2.946 2.151 2.946 2.170 2.965 2.170 2.965 2.151 2.946 2.151 2.946 2.135 2.930 2.135 2.930 1.730 2.406 1.719 2.395 1.719 2.395 1.730 2.406 1.730 2.406 1.719 2.395 1.719 2.395 1.708 2.384 1.708 2.384 1.879 2.579 1.860 2.560 1.860 2.560 1.879 2.579 1.879 2.579 1.860 2.560 1.860 2.560 1.844 2.544 1.844 2.544 1.803 2.475 1.784 2.456 1.784 2.456 1.803 2.475 1.803 2.475 1.784 2.456 1.784 2.456 1.768 2.440 1.768 2.440 2.170 2.965 2.151 2.946 2.151 2.946 2.170 2.965 2.170 2.965 2.151 2.946 2.151 2.946 2.135 2.930 2.135 2.930 -2.050 -1.974 -2.445 -1.918 -2.050 -1.974 -2.445 -1.617 -1.554 -1.919 -1.497 -1.617 -1.554 -1.919 -2.031 -1.955 -2.426 -1.907 -2.031 -1.955 -2.426 -1.617 -1.554 -1.919 -1.497 -1.617 -1.554 -1.919 -2.031 -1.955 -2.426 -1.907 -2.031 -1.955 -2.426 -1.636 -1.573 -1.938 -1.508 -1.636 -1.573 -1.938 -2.050 -1.974 -2.445 -1.918 -2.050 -1.974 -2.445 -1.636 -1.573 -1.938 -1.508 -1.636 -1.573 -1.938 -2.050 -1.974 -2.445 -1.918 -2.050 -1.974 -2.445 -1.617 -1.554 -1.919 -1.497 -1.617 -1.554 -1.919 -2.031 -1.955 -2.426 -1.907 -2.031 -1.955 -2.426 -1.617 -1.554 -1.919 -1.497 -1.617 -1.554 -1.919 -2.031 -1.955 -2.426 -1.907 -2.031 -1.955 -2.426 -1.601 -1.538 -1.903 -1.486 -1.601 -1.538 -1.903 -2.015 -1.939 -2.410 -1.896 -2.015 -1.939 -2.410 -1.601 -1.538 -1.903 -1.486 -1.601 -1.538 -1.903 -2.015 -1.939 -2.410 -1.896 -2.015 -1.939 -2.410 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL GCLK 1.2-V HSTL CLASS I GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-258 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-121. EP3SE110 Column Pins Input Timing Parameters (Part 4 of 4) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK 3.0-V PCI-X tsu th tsu th -1.041 1.183 -1.308 1.611 -1.017 1.155 -1.278 1.576 -1.453 1.647 -1.830 2.261 -1.615 1.840 -2.025 2.516 -1.846 -1.785 -2.147 -1.615 -1.846 -1.785 -2.147 2.092 2.792 2.016 2.688 2.384 3.179 1.840 2.516 2.092 2.792 2.016 2.688 2.384 3.179 -2.260 -2.186 -2.654 -2.025 -2.260 -2.186 -2.654 ns ns ns ns GCLK PLL Table 1-122 lists the EP3SE110 row pins input timing parameters for single-ended I/O standards. Table 1-122. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.917 1.041 1.022 -0.762 -0.917 1.041 1.022 -0.762 -0.923 1.047 1.016 -0.756 -0.923 1.047 1.016 -0.756 -0.911 1.035 1.028 -0.768 -0.987 1.112 1.040 -0.777 -0.960 1.099 1.000 -0.722 -0.960 1.099 1.000 -0.722 -0.971 1.110 0.989 -0.711 -0.971 1.110 0.989 -0.711 -0.964 1.103 0.996 -0.718 -1.042 1.182 1.054 -0.773 -1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064 1.561 1.632 1.698 1.851 1.978 1.964 1.873 1.893 2.261 1.808 1.720 1.901 1.989 1.982 1.922 1.864 2.300 1.859 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357 -1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064 1.561 1.632 1.698 1.851 1.978 1.964 1.873 1.893 2.261 1.808 1.720 1.901 1.989 1.982 1.922 1.864 2.300 1.859 3.3-V LVCMOS GCLK PLL GCLK -1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357 -1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069 1.558 1.635 1.699 1.850 1.981 1.961 1.876 1.890 2.264 1.805 1.719 1.902 1.994 1.977 1.927 1.859 2.305 1.854 3.0-V LVTTL GCLK PLL GCLK -1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352 -1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069 1.558 1.635 1.699 1.850 1.981 1.961 1.876 1.890 2.264 1.805 1.719 1.902 1.994 1.977 1.927 1.859 2.305 1.854 3.0-V LVCMOS GCLK PLL GCLK -1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352 -1.370 -1.490 -1.754 -1.660 -2.044 -1.496 -1.752 -1.698 -2.079 1.567 1.626 1.712 1.837 1.996 1.946 1.891 1.875 2.279 1.790 1.728 1.893 2.004 1.967 1.937 1.849 2.315 1.844 2.5 V GCLK PLL GCLK 1.8 V -1.212 -1.372 -1.431 -1.388 -1.291 -1.418 -1.441 -1.353 -1.342 -1.456 -1.570 -1.756 -1.705 -2.042 -1.576 -1.754 -1.707 -2.080 1.653 1.703 1.793 1.929 1.999 1.948 1.936 1.963 2.277 1.900 1.808 1.946 2.007 1.966 1.948 1.848 2.316 1.952 GCLK PLL -1.286 -1.461 -1.433 -1.472 -1.399 -1.468 -1.440 -1.352 -1.447 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-259 Table 1-122. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5 V tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.977 1.102 1.050 -0.787 -0.917 1.042 1.110 -0.847 -0.854 0.979 1.085 -0.824 -0.854 0.979 1.085 -0.824 -0.891 1.016 1.136 -0.873 -0.891 1.016 1.136 -0.873 -0.877 1.002 1.150 -0.887 -0.891 1.016 1.136 -0.873 -0.891 1.016 1.136 -0.873 -1.031 1.171 1.065 -0.784 -0.978 1.118 1.118 -0.837 -0.906 1.046 1.054 -0.775 -0.906 1.046 1.054 -0.775 -0.943 1.083 1.153 -0.872 -0.943 1.083 1.153 -0.872 -0.931 1.071 1.165 -0.884 -0.943 1.083 1.153 -0.872 -0.943 1.083 1.153 -0.872 -1.432 -1.538 -1.688 -1.637 -1.974 -1.545 -1.689 -1.642 -2.015 1.629 1.727 1.761 1.961 1.931 2.016 1.868 2.031 2.209 1.968 1.777 1.977 1.942 2.031 1.883 1.913 2.251 2.017 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.2 V -1.310 -1.493 -1.501 -1.540 -1.467 -1.499 -1.505 -1.417 -1.512 -1.353 -1.437 -1.529 -1.478 -1.815 -1.449 -1.534 -1.487 -1.860 1.550 1.806 1.660 2.062 1.772 2.175 1.709 2.190 2.050 2.127 1.681 2.073 1.787 2.186 1.728 2.068 2.096 2.172 GCLK PLL GCLK SSTL-2 CLASS I -1.389 -1.594 -1.660 -1.699 -1.626 -1.595 -1.660 -1.572 -1.667 -1.284 -1.381 -1.534 -1.440 -1.824 -1.384 -1.535 -1.481 -1.862 1.481 1.712 1.603 1.946 1.776 2.166 1.671 2.095 2.059 2.010 1.616 2.005 1.787 2.184 1.720 2.066 2.098 2.061 GCLK PLL GCLK -1.298 -1.481 -1.651 -1.608 -1.511 -1.530 -1.658 -1.570 -1.559 -1.284 -1.381 -1.534 -1.440 -1.824 -1.384 -1.535 -1.481 -1.862 1.481 1.712 1.603 1.946 1.776 2.166 1.671 2.095 2.059 2.010 1.616 2.005 1.787 2.184 1.720 2.066 2.098 2.061 SSTL-2 CLASS II GCLK PLL GCLK -1.298 -1.481 -1.651 -1.608 -1.511 -1.530 -1.658 -1.570 -1.559 -1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853 1.512 1.844 1.631 2.087 1.765 2.180 1.702 2.193 2.042 2.129 1.647 2.102 1.778 2.193 1.719 2.076 2.085 2.177 SSTL-18 CLASS I GCLK PLL GCLK -1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676 -1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853 1.512 1.844 1.631 2.087 1.765 2.180 1.702 2.193 2.042 2.129 1.647 2.102 1.778 2.193 1.719 2.076 2.085 2.177 SSTL-18 CLASS II GCLK PLL GCLK -1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676 -1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836 1.498 1.857 1.621 2.097 1.747 2.198 1.684 2.211 2.024 2.147 1.636 2.113 1.761 2.210 1.702 2.093 2.068 2.194 SSTL-15 CLASS I GCLK PLL GCLK -1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693 -1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853 1.512 1.844 1.631 2.087 1.765 2.180 1.702 2.193 2.042 2.129 1.647 2.102 1.778 2.193 1.719 2.076 2.085 2.177 1.8-V HSTL CLASS I GCLK PLL GCLK -1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676 -1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853 1.512 1.844 1.631 2.087 1.765 2.180 1.702 2.193 2.042 2.129 1.647 2.102 1.778 2.193 1.719 2.076 2.085 2.177 1.8-V HSTL CLASS II GCLK PLL -1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-260 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-122. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.5-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.877 1.002 1.150 -0.887 -0.877 1.002 1.150 -0.887 -0.868 0.993 1.159 -0.896 -0.868 0.993 1.159 -0.896 -0.923 1.047 1.016 -0.756 -0.923 1.047 1.016 -0.756 -0.931 1.071 1.165 -0.884 -0.931 1.071 1.165 -0.884 -0.919 1.059 1.177 -0.896 -0.919 1.059 1.177 -0.896 -0.971 1.110 0.989 -0.711 -0.971 1.110 0.989 -0.711 -1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836 1.498 1.857 1.621 2.097 1.747 2.198 1.684 2.211 2.024 2.147 1.636 2.113 1.761 2.210 1.702 2.093 2.068 2.194 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693 -1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836 1.498 1.857 1.621 2.097 1.747 2.198 1.684 2.211 2.024 2.147 1.636 2.113 1.761 2.210 1.702 2.093 2.068 2.194 1.5-V HSTL CLASS II GCLK PLL GCLK -1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693 -1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820 1.489 1.866 1.611 2.107 1.731 2.214 1.668 2.227 2.008 2.163 1.627 2.122 1.745 2.226 1.686 2.109 2.052 2.210 1.2-V HSTL CLASS I GCLK PLL GCLK -1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709 -1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820 1.489 1.866 1.611 2.107 1.731 2.214 1.668 2.227 2.008 2.163 1.627 2.122 1.745 2.226 1.686 2.109 2.052 2.210 1.2-V HSTL CLASS II GCLK PLL GCLK -1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709 -1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069 1.558 1.635 1.699 1.850 1.981 1.961 1.876 1.890 2.264 1.805 1.719 1.902 1.994 1.977 1.927 1.859 2.305 1.854 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X -1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352 -1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069 1.558 1.635 1.699 1.850 1.981 1.961 1.876 1.890 2.264 1.805 1.719 1.902 1.994 1.977 1.927 1.859 2.305 1.854 GCLK PLL -1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-261 Table 1-123 lists the EP3SE110 column pins output timing parameters for single-ended I/O standards. Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.489 3.868 3.422 3.801 3.336 3.715 3.329 3.709 3.495 3.874 3.340 3.719 3.347 3.726 3.331 3.710 3.453 3.831 3.342 3.724 3.306 3.686 3.288 3.667 3.489 3.881 3.422 3.814 3.336 3.728 3.329 3.721 3.495 3.887 3.340 3.732 3.347 3.739 3.331 3.723 3.453 3.845 3.342 3.734 3.306 3.698 3.288 3.680 4.830 5.415 4.721 5.306 4.617 5.203 4.600 5.186 4.834 5.420 4.627 5.213 4.621 5.207 4.599 5.184 4.797 5.382 4.667 5.252 4.604 5.189 4.575 5.160 5.213 5.837 5.102 5.726 5.003 5.628 4.975 5.600 5.218 5.842 5.020 5.645 4.999 5.624 4.974 5.599 5.181 5.805 5.047 5.674 4.978 5.602 4.950 5.575 5.686 6.442 5.573 6.329 5.481 6.237 5.440 6.196 5.693 6.449 5.492 6.248 5.466 6.222 5.437 6.193 5.653 6.409 5.515 6.272 5.441 6.198 5.413 6.169 5.551 6.278 5.438 6.165 5.346 6.073 5.305 6.032 5.558 6.285 5.357 6.084 5.331 6.058 5.302 6.029 5.518 6.245 5.381 6.109 5.307 6.035 5.278 6.005 5.863 6.680 5.750 6.567 5.658 6.475 5.617 6.434 5.870 6.687 5.669 6.486 5.643 6.460 5.614 6.431 5.830 6.647 5.691 6.509 5.618 6.435 5.590 6.407 5.213 5.837 5.102 5.726 5.003 5.628 4.975 5.600 5.218 5.842 5.020 5.645 4.999 5.624 4.974 5.599 5.181 5.805 5.047 5.674 4.978 5.602 4.950 5.575 5.686 6.442 5.573 6.329 5.481 6.237 5.440 6.196 5.693 6.449 5.492 6.248 5.466 6.222 5.437 6.193 5.653 6.409 5.515 6.272 5.441 6.198 5.413 6.169 5.551 6.278 5.438 6.165 5.346 6.073 5.305 6.032 5.558 6.285 5.357 6.084 5.331 6.058 5.302 6.029 5.518 6.245 5.381 6.109 5.307 6.035 5.278 6.005 5.863 6.680 5.750 6.567 5.658 6.475 5.617 6.434 5.870 6.687 5.669 6.486 5.643 6.460 5.614 6.431 5.830 6.647 5.691 6.509 5.618 6.435 5.590 6.407 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-262 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.367 3.748 3.288 3.669 3.283 3.662 3.274 3.653 3.489 3.868 3.389 3.771 3.345 3.726 3.307 3.687 3.367 3.759 3.288 3.680 3.283 3.675 3.274 3.666 3.489 3.881 3.389 3.781 3.345 3.737 3.307 3.699 4.701 5.286 4.577 5.163 4.570 5.155 4.556 5.141 4.908 5.493 4.789 5.374 4.702 5.287 4.663 5.248 5.081 5.707 4.952 5.577 4.945 5.570 4.930 5.554 5.308 5.932 5.182 5.807 5.091 5.716 5.049 5.674 5.550 6.307 5.415 6.172 5.407 6.163 5.392 6.148 5.797 6.554 5.665 6.422 5.570 6.326 5.527 6.283 5.416 6.144 5.281 6.009 5.272 5.999 5.257 5.984 5.663 6.391 5.531 6.259 5.435 6.162 5.392 6.119 5.726 6.544 5.591 6.413 5.584 6.401 5.569 6.387 5.974 6.791 5.841 6.659 5.747 6.564 5.704 6.521 5.081 5.707 4.952 5.577 4.945 5.570 4.930 5.554 5.308 5.932 5.182 5.807 5.091 5.716 5.049 5.674 5.550 6.307 5.415 6.172 5.407 6.163 5.392 6.148 5.797 6.554 5.665 6.422 5.570 6.326 5.527 6.283 5.416 6.144 5.281 6.009 5.272 5.999 5.257 5.984 5.663 6.391 5.531 6.259 5.435 6.162 5.392 6.119 5.726 6.544 5.591 6.413 5.584 6.401 5.569 6.387 5.974 6.791 5.841 6.659 5.747 6.564 5.704 6.521 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-263 Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.680 4.059 3.499 3.881 3.417 3.796 3.397 3.776 3.334 3.713 3.316 3.696 3.626 4.005 3.414 3.793 3.389 3.769 3.378 3.757 3.323 3.702 3.318 3.696 3.680 4.072 3.499 3.891 3.417 3.809 3.397 3.789 3.334 3.726 3.316 3.708 3.626 4.018 3.414 3.806 3.389 3.781 3.378 3.770 3.323 3.715 3.318 3.710 5.229 5.815 4.950 5.536 4.843 5.429 4.785 5.370 4.724 5.309 4.703 5.289 5.158 5.743 4.839 5.424 4.772 5.357 4.755 5.340 4.717 5.302 4.700 5.286 5.668 6.291 5.359 5.984 5.244 5.868 5.190 5.814 5.115 5.740 5.094 5.719 5.600 6.224 5.244 5.867 5.184 5.809 5.159 5.784 5.108 5.733 5.097 5.720 6.202 6.958 5.854 6.611 5.744 6.500 5.678 6.434 5.597 6.353 5.574 6.330 6.140 6.896 5.748 6.504 5.681 6.437 5.661 6.417 5.591 6.347 5.580 6.336 6.067 6.794 5.720 6.448 5.609 6.336 5.543 6.270 5.462 6.189 5.439 6.166 6.005 6.732 5.613 6.340 5.546 6.273 5.526 6.253 5.456 6.183 5.445 6.172 6.379 7.196 6.030 6.848 5.921 6.738 5.855 6.672 5.774 6.591 5.751 6.568 6.317 7.134 5.925 6.742 5.858 6.675 5.838 6.655 5.768 6.585 5.757 6.574 5.668 6.291 5.359 5.984 5.244 5.868 5.190 5.814 5.115 5.740 5.094 5.719 5.600 6.224 5.244 5.867 5.184 5.809 5.159 5.784 5.108 5.733 5.097 5.720 6.202 6.958 5.854 6.611 5.744 6.500 5.678 6.434 5.597 6.353 5.574 6.330 6.140 6.896 5.748 6.504 5.681 6.437 5.661 6.417 5.591 6.347 5.580 6.336 6.067 6.794 5.720 6.448 5.609 6.336 5.543 6.270 5.462 6.189 5.439 6.166 6.005 6.732 5.613 6.340 5.546 6.273 5.526 6.253 5.456 6.183 5.445 6.172 6.379 7.196 6.030 6.848 5.921 6.738 5.855 6.672 5.774 6.591 5.751 6.568 6.317 7.134 5.925 6.742 5.858 6.675 5.838 6.655 5.768 6.585 5.757 6.574 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-264 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.542 3.921 3.419 3.799 3.381 3.761 3.334 3.712 3.334 3.713 3.331 3.710 3.329 3.709 3.320 3.700 3.341 3.720 3.337 3.716 3.326 3.706 3.315 3.694 3.315 3.694 3.542 3.934 3.419 3.811 3.381 3.773 3.334 3.726 3.334 3.726 3.331 3.723 3.329 3.721 3.320 3.712 3.341 3.733 3.337 3.729 3.326 3.718 3.315 3.707 3.315 3.707 5.084 5.669 4.858 5.444 4.766 5.351 4.738 5.323 4.695 5.280 4.692 5.277 4.692 5.277 4.677 5.263 4.707 5.292 4.705 5.290 4.695 5.280 4.682 5.268 4.682 5.267 5.536 6.159 5.274 5.899 5.185 5.809 5.136 5.759 5.083 5.706 5.080 5.702 5.081 5.703 5.065 5.689 5.097 5.720 5.095 5.718 5.086 5.709 5.073 5.696 5.073 5.696 6.084 6.840 5.798 6.554 5.685 6.441 5.629 6.385 5.560 6.316 5.556 6.312 5.557 6.313 5.542 6.298 5.576 6.332 5.574 6.330 5.565 6.321 5.552 6.308 5.552 6.308 5.949 6.676 5.663 6.390 5.550 6.277 5.494 6.221 5.425 6.152 5.421 6.148 5.422 6.149 5.407 6.134 5.441 6.168 5.439 6.166 5.430 6.157 5.417 6.144 5.417 6.144 6.261 7.078 5.975 6.792 5.862 6.679 5.806 6.623 5.737 6.554 5.733 6.550 5.734 6.551 5.719 6.536 5.753 6.570 5.751 6.568 5.742 6.559 5.729 6.546 5.729 6.546 5.536 6.159 5.274 5.899 5.185 5.809 5.136 5.759 5.083 5.706 5.080 5.702 5.081 5.703 5.065 5.689 5.097 5.720 5.095 5.718 5.086 5.709 5.073 5.696 5.073 5.696 6.084 6.840 5.798 6.554 5.685 6.441 5.629 6.385 5.560 6.316 5.556 6.312 5.557 6.313 5.542 6.298 5.576 6.332 5.574 6.330 5.565 6.321 5.552 6.308 5.552 6.308 5.949 6.676 5.663 6.390 5.550 6.277 5.494 6.221 5.425 6.152 5.421 6.148 5.422 6.149 5.407 6.134 5.441 6.168 5.439 6.166 5.430 6.157 5.417 6.144 5.417 6.144 6.261 7.078 5.975 6.792 5.862 6.679 5.806 6.623 5.737 6.554 5.733 6.550 5.734 6.551 5.719 6.536 5.753 6.570 5.751 6.568 5.742 6.559 5.729 6.546 5.729 6.546 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-265 Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 8mA SSTL-18 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.321 3.701 3.324 3.703 3.345 3.723 3.331 3.711 3.320 3.699 3.319 3.698 3.316 3.695 3.318 3.697 3.321 3.700 3.321 3.713 3.324 3.716 3.345 3.737 3.331 3.723 3.320 3.712 3.319 3.711 3.316 3.708 3.318 3.710 3.321 3.713 4.681 5.266 4.689 5.274 4.716 5.302 4.706 5.291 4.692 5.278 4.695 5.281 4.690 5.275 4.679 5.264 4.686 5.271 5.070 5.693 5.079 5.702 5.109 5.731 5.099 5.722 5.085 5.708 5.088 5.711 5.083 5.705 5.069 5.692 5.078 5.700 5.547 6.303 5.559 6.315 5.589 6.345 5.580 6.336 5.566 6.322 5.570 6.326 5.564 6.320 5.547 6.303 5.558 6.314 5.412 6.139 5.424 6.151 5.454 6.181 5.445 6.172 5.431 6.158 5.435 6.162 5.429 6.156 5.412 6.139 5.423 6.150 5.724 6.541 5.736 6.553 5.766 6.583 5.757 6.574 5.743 6.560 5.747 6.564 5.741 6.558 5.724 6.541 5.735 6.552 5.070 5.693 5.079 5.702 5.109 5.731 5.099 5.722 5.085 5.708 5.088 5.711 5.083 5.705 5.069 5.692 5.078 5.700 5.547 6.303 5.559 6.315 5.589 6.345 5.580 6.336 5.566 6.322 5.570 6.326 5.564 6.320 5.547 6.303 5.558 6.314 5.412 6.139 5.424 6.151 5.454 6.181 5.445 6.172 5.431 6.158 5.435 6.162 5.429 6.156 5.412 6.139 5.423 6.150 5.724 6.541 5.736 6.553 5.766 6.583 5.757 6.574 5.743 6.560 5.747 6.564 5.741 6.558 5.724 6.541 5.735 6.552 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-266 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.328 3.707 3.321 3.701 3.313 3.693 3.316 3.695 3.313 3.692 3.321 3.700 3.333 3.712 3.329 3.708 3.325 3.704 3.318 3.697 3.319 3.697 3.317 3.695 3.328 3.720 3.321 3.713 3.313 3.705 3.316 3.708 3.313 3.705 3.321 3.713 3.333 3.725 3.329 3.721 3.325 3.717 3.318 3.710 3.319 3.711 3.317 3.709 4.681 5.266 4.679 5.264 4.671 5.257 4.674 5.260 4.677 5.262 4.676 5.261 4.689 5.275 4.690 5.276 4.686 5.271 4.679 5.264 4.686 5.271 4.667 5.252 5.069 5.691 5.067 5.691 5.060 5.683 5.063 5.686 5.067 5.689 5.064 5.687 5.079 5.701 5.080 5.704 5.076 5.699 5.069 5.692 5.077 5.699 5.055 5.677 5.545 6.301 5.544 6.300 5.537 6.293 5.541 6.297 5.545 6.301 5.541 6.297 5.556 6.312 5.559 6.315 5.554 6.310 5.547 6.303 5.557 6.313 5.531 6.287 5.410 6.137 5.409 6.136 5.402 6.129 5.406 6.133 5.410 6.137 5.406 6.133 5.421 6.148 5.424 6.151 5.419 6.146 5.412 6.139 5.422 6.149 5.396 6.123 5.722 6.539 5.721 6.538 5.714 6.531 5.718 6.535 5.722 6.539 5.718 6.535 5.733 6.550 5.736 6.553 5.731 6.548 5.724 6.541 5.734 6.551 5.708 6.525 5.069 5.691 5.067 5.691 5.060 5.683 5.063 5.686 5.067 5.689 5.064 5.687 5.079 5.701 5.080 5.704 5.076 5.699 5.069 5.692 5.077 5.699 5.055 5.677 5.545 6.301 5.544 6.300 5.537 6.293 5.541 6.297 5.545 6.301 5.541 6.297 5.556 6.312 5.559 6.315 5.554 6.310 5.547 6.303 5.557 6.313 5.531 6.287 5.410 6.137 5.409 6.136 5.402 6.129 5.406 6.133 5.410 6.137 5.406 6.133 5.421 6.148 5.424 6.151 5.419 6.146 5.412 6.139 5.422 6.149 5.396 6.123 5.722 6.539 5.721 6.538 5.714 6.531 5.718 6.535 5.722 6.539 5.718 6.535 5.733 6.550 5.736 6.553 5.731 6.548 5.724 6.541 5.734 6.551 5.708 6.525 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-267 Table 1-123. EP3SE110 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL = 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V UnitS Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.336 3.716 3.328 3.707 3.329 3.707 3.318 3.697 3.318 3.697 3.339 3.718 3.442 3.821 3.442 3.821 3.336 3.728 3.328 3.720 3.329 3.721 3.318 3.710 3.318 3.710 3.339 3.731 3.442 3.834 3.442 3.834 4.703 5.289 4.694 5.280 4.702 5.287 4.689 5.274 4.689 5.274 4.705 5.290 4.750 5.335 4.750 5.335 5.096 5.719 5.087 5.710 5.095 5.718 5.082 5.704 5.082 5.705 5.097 5.720 5.131 5.756 5.131 5.756 5.577 6.333 5.568 6.324 5.577 6.333 5.563 6.319 5.564 6.320 5.577 6.333 5.602 6.358 5.602 6.358 5.442 6.169 5.433 6.160 5.442 6.169 5.428 6.155 5.429 6.156 5.442 6.169 5.467 6.194 5.467 6.194 5.754 6.571 5.745 6.562 5.754 6.571 5.740 6.557 5.741 6.558 5.754 6.571 5.779 6.596 5.779 6.596 5.096 5.719 5.087 5.710 5.095 5.718 5.082 5.704 5.082 5.705 5.097 5.720 5.131 5.756 5.131 5.756 5.577 6.333 5.568 6.324 5.577 6.333 5.563 6.319 5.564 6.320 5.577 6.333 5.602 6.358 5.602 6.358 5.442 6.169 5.433 6.160 5.442 6.169 5.428 6.155 5.429 6.156 5.442 6.169 5.467 6.194 5.467 6.194 5.754 6.571 5.745 6.562 5.754 6.571 5.740 6.557 5.741 6.558 5.754 6.571 5.779 6.596 5.779 6.596 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Table 1-124 lists the EP3SE110 row pins output timing parameters for single-ended I/O standards. Table 1-124. EP3SE110 Row Pins Output Timing Parameters (Part 1 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL tco tco tco tco tco tco 3.208 1.452 3.142 1.359 3.063 1.260 3.456 1.625 3.385 1.554 3.296 1.465 4.797 5.180 5.703 5.543 5.850 5.304 5.827 5.696 5.930 2.008 2.086 2.326 2.346 2.347 2.239 2.435 2.455 2.342 4.687 5.069 5.589 5.429 5.736 5.191 5.712 5.581 5.815 1.898 1.975 2.181 2.201 2.202 2.098 2.286 2.306 2.193 4.581 4.969 5.493 5.333 5.640 5.092 5.612 5.481 5.715 1.792 1.875 2.053 2.073 2.074 1.971 2.154 2.174 2.061 ns ns ns ns ns ns 3.3-V LVTTL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-268 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-124. EP3SE110 Row Pins Output Timing Parameters (Part 2 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.210 1.462 3.067 1.264 3.169 1.406 3.068 1.281 3.031 1.242 3.090 1.320 3.018 1.220 3.195 1.432 3.110 1.322 3.053 1.276 3.458 1.663 3.233 1.438 3.168 1.373 3.108 1.313 3.463 1.632 3.300 1.469 3.417 1.586 3.305 1.474 3.267 1.436 3.329 1.498 3.251 1.420 3.454 1.623 3.351 1.520 3.307 1.476 3.730 1.874 3.528 1.672 3.426 1.570 3.352 1.496 4.801 5.186 5.712 5.552 5.859 5.312 5.839 5.708 5.942 2.012 2.092 2.330 2.350 2.351 2.245 2.439 2.459 2.346 4.592 4.984 5.503 5.343 5.650 5.104 5.621 5.490 5.724 1.803 1.890 2.059 2.079 2.080 1.977 2.161 2.181 2.068 4.764 5.149 5.669 5.509 5.816 5.272 5.793 5.662 5.896 1.975 2.055 2.282 2.302 2.303 2.196 2.393 2.413 2.300 4.627 5.007 5.524 5.364 5.671 5.130 5.648 5.516 5.750 1.838 1.913 2.118 2.138 2.139 2.034 2.229 2.248 2.135 4.567 4.942 5.454 5.294 5.601 5.062 5.574 5.443 5.677 1.778 1.848 2.030 2.050 2.051 1.948 2.136 2.155 2.042 4.662 5.042 5.560 5.400 5.707 5.163 5.684 5.552 5.786 1.873 1.948 2.172 2.192 2.193 2.088 2.282 2.301 2.188 4.539 4.913 5.426 5.266 5.573 5.032 5.546 5.414 5.648 1.750 1.819 1.991 2.011 2.012 1.908 2.096 2.115 2.002 4.872 5.275 5.814 5.654 5.961 5.404 5.945 5.814 6.048 2.083 2.181 2.454 2.474 2.475 2.356 2.572 2.591 2.478 4.748 5.140 5.672 5.512 5.819 5.267 5.801 5.669 5.903 1.959 2.046 2.284 2.304 2.305 2.189 2.398 2.417 2.304 4.664 5.054 5.581 5.421 5.728 5.178 5.706 5.575 5.809 1.875 1.960 2.158 2.178 2.179 2.066 2.268 2.287 2.174 5.334 5.790 6.350 6.220 6.500 5.931 6.493 6.365 6.600 2.520 2.669 2.929 2.949 2.954 2.792 3.056 3.075 2.967 5.007 5.421 5.945 5.815 6.095 5.566 6.087 5.958 6.193 2.193 2.300 2.524 2.544 2.549 2.427 2.650 2.668 2.560 4.854 5.271 5.786 5.656 5.936 5.398 5.914 5.786 6.021 2.040 2.150 2.365 2.385 2.390 2.259 2.477 2.496 2.388 4.777 5.177 5.691 5.559 5.839 5.303 5.820 5.692 5.927 1.963 2.056 2.268 2.288 2.293 2.164 2.383 2.402 2.294 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-269 Table 1-124. EP3SE110 Row Pins Output Timing Parameters (Part 3 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.369 1.574 3.127 1.332 3.100 1.305 3.091 1.296 3.312 1.517 3.132 1.337 3.057 1.261 3.052 1.249 3.043 1.234 3.069 1.274 3.054 1.259 3.043 1.248 3.030 1.228 3.030 1.228 3.648 1.792 3.390 1.534 3.343 1.487 3.334 1.478 3.573 1.717 3.384 1.528 3.295 1.464 3.291 1.460 3.280 1.449 3.308 1.452 3.294 1.438 3.282 1.426 3.267 1.404 3.266 1.403 5.244 5.703 6.278 6.148 6.428 5.838 6.417 6.289 6.524 2.430 2.582 2.857 2.877 2.882 2.699 2.980 2.999 2.891 4.839 5.266 5.787 5.657 5.937 5.392 5.913 5.785 6.020 2.025 2.145 2.366 2.386 2.391 2.253 2.476 2.495 2.387 4.766 5.170 5.691 5.551 5.834 5.294 5.816 5.685 5.916 1.952 2.049 2.260 2.280 2.285 2.155 2.371 2.390 2.282 4.744 5.152 5.672 5.532 5.815 5.276 5.797 5.666 5.897 1.930 2.031 2.241 2.261 2.266 2.137 2.349 2.368 2.260 5.154 5.617 6.203 6.073 6.353 5.750 6.333 6.205 6.440 2.340 2.496 2.782 2.802 2.807 2.611 2.896 2.915 2.807 4.861 5.294 5.828 5.698 5.978 5.417 5.955 5.827 6.062 2.047 2.173 2.407 2.427 2.432 2.278 2.518 2.537 2.429 4.657 5.045 5.571 5.411 5.718 5.165 5.692 5.561 5.795 1.868 1.951 2.126 2.146 2.147 2.033 2.230 2.250 2.137 4.654 5.043 5.569 5.409 5.716 5.164 5.691 5.560 5.794 1.865 1.949 2.118 2.138 2.139 2.025 2.223 2.243 2.130 4.639 5.027 5.552 5.392 5.699 5.147 5.673 5.542 5.776 1.850 1.933 2.097 2.111 2.112 1.999 2.202 2.221 2.103 4.672 5.065 5.586 5.433 5.729 5.184 5.707 5.576 5.807 1.858 1.944 2.142 2.162 2.167 2.045 2.246 2.265 2.157 4.669 5.063 5.585 5.431 5.728 5.182 5.705 5.574 5.805 1.855 1.942 2.140 2.160 2.165 2.043 2.244 2.263 2.155 4.652 5.046 5.575 5.414 5.718 5.165 5.696 5.565 5.796 1.838 1.925 2.123 2.143 2.148 2.026 2.228 2.247 2.139 4.636 5.030 5.562 5.399 5.705 5.150 5.684 5.553 5.784 1.822 1.909 2.108 2.128 2.133 2.011 2.213 2.232 2.124 4.635 5.029 5.562 5.398 5.705 5.149 5.684 5.553 5.784 1.821 1.908 2.107 2.127 2.132 2.010 2.213 2.232 2.123 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK SSTL-18 CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-270 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-124. EP3SE110 Row Pins Output Timing Parameters (Part 4 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.038 1.236 3.039 1.237 3.065 1.270 3.046 1.247 3.035 1.233 3.045 1.249 3.038 1.237 3.029 1.227 3.032 1.230 3.028 1.226 3.036 1.234 3.051 1.256 3.045 1.244 3.041 1.240 3.273 1.411 3.276 1.413 3.304 1.448 3.283 1.426 3.271 1.409 3.280 1.424 3.273 1.412 3.265 1.402 3.267 1.404 3.264 1.401 3.272 1.409 3.287 1.431 3.280 1.421 3.276 1.416 4.633 5.025 5.557 5.392 5.700 5.144 5.678 5.547 5.778 1.819 1.904 2.102 2.121 2.126 2.005 2.207 2.226 2.116 4.639 5.031 5.567 5.400 5.710 5.150 5.689 5.558 5.789 1.818 1.905 2.112 2.123 2.128 2.007 2.218 2.237 2.120 4.683 5.079 5.599 5.450 5.742 5.197 5.719 5.588 5.819 1.869 1.958 2.159 2.179 2.184 2.058 2.262 2.281 2.173 4.665 5.062 5.589 5.433 5.732 5.181 5.710 5.579 5.810 1.851 1.941 2.142 2.162 2.167 2.042 2.246 2.265 2.157 4.648 5.044 5.576 5.415 5.719 5.163 5.697 5.566 5.797 1.834 1.923 2.124 2.144 2.149 2.024 2.229 2.248 2.140 4.639 5.030 5.555 5.395 5.698 5.148 5.675 5.544 5.775 1.825 1.909 2.104 2.124 2.129 2.009 2.208 2.227 2.119 4.630 5.022 5.554 5.387 5.697 5.140 5.675 5.544 5.775 1.816 1.901 2.099 2.116 2.121 2.001 2.204 2.223 2.112 4.623 5.013 5.547 5.380 5.690 5.132 5.668 5.537 5.768 1.807 1.892 2.092 2.108 2.113 1.993 2.197 2.216 2.104 4.626 5.016 5.551 5.384 5.694 5.135 5.671 5.540 5.771 1.810 1.895 2.096 2.111 2.116 1.996 2.200 2.219 2.107 4.628 5.019 5.554 5.387 5.697 5.138 5.676 5.545 5.776 1.808 1.894 2.099 2.111 2.116 1.996 2.205 2.224 2.108 4.626 5.016 5.550 5.383 5.693 5.134 5.670 5.539 5.770 1.805 1.890 2.095 2.106 2.107 1.991 2.199 2.218 2.097 4.650 5.043 5.566 5.410 5.709 5.160 5.686 5.555 5.786 1.836 1.922 2.119 2.139 2.144 2.021 2.222 2.241 2.133 4.646 5.039 5.568 5.406 5.711 5.157 5.689 5.558 5.789 1.832 1.918 2.115 2.135 2.140 2.018 2.219 2.238 2.130 4.640 5.033 5.563 5.400 5.706 5.151 5.683 5.552 5.783 1.826 1.912 2.109 2.129 2.134 2.012 2.213 2.232 2.124 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.8-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 1.8-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA 1.5-V HSTL CLASS I GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-271 Table 1-124. EP3SE110 Row Pins Output Timing Parameters (Part 5 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco 3.053 1.255 3.044 1.243 3.043 1.241 3.163 1.354 3.163 1.354 3.287 1.430 3.279 1.418 3.279 1.416 3.401 1.570 3.401 1.570 4.661 5.057 5.585 5.428 5.728 5.174 5.705 5.574 5.805 1.847 1.936 2.137 2.157 2.162 2.035 2.239 2.258 2.150 4.650 5.045 5.576 5.416 5.719 5.163 5.696 5.565 5.796 1.836 1.924 2.125 2.145 2.150 2.024 2.228 2.247 2.139 4.654 5.050 5.585 5.422 5.728 5.169 5.706 5.575 5.806 1.840 1.929 2.131 2.151 2.156 2.030 2.235 2.254 2.146 4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837 1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149 4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837 1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149 ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Table 1-125 through Table 1-128 list the maximum I/O timing parameters for EP3SE110 devices for differential I/O standards. Table 1-125 lists the EP3SE110 column pins input timing parameters for differential I/O standards. Table 1-125. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK tsu th -0.997 1.133 0.960 -0.691 -0.997 1.133 0.960 -0.691 -0.997 1.133 0.960 -0.691 -0.813 0.942 1.144 -0.882 -1.029 1.184 0.994 -0.701 -1.029 1.184 0.994 -0.701 -1.029 1.184 0.994 -0.701 -0.852 0.999 1.171 -0.886 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL tsu th tsu -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 MINI-LVDS GCLK GCLK PLL th tsu th tsu th -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 1.415 1.879 1.436 2.224 1.618 2.401 1.551 2.288 1.927 2.194 1.411 2.277 1.858 2.567 1.524 2.345 1.966 2.245 RSDS GCLK tsu th -1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 -1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837 1.460 1.802 1.595 2.025 1.731 2.242 1.659 2.134 2.031 2.045 1.604 2.042 1.739 2.260 1.674 2.147 2.075 2.091 DIFFERENTIAL 1.2-V HSTL CLASS I GCLK GCLK PLL tsu th tsu th -1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-272 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-125. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.2-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.813 0.942 1.144 -0.882 -0.821 0.950 1.136 -0.874 -0.821 0.950 1.136 -0.874 -0.833 0.962 1.124 -0.862 -0.833 0.962 1.124 -0.862 -0.821 0.950 1.136 -0.874 -0.821 0.950 1.136 -0.874 -0.833 0.962 1.124 -0.862 -0.833 0.962 1.124 -0.862 -0.852 0.999 1.171 -0.886 -0.864 1.011 1.159 -0.874 -0.864 1.011 1.159 -0.874 -0.875 1.022 1.148 -0.863 -0.875 1.022 1.148 -0.863 -0.864 1.011 1.159 -0.874 -0.864 1.011 1.159 -0.874 -0.875 1.022 1.148 -0.863 -0.875 1.022 1.148 -0.863 -1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837 1.460 1.802 1.595 2.025 1.731 2.242 1.659 2.134 2.031 2.045 1.604 2.042 1.739 2.260 1.674 2.147 2.075 2.091 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V HSTL CLASS I -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V HSTL CLASS II -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V HSTL CLASS I -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V HSTL CLASS II -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V SSTL CLASS I -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 1.470 1.792 1.606 2.014 1.747 2.226 1.675 2.118 2.047 2.029 1.615 2.031 1.754 2.245 1.689 2.132 2.090 2.076 DIFFERENTIAL 1.5-V SSTL CLASS II -1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V SSTL CLASS I -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 -1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870 1.480 1.783 1.617 2.003 1.766 2.207 1.694 2.099 2.066 2.010 1.626 2.020 1.772 2.227 1.707 2.114 2.108 2.058 DIFFERENTIAL 1.8-V SSTL CLASS II -1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-273 Table 1-125. EP3SE110 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th -0.840 0.969 1.117 -0.855 -0.840 0.969 1.117 -0.855 -0.881 1.028 1.142 -0.857 -0.881 1.028 1.142 -0.857 -1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 1.493 1.771 1.625 1.998 1.769 2.207 1.697 2.097 2.070 2.011 1.633 2.016 1.772 2.232 1.706 2.116 2.109 2.062 ns ns ns ns ns ns ns ns -1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 -1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 1.493 1.771 1.625 1.998 1.769 2.207 1.697 2.097 2.070 2.011 1.633 2.016 1.772 2.232 1.706 2.116 2.109 2.062 DIFFERENTIAL 2.5-V SSTL CLASS II -1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 Table 1-126 lists the EP3SE110 row pins input timing parameters for differential I/O standards Table 1-126. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK LVDS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.944 1.077 0.961 -0.691 -0.944 1.077 0.961 -0.691 -0.944 1.077 0.961 -0.691 -0.749 0.875 1.156 -0.893 -0.749 0.875 1.156 -0.893 -0.979 1.130 0.989 -0.700 -0.979 1.130 0.989 -0.700 -0.979 1.130 0.989 -0.700 -0.794 0.936 1.174 -0.894 -0.794 0.936 1.174 -0.894 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK MINI-LVDS -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 GCLK PLL GCLK RSDS -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 1.288 1.951 1.285 2.328 1.447 2.533 1.389 2.408 1.737 2.342 1.257 2.387 1.412 2.599 1.355 2.472 1.777 2.394 GCLK PLL DIFFERENTIAL 1.2-V HSTL CLASS I -1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844 -1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 1.345 1.864 1.468 2.104 1.587 2.344 1.524 2.224 1.867 2.163 1.479 2.120 1.597 2.362 1.535 2.240 1.912 2.210 GCLK GCLK PLL GCLK GCLK PLL -1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 -1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677 1.345 1.864 1.468 2.104 1.587 2.344 1.524 2.224 1.867 2.163 1.479 2.120 1.597 2.362 1.535 2.240 1.912 2.210 DIFFERENTIAL 1.2-V HSTL CLASS II -1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-274 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-126. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.5-V HSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK tsu th tsu th tsu th tsu th tsu th tsu th tsu th -0.758 0.884 1.147 -0.884 -0.758 0.884 1.147 -0.884 -0.772 0.898 1.133 -0.870 -0.772 0.898 1.133 -0.870 -0.758 0.884 1.147 -0.884 -0.758 0.884 1.147 -0.884 -0.772 0.898 1.133 -0.870 -0.772 0.898 1.133 -0.870 -0.781 0.907 1.124 -0.861 -0.806 0.948 1.162 -0.882 -0.806 0.948 1.162 -0.882 -0.818 0.960 1.150 -0.870 -0.818 0.960 1.150 -0.870 -0.806 0.948 1.162 -0.882 -0.806 0.948 1.162 -0.882 -0.818 0.960 1.150 -0.870 -0.818 0.960 1.150 -0.870 -0.827 0.969 1.141 -0.861 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V HSTL CLASS II -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V HSTL CLASS I -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V HSTL CLASS II GCLK PLL tsu th -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 1.354 1.855 1.478 2.094 1.603 2.328 1.540 2.208 1.883 2.147 1.488 2.111 1.613 2.346 1.551 2.224 1.928 2.194 DIFFERENTIAL 1.5-V SSTL CLASS II -1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V SSTL CLASS I -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 1.364 1.842 1.488 2.084 1.621 2.310 1.558 2.190 1.901 2.129 1.499 2.100 1.630 2.329 1.568 2.207 1.945 2.177 DIFFERENTIAL 1.8-V SSTL CLASS II -1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 -1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 1.379 1.827 1.502 2.068 1.631 2.299 1.568 2.178 1.912 2.118 1.509 2.089 1.636 2.323 1.573 2.199 1.952 2.170 DIFFERENTIAL 2.5-V SSTL CLASS I -1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-275 Table 1-126. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS II GCLK GCLK PLL tsu th tsu th -0.781 0.907 1.124 -0.861 -0.827 0.969 1.141 -0.861 -1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 1.379 1.827 1.502 2.068 1.631 2.299 1.568 2.178 1.912 2.118 1.509 2.089 1.636 2.323 1.573 2.199 1.952 2.170 ns ns ns ns -1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 Table 1-127 lists the EP3SE110 column pins output timing parameters for differential I/O standards. Table 1-127. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1V C3 VCCL= 1.1V C4 VCCL= 1.1V VCCL= 1.1V C4L VCCL= 0.9V I3 VCCL= 1.1V I4 VCCL= 1.1V VCCL= 1.1V I4L VCCL= 0.9V Units Clock GCLK LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco 3.152 1.328 3.148 1.324 3.152 1.328 3.148 1.324 3.152 1.328 3.148 1.324 3.387 1.502 3.390 1.505 3.387 1.502 3.390 1.505 3.387 1.502 3.390 1.505 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899 1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965 1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns ns ns ns ns ns ns ns ns ns ns ns MINILVDS_E_1R MINILVDS_E_3R (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-276 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-127. EP3SE110 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1V C3 VCCL= 1.1V C4 VCCL= 1.1V VCCL= 1.1V C4L VCCL= 0.9V I3 VCCL= 1.1V I4 VCCL= 1.1V VCCL= 1.1V I4L VCCL= 0.9V Units Clock GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.2-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.5-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.179 1.355 3.169 1.345 3.169 1.345 3.162 1.338 3.161 1.337 3.183 1.359 3.173 1.349 3.168 1.344 3.166 1.342 3.158 1.334 3.159 1.335 3.158 1.334 3.420 1.535 3.410 1.525 3.410 1.525 3.404 1.519 3.402 1.517 3.424 1.539 3.413 1.528 3.409 1.524 3.407 1.522 3.398 1.513 3.400 1.515 3.397 1.512 4.828 5.233 5.750 5.610 5.910 5.358 5.875 5.736 5.985 1.984 2.084 2.298 2.309 2.335 2.190 2.407 2.417 2.323 4.818 5.222 5.740 5.600 5.900 5.347 5.865 5.726 5.975 1.974 2.073 2.288 2.299 2.325 2.179 2.397 2.407 2.313 4.821 5.226 5.744 5.604 5.904 5.352 5.870 5.731 5.980 1.977 2.077 2.292 2.303 2.329 2.184 2.402 2.412 2.318 4.814 5.220 5.738 5.598 5.898 5.345 5.864 5.725 5.974 1.970 2.071 2.286 2.297 2.323 2.177 2.396 2.406 2.312 4.811 5.217 5.735 5.595 5.895 5.342 5.860 5.721 5.970 1.967 2.068 2.283 2.294 2.320 2.174 2.392 2.402 2.308 4.832 5.237 5.754 5.614 5.914 5.362 5.880 5.741 5.990 1.988 2.088 2.302 2.313 2.339 2.194 2.412 2.422 2.328 4.811 5.214 5.729 5.589 5.889 5.338 5.853 5.714 5.963 1.967 2.065 2.277 2.288 2.314 2.170 2.385 2.395 2.301 4.811 5.214 5.730 5.590 5.890 5.339 5.855 5.716 5.965 1.967 2.065 2.278 2.289 2.315 2.171 2.387 2.397 2.303 4.810 5.213 5.728 5.588 5.888 5.338 5.854 5.715 5.964 1.966 2.064 2.276 2.287 2.313 2.170 2.386 2.396 2.302 4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954 1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292 4.806 5.210 5.727 5.587 5.887 5.336 5.853 5.714 5.963 1.962 2.061 2.275 2.286 2.312 2.168 2.385 2.395 2.301 4.789 5.191 5.705 5.565 5.865 5.315 5.829 5.690 5.939 1.945 2.042 2.253 2.264 2.290 2.147 2.361 2.371 2.277 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V HSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-277 Table 1-127. EP3SE110 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1V C3 VCCL= 1.1V C4 VCCL= 1.1V VCCL= 1.1V C4L VCCL= 0.9V I3 VCCL= 1.1V I4 VCCL= 1.1V VCCL= 1.1V I4L VCCL= 0.9V Units Clock GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.5-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.170 1.346 3.166 1.342 3.156 1.332 3.154 1.330 3.154 1.330 3.158 1.334 3.184 1.360 3.170 1.346 3.158 1.334 3.158 1.334 3.154 1.330 3.158 1.334 3.159 1.335 3.410 1.525 3.407 1.522 3.396 1.511 3.394 1.509 3.395 1.510 3.398 1.513 3.427 1.542 3.413 1.528 3.400 1.515 3.400 1.515 3.396 1.511 3.398 1.513 3.400 1.515 4.807 5.209 5.723 5.583 5.883 5.334 5.848 5.709 5.958 1.963 2.060 2.271 2.282 2.308 2.166 2.380 2.390 2.296 4.808 5.211 5.727 5.587 5.887 5.336 5.852 5.713 5.962 1.964 2.062 2.275 2.286 2.312 2.168 2.384 2.394 2.300 4.797 5.200 5.715 5.575 5.875 5.325 5.840 5.701 5.950 1.953 2.051 2.263 2.274 2.300 2.157 2.372 2.382 2.288 4.795 5.197 5.713 5.573 5.873 5.323 5.838 5.699 5.948 1.951 2.048 2.261 2.272 2.298 2.155 2.370 2.380 2.286 4.798 5.202 5.718 5.578 5.878 5.327 5.844 5.705 5.954 1.954 2.053 2.266 2.277 2.303 2.159 2.376 2.386 2.292 4.795 5.197 5.712 5.572 5.872 5.322 5.837 5.698 5.947 1.951 2.048 2.260 2.271 2.297 2.154 2.369 2.379 2.285 4.840 5.245 5.762 5.622 5.922 5.370 5.887 5.748 5.997 1.996 2.096 2.310 2.321 2.347 2.202 2.419 2.429 2.335 4.828 5.234 5.752 5.612 5.912 5.360 5.878 5.739 5.988 1.984 2.085 2.300 2.311 2.337 2.192 2.410 2.420 2.326 4.811 5.216 5.734 5.594 5.894 5.342 5.860 5.721 5.970 1.967 2.067 2.282 2.293 2.319 2.174 2.392 2.402 2.308 4.814 5.220 5.738 5.598 5.898 5.346 5.865 5.726 5.975 1.970 2.071 2.286 2.297 2.323 2.178 2.397 2.407 2.313 4.807 5.212 5.731 5.591 5.891 5.339 5.857 5.718 5.967 1.963 2.063 2.279 2.290 2.316 2.171 2.389 2.399 2.305 4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954 1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292 4.808 5.213 5.730 5.590 5.890 5.338 5.856 5.717 5.966 1.964 2.064 2.278 2.289 2.315 2.170 2.388 2.398 2.304 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-278 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-127. EP3SE110 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1V C3 VCCL= 1.1V C4 VCCL= 1.1V VCCL= 1.1V C4L VCCL= 0.9V I3 VCCL= 1.1V I4 VCCL= 1.1V VCCL= 1.1V I4L VCCL= 0.9V Units Clock GCLK 4mA GCLK PLL GCLK 6mA DIFFERENTIAL 1.8-V SSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 8mA DIFFERENTIAL 2.5-V SSTL CLASS I GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 16mA GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.187 1.363 3.176 1.352 3.171 1.347 3.157 1.333 3.155 1.331 3.159 1.335 3.159 1.335 3.175 1.351 3.175 1.351 3.165 1.341 3.158 1.334 3.430 1.545 3.418 1.533 3.414 1.529 3.399 1.514 3.397 1.512 3.399 1.514 3.400 1.515 3.417 1.532 3.417 1.532 3.407 1.522 3.399 1.514 4.839 5.243 5.760 5.620 5.920 5.369 5.885 5.746 5.995 1.995 2.094 2.308 2.319 2.345 2.201 2.417 2.427 2.333 4.827 5.231 5.748 5.608 5.908 5.357 5.873 5.734 5.983 1.983 2.082 2.296 2.307 2.333 2.189 2.405 2.415 2.321 4.827 5.232 5.749 5.609 5.909 5.358 5.875 5.736 5.985 1.983 2.083 2.297 2.308 2.334 2.190 2.407 2.417 2.323 4.809 5.213 5.730 5.590 5.890 5.339 5.857 5.718 5.967 1.965 2.064 2.278 2.289 2.315 2.171 2.389 2.399 2.305 4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302 4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289 4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302 4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977 1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315 4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977 1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315 4.813 5.216 5.732 5.592 5.892 5.342 5.858 5.719 5.968 1.969 2.067 2.280 2.291 2.317 2.174 2.390 2.400 2.306 4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 2.5-V SSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-279 Table 1-128 lists the EP3SE110 row pins output timing parameters for differential I/O standards. Table 1-128. EP3SE110 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 2.744 0.931 3.136 1.333 3.118 1.315 2.744 0.931 3.136 1.333 3.118 1.315 2.744 0.931 3.136 1.333 3.118 1.315 3.162 1.359 3.148 1.345 3.144 1.341 2.932 1.057 3.376 1.511 3.366 1.501 2.932 1.057 3.376 1.511 3.366 1.501 2.932 1.057 3.376 1.511 3.366 1.501 3.409 1.544 3.395 1.530 3.391 1.526 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107 1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456 4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871 1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229 4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932 1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290 4.828 5.236 5.751 5.613 5.884 5.365 5.880 5.742 5.961 2.004 2.106 2.318 2.332 2.330 2.217 2.433 2.442 2.319 4.815 5.223 5.738 5.600 5.871 5.351 5.867 5.729 5.948 1.991 2.093 2.305 2.319 2.317 2.203 2.420 2.429 2.306 4.813 5.223 5.739 5.601 5.872 5.351 5.869 5.731 5.950 1.989 2.093 2.306 2.320 2.318 2.203 2.422 2.431 2.308 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-280 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-128. EP3SE110 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.160 1.357 3.149 1.346 3.146 1.343 3.157 1.354 3.147 1.344 3.133 1.330 3.130 1.327 3.127 1.324 3.128 1.325 3.177 1.374 3.153 1.350 3.136 1.333 3.406 1.541 3.396 1.531 3.393 1.528 3.403 1.538 3.394 1.529 3.380 1.515 3.376 1.511 3.374 1.509 3.374 1.509 3.427 1.562 3.403 1.538 3.384 1.519 4.814 5.220 5.733 5.595 5.866 5.348 5.862 5.724 5.943 1.990 2.090 2.300 2.314 2.312 2.200 2.415 2.424 2.301 4.810 5.216 5.730 5.592 5.863 5.345 5.859 5.721 5.940 1.986 2.086 2.297 2.311 2.309 2.197 2.412 2.421 2.298 4.808 5.214 5.728 5.590 5.861 5.343 5.858 5.720 5.939 1.984 2.084 2.295 2.309 2.307 2.195 2.411 2.420 2.297 4.809 5.215 5.727 5.589 5.860 5.343 5.856 5.718 5.937 1.985 2.085 2.294 2.308 2.306 2.195 2.409 2.418 2.295 4.807 5.213 5.726 5.588 5.859 5.342 5.856 5.718 5.937 1.983 2.083 2.293 2.307 2.305 2.194 2.409 2.418 2.295 4.792 5.198 5.712 5.574 5.845 5.327 5.841 5.703 5.922 1.968 2.068 2.279 2.293 2.291 2.179 2.394 2.403 2.280 4.788 5.194 5.708 5.570 5.841 5.323 5.837 5.699 5.918 1.964 2.064 2.275 2.289 2.287 2.175 2.390 2.399 2.276 4.789 5.197 5.711 5.573 5.844 5.326 5.841 5.703 5.922 1.965 2.067 2.278 2.292 2.290 2.178 2.394 2.403 2.280 4.779 5.185 5.698 5.560 5.831 5.313 5.827 5.689 5.908 1.955 2.055 2.265 2.279 2.277 2.165 2.380 2.389 2.266 4.850 5.258 5.774 5.636 5.907 5.387 5.903 5.765 5.984 2.026 2.128 2.341 2.355 2.353 2.239 2.456 2.465 2.342 4.832 5.241 5.757 5.619 5.890 5.370 5.888 5.750 5.969 2.008 2.111 2.324 2.338 2.336 2.222 2.441 2.450 2.327 4.810 5.219 5.735 5.597 5.868 5.348 5.866 5.728 5.947 1.986 2.089 2.302 2.316 2.314 2.200 2.419 2.428 2.305 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA DIFFERENTIAL 1.8-V HSTL CLASS I 8mA 10mA 12mA DIFFERENTIAL 1.8-V 16mA HSTL CLASS II 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-281 Table 1-128. EP3SE110 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V C4L VCCL = 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.181 1.378 3.166 1.363 3.155 1.352 3.135 1.332 3.132 1.329 3.137 1.334 3.130 1.327 3.168 1.365 3.150 1.347 3.136 1.333 3.430 1.565 3.415 1.550 3.404 1.539 3.384 1.519 3.380 1.515 3.384 1.519 3.377 1.512 3.416 1.551 3.399 1.534 3.383 1.518 4.850 5.258 5.773 5.635 5.906 5.387 5.903 5.765 5.984 2.026 2.128 2.340 2.354 2.352 2.239 2.456 2.465 2.342 4.836 5.243 5.758 5.620 5.891 5.372 5.888 5.750 5.969 2.012 2.113 2.325 2.339 2.337 2.224 2.441 2.450 2.327 4.831 5.240 5.755 5.617 5.888 5.369 5.886 5.748 5.967 2.007 2.110 2.322 2.336 2.334 2.221 2.439 2.448 2.325 4.808 5.216 5.732 5.594 5.865 5.346 5.862 5.724 5.943 1.984 2.086 2.299 2.313 2.311 2.198 2.415 2.424 2.301 4.804 5.213 5.728 5.590 5.861 5.342 5.859 5.721 5.940 1.980 2.083 2.295 2.309 2.307 2.194 2.412 2.421 2.298 4.795 5.201 5.714 5.576 5.847 5.329 5.843 5.705 5.924 1.971 2.071 2.281 2.295 2.293 2.181 2.396 2.405 2.282 4.794 5.202 5.717 5.579 5.850 5.332 5.848 5.710 5.929 1.970 2.072 2.284 2.298 2.296 2.184 2.401 2.410 2.287 4.832 5.239 5.753 5.615 5.886 5.368 5.883 5.745 5.964 2.008 2.109 2.320 2.334 2.332 2.220 2.436 2.445 2.322 4.817 5.224 5.738 5.600 5.871 5.353 5.868 5.730 5.949 1.993 2.094 2.305 2.319 2.317 2.205 2.421 2.430 2.307 4.794 5.200 5.713 5.575 5.846 5.329 5.843 5.705 5.924 1.970 2.070 2.280 2.294 2.292 2.181 2.396 2.405 2.282 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA DIFFERENTIAL 1.8-V SSTL CLASS I 8mA 10mA 12mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS II 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V SSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-282 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-129 and Table 1-130 list the EP3SE110 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-129 lists the EP3SE110 column pin delay adders when using the regional clock. Table 1-129. EP3SE110 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL = 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.111 2.506 -0.281 -2.121 0.14 2.513 -0.062 -1.833 0.19 3.782 -2.75 0.103 4.081 0.105 4.579 0.103 4.381 0.177 4.923 0.085 4.222 0.056 0.101 4.603 0.051 0.098 4.401 0.054 0.146 4.984 -0.055 ns ns ns ns -0.079 -0.074 -0.074 -0.072 -0.128 -2.908 -3.127 -3.057 -3.165 -2.959 -3.157 -2.903 -3.172 Table 1-130 lists the EP3SE110 row pin delay adders when using the regional clock. Table 1-130. EP3SE110 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder -0.003 0.116 0.02 -0.103 -0.002 0.122 0.019 -0.105 0.001 0.192 0.027 -0.012 0.212 0.041 -0.01 0.227 0.044 -0.017 0.217 0.048 0.078 0.375 -0.038 -0.02 0.198 0.051 -0.02 0.219 0.057 -0.016 0.209 0.051 0.08 0.379 -0.04 ns ns ns ns -0.162 -0.179 -0.194 -0.185 -0.322 -0.167 -0.183 -0.175 -0.324 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-283 EP3SE260 I/O Timing Parameters Table 1-131 through Table 1-135 list the maximum I/O timing parameters for EP3SE260 devices for single-ended I/O standards. Table 1-131 lists the EP3SE260 column pins input timing parameters for single-ended I/O standards. Table 1-131. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.242 1.388 -1.417 1.732 -1.242 1.388 -1.417 1.732 -1.253 1.399 -1.428 1.743 -1.253 1.399 -1.428 1.743 -1.248 1.394 -1.423 1.738 -1.270 1.418 -1.443 1.760 -1.260 1.408 -1.433 1.750 -1.208 1.356 -1.381 1.698 -1.186 1.332 -1.465 1.778 -1.186 1.332 -1.465 1.778 -1.197 1.343 -1.476 1.789 -1.197 1.343 -1.476 1.789 -1.192 1.338 -1.471 1.784 -1.214 1.362 -1.493 1.808 -1.204 1.352 -1.483 1.798 -1.152 1.300 -1.431 1.746 -1.822 -1.915 -2.184 -2.050 -2.482 -1.915 -2.184 -2.050 -2.482 2.045 2.727 2.045 2.727 2.044 2.726 2.044 2.726 2.053 2.735 2.093 2.775 2.070 2.752 1.993 2.675 2.146 2.697 2.146 2.697 2.148 2.699 2.148 2.699 2.160 2.711 2.196 2.747 2.164 2.715 2.065 2.616 2.437 3.113 2.437 3.113 2.436 3.112 2.436 3.112 2.455 3.131 2.453 3.129 2.383 3.059 2.227 2.903 2.285 3.000 2.285 3.000 2.284 2.999 2.284 2.999 2.303 3.018 2.301 3.016 2.231 2.946 2.075 2.790 2.724 3.584 2.724 3.584 2.723 3.583 2.723 3.583 2.742 3.602 2.740 3.600 2.670 3.530 2.514 3.374 2.146 2.697 2.146 2.697 2.148 2.699 2.148 2.699 2.160 2.711 2.196 2.747 2.164 2.715 2.065 2.616 2.437 3.113 2.437 3.113 2.436 3.112 2.436 3.112 2.455 3.131 2.453 3.129 2.383 3.059 2.227 2.903 2.285 3.000 2.285 3.000 2.284 2.999 2.284 2.999 2.303 3.018 2.301 3.016 2.231 2.946 2.075 2.790 2.724 3.584 2.724 3.584 2.723 3.583 2.723 3.583 2.742 3.602 2.740 3.600 2.670 3.530 2.514 3.374 -2.238 -2.189 -2.558 -2.477 -3.038 -2.189 -2.558 -2.477 -3.038 -1.822 -1.915 -2.184 -2.050 -2.482 -1.915 -2.184 -2.050 -2.482 -2.238 -2.189 -2.558 -2.477 -3.038 -2.189 -2.558 -2.477 -3.038 -1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481 -2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037 -1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481 -2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037 -1.830 -1.929 -2.202 -2.068 -2.500 -1.929 -2.202 -2.068 -2.500 -2.246 -2.203 -2.576 -2.495 -3.056 -2.203 -2.576 -2.495 -3.056 -1.870 -1.965 -2.200 -2.066 -2.498 -1.965 -2.200 -2.066 -2.498 -2.286 -2.239 -2.574 -2.493 -3.054 -2.239 -2.574 -2.493 -3.054 -1.847 -1.933 -2.130 -1.996 -2.428 -1.933 -2.130 -1.996 -2.428 -2.263 -2.207 -2.504 -2.423 -2.984 -2.207 -2.504 -2.423 -2.984 -1.770 -1.834 -1.974 -1.840 -2.272 -1.834 -1.974 -1.840 -2.272 -2.186 -2.108 -2.348 -2.267 -2.828 -2.108 -2.348 -2.267 -2.828 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 3.3-V LVCMOS GCLK PLL GCLK 3.0-V LVTTL GCLK PLL GCLK 3.0-V LVCMOS GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V GCLK PLL GCLK 1.5 V GCLK PLL GCLK 1.2 V GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-284 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-131. EP3SE260 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-2 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.179 1.327 -1.352 1.669 -1.179 1.327 -1.352 1.669 -1.173 1.321 -1.346 1.663 -1.173 1.321 -1.346 1.663 -1.162 1.310 -1.335 1.652 -1.162 1.310 -1.335 1.652 -1.173 1.321 -1.346 1.663 -1.173 1.321 -1.346 1.663 -1.162 1.310 -1.335 1.652 -1.123 1.271 -1.402 1.717 -1.123 1.271 -1.402 1.717 -1.117 1.265 -1.396 1.711 -1.117 1.265 -1.396 1.711 -1.106 1.254 -1.385 1.700 -1.106 1.254 -1.385 1.700 -1.117 1.265 -1.396 1.711 -1.117 1.265 -1.396 1.711 -1.106 1.254 -1.385 1.700 -1.742 -1.818 -1.976 -1.842 -2.274 -1.818 -1.976 -1.842 -2.274 1.965 2.647 1.965 2.647 1.952 2.634 1.952 2.634 1.940 2.622 1.940 2.622 1.952 2.634 1.952 2.634 1.940 2.622 2.049 2.600 2.049 2.600 2.038 2.592 2.038 2.592 2.027 2.581 2.027 2.581 2.038 2.592 2.038 2.592 2.027 2.581 2.229 2.905 2.229 2.905 2.223 2.899 2.223 2.899 2.204 2.880 2.204 2.880 2.223 2.899 2.223 2.899 2.204 2.880 2.077 2.792 2.077 2.792 2.071 2.786 2.071 2.786 2.052 2.767 2.052 2.767 2.071 2.786 2.071 2.786 2.052 2.767 2.516 3.376 2.516 3.376 2.509 3.369 2.509 3.369 2.490 3.350 2.490 3.350 2.509 3.369 2.509 3.369 2.490 3.350 2.049 2.600 2.049 2.600 2.038 2.592 2.038 2.592 2.027 2.581 2.027 2.581 2.038 2.592 2.038 2.592 2.027 2.581 2.229 2.905 2.229 2.905 2.223 2.899 2.223 2.899 2.204 2.880 2.204 2.880 2.223 2.899 2.223 2.899 2.204 2.880 2.077 2.792 2.077 2.792 2.071 2.786 2.071 2.786 2.052 2.767 2.052 2.767 2.071 2.786 2.071 2.786 2.052 2.767 2.516 3.376 2.516 3.376 2.509 3.369 2.509 3.369 2.490 3.350 2.490 3.350 2.509 3.369 2.509 3.369 2.490 3.350 -2.158 -2.092 -2.350 -2.269 -2.830 -2.092 -2.350 -2.269 -2.830 -1.742 -1.818 -1.976 -1.842 -2.274 -1.818 -1.976 -1.842 -2.274 -2.158 -2.092 -2.350 -2.269 -2.830 -2.092 -2.350 -2.269 -2.830 -1.729 -1.810 -1.973 -1.837 -2.272 -1.810 -1.973 -1.837 -2.272 -2.145 -2.087 -2.347 -2.264 -2.828 -2.087 -2.347 -2.264 -2.828 -1.729 -1.810 -1.973 -1.837 -2.272 -1.810 -1.973 -1.837 -2.272 -2.145 -2.087 -2.347 -2.264 -2.828 -2.087 -2.347 -2.264 -2.828 -1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253 -2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809 -1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253 -2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809 -1.729 -1.810 -1.973 -1.837 -2.272 -1.810 -1.973 -1.837 -2.272 -2.145 -2.087 -2.347 -2.264 -2.828 -2.087 -2.347 -2.264 -2.828 -1.729 -1.810 -1.973 -1.837 -2.272 -1.810 -1.973 -1.837 -2.272 -2.145 -2.087 -2.347 -2.264 -2.828 -2.087 -2.347 -2.264 -2.828 -1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253 -2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK SSTL-2 CLASS II GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK SSTL-18 CLASS II GCLK PLL GCLK SSTL-15 CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK 1.5-V HSTL CLASS I GCLK PLL GCLK 1.5-V HSTL CLASS II GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-285 Table 1-131. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 1.2-V HSTL CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.162 1.310 -1.335 1.652 -1.150 1.298 -1.323 1.640 -1.150 1.298 -1.323 1.640 -1.253 1.399 -1.428 1.743 -1.106 1.254 -1.385 1.700 -1.094 1.242 -1.373 1.688 -1.094 1.242 -1.373 1.688 -1.197 1.343 -1.476 1.789 -1.718 -1.799 -1.954 -1.818 -2.253 -1.799 -1.954 -1.818 -2.253 1.940 2.622 1.930 2.612 1.930 2.612 2.044 2.726 2.027 2.581 2.016 2.570 2.016 2.570 2.148 2.699 2.204 2.880 2.188 2.864 2.188 2.864 2.436 3.112 2.052 2.767 2.036 2.751 2.036 2.751 2.284 2.999 2.490 3.350 2.474 3.334 2.474 3.334 2.723 3.583 2.027 2.581 2.016 2.570 2.016 2.570 2.148 2.699 2.204 2.880 2.188 2.864 2.188 2.864 2.436 3.112 2.052 2.767 2.036 2.751 2.036 2.751 2.284 2.999 2.490 3.350 2.474 3.334 2.474 3.334 2.723 3.583 -2.134 -2.076 -2.328 -2.245 -2.809 -2.076 -2.328 -2.245 -2.809 -1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237 -2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793 -1.708 -1.788 -1.938 -1.802 -2.237 -1.788 -1.938 -1.802 -2.237 -2.124 -2.065 -2.312 -2.229 -2.793 -2.065 -2.312 -2.229 -2.793 -1.821 -1.917 -2.183 -2.049 -2.481 -1.917 -2.183 -2.049 -2.481 -2.237 -2.191 -2.557 -2.476 -3.037 -2.191 -2.557 -2.476 -3.037 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK 1.2-V HSTL CLASS II GCLK PLL GCLK 3.0-V PCI GCLK PLL GCLK 3.0-V PCI-X GCLK PLL Table 1-132 lists the EP3SE260 row pins input timing parameters for single-ended I/O standards. Table 1-132. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.3-V LVTTL tsu th tsu th tsu th tsu th tsu th tsu th -1.219 1.355 0.983 -0.704 -1.219 1.355 0.983 -0.704 -1.225 1.361 0.977 -0.698 -1.374 1.524 0.983 -0.685 -1.374 1.524 0.983 -0.685 -1.385 1.535 0.972 -0.674 -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 1.749 2.293 1.864 2.233 1.862 2.553 1.767 2.431 1.884 2.902 1.864 2.260 1.883 2.659 1.767 2.431 1.884 2.902 ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 1.749 2.293 2.290 1.752 2.290 1.864 2.233 2.234 1.863 2.234 1.862 2.553 2.556 1.859 2.556 1.767 2.431 2.434 1.764 2.434 1.884 2.902 2.905 1.881 2.905 1.864 2.260 2.259 1.865 2.259 1.883 2.659 2.664 1.878 2.664 1.767 2.431 2.434 1.764 2.434 1.884 2.902 2.905 1.881 2.905 3.3-V LVCMOS GCLK PLL GCLK -2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 -2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 3.0-V LVTTL GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-286 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-132. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK 3.0-V LVCMOS tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.225 1.361 0.977 -0.698 -1.213 1.349 0.989 -0.710 -1.283 0.968 1.421 -1.273 0.978 1.411 -1.213 1.038 1.351 -1.155 1.047 1.292 -1.155 1.047 1.292 -1.187 1.064 1.325 -1.187 1.064 1.325 -1.173 1.078 1.311 -1.187 1.064 1.325 -1.187 -1.385 1.535 0.972 -0.674 -1.378 1.528 0.979 -0.681 -1.435 0.896 1.586 -1.424 0.907 1.575 -1.371 0.960 1.522 -1.320 1.038 1.471 -1.320 1.038 1.471 -1.336 0.995 1.487 -1.336 0.995 1.487 -1.324 1.007 1.475 -1.336 0.995 1.487 -1.336 2.299 1.743 2.299 1.617 2.364 1.617 1.641 2.340 1.720 2.261 1.829 2.213 1.758 2.223 -1.989 1.758 2.223 1.758 2.223 2.247 1.850 2.247 1.714 2.410 1.714 1.746 2.378 1.847 2.277 1.959 2.138 2.571 1.844 2.571 1.860 2.627 1.860 1.928 2.559 2.087 2.400 2.064 2.351 2.449 1.749 2.449 1.741 2.565 1.741 1.809 2.497 1.968 2.338 1.969 2.229 2.920 1.866 2.920 1.759 3.018 1.759 1.827 2.950 1.986 2.791 2.086 2.700 2.268 1.856 2.268 1.830 2.344 1.830 1.861 2.313 1.957 2.217 1.968 2.156 2.674 1.868 2.674 1.861 2.687 1.861 1.926 2.622 2.081 2.467 2.085 2.457 2.449 1.749 2.449 1.741 2.565 1.741 1.809 2.497 1.968 2.338 1.969 2.229 2.920 1.866 2.920 1.759 3.018 1.759 1.827 2.950 1.986 2.791 2.086 2.700 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -2.065 -2.002 -2.301 -2.195 -2.661 -2.011 -2.397 -2.195 -2.661 GCLK PLL GCLK 2.5 V GCLK PLL GCLK 1.8 V -2.130 -2.167 -2.360 -2.314 -2.765 -2.088 -2.409 -2.314 -2.765 GCLK PLL GCLK 1.5 V -2.106 -2.135 -2.292 -2.246 -2.697 -2.057 -2.344 -2.246 -2.697 -2.027 -2.034 -2.133 -2.087 -2.538 -1.961 -2.189 -2.087 -2.538 GCLK PLL GCLK 1.2 V -1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 2.248 1.874 1.874 2.393 2.092 2.092 2.331 1.974 1.974 2.783 1.990 1.990 2.185 1.986 1.986 2.457 2.088 2.088 2.331 1.974 1.974 2.783 1.990 1.990 GCLK PLL GCLK SSTL-2 CLASS I -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 2.248 1.874 2.393 2.092 2.331 1.974 2.783 1.990 2.185 1.986 2.457 2.088 2.331 1.974 2.783 1.990 GCLK PLL GCLK -1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 SSTL-2 CLASS II -1.989 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 -1.294 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 -1.974 2.209 1.758 2.223 1.758 2.223 -1.989 -1.294 2.238 1.884 1.884 2.375 2.110 2.110 2.313 1.992 1.992 2.765 2.008 2.008 2.174 1.997 1.997 2.440 2.105 2.105 2.313 1.992 1.992 2.765 2.008 2.008 GCLK PLL GCLK SSTL-18 CLASS I GCLK PLL GCLK -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 2.248 1.874 2.393 2.092 2.331 1.974 2.783 1.990 2.185 1.986 2.457 2.088 2.331 1.974 2.783 1.990 -1.989 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 SSTL-18 CLASS II GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-287 Table 1-132. EP3SE260 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK SSTL-15 CLASS I tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th 1.064 1.325 -1.173 1.078 1.311 -1.173 1.078 1.311 -1.164 1.087 1.302 -1.164 1.087 1.302 -1.225 1.361 0.977 -0.698 -1.225 1.361 0.977 -0.698 -1.219 1.355 0.983 -0.704 -1.219 1.355 0.983 -0.704 -1.225 1.361 0.977 -0.698 -1.225 1.361 0.995 1.487 -1.324 1.007 1.475 -1.324 1.007 1.475 -1.312 1.019 1.463 -1.312 1.019 1.463 -1.385 1.535 0.972 -0.674 -1.385 1.535 0.972 -0.674 -1.374 1.524 0.983 -0.685 -1.374 1.524 0.983 -0.685 -1.385 1.535 0.972 -0.674 -1.385 1.535 -1.974 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 2.209 1.773 -1.294 -1.303 2.200 1.782 -1.303 -1.303 1.752 2.290 -2.056 1.752 2.290 2.290 2.290 2.290 2.290 1.749 2.293 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 2.248 1.874 1.884 2.393 2.092 2.110 2.331 1.974 1.992 2.783 1.990 2.008 2.185 1.986 1.997 2.457 2.088 2.105 2.331 1.974 1.992 2.783 1.990 2.008 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK -1.974 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 -1.965 -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 2.238 1.884 1.894 2.375 2.110 2.126 2.313 1.992 2.008 2.765 2.008 2.024 2.174 1.997 2.006 2.440 2.105 2.121 2.313 1.992 2.008 2.765 2.008 2.024 1.8-V HSTL CLASS I GCLK PLL GCLK 1.8-V HSTL CLASS II GCLK PLL GCLK -1.965 -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 -2.056 -1.398 -1.575 -1.489 -1.492 -1.497 -1.559 -1.489 -1.492 -1.987 -2.094 -2.047 -2.500 -1.912 -2.149 -2.047 -2.500 2.228 1.894 2.359 2.126 2.297 2.008 2.749 2.024 2.165 2.006 2.424 2.121 2.297 2.008 2.749 2.024 1.5-V HSTL CLASS I GCLK PLL GCLK -1.398 -1.575 -1.489 -1.492 -1.497 -1.559 -1.489 -1.492 -1.987 -2.094 -2.047 -2.500 -1.912 -2.149 -2.047 -2.500 2.228 1.894 2.359 2.126 2.297 2.008 2.749 2.024 2.165 2.006 2.424 2.121 2.297 2.008 2.749 2.024 1.5-V HSTL CLASS II GCLK PLL GCLK -1.398 -1.575 -1.489 -1.492 -1.497 -1.559 -1.489 -1.492 -1.987 -2.094 -2.047 -2.500 -1.912 -2.149 -2.047 -2.500 1.864 2.233 1.862 2.553 1.767 2.431 1.884 2.902 1.864 2.260 1.883 2.659 1.767 2.431 1.884 2.902 1.2-V HSTL CLASS I GCLK PLL GCLK -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 1.2-V HSTL CLASS II -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 -2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 1.749 2.293 2.290 1.752 2.290 2.299 1.864 2.233 2.234 1.863 2.234 2.247 1.862 2.553 2.556 1.859 2.556 2.571 1.767 2.431 2.434 1.764 2.434 2.449 1.884 2.902 2.905 1.881 2.905 2.920 1.864 2.260 2.259 1.865 2.259 2.268 1.883 2.659 2.664 1.878 2.664 2.674 1.767 2.431 2.434 1.764 2.434 2.449 1.884 2.902 2.905 1.881 2.905 2.920 GCLK PLL GCLK 3.0-V PCI -2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 -2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 GCLK PLL GCLK 3.0-V PCI-X GCLK PLL -2.065 -2.002 -2.301 -2.195 -2.661 -2.011 -2.397 -2.195 -2.661 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-288 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-133 lists the EP3SE260 column pins output timing parameters for single-ended I/O standards. Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 1 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.644 4.087 3.577 4.020 3.491 3.934 3.484 3.927 3.650 4.093 3.495 3.938 3.502 3.945 3.486 3.929 3.608 4.051 3.497 3.940 3.461 3.904 3.443 3.886 3.677 4.076 3.610 4.009 3.524 3.923 3.517 3.916 3.683 4.082 3.528 3.927 3.535 3.934 3.519 3.918 3.641 4.040 3.530 3.929 3.494 3.893 3.476 3.875 5.302 5.937 5.193 5.828 5.089 5.724 5.072 5.707 5.306 5.941 5.099 5.734 5.093 5.728 5.071 5.706 5.269 5.904 5.139 5.774 5.076 5.711 5.047 5.682 5.460 6.144 5.349 6.033 5.250 5.934 5.222 5.906 5.465 6.149 5.267 5.951 5.246 5.930 5.221 5.905 5.428 6.112 5.294 5.978 5.225 5.909 5.197 5.881 6.139 6.701 5.969 6.588 5.817 6.496 5.792 6.455 6.153 6.708 5.823 6.507 5.792 6.481 5.735 6.452 6.104 6.668 5.942 6.531 5.840 6.457 5.790 6.428 5.837 6.529 5.724 6.416 5.632 6.324 5.591 6.283 5.844 6.536 5.643 6.335 5.617 6.309 5.588 6.280 5.804 6.496 5.668 6.360 5.594 6.286 5.564 6.256 6.259 7.188 6.146 7.018 6.054 6.866 6.013 6.841 6.266 7.202 6.065 6.872 6.039 6.841 6.010 6.784 6.226 7.153 6.088 6.990 6.014 6.888 5.986 6.838 5.460 6.144 5.349 6.033 5.250 5.934 5.222 5.906 5.465 6.149 5.267 5.951 5.246 5.930 5.221 5.905 5.428 6.112 5.294 5.978 5.225 5.909 5.197 5.881 6.139 6.701 5.969 6.588 5.817 6.496 5.792 6.455 6.153 6.708 5.823 6.507 5.792 6.481 5.735 6.452 6.104 6.668 5.942 6.531 5.840 6.457 5.790 6.428 5.837 6.529 5.724 6.416 5.632 6.324 5.591 6.283 5.844 6.536 5.643 6.335 5.617 6.309 5.588 6.280 5.804 6.496 5.668 6.360 5.594 6.286 5.564 6.256 6.259 7.188 6.146 7.018 6.054 6.866 6.013 6.841 6.266 7.202 6.065 6.872 6.039 6.841 6.010 6.784 6.226 7.153 6.088 6.990 6.014 6.888 5.986 6.838 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.3-V LVTTL 12mA 16mA 4mA 8mA 3.3-V LVCMOS 12mA 16mA 4mA 8mA 3.0-V LVTTL 12mA 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-289 Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 2 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.522 3.965 3.443 3.886 3.438 3.881 3.429 3.872 3.644 4.087 3.544 3.987 3.500 3.943 3.462 3.905 3.555 3.954 3.476 3.875 3.471 3.870 3.462 3.861 3.677 4.076 3.577 3.976 3.533 3.932 3.495 3.894 5.173 5.808 5.049 5.684 5.042 5.677 5.028 5.663 5.380 6.015 5.261 5.896 5.174 5.809 5.135 5.770 5.328 6.012 5.199 5.883 5.192 5.876 5.177 5.861 5.555 6.239 5.429 6.113 5.338 6.022 5.296 5.980 5.996 6.566 5.814 6.431 5.746 6.422 5.744 6.407 6.278 6.813 6.081 6.681 5.941 6.585 5.891 6.542 5.703 6.395 5.568 6.260 5.558 6.250 5.543 6.235 5.950 6.642 5.818 6.510 5.721 6.413 5.678 6.370 6.123 7.044 5.988 6.862 5.980 6.795 5.965 6.792 6.370 7.326 6.238 7.129 6.143 6.989 6.100 6.939 5.328 6.012 5.199 5.883 5.192 5.876 5.177 5.861 5.555 6.239 5.429 6.113 5.338 6.022 5.296 5.980 5.996 6.566 5.814 6.431 5.746 6.422 5.744 6.407 6.278 6.813 6.081 6.681 5.941 6.585 5.891 6.542 5.703 6.395 5.568 6.260 5.558 6.250 5.543 6.235 5.950 6.642 5.818 6.510 5.721 6.413 5.678 6.370 6.123 7.044 5.988 6.862 5.980 6.795 5.965 6.792 6.370 7.326 6.238 7.129 6.143 6.989 6.100 6.939 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 8mA 3.0-V LVCMOS 12mA 16mA 4mA 8mA 2.5 V 12mA 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-290 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 3 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.835 4.278 3.654 4.097 3.572 4.015 3.552 3.995 3.489 3.932 3.471 3.914 3.781 4.224 3.569 4.012 3.544 3.987 3.533 3.976 3.478 3.921 3.473 3.916 3.868 4.267 3.687 4.086 3.605 4.004 3.585 3.984 3.522 3.921 3.504 3.903 3.814 4.213 3.602 4.001 3.577 3.976 3.566 3.965 3.511 3.910 3.506 3.905 5.701 6.336 5.422 6.057 5.315 5.950 5.257 5.892 5.196 5.831 5.175 5.810 5.630 6.265 5.311 5.946 5.244 5.879 5.227 5.862 5.189 5.824 5.172 5.807 5.915 6.599 5.606 6.290 5.491 6.175 5.437 6.121 5.362 6.046 5.341 6.025 5.847 6.531 5.491 6.175 5.431 6.115 5.406 6.090 5.355 6.039 5.344 6.028 6.815 7.217 6.354 6.870 6.180 6.759 6.068 6.693 5.954 6.612 5.916 6.589 6.732 7.155 6.176 6.763 6.059 6.696 6.027 6.676 5.945 6.606 5.903 6.595 6.353 7.045 6.007 6.699 5.895 6.587 5.829 6.521 5.748 6.440 5.725 6.417 6.291 6.983 5.899 6.591 5.832 6.524 5.812 6.504 5.742 6.434 5.731 6.423 6.775 7.864 6.427 7.402 6.317 7.229 6.251 7.117 6.170 7.003 6.147 6.965 6.713 7.781 6.321 7.225 6.254 7.108 6.234 7.076 6.164 6.994 6.153 6.952 5.915 6.599 5.606 6.290 5.491 6.175 5.437 6.121 5.362 6.046 5.341 6.025 5.847 6.531 5.491 6.175 5.431 6.115 5.406 6.090 5.355 6.039 5.344 6.028 6.815 7.217 6.354 6.870 6.180 6.759 6.068 6.693 5.954 6.612 5.916 6.589 6.732 7.155 6.176 6.763 6.059 6.696 6.027 6.676 5.945 6.606 5.903 6.595 6.353 7.045 6.007 6.699 5.895 6.587 5.829 6.521 5.748 6.440 5.725 6.417 6.291 6.983 5.899 6.591 5.832 6.524 5.812 6.504 5.742 6.434 5.731 6.423 6.775 7.864 6.427 7.402 6.317 7.229 6.251 7.117 6.170 7.003 6.147 6.965 6.713 7.781 6.321 7.225 6.254 7.108 6.234 7.076 6.164 6.994 6.153 6.952 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA 1.8 V 8mA 10mA 12mA 2mA 4mA 6mA 1.5 V 8mA 10mA 12mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-291 Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 4 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.697 4.140 3.574 4.017 3.536 3.979 3.489 3.932 3.489 3.932 3.486 3.929 3.484 3.927 3.475 3.918 3.496 3.939 3.492 3.935 3.481 3.924 3.470 3.913 3.470 3.913 3.730 4.129 3.607 4.006 3.569 3.968 3.522 3.921 3.522 3.921 3.519 3.918 3.517 3.916 3.508 3.907 3.529 3.928 3.525 3.924 3.514 3.913 3.503 3.902 3.503 3.902 5.556 6.191 5.330 5.965 5.238 5.873 5.210 5.845 5.167 5.802 5.164 5.799 5.164 5.799 5.149 5.784 5.179 5.814 5.177 5.812 5.167 5.802 5.154 5.789 5.154 5.789 5.783 6.467 5.521 6.205 5.432 6.116 5.383 6.067 5.330 6.014 5.327 6.011 5.328 6.012 5.312 5.996 5.344 6.028 5.342 6.026 5.333 6.017 5.320 6.004 5.320 6.004 6.652 7.099 6.223 6.813 6.068 6.700 5.977 6.644 5.925 6.575 5.930 6.571 5.911 6.572 5.877 6.557 5.952 6.591 5.942 6.589 5.934 6.580 5.896 6.567 5.896 6.567 6.235 6.927 5.949 6.641 5.836 6.528 5.780 6.472 5.711 6.403 5.707 6.399 5.708 6.400 5.693 6.385 5.727 6.419 5.725 6.417 5.716 6.408 5.703 6.395 5.703 6.395 6.657 7.701 6.371 7.272 6.258 7.117 6.202 7.026 6.133 6.974 6.129 6.978 6.130 6.960 6.115 6.926 6.149 7.000 6.147 6.991 6.138 6.982 6.125 6.945 6.125 6.945 5.783 6.467 5.521 6.205 5.432 6.116 5.383 6.067 5.330 6.014 5.327 6.011 5.328 6.012 5.312 5.996 5.344 6.028 5.342 6.026 5.333 6.017 5.320 6.004 5.320 6.004 6.652 7.099 6.223 6.813 6.068 6.700 5.977 6.644 5.925 6.575 5.930 6.571 5.911 6.572 5.877 6.557 5.952 6.591 5.942 6.589 5.934 6.580 5.896 6.567 5.896 6.567 6.235 6.927 5.949 6.641 5.836 6.528 5.780 6.472 5.711 6.403 5.707 6.399 5.708 6.400 5.693 6.385 5.727 6.419 5.725 6.417 5.716 6.408 5.703 6.395 5.703 6.395 6.657 7.701 6.371 7.272 6.258 7.117 6.202 7.026 6.133 6.974 6.129 6.978 6.130 6.960 6.115 6.926 6.149 7.000 6.147 6.991 6.138 6.982 6.125 6.945 6.125 6.945 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 1.2 V 6mA 8mA 8mA SSTL-2 CLASS I 10mA 12mA SSTL-2 CLASS II 16mA 4mA 6mA SSTL-18 CLASS I 8mA 10mA 12mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-292 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 5 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 8mA SSTL-18 CLASS II 16mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.476 3.919 3.479 3.922 3.500 3.943 3.486 3.929 3.475 3.918 3.474 3.917 3.471 3.914 3.473 3.916 3.476 3.919 3.509 3.908 3.512 3.911 3.533 3.932 3.519 3.918 3.508 3.907 3.507 3.906 3.504 3.903 3.506 3.905 3.509 3.908 5.153 5.788 5.161 5.796 5.188 5.823 5.178 5.813 5.164 5.799 5.167 5.802 5.162 5.797 5.151 5.786 5.158 5.793 5.317 6.001 5.326 6.010 5.356 6.040 5.346 6.030 5.332 6.016 5.335 6.019 5.330 6.014 5.316 6.000 5.325 6.009 5.896 6.562 5.901 6.574 5.967 6.604 5.941 6.595 5.917 6.581 5.906 6.585 5.896 6.579 5.896 6.562 5.902 6.573 5.698 6.390 5.710 6.402 5.740 6.432 5.731 6.423 5.717 6.409 5.721 6.413 5.715 6.407 5.698 6.390 5.709 6.401 6.120 6.945 6.132 6.950 6.162 7.016 6.153 6.990 6.139 6.966 6.143 6.955 6.137 6.945 6.120 6.945 6.131 6.951 5.317 6.001 5.326 6.010 5.356 6.040 5.346 6.030 5.332 6.016 5.335 6.019 5.330 6.014 5.316 6.000 5.325 6.009 5.896 6.562 5.901 6.574 5.967 6.604 5.941 6.595 5.917 6.581 5.906 6.585 5.896 6.579 5.896 6.562 5.902 6.573 5.698 6.390 5.710 6.402 5.740 6.432 5.731 6.423 5.717 6.409 5.721 6.413 5.715 6.407 5.698 6.390 5.709 6.401 6.120 6.945 6.132 6.950 6.162 7.016 6.153 6.990 6.139 6.966 6.143 6.955 6.137 6.945 6.120 6.945 6.131 6.951 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 4mA 6mA SSTL-15 CLASS I 8mA 10mA 12mA 8mA SSTL-15 CLASS II 16mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-293 Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 6 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.483 3.926 3.476 3.919 3.468 3.911 3.471 3.914 3.468 3.911 3.476 3.919 3.488 3.931 3.484 3.927 3.480 3.923 3.473 3.916 3.474 3.917 3.472 3.915 3.516 3.915 3.509 3.908 3.501 3.900 3.504 3.903 3.501 3.900 3.509 3.908 3.521 3.920 3.517 3.916 3.513 3.912 3.506 3.905 3.507 3.906 3.505 3.904 5.153 5.788 5.151 5.786 5.143 5.778 5.146 5.781 5.149 5.784 5.148 5.783 5.161 5.796 5.162 5.797 5.158 5.793 5.151 5.786 5.158 5.793 5.139 5.774 5.316 6.000 5.314 5.998 5.307 5.991 5.310 5.994 5.314 5.998 5.311 5.995 5.326 6.010 5.327 6.011 5.323 6.007 5.316 6.000 5.324 6.008 5.302 5.986 5.910 6.560 5.906 6.559 5.879 6.552 5.882 6.556 5.881 6.560 5.878 6.556 5.926 6.571 5.915 6.574 5.909 6.569 5.896 6.562 5.892 6.572 5.871 6.546 5.696 6.388 5.695 6.387 5.688 6.380 5.692 6.384 5.696 6.388 5.692 6.384 5.707 6.399 5.710 6.402 5.705 6.397 5.698 6.390 5.708 6.400 5.682 6.374 6.118 6.959 6.117 6.954 6.110 6.928 6.114 6.931 6.118 6.929 6.114 6.927 6.129 6.975 6.132 6.964 6.127 6.958 6.120 6.945 6.130 6.941 6.104 6.920 5.316 6.000 5.314 5.998 5.307 5.991 5.310 5.994 5.314 5.998 5.311 5.995 5.326 6.010 5.327 6.011 5.323 6.007 5.316 6.000 5.324 6.008 5.302 5.986 5.910 6.560 5.906 6.559 5.879 6.552 5.882 6.556 5.881 6.560 5.878 6.556 5.926 6.571 5.915 6.574 5.909 6.569 5.896 6.562 5.892 6.572 5.871 6.546 5.696 6.388 5.695 6.387 5.688 6.380 5.692 6.384 5.696 6.388 5.692 6.384 5.707 6.399 5.710 6.402 5.705 6.397 5.698 6.390 5.708 6.400 5.682 6.374 6.118 6.959 6.117 6.954 6.110 6.928 6.114 6.931 6.118 6.929 6.114 6.927 6.129 6.975 6.132 6.964 6.127 6.958 6.120 6.945 6.130 6.941 6.104 6.920 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.8-V HSTL CLASS I 8mA 10mA 12mA 1.8-V HSTL CLASS II 16mA 4mA 6mA 1.5-V HSTL CLASS I 8mA 10mA 12mA 1.5-V HSTL CLASS II 16mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-294 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-133. EP3SE260 Column Pins Output Timing Parameters (Part 7 of 7) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL = 1.1 V C4L VCCL = 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.491 3.934 3.483 3.926 3.484 3.927 3.473 3.916 3.473 3.916 3.494 3.937 3.597 4.040 3.597 4.040 3.524 3.923 3.516 3.915 3.517 3.916 3.506 3.905 3.506 3.905 3.527 3.926 3.630 4.029 3.630 4.029 5.175 5.810 5.166 5.801 5.174 5.809 5.161 5.796 5.161 5.796 5.177 5.812 5.222 5.857 5.222 5.857 5.343 6.027 5.334 6.018 5.342 6.026 5.329 6.013 5.329 6.013 5.344 6.028 5.378 6.062 5.378 6.062 5.945 6.592 5.928 6.583 5.924 6.592 5.901 6.578 5.902 6.579 5.980 6.592 5.955 6.617 5.955 6.617 5.728 6.420 5.719 6.411 5.728 6.420 5.714 6.406 5.715 6.407 5.728 6.420 5.753 6.445 5.753 6.445 6.150 6.994 6.141 6.977 6.150 6.973 6.136 6.950 6.137 6.951 6.150 7.029 6.175 7.004 6.175 7.004 5.343 6.027 5.334 6.018 5.342 6.026 5.329 6.013 5.329 6.013 5.344 6.028 5.378 6.062 5.378 6.062 5.945 6.592 5.928 6.583 5.924 6.592 5.901 6.578 5.902 6.579 5.980 6.592 5.955 6.617 5.955 6.617 5.728 6.420 5.719 6.411 5.728 6.420 5.714 6.406 5.715 6.407 5.728 6.420 5.753 6.445 5.753 6.445 6.150 6.994 6.141 6.977 6.150 6.973 6.136 6.950 6.137 6.951 6.150 7.029 6.175 7.004 6.175 7.004 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA 1.2-V HSTL CLASS I 8mA 10mA 12mA 1.2-V HSTL CLASS II 16mA 3.0-V PCI -- 3.0-V PCI-X -- Table 1-134 lists the EP3SE260 row pins output timing parameters for single-ended I/O standards. Table 1-134. EP3SE260 Row Pins Output Timing Parameters (Part 1 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 12mA GCLK PLL tco tco tco tco tco tco 3.648 1.582 3.555 1.489 3.456 1.390 3.902 1.785 3.797 1.680 3.707 1.574 5.663 5.865 6.484 6.256 6.709 6.063 6.530 6.256 6.709 2.228 2.322 2.505 2.489 2.454 2.441 2.632 2.489 2.454 5.533 5.727 6.340 6.112 6.565 5.922 6.414 6.112 6.565 2.098 2.184 2.361 2.346 2.310 2.300 2.483 2.346 2.310 5.414 5.604 6.212 5.995 6.446 5.795 6.315 5.995 6.446 1.979 2.061 2.233 2.250 2.182 2.173 2.354 2.250 2.182 ns ns ns ns ns ns 3.3-V LVTTL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-295 Table 1-134. EP3SE260 Row Pins Output Timing Parameters (Part 2 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.658 1.592 3.460 1.394 3.602 1.536 3.477 1.411 3.438 1.372 3.516 1.450 3.416 1.350 3.628 1.562 3.518 1.452 3.472 1.406 3.886 1.787 3.661 1.562 3.596 1.497 3.536 1.437 3.906 1.789 3.711 1.580 3.848 1.731 3.721 1.604 3.678 1.553 3.767 1.650 3.662 1.531 3.884 1.767 3.785 1.668 3.718 1.592 4.170 2.014 3.968 1.812 3.866 1.710 3.792 1.649 5.671 5.870 6.489 6.261 6.714 6.069 6.542 6.261 6.714 2.236 2.327 2.510 2.494 2.459 2.447 2.637 2.494 2.459 5.420 5.616 6.218 6.005 6.456 5.801 6.324 6.005 6.456 1.985 2.067 2.239 2.260 2.188 2.179 2.363 2.260 2.188 5.615 5.818 6.441 6.213 6.666 6.020 6.496 6.213 6.666 2.180 2.275 2.462 2.446 2.411 2.398 2.590 2.446 2.411 5.463 5.659 6.277 6.049 6.502 5.858 6.351 6.049 6.502 2.028 2.116 2.298 2.282 2.247 2.236 2.426 2.282 2.247 5.381 5.576 6.189 5.961 6.414 5.772 6.277 5.961 6.414 1.946 2.033 2.210 2.211 2.159 2.150 2.333 2.211 2.159 5.510 5.711 6.330 6.102 6.555 5.912 6.387 6.102 6.555 2.075 2.168 2.351 2.335 2.300 2.290 2.479 2.335 2.300 5.351 5.545 6.150 5.928 6.379 5.732 6.249 5.928 6.379 1.911 1.994 2.171 2.183 2.120 2.110 2.293 2.183 2.120 5.748 5.972 6.613 6.385 6.838 6.180 6.648 6.385 6.838 2.313 2.429 2.634 2.618 2.583 2.558 2.769 2.618 2.583 5.593 5.809 6.443 6.215 6.668 6.013 6.504 6.215 6.668 2.158 2.266 2.464 2.448 2.413 2.391 2.595 2.448 2.413 5.482 5.690 6.317 6.089 6.542 5.890 6.409 6.089 6.542 2.047 2.147 2.338 2.338 2.287 2.268 2.465 2.338 2.287 6.174 6.450 7.088 6.750 7.260 6.640 7.070 6.750 7.260 2.698 2.822 3.109 3.100 3.058 2.988 3.253 3.100 3.058 5.848 6.082 6.683 6.390 6.855 6.275 6.709 6.390 6.855 2.372 2.454 2.704 2.695 2.653 2.623 2.847 2.695 2.653 5.694 5.932 6.524 6.289 6.709 6.107 6.603 6.289 6.709 2.218 2.304 2.545 2.536 2.494 2.455 2.674 2.536 2.494 5.617 5.839 6.428 6.224 6.644 6.012 6.531 6.224 6.644 2.141 2.227 2.449 2.440 2.398 2.360 2.580 2.440 2.398 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.3-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 3.0-V LVTTL 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 3.0-V LVCMOS 4mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 2.5 V 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK 2mA GCLK PLL GCLK 4mA 1.8 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-296 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-134. EP3SE260 Row Pins Output Timing Parameters (Part 3 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 2mA GCLK PLL GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.797 1.698 3.555 1.456 3.528 1.429 3.519 1.420 3.740 1.641 3.560 1.461 3.457 1.391 3.445 1.379 3.429 1.363 3.497 1.398 3.482 1.383 3.471 1.372 3.447 1.348 3.447 1.348 4.088 1.932 3.831 1.675 3.783 1.640 3.774 1.629 4.013 1.857 3.824 1.670 3.706 1.578 3.702 1.566 3.691 1.548 3.748 1.593 3.734 1.588 3.722 1.577 3.699 1.566 3.698 1.565 6.084 6.364 7.016 6.687 7.188 6.547 7.005 6.687 7.188 2.608 2.736 3.037 3.028 2.986 2.895 3.177 3.028 2.986 5.679 5.927 6.525 6.293 6.713 6.101 6.604 6.293 6.713 2.203 2.299 2.546 2.537 2.495 2.449 2.673 2.537 2.495 5.606 5.831 6.419 6.224 6.644 6.003 6.531 6.224 6.644 2.130 2.219 2.440 2.431 2.389 2.351 2.568 2.431 2.389 5.584 5.813 6.400 6.205 6.625 5.985 6.512 6.205 6.625 2.108 2.195 2.421 2.412 2.370 2.333 2.549 2.412 2.370 5.994 6.278 6.941 6.626 7.113 6.459 6.936 6.626 7.113 2.518 2.650 2.962 2.953 2.911 2.807 3.093 2.953 2.911 5.701 5.955 6.566 6.341 6.761 6.126 6.648 6.341 6.761 2.225 2.327 2.587 2.578 2.536 2.474 2.715 2.578 2.536 5.468 5.677 6.285 6.073 6.524 5.857 6.395 6.073 6.524 2.024 2.119 2.306 2.328 2.255 2.235 2.434 2.328 2.255 5.465 5.675 6.277 6.071 6.522 5.849 6.394 6.071 6.522 2.016 2.111 2.301 2.326 2.247 2.227 2.433 2.326 2.247 5.450 5.659 6.250 6.054 6.505 5.823 6.376 6.054 6.505 1.991 2.086 2.284 2.309 2.220 2.201 2.415 2.309 2.220 5.512 5.726 6.301 6.119 6.539 5.893 6.422 6.119 6.539 2.041 2.131 2.324 2.313 2.271 2.241 2.459 2.313 2.271 5.509 5.724 6.299 6.118 6.538 5.891 6.420 6.118 6.538 2.039 2.130 2.323 2.311 2.269 2.239 2.457 2.311 2.269 5.492 5.707 6.282 6.108 6.528 5.874 6.411 6.108 6.528 2.029 2.120 2.313 2.294 2.252 2.222 2.448 2.294 2.252 5.476 5.691 6.267 6.095 6.515 5.859 6.399 6.095 6.515 2.016 2.107 2.300 2.279 2.237 2.207 2.436 2.279 2.237 5.475 5.690 6.266 6.095 6.515 5.858 6.399 6.095 6.515 2.016 2.107 2.300 2.278 2.236 2.206 2.436 2.278 2.236 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 V 6mA GCLK PLL GCLK GCLK PLL GCLK 8mA GCLK PLL GCLK 2mA 1.2 V 4mA GCLK PLL GCLK GCLK PLL GCLK SSTL-2 CLASS I 8mA GCLK PLL GCLK 12mA GCLK PLL GCLK SSTL-2 CLASS II 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK SSTL-18 CLASS I 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-297 Table 1-134. EP3SE260 Row Pins Output Timing Parameters (Part 4 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.457 1.358 3.451 1.352 3.493 1.394 3.470 1.371 3.453 1.354 3.472 1.373 3.460 1.361 3.447 1.348 3.449 1.350 3.442 1.343 3.448 1.349 3.479 1.380 3.467 1.368 3.463 1.364 3.707 1.572 3.702 1.575 3.744 1.596 3.722 1.582 3.705 1.570 3.720 1.578 3.708 1.572 3.696 1.564 3.698 1.566 3.693 1.563 3.697 1.571 3.727 1.584 3.717 1.579 3.712 1.575 5.473 5.686 6.260 6.090 6.510 5.853 6.393 6.090 6.510 2.015 2.104 2.295 2.272 2.230 2.201 2.430 2.272 2.230 5.472 5.687 6.262 6.100 6.520 5.855 6.404 6.100 6.520 2.021 2.112 2.305 2.274 2.233 2.203 2.441 2.274 2.233 5.523 5.740 6.318 6.132 6.552 5.906 6.434 6.132 6.552 2.050 2.142 2.339 2.330 2.288 2.254 2.471 2.330 2.288 5.505 5.723 6.301 6.122 6.542 5.890 6.425 6.122 6.542 2.039 2.132 2.327 2.313 2.271 2.238 2.462 2.313 2.271 5.488 5.705 6.283 6.109 6.529 5.872 6.412 6.109 6.529 2.026 2.119 2.314 2.295 2.253 2.220 2.449 2.295 2.253 5.479 5.691 6.263 6.088 6.508 5.857 6.390 6.088 6.508 2.014 2.102 2.293 2.275 2.233 2.205 2.427 2.275 2.233 5.470 5.683 6.255 6.087 6.507 5.849 6.390 6.087 6.507 2.012 2.101 2.292 2.267 2.225 2.197 2.427 2.267 2.225 5.462 5.674 6.247 6.080 6.500 5.841 6.383 6.080 6.500 2.005 2.094 2.285 2.259 2.217 2.189 2.420 2.259 2.217 5.464 5.677 6.250 6.084 6.504 5.844 6.386 6.084 6.504 2.008 2.097 2.289 2.262 2.220 2.192 2.423 2.262 2.220 5.462 5.676 6.250 6.087 6.507 5.844 6.391 6.087 6.507 2.010 2.100 2.292 2.262 2.220 2.192 2.428 2.262 2.220 5.457 5.668 6.241 6.083 6.503 5.835 6.385 6.083 6.503 2.008 2.097 2.288 2.253 2.216 2.183 2.422 2.253 2.216 5.490 5.704 6.278 6.099 6.519 5.869 6.401 6.099 6.519 2.023 2.112 2.304 2.290 2.248 2.217 2.438 2.290 2.248 5.486 5.700 6.274 6.101 6.521 5.866 6.404 6.101 6.521 2.024 2.114 2.306 2.286 2.244 2.214 2.441 2.286 2.244 5.480 5.694 6.268 6.096 6.516 5.860 6.398 6.096 6.516 2.019 2.109 2.301 2.280 2.238 2.208 2.435 2.280 2.238 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SSTL-18 CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 4mA GCLK PLL GCLK SSTL-15 CLASS I 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA 1.8-V HSTL CLASS I GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK 1.8-V HSTL CLASS II 16mA GCLK PLL GCLK 4mA 1.5-V HSTL CLASS I GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-298 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-134. EP3SE260 Row Pins Output Timing Parameters (Part 5 of 5) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco 3.478 1.379 3.466 1.367 3.463 1.364 3.542 1.476 3.542 1.476 3.726 1.586 3.714 1.578 3.712 1.578 3.812 1.661 3.812 1.661 5.501 5.718 6.296 6.118 6.538 5.883 6.420 6.118 6.538 2.036 2.128 2.323 2.308 2.266 2.231 2.457 2.308 2.266 5.490 5.706 6.284 6.109 6.529 5.872 6.411 6.109 6.529 2.027 2.119 2.314 2.296 2.254 2.220 2.448 2.296 2.254 5.494 5.711 6.290 6.118 6.538 5.878 6.421 6.118 6.538 2.034 2.127 2.323 2.302 2.260 2.226 2.458 2.302 2.260 5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564 2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264 5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564 2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264 ns ns ns ns ns ns ns ns ns ns 1.2-V HSTL CLASS I 3.0-V PCI -- GCLK PLL GCLK 3.0-V PCI-X -- GCLK PLL Table 1-135 through Table 1-138 list the maximum I/O timing parameters for EP3SE260 devices for differential I/O standards. Table 1-135 lists the EP3SE260 column pins input timing parameters for differential I/O standards. Table 1-135. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock GCLK tsu th -1.153 1.289 1.103 -0.824 -1.153 1.289 1.103 -0.824 -1.161 1.297 1.095 -0.816 -1.161 1.297 1.095 -0.816 -1.221 1.376 1.122 -0.821 -1.221 1.376 1.122 -0.821 -1.233 1.388 1.110 -0.809 -1.233 1.388 1.110 -0.809 -1.879 2.114 1.882 -1.403 -1.879 2.114 1.882 -1.403 -1.889 2.124 1.872 -1.393 -1.889 2.124 1.872 -1.393 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LVDS GCLK PLL GCLK tsu th tsu th -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 MINI-LVDS GCLK PLL GCLK tsu th tsu th -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 RSDS GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.2-V HSTL CLASS I -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-299 Table 1-135. EP3SE260 Column Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.2-V HSTL CLASS II GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.173 1.309 1.083 -0.804 -1.173 1.309 1.083 -0.804 -1.161 1.297 1.095 -0.816 -1.161 1.297 1.095 -0.816 -1.173 1.309 1.083 -0.804 -1.173 1.309 1.083 -0.804 -1.180 1.316 1.076 -0.797 -1.180 1.316 1.076 -0.797 -1.153 1.289 1.103 -0.824 -1.244 1.399 1.099 -0.798 -1.244 1.399 1.099 -0.798 -1.233 1.388 1.110 -0.809 -1.233 1.388 1.110 -0.809 -1.244 1.399 1.099 -0.798 -1.244 1.399 1.099 -0.798 -1.250 1.405 1.093 -0.792 -1.250 1.405 1.093 -0.792 -1.221 1.376 1.122 -0.821 -1.898 2.133 1.863 -1.384 -1.898 2.133 1.863 -1.384 -1.889 2.124 1.872 -1.393 -1.889 2.124 1.872 -1.393 -1.898 2.133 1.863 -1.384 -1.898 2.133 1.863 -1.384 -1.910 2.146 1.851 -1.371 -1.910 2.146 1.851 -1.371 -1.879 2.114 1.882 -1.403 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.5-V HSTL CLASS I -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.5-V HSTL CLASS II -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 1.8-V HSTL CLASS I -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.8-V HSTL CLASS II -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 2.172 1.964 2.365 2.172 2.272 2.064 2.746 2.061 2.199 1.976 2.388 2.184 2.272 2.064 2.746 2.061 DIFFERENTIAL 1.5-V SSTL CLASS I -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 2.180 1.959 2.368 2.172 2.275 2.062 2.750 2.062 2.206 1.972 2.388 2.189 2.275 2.062 2.750 2.062 DIFFERENTIAL 1.5-V SSTL CLASS II -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 2.180 1.959 2.368 2.172 2.275 2.062 2.750 2.062 2.206 1.972 2.388 2.189 2.275 2.062 2.750 2.062 DIFFERENTIAL 1.8-V SSTL CLASS I -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 DIFFERENTIAL 1.8-V SSTL CLASS II -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-300 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-135. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th -1.153 1.289 1.103 -0.824 -1.161 1.297 1.095 -0.816 -1.221 1.376 1.122 -0.821 -1.233 1.388 1.110 -0.809 -1.879 2.114 1.882 -1.403 -1.889 2.124 1.872 -1.393 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 2.150 1.986 2.330 2.207 2.237 2.099 2.711 2.096 2.177 1.998 2.355 2.217 2.237 2.099 2.711 2.096 ns ns ns ns ns ns ns ns -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 2.161 1.975 2.346 2.191 2.253 2.083 2.727 2.080 2.188 1.987 2.370 2.202 2.253 2.083 2.727 2.080 DIFFERENTIAL 2.5-V SSTL CLASS II -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 Table 1-136 lists the EP3SE260 row pins input timing parameters for differential I/O standards. Table 1-136. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock GCLK LVDS GCLK PLL GCLK MINI-LVDS GCLK PLL GCLK RSDS GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.332 1.476 0.869 -0.581 -1.332 1.476 0.869 -0.581 -1.332 1.476 0.869 -0.581 -1.137 1.274 1.064 -0.783 -1.137 1.274 1.064 -0.783 -1.401 1.563 0.886 -0.578 -1.401 1.563 0.886 -0.578 -1.401 1.563 0.886 -0.578 -1.216 1.369 1.071 -0.772 -1.216 1.369 1.071 -0.772 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 1.994 1.991 1.939 2.205 2.157 2.405 2.071 2.282 2.526 2.297 1.934 2.252 2.145 2.458 2.071 2.282 2.526 2.297 -1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 -1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 2.088 1.866 2.122 1.981 2.297 2.216 2.206 2.098 2.656 2.118 2.156 1.985 2.330 2.221 2.206 2.098 2.656 2.118 DIFFERENTIAL 1.2-V HSTL CLASS I -1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 -1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 2.088 1.866 2.122 1.981 2.297 2.216 2.206 2.098 2.656 2.118 2.156 1.985 2.330 2.221 2.206 2.098 2.656 2.118 DIFFERENTIAL 1.2-V HSTL CLASS II -1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-301 Table 1-136. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 1.5-V HSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.146 1.283 1.055 -0.774 -1.146 1.283 1.055 -0.774 -1.160 1.297 1.041 -0.760 -1.160 1.297 1.041 -0.760 -1.146 1.283 1.055 -0.774 -1.146 1.283 1.055 -0.774 -1.160 1.297 1.041 -0.760 -1.160 1.297 1.041 -0.760 -1.169 1.306 1.032 -0.751 -1.228 1.381 1.059 -0.760 -1.228 1.381 1.059 -0.760 -1.240 1.393 1.047 -0.748 -1.240 1.393 1.047 -0.748 -1.228 1.381 1.059 -0.760 -1.228 1.381 1.059 -0.760 -1.240 1.393 1.047 -0.748 -1.240 1.393 1.047 -0.748 -1.249 1.402 1.038 -0.739 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 DIFFERENTIAL 1.5-V HSTL CLASS II -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 DIFFERENTIAL 1.8-V HSTL CLASS I -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 DIFFERENTIAL 1.8-V HSTL CLASS II GCLK PLL tsu th -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 DIFFERENTIAL 1.5-V SSTL CLASS I GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th tsu th -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 2.097 1.857 2.132 1.971 2.313 2.200 2.222 2.082 2.672 2.102 2.165 1.976 2.346 2.205 2.222 2.082 2.672 2.102 DIFFERENTIAL 1.5-V SSTL CLASS II -1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 DIFFERENTIAL 1.8-V SSTL CLASS I -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 2.106 1.844 2.142 1.961 2.331 2.182 2.240 2.064 2.690 2.084 2.176 1.965 2.363 2.188 2.240 2.064 2.690 2.084 DIFFERENTIAL 1.8-V SSTL CLASS II -1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 -1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 2.121 1.829 2.156 1.945 2.341 2.171 2.250 2.052 2.701 2.073 2.186 1.954 2.369 2.182 2.250 2.052 2.701 2.073 DIFFERENTIAL 2.5-V SSTL CLASS I -1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-302 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-136. EP3SE260 Row Pins Input Timing Parameters (Part 3 of 3) Parameter Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units I/O Standard Clock DIFFERENTIAL 2.5-V SSTL CLASS II GCLK GCLK PLL tsu th tsu th -1.169 1.306 1.032 -0.751 -1.249 1.402 1.038 -0.739 -1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 2.121 1.829 2.156 1.945 2.341 2.171 2.250 2.052 2.701 2.073 2.186 1.954 2.369 2.182 2.250 2.052 2.701 2.073 ns ns ns ns -1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 Table 1-137 lists the EP3SE260 column pins output timing parameters for differential I/O standards. Table 1-137. EP3SE260 Column Pins Output Timing Parameters (Part 1 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK tco tco tco tco tco tco tco tco tco tco tco tco 3.479 3.475 3.479 3.475 3.479 3.475 3.506 3.496 3.496 3.489 3.488 3.510 3.750 3.753 3.750 3.753 3.750 3.753 3.783 3.773 3.773 3.767 3.765 3.787 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 5.567 5.779 6.344 6.180 6.587 5.923 6.487 6.180 6.587 5.570 5.783 6.348 6.184 6.591 5.928 6.492 6.184 6.591 5.563 5.777 6.342 6.178 6.585 5.921 6.486 6.178 6.585 5.560 5.774 6.339 6.175 6.582 5.918 6.482 6.175 6.582 5.581 5.794 6.358 6.194 6.601 5.938 6.502 6.194 6.601 ns ns ns ns ns ns ns ns ns ns ns ns LVDS_E_1R -- GCLK PLL GCLK LVDS_E_3R -- GCLK PLL GCLK MINILVDS_E_1R MINILVDS_E_3R -- GCLK PLL GCLK -- GCLK PLL GCLK RSDS_E_1R -- GCLK PLL GCLK RSDS_E_3R -- GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-303 Table 1-137. EP3SE260 Column Pins Output Timing Parameters (Part 2 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK GCLK PLL tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.500 3.495 3.493 3.485 3.486 3.485 3.497 3.493 3.483 3.481 3.481 3.485 3.511 3.497 3.485 3.485 3.481 3.485 3.486 3.514 3.503 3.498 3.484 3.482 3.776 3.772 3.770 3.761 3.763 3.760 3.773 3.770 3.759 3.757 3.758 3.761 3.790 3.776 3.763 3.763 3.759 3.761 3.763 3.793 3.781 3.777 3.762 3.760 5.560 5.771 6.333 6.169 6.576 5.914 6.475 6.169 6.576 5.560 5.771 6.334 6.170 6.577 5.915 6.477 6.170 6.577 5.559 5.770 6.332 6.168 6.575 5.914 6.476 6.168 6.575 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.555 5.767 6.331 6.167 6.574 5.912 6.475 6.167 6.574 5.538 5.748 6.309 6.145 6.552 5.891 6.451 6.145 6.552 5.556 5.766 6.327 6.163 6.570 5.910 6.470 6.163 6.570 5.557 5.768 6.331 6.167 6.574 5.912 6.474 6.167 6.574 5.546 5.757 6.319 6.155 6.562 5.901 6.462 6.155 6.562 5.544 5.754 6.317 6.153 6.560 5.899 6.460 6.153 6.560 5.547 5.759 6.322 6.158 6.565 5.903 6.466 6.158 6.565 5.544 5.754 6.316 6.152 6.559 5.898 6.459 6.152 6.559 5.589 5.802 6.366 6.202 6.609 5.946 6.509 6.202 6.609 5.577 5.791 6.356 6.192 6.599 5.936 6.500 6.192 6.599 5.560 5.773 6.338 6.174 6.581 5.918 6.482 6.174 6.581 5.563 5.777 6.342 6.178 6.585 5.922 6.487 6.178 6.585 5.556 5.769 6.335 6.171 6.578 5.915 6.479 6.171 6.578 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.557 5.770 6.334 6.170 6.577 5.914 6.478 6.170 6.577 5.588 5.800 6.364 6.200 6.607 5.945 6.507 6.200 6.607 5.576 5.788 6.352 6.188 6.595 5.933 6.495 6.188 6.595 5.576 5.789 6.353 6.189 6.596 5.934 6.497 6.189 6.596 5.558 5.770 6.334 6.170 6.577 5.915 6.479 6.170 6.577 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 16mA 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 16mA 1.5-V HSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-304 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-137. EP3SE260 Column Pins Output Timing Parameters (Part 3 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK GCLK PLL GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.486 3.486 3.502 3.502 3.492 3.485 3.479 3.475 3.479 3.475 3.479 3.475 3.506 3.496 3.496 3.489 3.488 3.510 3.500 3.495 3.493 3.485 3.486 3.485 3.497 3.493 3.762 3.763 3.780 3.780 3.770 3.762 3.750 3.753 3.750 3.753 3.750 3.753 3.783 3.773 3.773 3.767 3.765 3.787 3.776 3.772 3.770 3.761 3.763 3.760 3.773 3.770 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.562 5.773 6.336 6.172 6.579 5.918 6.480 6.172 6.579 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 5.567 5.779 6.344 6.180 6.587 5.923 6.487 6.180 6.587 5.570 5.783 6.348 6.184 6.591 5.928 6.492 6.184 6.591 5.563 5.777 6.342 6.178 6.585 5.921 6.486 6.178 6.585 5.560 5.774 6.339 6.175 6.582 5.918 6.482 6.175 6.582 5.581 5.794 6.358 6.194 6.601 5.938 6.502 6.194 6.601 5.560 5.771 6.333 6.169 6.576 5.914 6.475 6.169 6.576 5.560 5.771 6.334 6.170 6.577 5.915 6.477 6.170 6.577 5.559 5.770 6.332 6.168 6.575 5.914 6.476 6.168 6.575 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.555 5.767 6.331 6.167 6.574 5.912 6.475 6.167 6.574 5.538 5.748 6.309 6.145 6.552 5.891 6.451 6.145 6.552 5.556 5.766 6.327 6.163 6.570 5.910 6.470 6.163 6.570 5.557 5.768 6.331 6.167 6.574 5.912 6.474 6.167 6.574 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V HSTL CLASS I DIFFERENTIAL 16mA 1.8-V HSTL CLASS II DIFFERENTIAL 1.5-V SSTL CLASS I DIFFERENTIAL 1.5-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-305 Table 1-137. EP3SE260 Column Pins Output Timing Parameters (Part 4 of 4) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL = 1.1 V I4L VCCL= 0.9 V Units Clock GCLK 4mA GCLK PLL GCLK 6mA GCLK PLL GCLK 8mA GCLK PLL GCLK 10mA GCLK PLL GCLK 12mA GCLK PLL GCLK tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.483 3.481 3.481 3.485 3.511 3.497 3.485 3.485 3.481 3.485 3.486 3.514 3.503 3.498 3.484 3.482 3.486 3.486 3.502 3.502 3.492 3.485 3.759 3.757 3.758 3.761 3.790 3.776 3.763 3.763 3.759 3.761 3.763 3.793 3.781 3.777 3.762 3.760 3.762 3.763 3.780 3.780 3.770 3.762 5.546 5.757 6.319 6.155 6.562 5.901 6.462 6.155 6.562 5.544 5.754 6.317 6.153 6.560 5.899 6.460 6.153 6.560 5.547 5.759 6.322 6.158 6.565 5.903 6.466 6.158 6.565 5.544 5.754 6.316 6.152 6.559 5.898 6.459 6.152 6.559 5.589 5.802 6.366 6.202 6.609 5.946 6.509 6.202 6.609 5.577 5.791 6.356 6.192 6.599 5.936 6.500 6.192 6.599 5.560 5.773 6.338 6.174 6.581 5.918 6.482 6.174 6.581 5.563 5.777 6.342 6.178 6.585 5.922 6.487 6.178 6.585 5.556 5.769 6.335 6.171 6.578 5.915 6.479 6.171 6.578 5.549 5.760 6.323 6.159 6.566 5.904 6.466 6.159 6.566 5.557 5.770 6.334 6.170 6.577 5.914 6.478 6.170 6.577 5.588 5.800 6.364 6.200 6.607 5.945 6.507 6.200 6.607 5.576 5.788 6.352 6.188 6.595 5.933 6.495 6.188 6.595 5.576 5.789 6.353 6.189 6.596 5.934 6.497 6.189 6.596 5.558 5.770 6.334 6.170 6.577 5.915 6.479 6.170 6.577 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 5.556 5.768 6.332 6.168 6.575 5.913 6.476 6.168 6.575 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.572 5.783 6.346 6.182 6.589 5.928 6.489 6.182 6.589 5.562 5.773 6.336 6.172 6.579 5.918 6.480 6.172 6.579 5.548 5.758 6.320 6.156 6.563 5.902 6.463 6.156 6.563 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DIFFERENTIAL 1.8-V SSTL CLASS I DIFFERENTIAL 1.8-V SSTL CLASS II 8mA GCLK PLL GCLK 16mA GCLK PLL GCLK 8mA DIFFERENTIAL 2.5-V SSTL 10mA CLASS I GCLK PLL GCLK GCLK PLL GCLK 12mA GCLK PLL GCLK GCLK PLL DIFFERENTIAL 16mA 2.5-V SSTL CLASS II (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-306 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-138 lists the EP3SE260 row pins output timing parameters for differential I/O standards. Table 1-138. EP3SE260 Row Pins Output Timing Parameters (Part 1 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK LVDS -- tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.152 3.536 3.518 3.152 3.536 3.518 3.152 3.536 3.518 3.562 3.548 3.544 3.560 3.549 3.546 3.557 3.547 3.533 3.530 3.527 3.528 3.577 3.553 3.535 3.376 3.812 3.802 3.376 3.812 3.802 3.376 3.812 3.802 3.845 3.831 3.827 3.842 3.832 3.829 3.839 3.830 3.816 3.812 3.810 3.810 3.863 3.839 3.820 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 5.657 5.871 6.443 6.276 6.655 6.023 6.597 6.276 6.655 5.642 5.856 6.429 6.262 6.641 6.008 6.582 6.262 6.641 5.638 5.852 6.425 6.258 6.637 6.004 6.578 6.258 6.637 5.639 5.855 6.428 6.261 6.640 6.007 6.582 6.261 6.640 5.629 5.843 6.415 6.248 6.627 5.994 6.568 6.248 6.627 5.700 5.916 6.491 6.324 6.703 6.068 6.644 6.324 6.703 5.682 5.899 6.474 6.307 6.686 6.051 6.629 6.307 6.686 5.660 5.877 6.452 6.285 6.664 6.029 6.607 6.285 6.664 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL LVDS_E_1R -- LVDS_E_3R -- MINI-LVDS -- MINILVDS_E_1R -- MINILVDS_E_3R -- RSDS -- RSDS_E_1R -- RSDS_E_3R -- 4mA DIFFERENTIAL 1.2-V HSTL CLASS I 6mA 8mA Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-307 Table 1-138. EP3SE260 Row Pins Output Timing Parameters (Part 2 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.581 3.566 3.555 3.535 3.532 3.537 3.530 3.568 3.550 3.536 3.152 3.536 3.518 3.152 3.536 3.518 3.152 3.536 3.518 3.562 3.548 3.544 3.560 3.549 3.866 3.851 3.840 3.820 3.816 3.820 3.813 3.852 3.835 3.819 3.376 3.812 3.802 3.376 3.812 3.802 3.376 3.812 3.802 3.845 3.831 3.827 3.842 3.832 5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 5.686 5.901 6.475 6.308 6.687 6.053 6.629 6.308 6.687 5.681 5.898 6.472 6.305 6.684 6.050 6.627 6.305 6.684 5.658 5.874 6.449 6.282 6.661 6.027 6.603 6.282 6.661 5.654 5.871 6.445 6.278 6.657 6.023 6.600 6.278 6.657 5.645 5.859 6.431 6.264 6.643 6.010 6.584 6.264 6.643 5.644 5.860 6.434 6.267 6.646 6.013 6.589 6.267 6.646 5.682 5.897 6.470 6.303 6.682 6.049 6.624 6.303 6.682 5.667 5.882 6.455 6.288 6.667 6.034 6.609 6.288 6.667 5.644 5.858 6.430 6.263 6.642 6.010 6.584 6.263 6.642 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL DIFFERENTIAL 1.5-V HSTL CLASS I 6mA 8mA 4mA 6mA DIFFERENTIAL 1.8-V HSTL CLASS I 8mA 10mA 12mA DIFFERENTIAL 1.8-V HSTL CLASS II 16mA 4mA DIFFERENTIAL 1.5-V SSTL CLASS I 6mA 8mA (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-308 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-138. EP3SE260 Row Pins Output Timing Parameters (Part 3 of 3) Parameter I/O Standard Current Strength Fast Model Industrial Commercial C2 VCCL= 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V C4L VCCL= 1.1 V VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL = 0.9 V Units Clock GCLK 4mA tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco tco 3.546 3.557 3.547 3.533 3.530 3.527 3.528 3.577 3.553 3.535 3.581 3.566 3.555 3.535 3.532 3.537 3.530 3.568 3.550 3.536 3.829 3.839 3.830 3.816 3.812 3.810 3.810 3.863 3.839 3.820 3.866 3.851 3.840 3.820 3.816 3.820 3.813 3.852 3.835 3.819 5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 5.657 5.871 6.443 6.276 6.655 6.023 6.597 6.276 6.655 5.642 5.856 6.429 6.262 6.641 6.008 6.582 6.262 6.641 5.638 5.852 6.425 6.258 6.637 6.004 6.578 6.258 6.637 5.639 5.855 6.428 6.261 6.640 6.007 6.582 6.261 6.640 5.629 5.843 6.415 6.248 6.627 5.994 6.568 6.248 6.627 5.700 5.916 6.491 6.324 6.703 6.068 6.644 6.324 6.703 5.682 5.899 6.474 6.307 6.686 6.051 6.629 6.307 6.686 5.660 5.877 6.452 6.285 6.664 6.029 6.607 6.285 6.664 5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 5.686 5.901 6.475 6.308 6.687 6.053 6.629 6.308 6.687 5.681 5.898 6.472 6.305 6.684 6.050 6.627 6.305 6.684 5.658 5.874 6.449 6.282 6.661 6.027 6.603 6.282 6.661 5.654 5.871 6.445 6.278 6.657 6.023 6.600 6.278 6.657 5.645 5.859 6.431 6.264 6.643 6.010 6.584 6.264 6.643 5.644 5.860 6.434 6.267 6.646 6.013 6.589 6.267 6.646 5.682 5.897 6.470 6.303 6.682 6.049 6.624 6.303 6.682 5.667 5.882 6.455 6.288 6.667 6.034 6.609 6.288 6.667 5.644 5.858 6.430 6.263 6.642 6.010 6.584 6.263 6.642 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL GCLK GCLK PLL 6mA DIFFERENTIAL 1.8-V SSTL CLASS I 8mA 10mA 12mA 8mA DIFFERENTIAL 1.8-V SSTL CLASS II 16mA 8mA DIFFERENTIAL 2.5-V SSTL CLASS I 12mA DIFFERENTIAL 2.5-V 16mA SSTL CLASS II Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-309 Table 1-139 and Table 1-140 list the EP3SE260 regional clock (RCLK) adder values that must be added to the GCLK values. Use these adder values to determine I/O timing when the I/O pin is driven using the regional clock. This applies to all I/O standards supported by Stratix III devices. Table 1-139 lists the EP3SE260 column pin delay adders when using the regional clock. Table 1-139. EP3SE260 Column Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL = 1.1 V C3 VCCL= 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.233 -0.036 -0.204 1.899 0.311 0.028 -0.237 1.965 0.488 0.059 3.193 0.489 0.06 3.323 0.45 0.113 3.677 0.439 0.11 3.512 0.515 -0.44 3.802 0.416 -0.32 3.346 0.458 0.121 -0.371 3.705 0.439 0.11 -0.405 3.512 0.515 -0.005 -0.44 3.802 ns ns ns ns -0.005 -0.038 -0.334 -0.331 -0.413 -0.405 Table 1-140 lists the EP3SE260 row pin delay adders when using the regional clock in Stratix III devices. Table 1-140. EP3SE260 Row Pin Delay Adders for Regional Clock Fast Model Parameter Industrial Commercial C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL= 1.1 V VCCL= 1.1 V C4L VCCL = 0.9 V I3 VCCL = 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units RCLK input adder RCLK PLL input adder RCLK output adder RCLK PLL output adder 0.244 0.124 -0.256 -0.134 0.293 0.134 -0.289 -0.147 0.438 0.21 0.412 0.215 0.471 0.234 0.427 0.228 0.577 0.297 0.421 0.217 0.452 0.239 0.427 0.228 0.577 0.297 ns ns ns ns -0.418 -0.424 -0.484 -0.438 -0.591 -0.443 -0.464 -0.438 -0.591 -0.228 -0.233 -0.254 -0.261 -0.322 -0.236 -0.262 -0.261 -0.322 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-310 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Dedicated Clock Pin Timing Table 1-141 to Table 1-201 list clock pin timing for Stratix III devices when the clock is driven by the global clock, regional clock, periphery clock, and a PLL. Table 1-141 lists the Stratix III clock timing parameters. Table 1-141. Clock Timing Parameters for Stratix III Devices Symbol tCIN tCOUT tPLLCIN tPLLCOUT Parameter Delay from the clock pad to the I/O input register Delay from the clock pad to the I/O output register Delay from the PLL inclk pad to the I/O input register Delay from the PLL inclk pad to the I/O output register EP3SL50 Clock Timing Parameters Table 1-142 and Table 1-143 list the global clock timing parameters for EP3SL50 devices. Table 1-142. EP3SL50 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.736 1.736 -0.018 -0.018 Commercial 1.737 1.737 -0.026 -0.026 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.436 2.436 -0.261 -0.261 2.691 2.691 -0.312 -0.312 3.056 3.056 -0.251 -0.251 2.925 2.925 -0.230 -0.230 3.433 3.433 -0.011 -0.011 2.691 2.691 -0.312 -0.312 3.056 3.056 0.161 0.161 2.925 2.925 -0.230 -0.230 3.433 3.433 -0.011 -0.011 Table 1-143. EP3SL50 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.732 1.650 0.048 -0.034 Commercial 1.843 1.752 0.116 0.025 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.527 2.385 -0.142 -0.284 2.758 2.595 -0.216 -0.379 3.099 2.918 -0.181 -0.362 2.997 2.826 -0.136 -0.307 3.227 3.068 -0.188 -0.347 2.811 2.641 -0.173 -0.343 3.146 2.957 0.265 0.076 3.055 2.876 -0.087 -0.266 3.260 3.101 -0.230 -0.389 Table 1-144 and Table 1-145 list the regional clock timing parameters for EP3SL50 devices. Table 1-144. EP3SL50 Column Pin Regional Clock Timing Specifications (Part 1 of 2) Fast Model Parameter Industrial tCIN tCOUT 1.689 1.689 Commercial 1.669 1.669 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns 2.371 2.371 2.645 2.645 3.004 3.004 2.719 2.719 3.136 3.136 2.645 2.645 3.009 3.009 2.719 2.719 3.136 3.136 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-311 Table 1-144. EP3SL50 Column Pin Regional Clock Timing Specifications (Part 2 of 2) Fast Model Parameter Industrial tPLLCIN tPLLCOUT -0.019 -0.019 Commercial -0.025 -0.025 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns -0.264 -0.264 -0.315 -0.315 -0.256 -0.256 -0.236 -0.236 -0.017 -0.017 -0.315 -0.315 0.224 0.224 -0.236 -0.236 -0.017 -0.017 Table 1-145. EP3SL50 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.636 1.554 0.018 -0.064 Commercial 1.729 1.638 0.084 -0.007 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.356 2.214 -0.178 -0.320 2.567 2.404 -0.255 -0.418 2.894 2.713 -0.222 -0.403 2.800 2.629 -0.169 -0.340 2.964 2.805 -0.226 -0.385 2.622 2.452 -0.203 -0.373 2.941 2.752 0.298 0.109 2.853 2.674 -0.123 -0.302 2.997 2.838 -0.272 -0.431 Table 1-146 and Table 1-147 list the periphery clock timing parameters for EP3SL50 devices. Table 1-146. EP3SL50 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.468 1.468 -0.081 -0.081 Commercial 1.469 1.469 -0.081 -0.081 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.143 2.143 -0.327 -0.327 2.418 2.418 -0.383 -0.383 2.797 2.797 -0.334 -0.334 2.668 2.668 -0.310 -0.310 3.219 3.219 -0.105 -0.105 2.418 2.418 -0.383 -0.383 2.801 2.801 0.273 0.273 2.668 2.668 -0.310 -0.310 3.219 3.219 -0.105 -0.105 Table 1-147. EP3SL50 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.482 1.400 -0.014 -0.096 Commercial 1.556 1.465 0.042 -0.049 C2 VCCL = 1.1 V C3 VCCL = 1.1V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.223 2.078 -0.222 -0.364 2.488 2.325 -0.299 -0.462 2.859 2.678 -0.278 -0.459 2.740 2.569 -0.224 -0.395 3.034 2.875 -0.295 -0.454 2.539 2.369 -0.256 -0.426 2.897 2.708 0.368 0.179 2.785 2.606 -0.177 -0.356 3.056 2.897 -0.257 -0.416 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-312 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing EP3SL70 Clock Timing Parameters Table 1-148 and Table 1-149 list the global clock timing specifications for EP3SL70 devices. . Table 1-148. EP3SL70 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.749 1.749 -0.012 -0.012 Commercial 1.735 1.735 -0.021 -0.021 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.434 2.434 -0.255 -0.255 2.702 2.702 -0.306 -0.306 3.056 3.056 -0.251 -0.251 2.950 2.950 -0.203 -0.203 3.403 3.403 -0.044 -0.044 2.702 2.702 -0.306 -0.306 3.056 3.056 0.161 0.161 2.950 2.950 -0.203 -0.203 3.403 3.403 -0.044 -0.044 Table 1-149. EP3SL70 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.732 1.650 0.051 -0.031 Commercial 1.840 1.749 0.115 0.024 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.524 2.382 -0.144 -0.286 2.758 2.595 -0.219 -0.382 3.083 2.902 -0.193 -0.374 2.986 2.815 -0.144 -0.315 3.227 3.068 -0.188 -0.347 2.811 2.641 -0.170 -0.340 3.157 2.968 0.275 0.086 3.042 2.863 -0.097 -0.276 3.260 3.101 -0.234 -0.393 Table 1-150 and Table 1-151 list the regional clock timing parameters for EP3SL70 devices. Table 1-150. EP3SL70 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.689 1.689 -0.011 -0.011 Commercial 1.689 1.689 -0.022 -0.022 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.388 2.388 -0.261 -0.261 2.649 2.649 -0.308 -0.308 3.004 3.004 -0.256 -0.256 2.723 2.723 -0.207 -0.207 3.132 3.132 -0.054 -0.054 2.649 2.649 -0.308 -0.308 3.014 3.014 0.224 0.224 2.723 2.723 -0.207 -0.207 3.132 3.132 -0.054 -0.054 Table 1-151. EP3SL70 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.637 1.555 0.018 -0.064 Commercial 1.726 1.635 0.085 -0.006 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.353 2.211 -0.176 -0.318 2.566 2.403 -0.252 -0.415 2.885 2.704 -0.230 -0.411 2.786 2.615 -0.180 -0.351 2.964 2.805 -0.226 -0.385 2.625 2.455 -0.203 -0.373 2.948 2.759 0.307 0.118 2.839 2.660 -0.139 -0.318 3.001 2.842 -0.272 -0.431 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-313 Table 1-152 and Table 1-153 list the periphery clock timing parameters for EP3SL70 devices. Table 1-152. EP3SL70 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.465 1.465 -0.068 -0.068 Commercial 1.468 1.468 -0.083 -0.083 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.142 2.142 -0.330 -0.330 2.410 2.410 -0.370 -0.370 2.792 2.792 -0.334 -0.334 2.673 2.673 -0.288 -0.288 3.220 3.220 -0.133 -0.133 2.410 2.410 -0.370 -0.370 2.802 2.802 0.273 0.273 2.673 2.673 -0.288 -0.288 3.220 3.220 -0.133 -0.133 Table 1-153. EP3SL70 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.482 1.400 -0.019 -0.101 Commercial 1.558 1.467 0.039 -0.052 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.227 2.082 -0.225 -0.367 2.488 2.325 -0.302 -0.465 2.851 2.670 -0.291 -0.472 2.727 2.556 -0.235 -0.406 3.031 2.872 -0.295 -0.454 2.539 2.369 -0.261 -0.431 2.905 2.716 0.376 0.187 2.777 2.598 -0.188 -0.367 3.056 2.897 -0.257 -0.416 EP3SL110 Clock Timing Parameters Table 1-154 and Table 1-155 list the global clock timing parameters for EP3SL110 devices. . Table 1-154. EP3SL110 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.909 1.909 -0.048 -0.048 Commercial 1.907 1.907 -0.050 -0.050 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.674 2.674 -0.274 -0.274 2.936 2.936 -0.330 -0.330 3.285 3.285 -0.290 -0.290 3.182 3.182 -0.251 -0.251 3.700 3.700 -0.032 -0.032 2.936 2.936 -0.330 -0.330 3.285 3.285 -0.290 -0.290 3.182 3.182 -0.251 -0.251 3.700 3.700 -0.032 -0.032 Table 1-155. EP3SL110 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.882 1.800 -0.002 -0.084 Commercial 2.014 1.923 0.059 -0.032 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Unit ns ns ns ns 2.754 2.612 -0.202 -0.347 2.975 2.812 -0.271 -0.434 3.344 3.163 -0.231 -0.412 3.221 3.050 -0.184 -0.355 3.511 3.352 -0.212 -0.371 3.062 2.892 -0.219 -0.389 3.413 3.224 -0.184 -0.373 3.287 3.108 -0.138 -0.317 3.551 3.392 -0.260 -0.419 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-314 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-156 and Table 1-157 list the regional clock timing parameters for EP3SL110 devices. Table 1-156. EP3SL110 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.689 1.689 -0.036 -0.036 Commercial 1.687 1.687 -0.038 -0.038 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.360 2.360 -0.262 -0.262 2.600 2.600 -0.317 -0.317 2.924 2.924 -0.278 -0.278 2.836 2.836 -0.239 -0.239 3.241 3.241 -0.020 -0.020 2.600 2.600 -0.317 -0.317 2.924 2.924 -0.278 -0.278 2.836 2.836 -0.239 -0.239 3.241 3.241 -0.020 -0.020 Table 1-157. EP3SL110 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.684 1.602 0.008 -0.074 Commercial 1.792 1.701 0.071 -0.020 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.440 2.298 -0.189 -0.334 2.644 2.481 -0.276 -0.439 2.985 2.804 -0.218 -0.399 2.879 2.708 -0.188 -0.359 3.044 2.885 -0.214 -0.373 2.720 2.550 -0.209 -0.379 3.044 2.855 -0.174 -0.363 2.938 2.759 -0.141 -0.320 3.083 2.924 -0.263 -0.422 Table 1-158 and Table 1-159 list the periphery clock timing parameters for EP3SL110 devices. . Table 1-158. EP3SL110 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.541 1.541 -0.029 -0.029 Commercial 1.538 1.538 -0.031 -0.031 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.257 2.257 -0.253 -0.253 2.539 2.539 -0.310 -0.310 2.931 2.931 -0.276 -0.276 2.810 2.810 -0.222 -0.222 3.345 3.345 -0.020 -0.020 2.539 2.539 -0.310 -0.310 2.931 2.931 -0.276 -0.276 2.810 2.810 -0.222 -0.222 3.345 3.345 -0.020 -0.020 Table 1-159. EP3SL110 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.430 1.348 0.015 -0.067 Commercial 1.503 1.412 0.072 -0.019 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.156 2.011 -0.188 -0.333 2.416 2.253 -0.267 -0.430 2.783 2.602 -0.219 -0.400 2.665 2.494 -0.180 -0.351 2.926 2.767 -0.214 -0.373 2.465 2.295 -0.206 -0.376 2.828 2.639 -0.170 -0.359 2.711 2.532 -0.133 -0.312 2.951 2.792 -0.263 -0.422 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-315 EP3SL150 Clock Timing Parameters Table 1-160 and Table 1-161 list the global clock timing parameters for EP3SL150 devices. Table 1-160. EP3SL150 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.898 1.898 -0.054 -0.054 Commercial 1.926 1.926 -0.028 -0.028 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Unit ns ns ns ns 2.692 2.692 -0.252 -0.252 2.920 2.920 -0.342 -0.342 3.294 3.294 -0.296 -0.296 3.170 3.170 -0.239 -0.239 3.719 3.719 -0.018 -0.018 2.920 2.920 -0.342 -0.342 3.294 3.294 -0.296 -0.296 3.170 3.170 -0.239 -0.239 3.719 3.719 -0.018 -0.018 Table 1-161. EP3SL150 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.868 1.786 0.007 -0.075 Commercial 2.010 1.919 0.059 -0.032 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.750 2.608 -0.202 -0.347 2.982 2.819 -0.255 -0.418 3.347 3.166 -0.231 -0.412 3.224 3.053 -0.184 -0.355 3.506 3.347 -0.214 -0.373 3.048 2.878 -0.210 -0.380 3.400 3.211 -0.173 -0.362 3.293 3.114 -0.122 -0.301 3.549 3.390 -0.249 -0.408 Table 1-162 and Table 1-163 list the regional clock timing parameters for EP3SL150 devices. Table 1-162. EP3SL150 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.683 1.683 -0.043 -0.043 Commercial 1.701 1.701 -0.016 -0.016 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.375 2.375 -0.240 -0.240 2.595 2.595 -0.329 -0.329 2.936 2.936 -0.284 -0.284 2.833 2.833 -0.227 -0.227 3.255 3.255 -0.005 -0.005 2.595 2.595 -0.329 -0.329 2.936 2.936 -0.284 -0.284 2.833 2.833 -0.227 -0.227 3.255 3.255 -0.005 -0.005 Table 1-163. EP3SL150 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.683 1.601 -0.007 -0.089 Commercial 1.793 1.702 0.068 -0.023 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.441 2.299 -0.192 -0.337 2.659 2.496 -0.269 -0.432 2.987 2.806 -0.221 -0.402 2.875 2.704 -0.188 -0.359 3.042 2.883 -0.211 -0.370 2.719 2.549 -0.226 -0.396 3.047 2.858 -0.186 -0.375 2.951 2.772 -0.135 -0.314 3.096 2.937 -0.260 -0.419 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-316 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-164 and Table 1-165 list the periphery clock timing parameters for EP3SL150 devices. Table 1-164. EP3SL150 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.537 1.537 -0.040 -0.040 Commercial 1.550 1.550 -0.012 -0.012 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.268 2.268 -0.235 -0.235 2.535 2.535 -0.326 -0.326 2.929 2.929 -0.267 -0.267 2.812 2.812 -0.234 -0.234 3.354 3.354 0.002 0.002 2.535 2.535 -0.326 -0.326 2.929 2.929 -0.267 -0.267 2.812 2.812 -0.234 -0.234 3.354 3.354 0.002 0.002 Table 1-165. EP3SL150 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.438 1.356 0.002 -0.080 Commercial 1.505 1.414 0.076 -0.015 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.159 2.014 -0.183 -0.328 2.429 2.266 -0.266 -0.429 2.783 2.602 -0.217 -0.398 2.657 2.486 -0.185 -0.356 2.934 2.775 -0.206 -0.365 2.475 2.305 -0.220 -0.390 2.838 2.649 -0.182 -0.371 2.725 2.546 -0.132 -0.311 2.972 2.813 -0.260 -0.419 EP3SL200 Clock Timing Parameters Table 1-166 and Table 1-167 list the global clock timing parameters for EP3SL200 devices. Table 1-166. EP3SL200 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.237 2.237 0.032 0.032 Commercial 2.264 2.264 0.060 0.060 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Unit ns ns ns ns 3.331 3.331 -0.177 -0.177 3.416 3.416 -0.219 -0.219 3.842 3.842 -0.137 -0.137 3.686 3.686 -0.122 -0.122 4.345 4.345 0.088 0.088 3.416 3.416 -0.219 -0.219 3.834 3.834 0.287 0.287 3.686 3.686 -0.122 -0.122 4.345 4.345 0.088 0.088 Table 1-167. EP3SL200 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.208 2.126 0.102 0.020 Commercial 2.371 2.280 0.174 0.083 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.453 3.301 -0.085 -0.237 3.526 3.366 -0.115 -0.278 3.900 3.719 -0.076 -0.257 3.747 3.576 -0.043 -0.214 4.190 4.031 -0.063 -0.222 3.601 3.433 -0.067 -0.237 3.977 3.788 0.409 0.220 3.747 3.576 -0.043 -0.214 4.190 4.031 -0.063 -0.222 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-317 Table 1-168 and Table 1-169 list the regional clock timing parameters for EP3SL200. Table 1-168. EP3SL200 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.006 2.006 0.059 0.059 Commercial 2.035 2.035 0.086 0.086 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.020 3.020 -0.150 -0.150 3.113 3.113 -0.191 -0.191 3.494 3.494 -0.109 -0.109 3.213 3.213 -0.094 -0.094 3.743 3.743 0.116 0.116 3.113 3.113 -0.191 -0.191 3.531 3.531 0.291 0.291 3.213 3.213 -0.094 -0.094 3.743 3.743 0.116 0.116 Table 1-169. EP3SL200 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.937 1.855 0.126 0.044 Commercial 2.065 1.974 0.197 0.106 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.000 2.848 -0.059 -0.211 3.070 2.910 -0.091 -0.254 3.414 3.233 -0.051 -0.232 3.275 3.104 -0.036 -0.207 3.597 3.438 -0.041 -0.200 3.139 2.971 -0.043 -0.213 3.479 3.290 0.410 0.221 3.275 3.104 -0.036 -0.207 3.597 3.438 -0.041 -0.200 Table 1-170 and Table 1-171 list the periphery clock timing parameters for EP3SL200 devices. Table 1-170. EP3SL200 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.720 1.720 0.037 0.037 Commercial 1.712 1.712 0.064 0.064 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.615 2.615 -0.173 -0.173 2.776 2.776 -0.213 -0.213 3.177 3.177 -0.135 -0.135 3.044 3.044 -0.118 -0.118 3.660 3.660 0.090 0.090 2.776 2.776 -0.213 -0.213 3.177 3.177 0.292 0.292 3.044 3.044 -0.118 -0.118 3.660 3.660 0.090 0.090 Table 1-171. EP3SL200 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.501 1.419 0.105 0.023 Commercial 1.575 1.484 0.174 0.083 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.380 2.225 -0.081 -0.233 2.518 2.355 -0.118 -0.281 2.892 2.711 -0.077 -0.258 2.761 2.590 -0.061 -0.232 3.077 2.918 -0.063 -0.222 2.567 2.397 -0.067 -0.237 2.938 2.749 0.411 0.222 2.761 2.590 -0.061 -0.232 3.077 2.918 -0.063 -0.222 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-318 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing EP3SL340 Clock Timing Parameters Table 1-172 and Table 1-173 list the global clock timing parameters for EP3S340 devices. Table 1-172. EP3SL340 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.357 2.357 0.091 0.091 Commercial 2.331 2.331 0.058 0.058 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.440 3.440 -0.165 -0.165 3.566 3.566 -0.152 -0.152 3.938 3.938 -0.140 -0.140 3.807 3.807 -0.096 -0.096 4.482 4.482 0.111 0.111 3.566 3.566 -0.152 -0.152 3.938 3.938 -0.140 -0.140 3.807 3.807 -0.096 -0.096 4.482 4.482 0.111 0.111 Table 1-173. EP3SL340 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.293 2.211 0.121 0.039 Commercial 2.479 2.388 0.210 0.119 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.608 3.456 -0.034 -0.186 3.630 3.470 -0.098 -0.261 4.020 3.839 -0.045 -0.226 3.880 3.709 -0.001 -0.172 4.324 4.165 -0.042 -0.201 3.746 3.578 -0.031 -0.201 4.099 3.910 0.005 -0.184 3.977 3.798 0.051 -0.128 4.369 4.210 -0.083 -0.242 Table 1-174 and Table 1-175 list the regional clock timing parameters for EP3SL340 devices. Table 1-174. EP3SL340 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.031 2.031 0.127 0.127 Commercial 2.013 2.013 0.094 0.094 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.958 2.958 -0.128 -0.128 3.073 3.073 -0.116 -0.116 3.435 3.435 -0.104 -0.104 3.308 3.308 -0.061 -0.061 3.803 3.803 0.148 0.148 3.073 3.073 -0.116 -0.116 3.435 3.435 -0.104 -0.104 3.308 3.308 -0.061 -0.061 3.803 3.803 0.148 0.148 Table 1-175. EP3SL340 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.998 1.916 0.157 0.075 Commercial 2.161 2.070 0.248 0.157 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.129 2.977 0.006 -0.146 3.149 2.989 -0.069 -0.232 3.501 3.320 -0.009 -0.190 3.376 3.205 0.017 -0.154 3.648 3.492 -0.011 -0.170 3.242 3.074 0.003 -0.167 3.570 3.381 0.039 -0.150 3.463 3.284 0.093 -0.086 3.707 3.551 -0.057 -0.216 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-319 Table 1-176 and Table 1-177 list the periphery clock timing parameters for EP3SL340 devices. Table 1-176. EP3SL340 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.778 1.778 0.086 0.086 Commercial 1.760 1.760 0.061 0.061 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.687 2.687 -0.164 -0.164 2.847 2.847 -0.161 -0.161 3.240 3.240 -0.140 -0.140 3.099 3.099 -0.097 -0.097 3.718 3.718 0.101 0.101 2.847 2.847 -0.161 -0.161 3.240 3.240 -0.140 -0.140 3.099 3.099 -0.097 -0.097 3.718 3.718 0.101 0.101 Table 1-177. EP3SL340 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.524 1.442 0.116 0.034 Commercial 1.616 1.525 0.211 0.120 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.435 2.280 -0.039 -0.191 2.567 2.404 -0.116 -0.279 2.958 2.777 -0.055 -0.236 2.823 2.652 -0.030 -0.201 3.141 2.982 -0.051 -0.210 2.605 2.435 -0.040 -0.210 3.002 2.813 -0.006 -0.195 2.861 2.682 0.050 -0.129 3.165 3.006 -0.098 -0.257 EP3SE50 Clock Timing Parameters Table 1-178 and Table 1-179 list the global clock timing parameters for EP3SE50 devices. Table 1-178. EP3SE50 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.786 1.786 0.023 0.083 Commercial 1.789 1.789 0.027 0.103 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.495 2.495 -0.204 -0.068 2.748 2.748 -0.268 -0.131 3.111 3.111 -0.226 -0.226 2.993 2.993 -0.180 -0.010 3.489 3.489 0.025 0.025 2.748 2.748 -0.268 -0.131 3.105 3.105 0.249 0.249 2.993 2.993 -0.180 -0.010 3.489 3.489 0.025 0.025 Table 1-179. EP3SE50 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.739 1.657 0.044 -0.038 Commercial 1.849 1.758 0.117 0.026 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.536 2.394 -0.143 -0.285 2.769 2.606 -0.220 -0.383 3.112 2.931 -0.183 -0.364 3.010 2.839 -0.135 -0.306 3.250 3.091 -0.189 -0.348 2.830 2.660 -0.171 -0.341 3.171 2.982 0.345 0.156 3.069 2.890 -0.088 -0.267 3.276 3.117 -0.242 -0.401 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-320 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-180 and Table 1-181 list the regional clock timing parameters for EP3SE50 devices. Table 1-180. EP3SE50 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.711 1.711 0.034 0.106 Commercial 1.721 1.721 0.038 0.102 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.429 2.429 -0.193 -0.074 2.679 2.679 -0.255 -0.101 3.053 3.053 -0.212 -0.212 2.767 2.767 -0.168 -0.168 3.191 3.191 0.040 0.040 2.679 2.679 -0.255 -0.101 3.053 3.053 0.263 0.263 2.767 2.767 -0.168 -0.168 3.191 3.191 0.040 0.040 Table 1-181. EP3SE50 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.640 1.558 0.020 -0.062 Commercial 1.732 1.641 0.091 0.000 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.361 2.219 -0.168 -0.310 2.580 2.417 -0.241 -0.404 2.905 2.724 -0.208 -0.389 2.810 2.639 -0.155 -0.326 2.977 2.818 -0.210 -0.369 2.636 2.466 -0.191 -0.361 2.960 2.771 0.321 0.132 2.868 2.689 -0.108 -0.287 3.003 2.844 -0.264 -0.423 Table 1-182 and Table 1-183 list the periphery clock timing parameters for EP3SE50 devices. Table 1-182. EP3SE50 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.472 1.472 -0.047 -0.047 Commercial 1.481 1.481 -0.044 -0.044 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.155 2.155 -0.288 -0.288 2.417 2.417 -0.347 -0.347 2.825 2.825 -0.302 -0.302 2.681 2.681 -0.266 -0.266 3.247 3.247 -0.079 -0.079 2.417 2.417 -0.347 -0.347 2.819 2.819 0.300 0.300 2.681 2.681 -0.266 -0.266 3.247 3.247 -0.079 -0.079 Table 1-183. EP3SE50 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.467 1.385 -0.021 -0.103 Commercial 1.543 1.452 0.036 -0.055 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.208 2.063 -0.231 -0.373 2.472 2.309 -0.307 -0.470 2.843 2.662 -0.282 -0.463 2.729 2.558 -0.230 -0.401 3.012 2.853 -0.301 -0.460 2.521 2.351 -0.262 -0.432 2.891 2.702 0.372 0.183 2.771 2.592 -0.184 -0.363 3.028 2.869 -0.361 -0.520 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-321 EP3SE80 Clock Timing Parameters Table 1-184 and Table 1-185 list the global clock timing parameters for EP3SE80 devices. Table 1-184. EP3SE80 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.037 2.037 -0.024 -0.024 Commercial 2.059 2.059 -0.007 -0.007 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.879 2.879 -0.235 -0.235 3.127 3.127 -0.315 -0.315 3.524 3.524 -0.292 -0.292 3.430 3.430 -0.199 -0.199 3.989 3.989 -0.042 -0.042 3.127 3.127 -0.315 -0.315 3.524 3.524 -0.292 -0.292 3.430 3.430 -0.199 -0.199 3.989 3.989 -0.042 -0.042 Table 1-185. EP3SE80 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.994 1.912 0.020 -0.062 Commercial 2.143 2.052 0.086 -0.005 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.942 2.800 -0.177 -0.319 3.188 3.025 -0.249 -0.412 3.552 3.371 -0.221 -0.402 3.446 3.275 -0.171 -0.342 3.769 3.610 -0.221 -0.380 3.258 3.089 -0.199 -0.369 3.633 3.444 -0.173 -0.362 3.515 3.336 -0.121 -0.300 3.813 3.654 -0.266 -0.425 Table 1-186 and Table 1-187 list the regional clock timing parameters for EP3SE80 devices. Table 1-186. EP3SE80 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.828 1.828 -0.013 -0.013 Commercial 1.849 1.849 0.004 0.004 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.578 2.578 -0.224 -0.224 2.811 2.811 -0.303 -0.303 3.171 3.171 -0.280 -0.280 3.087 3.087 -0.187 -0.187 3.547 3.547 -0.030 -0.030 2.811 2.811 -0.303 -0.303 3.171 3.171 -0.280 -0.280 3.087 3.087 -0.187 -0.187 3.547 3.547 -0.030 -0.030 Table 1-187. EP3SE80 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.812 1.730 0.010 -0.072 Commercial 1.928 1.837 0.087 -0.004 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.638 2.496 -0.176 -0.318 2.874 2.711 -0.259 -0.422 3.205 3.024 -0.231 -0.412 3.107 2.936 -0.167 -0.338 3.332 3.173 -0.229 -0.388 2.938 2.768 -0.210 -0.380 3.277 3.088 -0.169 -0.358 3.169 2.990 -0.118 -0.297 3.373 3.214 -0.275 -0.434 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-322 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Table 1-188 and Table 1-189 list the periphery clock timing parameters for EP3SE80 devices. Table 1-188. EP3SE80 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.564 1.564 -0.028 -0.028 Commercial 1.585 1.584 -0.006 -0.006 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.309 2.308 -0.234 -0.234 2.566 2.566 -0.327 -0.327 2.962 2.962 -0.270 -0.270 2.838 2.844 -0.193 -0.193 3.377 3.377 -0.018 -0.018 2.566 2.566 -0.327 -0.327 2.962 2.962 -0.270 -0.270 2.838 2.844 -0.193 -0.193 3.377 3.377 -0.018 -0.018 Table 1-189. EP3SE80 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.441 1.359 0.004 -0.078 Commercial 1.503 1.412 0.077 -0.014 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.156 2.011 -0.186 -0.328 2.429 2.266 -0.268 -0.431 2.776 2.595 -0.243 -0.424 2.665 2.494 -0.177 -0.348 2.934 2.775 -0.238 -0.397 2.477 2.307 -0.219 -0.389 2.828 2.639 -0.177 -0.366 2.711 2.532 -0.128 -0.307 2.959 2.800 -0.287 -0.446 EP3SE110 Clock Timing Parameters Table 1-190 and Table 1-191 list the global clock timing parameters for EP3SE110 devices. Table 1-190. EP3SE110 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.046 2.046 -0.020 -0.020 Commercial 2.046 2.046 -0.034 -0.034 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.868 2.868 -0.265 -0.265 3.144 3.144 -0.311 -0.311 3.524 3.524 -0.267 -0.267 3.429 3.429 -0.198 -0.198 3.989 3.989 -0.034 -0.034 3.144 3.144 -0.311 -0.311 3.524 3.524 -0.267 -0.267 3.429 3.429 -0.198 -0.198 3.989 3.989 -0.034 -0.034 Table 1-191. EP3SE110 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.985 1.903 0.012 -0.070 Commercial 2.130 2.039 0.084 -0.007 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.928 2.786 -0.180 -0.322 3.183 3.020 -0.253 -0.416 3.546 3.365 -0.223 -0.404 3.437 3.266 -0.173 -0.344 3.772 3.613 -0.223 -0.382 3.250 3.082 -0.207 -0.377 3.615 3.426 -0.173 -0.362 3.507 3.328 -0.123 -0.302 3.815 3.656 -0.267 -0.426 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-323 Table 1-192 and Table 1-193 list the regional clock timing parameters for EP3SE110 devices. Table 1-192. EP3SE110 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.828 1.828 -0.008 -0.008 Commercial 1.849 1.849 -0.022 -0.022 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.578 2.578 -0.254 -0.254 2.811 2.811 -0.299 -0.299 3.155 3.155 -0.255 -0.255 3.082 3.082 -0.186 -0.186 3.560 3.560 -0.021 -0.021 2.811 2.811 -0.299 -0.299 3.155 3.155 -0.255 -0.255 3.082 3.082 -0.186 -0.186 3.560 3.560 -0.021 -0.021 Table 1-193. EP3SE110 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.798 1.716 0.001 -0.081 Commercial 1.924 1.833 0.076 -0.015 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.631 2.489 -0.188 -0.330 2.860 2.697 -0.262 -0.425 3.204 3.023 -0.231 -0.412 3.101 2.930 -0.184 -0.355 3.332 3.173 -0.229 -0.388 2.920 2.750 -0.218 -0.388 3.268 3.079 -0.180 -0.369 3.163 2.984 -0.134 -0.313 3.373 3.214 -0.277 -0.436 Table 1-194 and Table 1-195 list the periphery clock timing parameters for EP3SE110 devices. Table 1-194. EP3SE110 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.564 1.564 -0.019 -0.019 Commercial 1.585 1.584 -0.019 -0.019 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.309 2.308 -0.245 -0.245 2.566 2.566 -0.310 -0.310 2.951 2.951 -0.267 -0.267 2.843 2.843 -0.194 -0.194 3.398 3.398 -0.018 -0.018 2.566 2.566 -0.310 -0.310 2.951 2.951 -0.267 -0.267 2.843 2.843 -0.194 -0.194 3.398 3.398 -0.018 -0.018 Table 1-195. EP3SE110 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.423 1.341 0.001 -0.081 Commercial 1.502 1.411 0.069 -0.022 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.156 2.011 -0.195 -0.337 2.411 2.248 -0.271 -0.434 2.781 2.600 -0.241 -0.422 2.659 2.488 -0.188 -0.359 2.934 2.775 -0.238 -0.397 2.455 2.285 -0.222 -0.392 2.826 2.637 -0.190 -0.379 2.704 2.525 -0.139 -0.318 2.949 2.790 -0.288 -0.447 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-324 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing EP3SE260 Clock Timing Parameters Table 1-196 and Table 1-197 list the global clock timing parameters for EP3SE260 devices. Table 1-196. EP3SE260 Column Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.237 2.237 0.040 0.040 Commercial 2.237 2.237 0.040 0.040 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.302 3.302 -0.199 -0.199 3.416 3.416 -0.211 -0.211 3.837 3.837 -0.135 -0.135 3.683 3.683 -0.127 -0.127 4.331 4.331 0.074 0.074 3.416 3.416 -0.211 -0.211 3.837 3.837 0.296 0.296 3.683 3.683 -0.127 -0.127 4.331 4.331 0.074 0.074 Table 1-197. EP3SE260 Row Pin Global Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 2.171 2.089 0.091 0.009 Commercial 2.374 2.283 0.172 0.081 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.458 3.306 -0.087 -0.239 3.526 3.366 -0.116 -0.279 3.868 3.687 -0.085 -0.266 3.768 3.597 -0.031 -0.202 4.184 4.025 -0.071 -0.230 3.564 3.396 -0.077 -0.247 3.943 3.754 0.399 0.210 3.768 3.597 -0.031 -0.202 4.184 4.025 -0.071 -0.230 Table 1-198 and Table 1-199 list the regional clock timing parameters for EP3SE260 devices. Table 1-198. EP3SE260 Column Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.930 1.930 0.061 0.061 Commercial 2.003 2.003 0.066 0.066 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.983 2.983 -0.172 -0.172 2.955 2.955 -0.191 -0.191 3.531 3.531 -0.109 -0.109 3.209 3.209 -0.091 -0.091 3.736 3.736 0.102 0.102 2.955 2.955 -0.191 -0.191 3.531 3.531 0.302 0.302 3.209 3.209 -0.091 -0.091 3.736 3.736 0.102 0.102 Table 1-199. EP3SE260 Row Pin Regional Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.903 1.821 0.088 0.006 Commercial 2.065 1.974 0.199 0.108 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 3.000 2.848 -0.056 -0.208 3.070 2.910 -0.091 -0.254 3.388 3.207 -0.081 -0.262 3.294 3.123 -0.009 -0.180 3.593 3.434 -0.049 -0.208 3.103 2.935 -0.078 -0.248 3.457 3.268 0.379 0.190 3.294 3.123 -0.009 -0.180 3.593 3.434 -0.049 -0.208 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing 1-325 Table 1-200 and Table 1-201 list the periphery clock timing parameters for EP3SE260 devices. Table 1-200. EP3SE260 Column Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.709 1.709 0.037 0.037 Commercial 1.716 1.716 0.037 0.037 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.620 2.620 -0.202 -0.202 2.765 2.765 -0.213 -0.213 3.177 3.177 -0.140 -0.140 3.039 3.039 -0.119 -0.119 3.668 3.668 0.075 0.075 2.765 2.765 -0.213 -0.213 3.177 3.177 0.293 0.293 3.039 3.039 -0.119 -0.119 3.668 3.668 0.075 0.075 Table 1-201. EP3SE260 Row Pin Periphery Clock Timing Specifications Fast Model Parameter Industrial tCIN tCOUT tPLLCIN tPLLCOUT 1.495 1.413 0.065 -0.017 Commercial 1.574 1.483 0.172 0.081 C2 VCCL = 1.1 V C3 VCCL = 1.1 V C4 VCCL = 1.1 V VCCL= 1.1 V C4L VCCL= 0.9 V I3 VCCL= 1.1 V I4 VCCL= 1.1 V VCCL= 1.1 V I4L VCCL= 0.9 V Units ns ns ns ns 2.378 2.223 -0.084 -0.236 2.518 2.355 -0.118 -0.281 2.878 2.697 -0.103 -0.284 2.776 2.605 -0.033 -0.204 3.072 2.913 -0.071 -0.230 2.555 2.385 -0.103 -0.273 2.926 2.737 0.384 0.195 2.776 2.605 -0.033 -0.204 3.072 2.913 -0.071 -0.230 (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-326 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Glossary Glossary The following table lists the glossary for this chapter. Table 1. Glossary Table (Part 1 of 4) Letter A B C D Subject Definitions -- -- -- Receiver Input Waveforms Single-Ended Waveform -- -- -- Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Differential I/O Standards Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD E F -- fH S C L K fH S D R fH S D R D P A -- High-Speed I/O Block: High-speed receiver/transmitter input and output clock frequency. High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (fH S D R = 1/TUI), non-DPA. High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (fH S D R D P A = 1/TUI), DPA. -- -- -- G H I -- -- -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Glossary 1-327 Table 1. Glossary Table (Part 2 of 4) Letter J Subject Definitions J High-Speed I/O Block: Deserialization factor (width of parallel data bus). JTAG Timing Specifications are in the following figure: TMS TDI JTAG Timing Specifications TCK tJCP tJCH tJCL t JPSU tJPH tJPZX tJPCO tJPXZ TDO K L M N O P -- -- -- -- -- Diagram of PLL Specifications (1) -- -- -- -- -- The block diagram shown in the following figure highlights the PLL Specification parameters: CLKOUT Pins Switchover fOUT_EXT CLK fIN N fINPFD PFD CP LF VCO fVCO PLL Specifications Core Clock Counters C0..C9 fOUT GCLK RCLK M Key Reconfigurable in User Mode External Feedback Note: (1) CoreClock can only be fed by dedicated clock input pins or PLL outputs. Q R -- RL -- Receiver differential input discrete resistor (external to Stratix III device). (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-328 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Glossary Table 1. Glossary Table (Part 3 of 4) Letter S Subject Definitions The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window (the following figure): SW (sampling window) Timing Diagram Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing (The following figure): Single-ended Voltage Referenced I/O Standard Single-Ended Voltage Referenced I/O Standard VCCIO VOH VIH (AC ) VIH(DC) VREF VIL(DC) VIL(AC ) VOL VSS T tC High-Speed receiver/transmitter input and output clock period. The timing difference between the fastest and slowest output edges, including tco variation TCCS (channeland clock skew, across channels driven by the same PLL. The clock is included in the TCCS to-channel-skew) measurement (refer to the Timing Diagram figure under S in this table) High-Speed I/O Block: Duty cycle on high-speed transmitter output clock. tD U T Y Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) Signal high-to-low transition time (80-20%) Cycle-to-cycle jitter tolerance on PLL clock input Period jitter on general purpose I/O driven by a PLL Period jitter on dedicated clock output driven by a PLL Signal low-to-high transition time (20-80%) -- tF A L L tIN C C J tO U T P J _ I O tO U T P J _ D C tR I S E U -- Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Glossary 1-329 Table 1. Glossary Table (Part 4 of 4) Letter V Subject Definitions VC M ( D C ) VI C M VI D VD I F ( A C ) VD I F ( D C ) VI H VI H ( A C ) VI H ( D C ) VI L VI L ( A C ) VI L ( D C ) VO C M VO D DC Common Mode Input Voltage. Input Common Mode Voltage: The common mode of the differential signal at the receiver. Input Differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. AC Differential Input Voltage: Minimum AC input differential voltage required for switching. DC Differential Input Voltage: Minimum DC input differential voltage required for switching. Voltage Input High: The minimum positive voltage applied to the input that is accepted by the device as a logic high. High-level AC input voltage High-level DC input voltage Voltage Input Low: The maximum positive voltage applied to the input that is accepted by the device as a logic low. Low-level AC input voltage Low-level DC input voltage Output Common Mode Voltage: The common mode of the differential signal at the transmitter. Output differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. High-Speed I/O Block: Clock Boost Factor -- -- -- W X Y Z W -- -- -- (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1-330 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Chapter Revision History Chapter Revision History Table 1-202 lists the revision history for this chapter. Table 1-202. Chapter Revision History (Part 1 of 2) Date July 2010 Version 2.3 Changes Made Updated Table 1-11, Table 1-20, Table 1-25, and Table 1-33. Updated for the Quartus II software version 9.1 SP2 release: March 2010 2.2 Updated Table 1-7, Table 1-8, Table 1-11, Table 1-19, Table 1-23, Table 1-25, Table 1-28, Table 1-29, and Table 1-33. Updated the "Sinusoidal Maximum Allowed Overshoot/Undershoot Voltage" and "External Memory Interface Specifications" sections. Minor text edits. Updated Table 1-1, Table 1-7, Table 1-9, Table 1-18, Table 1-21, Table 1-22, Table 1-23, Table 1-25, Table 1-26, Table 1-28, Table 1-29, Table 1-30, Table 1-33, Table 1-35, Table 1-41, Table 1-43, Table 1-51, Table 1-53, Table 1-61, Table 1-63, Table 1-71, Table 1-73, Table 1-81, Table 1-83, Table 1-91, Table 1-93, Table 1-101, Table 1-103, Table 1-111, Table 1-113, Table 1-121, Table 1-123, Table 1-131, and Table 1-133. Updated Equation 1-1. Updated "Programmable IOE Delay", "PLL Specifications", "DSP Block Specifications", "TriMatrix Memory Block Specifications", "External Memory Interface Specifications", and "High-Speed I/O Specifications" sections. Updated all Timing Information Tables in "User I/O Pin Timing" and "Dedicated Clock Pin Timing" sections. Removed "Referenced Documents" and "Maximum Input and Output Toggle Rate" sections. Updated "Operating Conditions". Added "Bus Hold Specifications". Updated Table 1-3, Table 1-6, Table 1-7, Table 1-11, and Table 1-14. Updated Table 1-17 to Table 1-25. Updated Table 1-39 to Table 1-47. Updated Table 1-50 to Table 1-210. Added (Note 3) to Table 1-11. Added (Note 1) to Table 1-14. Added (Note 6) to Table 1-17. Added (Note 1) to Table 1-47. Added Table 1-26. Added Figure 1-2. July 2009 2.1 Minor text edits. May 2009 2.0 February 2009 1.9 October 2008 1.8 Stratix III Device Handbook, Volume 2 (c) July 2010 Altera Corporation Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Chapter Revision History 1-331 Table 1-202. Chapter Revision History (Part 2 of 2) Date Version Changes Made Updated "Operating Conditions" introduction section. Updated Table 1-3, Table 1-7, Table 1-8, Table 1-19, Table 1-21, Table 1-22, Table 1-25, Table 1-26,Table 1-28, Table 1-29, Table 1-30, Table 1-31, Table 1-32, Table 1-33, Table 1-35, and Table 1-48. Updated "PLL Specifications" introduction section. Updated "I/O Timing Measurement Methodology" section. Updated Figure 1-5, Figure 1-6, and Figure 1-7. Updated all tables for timing section. Added "Internal Weak Pull-Up Resistor" section. Removed "Stratix III Temperature Sensing Diode Specifications" section. Added Figure 1-6 and Figure 1-7. Added derating factors Table 1-45 and Table 1-46. Updated Table 1-90 to Table 1-109. Updated Table 1-140 to Table 1-149. Updated Table 1-175 to Table 1-180. Updated Table 1-181 to Table 1-186. Updated Table 1-205 to Table 1-210. Updated I/O Timing Added new device packages for EP3SL50, EP3SL110, EP3SE80. July 2008 1.7 May 2008 1.6 November 2007 1.5 October 2007 May 2007 May 2007 March 2007 November 2006 1.4 1.3 1.2 1.1 1.0 Added new contact information table to the About this Handbook section. Updated Table 1-44 through Table 1-205. Added I/O Timing section. Initial Release. (c) July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 |
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