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| APPENDIX D APPLICATION NOTE PROGRAMMING FLASH MEMORY OF THE ST10F166 by S. Fruhauf, G. Petrosino INTRODUCTION The ST10F166 high end microcontroller with onchip Flash Memory fulfills the requirements of applications requiring an update to a part or all the program code. The block erase capability is also of use during the application development stage or for program updating. For data acquisition, the ST10F166 allows the programming of 16 or 32 bits data independently. Operations on the Flash memory are under software control. Erasure or programming is a simple procedure, however precautions must be taken to prevent damage to the ST10F166. Figure 1. SGS-THOMSON Flash Cell VS Eprom Cell This application note describes the basic characteristics of the Flash memory cell, and the different algorithms used for erasure and programming. FUNDAMENTALS OF FLASH MEMORY The Flash memory included in the ST10F166 combines the EPROM programming mechanism with electrical erasability (like EEPROM) to create a highly reliable and cost effective memory. A Flash memory cell consists of a single transistor with a floating gate for charge storage like EPROM, the main difference being that Flash memory uses a thinner gate oxide. CONTROL GATE FLOATING GATE N+ SOURCE FLASH CELL N+ DRAIN SOURCE N+ N+ DRAIN EPROM CELL PROGRAMMATION: HOT e INJECTION ERASURE: THROUGH TUNNEL OXIDE F N MECHANISM BULK ERASURE OF ENTIRE MEMORY IN 1 SEC RANGE PROGRAMMATION: HOT e INJECTION ERASURE: UV AN490/0592 1/20 PROGRAMMING FLASH MEMORY FUNDAMENTALS OF FLASH MEMORY (Cont'd) The programming mechanism of a cell is based on hot electron injection. This means that the cell control gate and drain are set to a high voltage and the cell source is grounded. The high voltage on the drain generates "hot" electrons through the channel, and the high voltage on the control gate traps the free electrons into the floating gate. The cell erase mechanism is based on "FowlerNordheim" tunnelling. This means that the cell control gate is grounded, the cell drain is disconnected and the high voltage is applied to the cell source. The high electric field between the floating gate and the source removes electrons from the floating gate. Unlike standard EEPROM memory, where individual bytes can be erased, the Flash memory of the ST10F166 performs erase on blocks where the high voltage is applied to all cells simultaneously. Figure 2. Flash Memory Cell Programming Mechanism VCG = VPP CONTROL GATE FLOATING GATE eeVD VPP SOURCE P- SUBSTRATE DRAIN Figure 3. Flash Memory Cell Erase Mechanism CONTROL GATE FLOATING GATE VS = VPP ee- SOURCE FN DRAIN P- SUBSTRATE 2/20 PROGRAMMING FLASH MEMORY FUNDAMENTALS OF FLASH MEMORY (Cont'd) A difficulty with Flash memory concerns the requirement to set all the cells of a block to a minimum threshold level suitable for programming and erase operations. Applying a new erasing pulse to a block with a different storage level on each cell (a different threshold level), can be very dangerous for the functionality of the Flash memory. A fast erasing cell may have a threshold voltage too low or negative, in this case the transistor is always on and is read at "one". This has the effect of leakage on other cells placed on the same array column. Thus all cells of the column will be read at "one" instead of "zero". To avoid this, the user must equalize the amount of charge on each cell by performing a programming operation before every erasure. For increased reliability, the SGS-THOMSON Flash memory technology, combined with the use of the Erase-verify PRESTO F algorithm, provides a tight erase threshold voltage distribution, generating sufficient margin to the faster erasing cell and the minimum threshold level required to read a "one" data value. ERASE & PROGRAMMING CONTROL To simplify control of the Flash operation modes, the ST10F166 Flash memory includes a Flash Control Register (FCR) used for all programming or erase operations. Mapped virtually into the Flash address space, FCR is not accessible during normal memory access modes and must be unlocked by a special instruction sequence. To avoid unpredictable programming or erase operation on the Flash memory, the ST10F166 provides several levels of security: First level: the user must perform a special sequence to enable the FCR and to enter into the program mode. Second level: to operate on the Flash memory, two steps are necessary. First the user must set up the FCR in the desired configuration, second the operation begins ONLY with the appropriate command. Third level: during the program mode, two bits of FCR (VPPRIV & FCVPP) indicate to the user the status of VPP (the high voltage) before and during an operation. It is advisable for the user to test them in the erase or programming routine. Figure 4. Flash Erasure CELL THRESHOLD programming curve ~6V CELL SET TO 0 VERY SMALL DISPERSION erasing curves CELL SET TO 1 (erased) FORBIDDEN AREA TIME ms ERASING A CELL SET TO 1 = PROBLEM ALL CELLS MUST BE SET TO 0 BEFORE ERASING 3/20 PROGRAMMING FLASH MEMORY THE PRESTO F PROGRAM WRITE ALGORITHM The following section explains the Presto F Program Write Algorithm shown in figure 5 for a better understanding of the user. For high reliability, it is necessary to follow this algorithm to program the Flash memory. It is considered that the EBC1/VPP pin has been switched to the VPP supply after reset, and the program mode has been unlocked. Before performing the unlock sequence, remember that the interrupts should be disabled, bit IEN of PSW cleared. After exiting the write mode, bit IEN should be set, to enable the interrupts again. - READ VPPRIV After setting the writing mode, a delay of 10 s must be inserted to allow the device to set its internal high voltage signals. Then, before starting the proper programming operation, the VPP level must be checked. VPPRIV is at the "one" level if VPP is correct. If it is not the programming algorithm must be held until VPP reaches its correct value or until the VPP supply is set correctly. mov fcrrd, FCR jnb vppriv, vpp_fail ; read FCR ; test if VPP is high - PCOUNT = 0 Initialization of PCOUNT variable to zero. The Presto F Program Write algorithm consist of applying several pulses to each word until a correct verify occurs. The maximum number of programming pulses is fixed and depends on the CPU clock. The maximum cumulated programming time is 2.5 ms for the ST10F166B. If this limit is reached the word will never be programmed. In case of several words to program, an Address variable can be initialized. mov lpcnt, #ALL0 ; reset algo. loop counter - Write Programming Setup command into FCR First step for programming: Set FCR with the desired value. Set FWE bit to enable programming operation. Clear CKCTL0 & CKCTL1 bits to define the programming pulse width: 6.4 s at 20MHz CPU clock. Choose the configuration: Set WDWW bit for double word programming. Clear WDWW bit for word programming. Set FWMSET bit for program mode. Take care at this point as this step prepares the device for programming but does not activate the process. mov bset bclr bclr bset bset mov fcrval, #ALL0 fwe ckctl0 ckctl1 wdww fwmset FCR, fcrval ; reset FCR data value ; FWE=1 define programming operation ; CKCTL0=0 ) ; CKCTL1=0 ) define the pulse width ; WDWW=1 define 32-bit configuration ; FWMSET=1 confirm write mode ; load FCR with the desired value 4/20 PROGRAMMING FLASH MEMORY THE PRESTO F PROGRAM WRITE ALGORITHM (Cont'd) Figure 5. PRESTO F Program Write Algorithm =0 PCOUNT=PNmax? PCOUNT=PCOUNT+1 VR02057A 5/20 PROGRAMMING FLASH MEMORY THE PRESTO F PROGRAM WRITE ALGORITHM (Cont'd) - Write valid data address The following command starts automatically the programming process. For word programming: mov [addrev],dat al For double word programming: mov [addrev],data l mov [addrev],data h ; programming command ; programming command, even word ; programming command, odd word - WAIT PT The programming time (PT) depends on the bits CKCTL0 & CKCTL1 of FCR (see setting of FCR). The end of programming can be detected by polling on the FBUSY bit of FCR. FBUSY set to "1" indicates programming is in progress. FBUSY cleared indicates programming has ended waitpr: mov jb fcrrd, FCR busy, waitpr ; read FCR ; jump if programming is not ended - FCVPP = "0" ? To have a well programmed word, it is important to check if VPP was at the correct value during programming. This is indicated by the status of the FCVPP bit of FCR. If FCVPP = "0" there was no problem, continue with the algorithm. If FCVPP = "1" VPP was not enough high during programming, jump to the user defined VPP-fail routine. An example of this routine could be a reset of FCR, then a new test of the VPPRIV bit and, if all is correct, redo a programming operation, otherwise exit the programming routine. jb fcvpp, vpp_fail ; jump if FCVPP is set - PROGRAM VERIFY READ To check if the word is correctly programmed, a comparison must be performed with the data expected. A Program Verify Read will check the cell margin of the word. Perform twice the same reading instruction separated by a time of 4 s. This sequence must be made to get a correct reading of the word. This time corresponds to an internal switching of signals. 6/20 PROGRAMMING FLASH MEMORY THE PRESTO F PROGRAM WRITE ALGORITHM (Cont'd) - COMPARE WITH DATA EXPECTED This step can be merged with the Program Verify Read step as the comparison instruction is a read instruction. If the data programmed at the address given is different from the data expected, an extra programming operation must be performed (the next step). cmp calla cmp jmpr cmp calla cmp jmpr datal, [addrev] cc_UC, wait4 datal, [addrev] cc_NZ, prog datah, [addrod] cc_UC, wait4 datah, [addrod] cc_NZ, prog ; first instruction for PVM (even) ; 4s ; second instruction for PVM ; jump if the word is not correctly ; programmed, restart programming ; first instruction for PVM (odd) ; 4s ; second instruction for PVM ; jump if the word is not correctly ; programmed, restart programming - PCOUNT = PN max For each new programming operation the PCOUNT variable must be incremented; at this point, it must be tested to verify whether the PN max limit has been reached or not. If yes, the word will never be programmed and the algorithm should be exited from. In this case a possible solution is to change the address of the word to program. add cmp jmpr lpcnt, #01h lpcnt, #MAXLOOP1 cc_Z, prg_fail ; increment the algo. loop counter ; compare to the limit ; jump if limit has been reached - LAST ADDRESS In case of consecutives words to program, check the address variable to know if the last address has been reached. If not, increment the address variable and start another programming operation from the beginning of the algorithm. - WRITE FWE = "0" All the words are programmed, exit the presto F program Write algorithm. All programming or Program Verify Read operation are stopped by a reset of FCR register (especially FWE bit cleared). Normal reading of the Flash memory can be performed only after this step. mov mov fcrval, FCR, #ALLO fcrval ; reset FCR and exit program mode 7/20 PROGRAMMING FLASH MEMORY THE PRESTO F ERASE ALGORITHM The following section explains the Presto F Erase Algorithm shown in figure 6 but all parts already described in the previous section will not be explained again. Note that an entire block will be erased instead of one or two words as programming. - ALL WORDS AT 0000h Prior to erasure, program all block addresses to 0000h. This step equalizes the charge on each memory cell of the block. Erasure removes charge from all memory cells regardless of their previous state, and not performing this programming will drive cells previously at a "one" to be stuck at "one" (as explained in the Fundamentals of Flash memory section). The Presto F Program Write Algorithm must be used for this block programming. (refer to the previous section). - VARIABLE INITIALIZATION Initialize two variables: PCOUNT = 0 for the pulse count, and the address variable to the first address of the block. N can be incremented from 0 to EN max. The maximum cumulated erase time is 30s. Note: with each pulse, all the block will be erased. - WRITE ERASE SETUP COMMAND INTO FCR As for programming, this step only prepares the device for erasure. Set FWE,FEE bits to enable erasure. Clear CKCTL0 & set CKCTL1 bits to define a the erasing pulse width: 1.64ms at 20MHz CPU clock. Choose the block configuration for erasure (BE0,BE1). Clear WDWW bit. Set FWMSET bit for write mode. - WRITE ERASE COMMAND Perform the specific instruction to start automatically the erase process. mov [fl_scan],fl_scan ; erase command, erasure start - WAIT ET The erasing time (ET) depends on the bits CKCTL0 & CKCTL1 of FCR (see setting of FCR). The end of erasure can be detected by polling on the FBUSY bit of FCR. FBUSY set to "1" indicates erase is in progress. FBUSY cleared indicates erase has ended. - FCVPP = "0" ? Test VPP to detect any discontinuity in VPP during erasure (see previous section). 8/20 PROGRAMMING FLASH MEMORY THE PRESTO F ERASE ALGORITHM (Cont'd) Figure 6. PRESTO F Erase algorithm =0 PCOUNT=ENmax? PCOUNT=PCOUNT+1 VR02057B 9/20 PROGRAMMING FLASH MEMORY THE PRESTO F ERASE ALGORITHM (Cont'd) - ERASE VERIFY READ This mode, equivalent to the Program Verify Read, guarantees a improved cell margin of a word. Read the data at the address given by the address variable twice with the same instruction separated by a time of 4 s. - COMPARE DATA = FFFFh Compare the data read to FFFFh. If it equals FFFFh, this address has been erased; continue verification until the last address of the block has been verified. If not, increment PCOUNT variable. Apply a new erasing pulse to the block, and continue until the data is correctly checked or the maximum erasing pulse count has been reached. read_ff: cmp cmp jmpr all1, all1, [fl_scan] ; first instruction for EVM ; 4s ; second instruction for EVM ; jump if the word is not erased calla cc_UC, wait4 [fl_scan] cc_NZ, erase - LAST ADDRESS Check the address variable to see if the last address of the block has been reached. If not, increment the address variable and start another Erase Verify Read. add cmp jmpr fl_scan,#02h fl_scan,#FL_SIZE cc_NZ, read_ff ; increment the bank pointer ; compare to the last bank address ; jump to verify the next address - WRITE FWE = "0" All the block is erased, exit the Presto F Erase algorithm stopping all erasure or Erase Verify Read operations with a reset of FCR register (especially FWE, FEE bits cleared) Normal reading of Flash memory can be performed only after this step. 10/20 PROGRAMMING FLASH MEMORY RULES FOR USING THE FLASH MEMORY - Follow the Presto F Algorithm and verify its correct implementation. This will ensure that all the block has been programmed before erasure to minimize internal stresses on the memory cells, and to perform writing operation in a fast and reliable way. - Verify VPP status before and after every writing operation. BASIC ROUTINES PROGRAMMING FOR ERASURE AND This section describes basic routines which can be helpful for the user. Erasure, 32-bit programming and 16-bit programming routines are written as subroutines to allow easy inclusion in a user program. The following routines are written in a way to clarify the operations as well as possible. The initial conditions are described at the head of the routine, if needed. Table 1. Recommended CKCTL values depending on the CPU clock used FCPU 1MHz 10 MHz 16 MHz 20 MHz CKCTL PROG. 00 00 00 00 ERASE 01 10 10 10 PROG. 128s 12.8s 8s 6.4s TPRG ERASE 2.05ms 3.28ms 2.05ms 1.64ms PROG. 19 195 312 390 N MAX ERASE 14648 9157 14648 18315 11/20 PROGRAMMING FLASH MEMORY ; VARIABLE DEFINITIONS FOR THE FLASH MEMORY ROUTINES ALL0 ALL1 BLK_START FL_SIZE FCR ADDREV ADDROD DATAH DATAL MAXLOOP1 MAXLOOP2 UNLOCK WAIT4 WAIT10 addrev fcrval addrod datal datah lpcnt all1 unlock val10u val4u wait_cnt fl_scan fcrrd fwe fee ckctl0 ckctl1 wdww be0 be1 busy fcvpp vppriv 12/20 equ equ equ equ equ equ equ equ equ equ equ equ equ equ LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT LIT 00000h ;constant 0 0FFFFh ;constant FFFF 03000h ;first address of bank 1 03000h ;size of bank 1 07FFEh ;dummy address chosen for FCR 0000Ch ;address even (least significant bit) 0000Eh ;address odd (most significant bit) 09753h ;data to program to odd address 08642h ;data to program to even address 00186h ;limit of the programming loop 0478Bh ;limit of the erase loop 01000h ;data to unlock the program mode 0000Bh ;loop 4 s 0001Fh ;loop 10 s 'R0' 'R1' 'R2' 'R3' 'R4' 'R5' 'R6' 'R7' 'R8' 'R9' 'R10' 'R13' 'R15' ;even address pointer ;register for FCR writing ;odd address pointer ;register with first data ;register with second data ;algorithm loop counter ;register used in EVM ;register used to unlock ;counter 10s ;counter 4s ;register to control wait loop ;bank address pointer ;register for FCR reading 'R1.0' ;FCR FWE bit 'R1.1' ;FCR FEE bit 'R1.5' ;FCR CKCTL0 bit 'R1.6' ;FCR CKCTL1 bit 'R1.7' ;FCR WDWW bit 'R1.8' ;FCR BE0 bit 'R1.9' ;FCR BE1 bit 'R15.2' ;FCR BUSY bit 'R15.3' ;FCR FCVPP bit 'R15.4' ;FCR VPPRIV bit PROGRAMMING FLASH MEMORY ;ERASE ROUTINE: erasure of bank 1, this routine assumes that the bank ;______________ was previously programmed to 0000h before erasure ;************* INITIAL CONDITIONS: ***************** ********************* ; ; ; ; ;***************************************** ****************************** f_erase: ; ; REGISTERS INITIALIZATION ; mov mov mov mov mov mov mov mov ; ; UNLOCK SEQUENCE FOR ENTERING IN THE PROGRAM MODE ; mov mov calla ; ; FCR SET UP FOR ERASURE ; bset bset bclr bset bclr bset bclr bset mov fwe fee ckctl0 ckctl1 wdww be0 be1 fwmset FCR, fcrval ; FWE=1 ) these two instructions ; FEE=1 ) define the erasure ; CKCTL0=0 ) ; CKCTL1=1 ) define the pulse ; WDWW=0 ; BE0=1 ) ; BE1=0 ) select bank 1 ; FWMSET=1 enable program mode ; load FCR set up 13/20 ALL WORDS IN BANK 1 HAVE TO BE PROGRAMMED AT "ZERO" WITH THE PRESTO F PROGRAM WRITE ALGORITHM lpcnt, #ALL0 fcrval, #ALL0 unlock, #UNLOCK val10u, #WAIT10 val4u, #WAIT4 wait_cnt,#ALL0 all1, #ALL1 fl_scan,#BLK_START ; reset algo. loop counter ; reset FCR data value ; load unlock data ; load 10s loop data ; load 4s loop data ; reset wait loop counter ; set R2 to FFFFh ; load first bank address FCR, unlock ; first instruction ; second instruction of unlock ; sequence to enter in the program mode ; time out 10 s to set internal signals [unlock],unlock cc_UC, wait10 PROGRAMMING FLASH MEMORY ; ; TEST VPP ; mov jnb ; ; FLASH ERASURE ; erase: add cmp jmpr mov waiter: mov jb ; ; TEST VPP ; jb fcvpp, vpp_fail ; jump if FCVPP is set, to know if ; a fail occured because VPP did not ; have the correct value during ; erasure ; ; ERASE VERIFY MODE ; read_ff:cmp calla cmp jmpr add cmp jmpr ; ; EXIT OF PROGRAM MODE ; mov ret FCR, #ALL0 ; reset FCR and exit program mode ; return to main program all1, all1, [fl_scan] [fl_scan] ; first instruction for EVM ; time out 4s ; second instruction for EVM ; jump if the word is not erased ; increment the bank pointer ; compare to the last bank address ; jump to verify the next address cc_UC, wait4 cc_NZ, erase fl_scan,#02h fl_scan,#FL_SIZE cc_NZ, read_ff lpcnt, #01h lpcnt, #MAXLOOP2 cc_Z, eras_fail [fl_scan],fl_scan fcrrd, FCR busy, waiter ; increment the algo. loop counter ; compare to the limit ; jump if limit has been reached ; erase command, erasure start ; read FCR ; jump if erasure is not ended fcrrd, FCR vppriv, vpp_fail ; read FCR ; test if VPP is high 14/20 PROGRAMMING FLASH MEMORY ;32-BIT PROGRAMMING ROUTINE: bit32prg: ; programming of address 0000Ch with 08642h ;____________________________ and address 0000Eh with 09753h ; REGISTER INITIALIZATION ; mov mov mov mov mov mov mov mov mov mov mov ; ; UNLOCK SEQUENCE FOR ENTERING IN THE PROGRAM MODE ; mov mov calla ; ; FCR SET UP FOR PROGRAMMING ; bset bclr bclr bset bset mov ; ; TEST VPP ; mov jnb fcrrd, FCR vppriv, vpp_fail ; read FCR ; test if VPP is high fwe ckctl0 ckctl1 wdww fwmset FCR, fcrval ; FWE=1 define programming operation ; CKCTL0=0 ) ; CKCTL1=0 ) define the pulse width ; WDWW=1 define 32-bit configuration ; FWMSET=1 confirm program mode ; load FCR set up FCR, unlock ; first instruction ; second instruction of unlock ; sequence to enter in the program mode cc_UC, wait10 ; time out 10 s to set internal signals [unlock],unlock lpcnt, #ALL0 fcrval, #ALL0 unlock, #UNLOCK val10u, #WAIT10 val4u, #WAIT4 wait_cnt,#ALL0 all1, #ALL1 datal, #DATAL datah, #DATAH addrev, #ADDREV addrod, #ADDROD ; reset algo. loop counter ; reset FCR data value ; load unlock data ; load 10s loop data ; load 4s loop data ; reset wait loop counter ; set R2 to FFFF ; load data for even address ; load data for odd address ; load even address ; load odd address 15/20 PROGRAMMING FLASH MEMORY ; FLASH PROGRAMMING ; prog: add cmp jmpr mov mov waitpr:mov jb ; ; TEST VPP ; jb fcvpp, vpp_fail ; jump if FCVPP is set, to know if ; a fail occured because VPP did not ; have the correct value during ; programming ; ; PROGRAM VERIFY MODE ; cmp calla cmp jmpr cmp calla cmp jmpr ; ; EXIT OF PROGRAM MODE ; mov ret FCR, #ALL0 ; reset FCR and exit program mode ; return to main program datal, [addrev] cc_UC, wait4 datal, [addrev] cc_NZ, prog datah, [addrod] cc_UC, wait4 datah, [addrod] cc_NZ, prog ; first instruction for PVM (even) ; time out 4s ; second instruction for PVM ; jump if the word is not correctly ; programmed, restart programming ; first instruction for PVM (odd) ; time out 4s ; second instruction for PVM ; jump if the word is not correctly ; programmed, restart programming lpcnt, #01h lpcnt, #MAXLOOP1 cc_Z, prg_fail [addrev],datal [addrev],datah fcrrd, FCR busy, waitpr ; increment the algo. loop counter ; compare to the limit ; jump if limit has been reached ; programming command, even word ; programming command, odd word ; read FCR ; jump if programming is not ended 16/20 PROGRAMMING FLASH MEMORY ;16-BIT PROGRAMMING ROUTINE: programming of address 0000Ch with 08642h ;____________________________ bit16prg: ; ; REGISTERS INITIALIZATION ; mov mov mov mov mov mov mov mov mov ; ; UNLOCK SEQUENCE FOR ENTERING IN THE PROGRAM MODE ; mov mov calla ; ; FCR SET UP FOR PROGRAMMING ; bset bclr bclr bclr bset mov ; ; TEST VPP ; mov jnb fcrrd, FCR vppriv, vpp_fail ; read FCR ; test if VPP is high fwe ckctl0 ckctl1 wdww fwmset FCR, fcrval ; FWE=1 define programming operation ; CKCTL0=0 ) ; CKCTL1=0 ) define the pulse width ; WDWW=0 define 16-bit configuration ; FWMSET=1 confirm program mode ; load FCR set up FCR, unlock ; first instruction ; second instruction of unlock ; sequence to enter into the program mode cc_UC, wait10 ; time out 10 s to set internal signals [unlock],unlock lpcnt, #ALL0 fcrval, #ALL0 unlock, #UNLOCK val10u, #WAIT10 val4u, #WAIT4 wait_cnt,#ALL0 all1, #ALL1 datal, #DATAL addrev, #ADDREV ; reset algo. loop counter ; reset FCR data value ; load unlock data ; load 10s loop data ; load 4s loop data ; reset wait loop counter ; set R2 to FFFF ; load data ; load address 17/20 PROGRAMMING FLASH MEMORY ; FLASH PROGRAMMING ; progw: add cmp jmpr mov waitprw:mov jb ; ; TEST VPP ; jb fcvpp, vpp_fail ; jump if FCVPP is set, to know if ; a fail occured because VPP did not ; have the correct value during ; programming ; ; PROGRAM VERIFY MODE ; cmp calla cmp jmpr ; ; EXIT OF PROGRAM MODE ; mov ret FCR, #ALL0 ; reset FCR and exit program mode ; return to main program datal, [addrev] cc_UC, wait4 datal, [addrev] cc_NZ, progw ; first instruction for PVM ; time out 4s ; second instruction for PVM ; jump if the word is not correctly ; programmed, restart programming lpcnt, #01h lpcnt, #MAXLOOP1 cc_Z, prg_fail [addrev], datal fcrrd, FCR busy, waitprw ; increment the algo. loop counter ; compare to the limit ; jump if limit has been reached ; programming command ; read FCR ; jump if programming is not ended 18/20 PROGRAMMING FLASH MEMORY SUBROUTINES USED IN WRITING OPERATION ___________________ _____________ _____ wait4:add cmp jmpr mov ret wait10:add cmp jmpr mov ret vpp_fail: ; VPP FAIL ROUTINE DEFINED BY THE USER prg_fail: ; PROGRAM FAIL ROUTINE DEFINED BY THE USER eras_fail: ; ERASE FAIL ROUTINE DEFINED BY THE USER wait_cnt,#01h wait_cnt,val10u cc_NZ, wait10 wait_cnt,#ALL0 ; increment counter ; compare with final value ; jump if not equal ; reset counter wait_cnt,#01h wait_cnt,val4u cc_NZ, wait4 wait_cnt,#ALL0 ; increment counter ; compare with final value ; jump if not equal ; reset counter 19/20 PROGRAMMING FLASH MEMORY THE SOFTWARE INCLUDED IN THIS NOTE IS FOR GUIDANCE ONLY. SGS-THOMSON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THE SOFTWARE. Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 20/20 |
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