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The V850 Series of high-performance microcontrollers answers many different application system needs. It realizes superlatively low power consumption and low noise while offering high performance and a wide array of functions. The broad V850 product lineup provides optimum solutions for the nextgeneration systems of customers.
High performance
Performance range of 20 to over 300 MIPS with single instruction set
Product deployment
Low-end/Middle-range/ high-end/ASSP deployment
Additional functions
Rich middleware lineup
System LSIs
Smooth transition to system LSIs
Development environment
Rich development environment lineup
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INDEX
Roadmap/Features
04
V850 Series Product Roadmap * * * 4 NEC Electronics Microcontroller Deployment * 5 Set Application Examples * * * * 5 5 Keys of V850 *
************
6
Product Lineup
08
Low-End Lineup * * * * * * * * * * * * * 8 Middle-Range Lineup * * * * * * * * 10 High-End Lineup * * * * * * * * * * * * 12 ASSP Lineup * * * * * * * * * * * * * * * 14 Memory Lineup * * * * * * * * * * * * * 18 Package Lineup * * * * * * * * * * * * * 19
CPU
20
CPU Roadmap * * * * * * * * * * * * * * 20 CPU Core Function Comparison * * 20 System LSI Support * * * * * * * * * 21 V850 Series Common Architecture * * * 22 V850E1,V850ES Architecture * * * 26 V850E2 Architecture * * * * * * * * * 27
Variety of Peripheral Functions
28
Memory Access Functions * * * * 28 Analog Circuits * * * * * * * * * * * * * 29 Timer/Counter * * * * * * * * * * * * * 30 Serial Interface * * * * * * * * * * * * * * 31 Other * * * * * * * * * * * * * * * * * * * * * * 32
Performance
34
V850 Series Benchmark * * * * * * 34 Low Power Consumption * * * * 34 Low Noise Countermeasures * * 35
Middleware
36
V850 Series Middleware List * * 36 Speech Recognition * * * * * * * * * 37 JPEG * * * * * * * * * * * * * * * * * * * * * 37 Text to Speech (for Japanese Text)
*********
37
Flash
Features * * * * * * * * * * * * * * * * * * * * 38 Rewrite Modes * * * * * * * * * * * * * 38 Flash Specifications List * * * * * * 39 Flash Memory Programmers
**
38
40
Product Specifications List
42
Low-End Lineup * * * * * * * * * * * * 42 Middle-Range Lineup * * * * * * * * 44 ASSP Lineup * * * * * * * * * * * * * * * 47 High-End Lineup * * * * * * * * * * * * 50
Development Environment
52
Low-Price Development Environment Lineup * * * 53 Development Flow * * * * * * * * * * 54 Development Tools * * * * * * * * * * 54 V850 Series Development Environment * * * 57 Software Product * * * * * * * * * * * * 59
Information Dissemination
62
V850 Series Website * * * * * * * * * 62
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Roadmap/Features
V850 Series Product Roadmap
Continuously evolving V850 Series through an expanding product lineup
V850E2 core 200 to 400 MHz
CPU core release completed Product deployment under planning
V850E1 core
150 MHz @ 215 MIPS
High-end lineup High-end lineup
High performance: On-chip MEMC/DMA
* Frequency: 33 to 150 MHz * Memory size: ROM: ROM-less to 512 KB RAM: 4 to 128 KB * PKG: 100 to 240 pins (QFP & FBGA)
ASSP lineup ASSP lineup
Inverter control DVC control Car audio control Power meter control Dashboard control
* Frequency: 16 to 64 MHz * Memory size: ROM: ROM-less to 640 KB
V850 core
33 MHz @ 38 MIPS
Middle-range lineup Middle-range lineup
Realization of low EMI noise
* Frequency: 20 to 34 MHz * Memory size: ROM: ROM-loss to 640 KB RAM: 4 to 48 KB * PKG: 100 to 144 pins (QFP & FBGA)
RAM: 4 to 48 KB * PKG: 64 to 257 pins (QFP & FBGA)
V850ES core
20 MHz @ 29 MIPS
Low-end lineup Low-end lineup
High cost-performance
* Frequency: 20 MHz * Memory size: ROM: 64 to 256 KB RAM: 4 to 16 KB * PKG: 64 to 144 pins (QFP)
Standard lineups
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Field-specific lineups
NEC Electronics Microcontroller Deployment
High performance
TM
64-bit RISC
VR5000 Series VR4100 Series V850E/Mxx high-end lineup
VR7700 Series
Inverter, DVC, storage ASSP lineup
32-bit RISC
V850ES/Sxx, V850/Sxx middle-range lineup Kx1 Series V850ES/Kxx, 78K0/Kxx low-end lineup
Upward compatible instruction sets
78K4
8/16-bit CISC
78K0 78K0S 75X/XL
8 to 16-bit applications
S
m yste
con
trol
Da
ro ta p
ces
sing
17K
32-bit applications
64-bit applications Price
Set Application Examples
Automotive Audio Portable devices Camera Computer peripherals Home appliances Industrial equipment Video and recording equipment Other
The V850 Series is suitable for various application fields and raises the commercial value of customer systems.
Engines, dashboards, power steering, ABS
Car audio, portable audio, component stereo systems
PDA, IC recorders
DVC, DSC, SLR cameras Laser-beam printers, inkjet printers, scanners, fax machines Air conditioners, refrigerators, washing machines, microwave ovens Industrial motors, control equipment, vending machines, power meters
DVD players, D-VHS, industrial cameras Electronic instruments, electric bidets, toys, learning devices, remote controllers, etc.
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Roadmap/Features
5 Keys of V850
High performance
5 points supporting the high performance of the V850 Series
Performance ranging from 20 to over 300 MIPS with single instruction set
High performance
> =200 MHz
Processor products
Not compatible
Data processing
V850E2
Other manufacturers' 32-bit microcontrollers 8-/16-bit microcontroller, offer MIPS *Compared to 10 or more times higher for theasame performance
150 MHz
Compatible with up to middle-range class
V850E1
33 MHz
66 MHz
Not compatible
V850
32 MHz
* *
frequency, and 2 to 3 times higher at the actual application level (based on NEC evaluation) System operation at frequencies 1/2 to 1/3 those of 8/16-bit microcontrollers is enabled, contributing to lowering system power consumption. The V850 core, V850ES core, V850E1 core, and V850E2 core are upward compatible at the object level.
Other Compatible with up to high-end class manufacturers' 16-bit models with MIPS performance up to 10 times higher microcontrollers System control
V850ES V850
20 MHz
Compatible at object level!
Product lineup
Low-end/Middle-range/High-end/ASSP deployment
Product lineup
High-End lineup Automotive Office equipment ASSP lineup
V850E/Mxx
High performance
V850E2 core V850E1 core V850ES core
On-chip dedicated hardware
V850E/xxx V850ES/xxx V850/xxx
Industrial
Series of *Low-end lineup: Kx116 to 32-bitgeneral-purpose for high microcontrollers for market designed low power consumption, *Middle-range lineup: Low noise,low-voltage operation support large-capacity memory lineup, lineup: *High-EndcontrollerDesigned for high performance, on-chip memory and DMA *ASSP lineup: Field-specific product lineup, on-chip dedicated hardware cost-performance.
V850 core
Low noise, low power consumption
Middle-range lineup
V850ES/Sxx V850/Sxx
Communication Home appliances Consumer electronics
High cost-performance
Low-end lineup
V850ES/Kxx
Additional functions
Rich middleware lineup
Additional functions
Amusement machines
FAX DSC
Toys
JBIG MH/MR/MMR
Handwriting recognition
Portable devices Electronic dictionaries
Car audio
ADPCM TTS
Image processing
of systems with high added value *Realizationsupplementary functions to existingthrough the addition of systems
JPEG
Human interface
Middleware
Browser
Speech recognition
* *
6
via middleware Realization of functions heretofore realized with peripheral ICs through V850 + middleware, reducing development time and reducing system costs Rich lineup of video, audio, network-related, and other middleware tuned for V850 Series
Home appliances
AV equipment
Networks
Java
TM
TCP/IP
Phones
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System LSI
Smooth transition to system LSIs
System Processes
Micro-fabrication technology Multi-layer wiring technology Mixed-process technology High-pin-count packages
System LSI
Design environment
CPU DSP
Analog
IP
actively *The V850 Series is also beingtransition expanded for ASIC CPU cores, realizing smooth to system LSIs *Theafollowing elements essential for system LSIs are provided on timely basis: <1> Leading-edge process technology <2> High-performance CPU core <3> Rich lineup of IP cores <4> Top-down design environment <5> Flexible application design
1000
Memory Flash Logic DRAM
middleware
IP cores
MPU, DSP, DRAM, SRAM, AV, communication, BUS, high-speed I/O
PC I/F
Chip design environment Synthesis/verification Software development environment Hardware/software coordinated design
Middleware
Voice recognition/synthesis AV processing (JPEG1, MPEG1, etc.) Modem
700
Next-generation process
Next-generation core 800 to 1000 MIPS V850E2
Nx85E2 200 MHz Nx85E2 400 MHz
Performance (MIPS)
500 300
0.13 m process
Nx85E2 266 MHz
V850E2/xxx
200
Nx85E 150 MHz
100
0.18 m process 0.25 m process
V850E1
Nx85E 66 MHz
66
V850E/MA1
V850E/ME2
MA2
MA3
Under planning Under development In mass production
33
V850
0.35 m process
Generation
Development environment
Rich development environment lineup
78K environment
Development environment
V850 development environment PM Project Manager
Improved versatility
Utilization of existing functions Improved usability development
PM Project Manager
CC (Compiler) RX (Real-time OS)
CA (Compiler) RX (Real-time OS)
+RD (task debugger) +AZ (Analyzer)
V850 products
Realization of highperformance powerful development environment making use of * High performance * General-purpose registers * Large memory capacity
Improved performance Debugging support
, a low-cost high-performance emulator, and *IECUBECARD, an ultra-low cost on-chip emulator are N-Wire
TM
SM (Simulator) ID (Debugger)
Debugging support
SM (Simulator) ID (Debugger) TW
(Performance analysis tuning tool)
*Realization of better connectivity with target boards, addition of GUI customization function, improved online help, etc. shorter *Realization ofaccurate development TAT through support of quick and software development via a rich
development environment lineup featuring easy operation and sophisticated functions
available
Improved usability
IE, IECUBE (In-circuit emulator)
Support of high speed
IE, IECUBE
(In-circuit emulator)
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Product Lineup
Low-End Lineup
Under planning
Kx1 Series of general-purpose microcontrollers for 16 to 32-bit market designed for high cost-performance
NEXT Generation
Under development
In mass production
V850ES/KE1+
64-pin version
V850ES/KF1+
80-pin version
V850ES/KG1+
100-pin version
V850ES/KJ1+
144-pin version
Single-power-supply flash On-chip POC/LVI On-chip debugging function DMA function (only KG1+, KJ1+)
V850ES/KE1
64-pin version
8-bit microcontrollers
V850ES/KF1
80-pin version
V850ES/KG1
100-pin version
V850ES/KJ1
144-pin version
78K0/Kxx 78K0S/Kxx
Rich memory and package lineup Large array of on-chip peripheral functions common with 78K0/Kx1 of 8-bit microcontrollers Low EMI noise design
Development environment usable in common for all series Wide voltage range support (2.7 to 5.5 V) Single-power-supply flash lineup (self programming, EEPROMTM emulation support)
Kx1+ features
Kx1+ are microcontrollers featuring additional functions.
V850ES/Kx1 V850ES/Kx1+
128K
Kx1 Series lineup
Rich memory & package lineup
ROM (Bytes) 256K
V850ES
lin p eu
KE1
KF1+ KG1+ KJ1+ KE1+ KF1 KG1 KJ1
Runaway detection Watchdog timer running plus High-reliability watchdog timer operating function with uninterruptible Ring OSC on main clock On-chip voltage detection circuit (LVI: variable detection voltage)
96K 60/64K 48K
Voltage detection circuit
None
Reset functions
External reset, WDT reset
plus *On-chip reset detection circuit (POC: Fixed voltage)
*Also possible with voltage detection circuit (LVI: Variable detection voltage)
32K 24K
a Se
m
le
ss
78K0
KC1+ KD1+ KB1+
KF1+
KE1+ KF1
DMA function
None
plus
4 on-chip channels (KG1+, KJ1+)
16K
KB1
Oscillation stabilization time reduction Fixed at reset release
8K
KC1
KD1
KE1
Can be reduced with optional function
4K
78K0S
KU1+ KA1+ KY1+
KB1+
A/D converter
Conversion time 14 s (min.) Successive approximation mode
Conversion interval of 3 s (min.) Successive approximation, scan mode
2K 1K
LIN bus interface
No hardware
1 hardware channel for each product
8 16 20 30 44 52 64 80 100 144 pins
Product specifications
Item
KE1 KF1 V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 128 KB 128 KB 4 KB 256 KB/128 KB 256 KB/128 KB/96 KB/64 KB 12 KB/6 KB/4 KB 4.5 V to 5.5 V @ 20 MHz 4.0 V to 5.5 V @ 16 MHz 2.7 V to 5.5 V @ 10 MHz 16-bitx2 ch Address: Multiplexed 16-bitx 2 ch (256 KB: 3 ch) 8-bitx5 ch WDTx2 ch Watch timerx1 ch Address: Multiplexed/separate Data: 8/16-bit 16-bitx6 ch (256 KB: 7 ch) 16-bitx4 ch (256 KB: 5 ch) 16 KB/6 KB/4 KB 128 KB/96 KB 16 KB/6 KB V850ES/Kx1 KG1 KJ1
CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter
Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask version, Typ.) Package
2
CSIx2 ch, UARTx2 ch I 2 Cx1 ch* -
CSIx2 ch, UARTx2 ch I 2 Cx1 ch* CSI with automatic transfer functionx1 ch 10-bitx8 ch
CSIx2 ch, UARTx2 ch I 2 Cx1ch* CSI with automatic transfer functionx2 ch 8-bitx2 ch
CSIx3 ch, UARTx2 ch UART/I 2 Cx1 ch*, I 2 Cx1 ch* CSI with automatic transfer functionx2 ch 10-bitx16 ch
51
ROM correction function, real-time output, key return function 67 150 mW (20 MHz @5V) 80-pin TQFP(12x12 mm) 80-pin QFP(14x14 mm)
84
On-chip debug function, ROM correction function, real-time output, key-return function 128
64-pin TQFP(12x12 mm) 64-pin LQFP(10x10 mm)
100-pin LQFP(14x14 mm) 100-pin QFP(14x20 mm)
144-pin LQFP(20x20 mm)
* : Only Y products have an on-chip I C interface.
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System cost reduction
Conventional set
Voltage detector
>Set space reduction! >Total set cost reduction! >Lower number of used ports!
WDT independent from CPU clock
Kx1 SeriesNote set
Voltage drop detection
>Higher reliability!!!
LVI VDD POC
RESET output
VDD
Micro
Port Port X2
Watchdog IC
Peripheral functions on single chip
RingOSC Clock monitor X1 X2 WDT
X1
RESET
RESET IC
Oscillation stop monitoring
RESET
System reset voltage detection
External IC
External IC
RESET
Note: V850ES is supported from Kx1+
Common peripheral functions
Large array of peripheral functions common with 8-bit 78K0 Series
ROM size(bytes)
KU1+ 1K 2K 4K
78K0S KY1+ KA1+ KB1+ 1K 2K 4K 2K 4K 8K 4K
KB1 KB1+ KC1 8K 8K 16K 16K 24K 24K 16K 24K 32K 1 1 2 1 1 2 1 1 2 1 2 2 1 1
KC1+ 16K 24K 32K
KD1 8K 16K 24K 32K 1 2 2 1 1
78K0 KD1+ KE1 16K 8K 24K 24K 16K 32K 32K 48K 60K 1 2 2 1 1 1 2 2 1 1 2 2 2 1 1
KE1+ 16K 24K 32K 48K 60K 1 2 2 1 1 2 2 2 1 1
KF1 KF1+ 24K 48K 60K 32K 60K
V850ES KF1 KG1 KJ1 KE1 KE1+ KF1+ KG1+ KJ1+ 128K 128K 64K 256K 128K 64K 256K 128K 96K 256K 128K 96K 256K 96K 256K 128K 256K 128K 128K 1 1 2 2 1 1 1 2 2 1 8 ch 1 1 2 2 1 1 1 2 1 1 1 8 ch 1 2 2 2 1 1 1 2 1 2 1 8 ch 1 2 2 2 1 1 1 2 1 1 1 1 8 ch 1 4 2 2 1 1 1 2 2 2 1 8 ch 2 ch 1 4 2 2 1 6 2 2 1 6 2 2
TMP TM0 TM5 TMH TM8 WT WDT(Powerful WDT) WDT DMA CSI Auto CSI UART UART(LIN) IIC A/D D/A Ring-OSC(8 MHz) Ring-OSC(240 kHz) Sub-OSC REG. Key return ROM correction Real-time Output H.MUL/DIV POC/LVI RESET OUT Clock Monitor
1 1
1 1
1 1 1 1
1 1 1 1
1 2 2 1 1
1 2 2 1 1
2 2 2 1 1
2 2 2 1 1
2 2 2 1 1 1 2 1 2 1 8 ch
4 2 2 1 1 1 2 2 2 1 8 ch 2 ch
6 2 2
1
1
1
1
1
1
1 1 1 4 ch
1 1 1 4 ch
1 1 1 8 ch
1 1 1 8 ch
1 1 1 8 ch
1 1 1 8 ch
1 1 1 8 ch
2 1 1 8 ch
1 1 1 8 ch
2 1 1 8 ch
1 4 ch Y Y* 4 ch Y Y* 4 ch Y Y*
1 4 ch Y Y*
1 4 ch
1 1 1 1 8 ch
2 1 1 1 8 ch
2 1 1 1 8 ch
1 1 1 1 1 1 1 1 1 1 1 1 4 4 2 3 3 3 2 2 2 2 2 3 3 2 1 1 1 2 2 2 8 ch 16 ch 16 ch 16 ch 2 ch 2 ch 2 ch 2 ch Y* Y Y Y Y Y Y Y Y Y* Y Y Y Y Y Y Y
Y
Y
Y
Y Y Y
Y Y Y
Y Y Y Y
Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y
Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y
Y Y Y Y
Y* Y Y Y Y Y Y Y
Y Y Y Y Y
Y Y Y Y Y
Y* Y Y Y Y Y Y Y Y
Y Y Y Y Y
Y Y Y Y Y
Y Y Y Y Y
Y Y Y Y Y
Y
Y
Y
Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
Y Y Y Y
* : Only for WDT/TMH
Common to all products
Common to V850ES products
Common to 78K0 products
Common to 78K0S products
Item
KE1+ KF1+
V850ES/Kx1+ KG1+ V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 MHz (subclock) 128 KB 128 KB 4 KB 256 KB/128 KB 256 KB 12 KB/6 KB 4.5 V to 5.5 V @ 20 MHz 4.0 V to 5.5 V @ 16 MHz 2.7 V to 5.5 V @ 10 MHz 16-bitx2 ch Address: Multiplexed 16-bitx3 ch Data: 8/16 bits 16-bitx5 ch Address: Multiplexed/separate 16-bitx7 ch 16KB/6KB KJ1+
CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter
Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
CS x 2 ch, LIN compatible UART x 1 ch UART x 1 ch, I 2 C x 1 ch* -
8-bitx5 ch WDTx 2 ch Watch timerx1 ch CS I x 1 ch, LIN compatible UART x 1 ch CS I x 2 ch, LIN compatible UART x 1 ch UART x 1 ch, I 2 C x 1 ch*, UART/CSI x 1 ch UART x 1 ch, I 2 C x 1 ch* CSI with automatic transfer function x 1 ch CSI with automatic transfer function x 2 ch 10-bitx8 ch
51
POC/LVI, Ring OSC, clock monitor function ROM correction function, real-time output, key return function 67 T.B.D. 80-pin TQFP (12x12 mm) 80-pin QFP (14x14 mm)
84
CSI x 2 ch, LIN compatible UART x 1 ch, UART x 1 ch I 2 C x 1ch*, UART/CSI x 1 ch, UART/I 2 C x 1 ch CSI with automatic transfer function x 2 ch 10-bitx16 ch 8-bitx2 ch 4ch On-chip debug function, POC/LVI, Ring OSC, clock monitor function, real-time output, key-return function 127 (Y products, 128)
64-pin TQFP (12x12 mm) 64-pin LQFP (10x10 mm)
2
100-pin LQFP (14x14 mm) 100-pin QFP (14x20 mm)
144-pin LQFP (20x20 mm)
* : Only Y products have an on-chip I C interface.
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Product Lineup
Middle-Range Lineup
Under planning
Large-capacity memory, 2.5 V/3 V/5 V general-purpose product lineup
Under development
In mass production
V850/SC1 V850/SB1
5 V low-power version 100-pin version 5 V low-power version 144-pin version
PD703229Y
5 V large-capacity RAM version 100-pin version
5 V generalpurpose low noise
Pin compatible Same peripheral functions Single-power-supply flash Larger capacity memory Enhanced peripheral functions
V850ES/SJx V850ES/SGx
Large-capacity internal memory
V850ES/SJ2 V850ES/SG2 3 V low-power version
3 V low-power version 100-pin version 144-pin version
3 V generalpurpose, Low power consumption, Low noise
V850/SA1
3 V low-power version
ROM-less
V850ES/ST2
ROM-less, high-capacity RAM 120-/144-pin version
Peripheral function memory capacity optimization V850ES/SGx
Single-power-supply flash Lower voltage Enhanced peripheral functions
V850ES/SA2 V850ES/SA3
Low voltage, super-low power consumption
2.5 V generalpurpose, super-low power consumption
Product specifications
Item
SA2 V850ES/SAx SA3 V850ES 29 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 256 KB 256 KB/128 KB 16 KB/8 KB 2.2 V to 2.7 V 256 KB 16 KB SG2 V850ES/Sx2 SJ2 V850ES 29MIPS (@20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 640KB/384KB 640KB/512KB/384KB/256KB 640KB/512KB/384KB 48KB/40KB/32KB/24KB 48KB/40KB/32KB 2.85 V to 3.6 V
CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter
PD70F3229Y PD703229Y V850ES 29MIPS (@20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 384KB 384KB 32KB 3.5 V to 5.5 V (internal) 3.0 V to 5.5 V (external bus) Address: Multiplexed Data: 8/16 bits 16-bit x 6 ch WDT x 1 ch Watch timer x 1 ch
Address: Multiplexed/separate Data: 8/16 bits 16-bit x 2 ch 8-bit x 4 ch WDT x 1 ch CSI x 2 ch, CSI/UART x 1 ch UART x 1 ch, CSI/I 2 C x 1 ch* 10-bit x 12 ch CSI x 3 ch, CSI/UART x 1 ch UART x 1 ch, CSI/I 2 C x 1 ch*
Address: Multiplexed/separate Data: 8/16 bits 16-bitx8 ch WDTx1 ch Watch timerx1 ch 16-bit x 11 ch WDT x 1 ch Watch timer x 1 ch
Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
10-bit x 16 ch 8-bitx2 ch 4 ch Real-time counter (watch function), ROM correction function 82 38 mW (20 MHz @ 2.5 V) 100-pin TQFP (14 x 14 mm)
2
102 121-pin FBGA (12 x 12 mm)
CSIx1 ch, LIN compatible UART x 3 ch CSI x 3 ch, CSI/LIN compatible UART x 1 ch CSI x 4 ch, CSI/LIN compatible UART x 1 ch CSI/I 2 C x 1 ch* CSI/I 2 C x 1 ch* LIN compatible UART x 1 ch, CSI/I2 C x 1 ch* LIN compatible UART/I 2 C x 2 ch* UART/I2 C x 2 ch* 10-bit x 12 ch 10-bit x 16 ch 10-bit x 12 ch 8-bitx2 ch 4 ch 4 ch On-chip debugging function, CRC circuit, ROM correction function, Ring OSC, On-chip debugging function, ROM correction function, low voltage detection circuit, clock monitoring function, automotive bus (IEBusTM, aFCAN)Note low voltage detection circuit, clock monitoring function 84 128 84 59.4 mW (20 MHz @ 3.3 V) 66 mW (20 MHz @ 3.3 V) 100 mW (20 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm)
Note
144-pin LQFP (20 x 20 mm)
100-pin LQFP (14 x 14 mm)
* : Only Y products have an on-chip I C interface.
Products without automotive bus, products with on-chip IEBus, and products with on-chip aFCAN are available.
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Features
V850ES/SG2, SJ2
Low EMI noise 20 MHz @ 2.85 to 3.6 V operation 5 V withstand voltage ports incorporated, and 5 V output is possible by setting the N-ch open-drain output On-chip large-capacity single-power-supply flash memory
PD70F3229Y, 703229Y
Large-capacity memory ROM/RAM:384 KB/32 KB 3 V/5 V mixed system support (Internal: 3.3 V/External: 5 V) Peripheral functions and pin assignment common with V850ES/SG2 100-pin LQFP
ROM/RAM:640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB, 256 KB/24 KB (SG2 only) Automotive on-chip bus support: IEBus*, aFCAN* (*: Only products with on-chip SG2, SJ2) On-chip debugging function 100-pin QFP (SG2)/100-pin LQFP (SG2)/144-pin LQFP (SJ2)
V850ES/ST2
ROM-less version On-chip high-capacity RAM (48 KB) 3.3 V, 34 MHz operation Thin-type, compact type packages supported: 120-pin TQFP/144-pin LQFP
V850ES/SA2, SA3
Min. 2.2 V low-voltage operation (including A/D, D/A converter, flash) Low power consumption and high-speed operation during 38 mW @ 2.5 V, 20 MHz operation Single-power-supply flash ROM/RAM: 256 KB/16 KB (SA2, SA3), 128 K/8 KB (SA2 mask ROM version) Thin and compact package support: 100-pin TQFP (SA2)/121-pin FBGA (SA3)
V850/SA1
Low power consumption and high-speed operation during 66 mW @ 3.3 V, 20 MHz operation Large memory selection ROM/RAM:256 KB/8 KB, 128 KB/4 KB, 64 KB/4 KB 100-pin LQFP/121-pin FBGA
V850/SB1
Low EMI noise Large-capacity memory and large memory selection ROM/RAM:512 KB/24 KB, 384 KB/24 KB, 256 KB/16 KB, 128 KB/8 KB 100-pin QFP/100-pin LQFP
V850/SC1
Low EMI noise Large-capacity memory (ROM/RAM: 512 KB/24 KB) Enhanced peripheral functions for SB1 144-pin LQFP
Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter
V850/SA1 V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 256 KB/128 KB 256 KB/128 KB/64 KB 8 KB/4 KB 2.7 V to 3.6 V (@ 17 MHz) 3.0 V to 3.6 V (@ 20 MHz) Address: Multiplexed/separate Data: 16-bits 16-bitx2 ch 8-bitx4 ch WDTx1 ch Watch timerx1 ch CSIx1 ch, CSI/UARTx1 ch CSI/I 2 Cx1 ch*, UARTx1 ch 10-bitx12 ch 3 ch (internal RAM-on-chip peripheral I/O) -
V850/SB1 V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 512 KB/384 KB/256 KB 512 KB/384 KB/256 KB/128 KB 24 KB/16 KB/8 KB 4.0 V to 5.5 V Address: Multiplexed/separate Data: 16-bits 16-bitx2 ch 8-bitx6 ch WDTx1 ch Watch timerx1 ch CSIx1 ch, CSI/UARTx2 ch CSI/I 2 Cx2 ch* 10-bitx12 ch 6ch (internal RAM-on-chip peripheral I/O) ROM correction function 83 125 mW (20 MHz @ 5 V) 100-pin LQFP (14x14 mm) 100-pin QFP (14x20 mm)
V850/SC1 V850 23 MIPS (@ 20 MHz) 20 MHz (main clock) 32.768 kHz (subclock) 512 KB 512 KB 24 KB 3.5 V to 5.5 V (mask ROM versions) 4.0 V to 5.5 V (flash memory versions) Address: Multiplexed/separate Data: 16-bits 16-bitx10 ch WDTx1 ch Watch timerx1 ch CSIx2 ch, CSI/UARTx2 ch UARTx2 ch, CSI/I 2 Cx2 ch 10-bitx12 ch 6 ch (internal RAM-on-chip peripheral I/O) ROM correction function 124 125 mW (20 MHz @ 5 V) 144-pin LQFP (20x20 mm)
V850ES/ST2 V850ES 34 MHz ROM-less 48 KB 3.0 V to 3.6 V Address: Separate/multiplexed (selectable only for CS1) Data: 8/16 16-bitx7 ch WDTx1 ch
Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
CSIx1 ch, CSI/UARTx1 ch UARTx1 ch 10-bitx8 ch 8-bitx2 ch Real-time output 65 T.B.D. 120-pin TQFP (14x14 mm) 144-pin LQFP (20x20 mm)
*
85 66 mW (20 MHz @ 3.3 V) 56 mW (17 MHz @ 3 V) 100-pin LQFP (14x14 mm) 121-pin FBGA (12x12 mm) 2 : Only Y products have an on-chip I C interface.
Pamphlet U15412EJ4V1PF
11
Product Lineup
High-End Lineup
Under planning
High performance, on-chip MEMC/DMA
Higher performance Parallel execution
V850E2/Mxx V850E2/Mxx
Superscalar On-chip instruction cache & RAM On-chip SDRAM controller
Higher performance On-chip instruction cache On-chip USB
In mass production
V850E/ME2
150 MHz @ 215 MIPS 176-pin/240-pin
V850E/MA3
80 MHz @ 106 MIPS 144-pin/161-pin
V850Ex/Mxx
Higher performance Large-capacity internal memory
V850E/MA1
50 MHz @ 67 MIPS 144-pin/161-pin
Higher performance Large-capacity internal memory Enhanced peripheral functions
V850E/MA2
40 MHz, ROM-less 100-pin
V850E/MS1
33 MHz @ 47 MIPS 144-pin/157-pin
V850E/MS2
33 MHz, ROM-less 100-pin
Features
V850E/ME2
215 MIPS @150 MHz, internal 1.5 V/external 3.3 V operation ROM-less microcontroller Large-capacity internal RAM (128 KB), real-time control On-chip SSCG*, EMI peak reduction USB full-speed (function), on-chip debugging function On-chip SDRAM interface 176-pin LQFP/240-pin FBGA
V850E/MA1,MA2
67 MIPS @50 MHz Internal 3.3 V/external 5 V tolerant operation single-chip microcontroller (MA1) ROM-less product lineup also available 40 MHz @3.3 V ROM-less microcontroller (MA2) ROM/RAM: 256 KB/10 KB (MA1), ROM-less/4 KB (MA1, MA2) On-chip SDRAM interface, DMA 144-pin LQFP/161-pin FBGA (MA1), 100-pin LQFP (MA2)
*
Spread Spectrum Frequency Synthesizer Clock Generator
V850E/MA3
106 MIPS @80 MHz, internal 2.5 V/external 3.3 V operation single-chip microcontroller Large-capacity internal ROM/RAM (512 KB/32 KB) Internal single power supply flash SDRAM interface, motor control function, on-chip debugging function 144-pin LQFP/161-pin FBGA
V850E/MS1,MS2
47 MIPS @33 MHz, 3.3 V & 5 V single-chip microcontroller (MS1) ROM-less product (Max. 40 MHz) lineup available 33 MHz @ internal 3.3 V/external 5 V ROM-less microcontroller (MS2) ROM/RAM: 128 KB/4 KB (MS1), ROM-less/4 KB (MS1, MS2) 144-pin LQFP (MS1)/157-pin FBGA (MS1)/100-pin LQFP (MS2)
Product specifications
V850E/ME2 Item V850E1 CPU core 215 MIPS(@ 150 MHz) Performance 150 MHz Maximum operating frequency Internal flash memory Internal mask ROM Instruction RAM: 128 KB; Data RAM: 16 KB Internal RAM Instruction:8 KB Cache 1.35 V to 1.65 V (internal)Note Power supply voltage 3.0 V to 3.6 V (external) V850E/MA3 V850E1 106 MIPS(@ 80 MHz) 80 MHz 512 KB 512 KB/256 KB 32 KB/16 KB 2.3 V to 2.7 V (internal) 3.0 V to 3.6 V (external) V850E/MA1 V850E1 67 MIPS(@ 50 MHz) 50 MHz 256 KB 256 KB/128 KB/ROM-less 10 KB/4 KB 3.0 V to 3.6 V V850E/MA2 V850E1 40 MHz ROM-less 4 KB 3.0 V to 3.6 V V850E/MS1 V850E1 47 MIPS(@ 33 MHz) 33 MHz (internal ROM products) 40 MHz (ROM-less products) 128 KB 128 KB/96 KB/ROM-less 4 KB 3.0 V to 3.6 V (internal/external) (3 V products) 3.0 V to 3.6 V (internal) (5 V products) /4.5 V to 5.5 V (external) EDO DRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 8 ch CSIx2 ch, CSI/UART x 2 ch 10-bit x 8 ch 4 ch V850E/MS2 V850E1 33 MHz ROM-less 4 KB 3.0 V to 3.6 V (internal) /4.5 V to 5.5 V (external) EDO DRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 6 ch CSI/UART x 2 ch 10-bit x 4 ch 4 ch -
Memory controller External bus Timer/counter
Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
SDRAM, SRAM, etc. SDRAM, EDO DRAM, SRAM, etc. Address: Separate/multiplexed Address: Separate Data: 8/16 bits Data: 8/16 bits 16-bitx 9 ch 16-bit x 8 ch WDT x 1 ch CSI x 1 ch, CSI/UART x 1 ch CSI/UART x 3 ch, UART/I 2 C x 1 ch* CSIx1 ch, CSI/UART x 2 ch UART x 1 ch UART x 1 ch 10-bit x 8 ch 10-bit x 8 ch 10-bit x 8 ch 8-bit x 2 ch 4 ch 4 ch 4 ch ROM correction function PWM output: 2 ch USBx1 ch, on-chip debugging On-chip debugging function function (with trace), PWM output: 2 ch 112 115 78 528 mW (50 MHz @ 3.3 V) T.B.D. 200 mW (150 MHz @ 1.5 V) SDRAM, SRAM, etc. Address: Separate Data: 8/16/32 bits 16-bit x 12 ch 176-pin LQFP (24 x 24 mm) 240-pin FBGA (16 x 16 mm) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm)
SDRAM, SRAM, etc. Address: Separate Data: 8/16 bits 16-bit x 6 ch CSI/UART x 2 ch 10-bit x 4 ch 4 ch 79 416 mW (40 MHz @ 3.3 V) 100-pin LQFP (14 x 14 mm)
* : Only Y products have an on-chip I2C interface.
12
Pamphlet U15412EJ4V1PF
57 131 330 mW (40 MHz @ 3.3 V) 218 mW (33 MHz @ 3.3 V) 272 mW (33 MHz @ 3.3 V) 100-pin LQFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) 157-pin FBGA (14 x 14 mm) Note : 1.35 V to 1.65 V : @ 10 MHz to 133 MHz 1.40 V to 1.65 V : @ 10 MHz to 150 MHz
Application examples
MFP (Multifunction printer)
ASIC CCD S/H A/D
Image processing Shooting correction/ binarization
V850E/ME2
Instruction RAM 128 KB Data RAM 16 KB
RPU PORT INTC DMA
Engine controller
Multi Function Printer
Memory SDRAM For storing image data
Motor Control panel
PC
CPU
JPEG MH/MR/MMR
Communication ASIC system
SIO USB LAN IEEE1394
V850E/ME2
Document
ROM, Flash SRAM RTC
Browser function
Interface control circuit
Modem Image processing
NCU
Telephone network Printing paper
Printer engine
Thermal printer
Thermal Printer
ADC
Thermistor
4-phase PWM
Data Clock
Data latch
Applied STB
V850E/MA3
DVD player
Sensor
;;; ; ;;;
V850E/MA3
CPU
SRAM/ SDRAM
CG-ROM
Internal ROM (512 KB) Internal RAM (32 KB)
MEMC
Address/Data/Control DMARQ/DMAAK/TC
DMAC
ASIC
IEEE1284 interface controller USB interface controller
TMQ
SIO
Port
Uart
TMP
TxD/RxD
Distributed control
Driver
RS-232C driver/receiver
Stepping motor
Thermal head
Preceding stage processing block
Optical pickup unit Preceding stage processing processor
SDRAM
Latter stage processing block
DVD Player
Motor driver
V850E/MA2
Disk servo control
Optical disk control
Stream control
MPEG2 decoder
DAC ADC
Video amp Audio DAC
Display driver Remote control Key input Sub-CPU
V850E/MA2, V850ES/ST2
Flash memory
Fax machine
System bus Optical system Document
S/H CCD A/D
V850E/MS1
ROM: 128 KB MH/MR/MMR JBIG RAM 4 KB RPU
Image processing Shading correction/ binarization
Motor driver
PORT
Memory
INTC
Motor Operation panel
FAX Machine
SRAM
CPU
DMA
V850E/MS1
ROM
SIO
RAM for storing image data
Communication system AFE
NCU
Telephone network Paper
Printing system Watch Real-time clock Image processing Printer engine
Pamphlet U15412EJ4V1PF
serial interface
USB I/F
IEEE1284 I/F
13
Product Lineup
ASSP Lineup (1)
Field-specific lineups
V850E/MA3
On-chip inverter and timer, 80 MHz, 144-/161-pin In mass production Under development
Inverter control
On-chip inverter and timer
V850E/IA1
On-chip inverter and timer 50 MHz, 144-pin
V850E/IA3 V850E/IA2
Compact version 40 MHz, 100-pin Compact version 64 MHz, 80-pin
V850E/IA4
On-chip inverter and timer 64 MHz, 100-pin
V850ES/IK1
On-chip inverter and timer, 32 MHz, 64-pin
V850E/SV2 V850/SV1
3 V low-power version 176/180-pin, on-chip VCR servo timer Enhanced peripheral functions 257-pin version, on-chip VCR servo timer
DVC control
On-chip VCR servo timer
V850ES/PM1
On-chip 16-bit ADC
Power meter instrument measuring control
On-chip 16-bit ADC
Features
V850E/IA3, IA4
sFor inverter control s82 MIPS @ 64 MHz, internal 2.5 V/external 5 V operation sOn-chip 6-phase sinusoidal PWM timer, on-chip operational
amplifier/comparator, on-chip high-speed A/D
V850E/SV2
sFor camcorders (incl. DVC) s32-bit servo timer ideal for camcorder control, boundary scan
function, on-chip debugging function, and many other on-chip peripheral functions
sOn-chip debugging function (IA4 only) sROM/RAM: 256 KB/12 KB, 128 KB/6 KB (mask ROM version only) s80-pin QFP (IA3), 100-pin LQFP/100-pin QFP (IA4)
s55 MIPS @ 40.5 MHz, 2.5 V low-voltage/high-speed operation sLarge-capacity memory (ROM/RAM: 512 KB/24 KB) sInternal single-power-supply flash sCompact high-pin-count 257-pin FBGA (14x14 mm, 0.65 mm pitch)
V850ES/IK1
sFor inverter control s41 MIPS @ 32 MHz, 4.5 V to 5.5 V (on-chip regulator) sOn-chip 6-phase sinusoidal PWM timer, POC/LVI, and clock
monitor functions
V850ES/PM1
sFor power meter control sOn-chip high-resolution, high-accuracy 16-bit A/D converter sROM/RAM: 128 KB/10 KB, ROM-less/10 KB s29 MIPS @ 20 MHz, 3.0 V to 3.6 V operation s100-pin LQFP
sROM/RAM: 128 KB/6 KB, 64 KB/4 KB s64-pin LQFP Product specifications
Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
V850E/IA1 V850E1 67 MIPS (@ 50 MHz) 50 MHz 256 KB 256 KB 10 KB 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) Address: Multiplexed Data: 8/16 bits 16-bit x 8 ch CSI x 2ch, UART x 3ch 10-bit x (8 ch + 8 ch) 4 ch FCAN x 1 ch 83 630 mW (50 MHz @ 3.3 V) 144-pin LQFP (20 x 20 mm) V850E/IA2 V850E1 54 MIPS (@ 40 MHz) 40 MHz 128 KB 128 KB 6 KB 4.5 V to 5.5 V Address: Multiplexed Data: 8/16 bits 16-bit x 7 ch CSI x 1 ch, CSI/UART x 1 ch UART x 1 ch 10-bit x (6 ch + 8 ch) 4 ch 53 440 mW (40 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm)
V850E/IA3 V850E1 82 MIPS (@ 64 MHz) 64 MHz 256 KB 128 KB 12 KB/6 KB 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) -
V850E/IA4 V850E1 82 MIPS (@ 64 MHz) 64 MHz 256 KB 256 KB/128 KB 12 KB/6 KB 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) -
V850ES/IK1 V850ES 41 MIPS (@ 32 MHz) 32 MHz 128 KB 128 KB/64 KB 6 KB/4 KB 3.5 V to 5.5 V 16-bit x 7 ch WDT x 1 ch CSI x 1 ch, UART x 2 ch 10-bit x (4 ch+4 ch) ROM correction function, pull-up function, POC/LVI, clock monitor function 39 T.B.D. 64-pin LQFP (14 x 14 mm)
16-bi t x 8 ch 16-bit x 9 ch WDT x 1 ch WDT x 1 ch CSI x 1 ch, CSI/UART x 1 ch CSI x 1 ch, CSI/UART x 1 ch UART x 1 ch UART x 1 ch 10-bitx(4 ch + 2 ch), 8/10-bitx6 ch 10-bitx (4 ch + 4 ch), 8/10-bi tx 8 ch 4 ch 4 ch ROM correction function On-chip debugging and ROM correction functions operational amplifier, comparator, pull-up function Operational amplifier, comparator, pull-up function 50 64 175 mW 175 mW (64 MHz @ 2.5 V) (64 MHz @ 2.5 V) 80-pin QFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) 100-pin LQFP (14 x 14 mm)
14
Pamphlet U15412EJ4V1PF
Application examples
s Air conditioner
Compressor motor M
Power module Photocoupler
A/D converter
V850E1
64M Hz
SIO3ch N-Wire
ROM256K A/D16ch CSI
RAM12K
V850E/IA4
EVDD
PC2925
Timer 10ch
INT
UART
INT
VDD
WDT
EEPROM
A/D converter
Air Conditioner
;;;
Photocoupler
Power module
Fan motor
M
V850E/IA4
PWM
output
PWM
output
Indoor unit
s DVC
Camera control block A/D, CDS, SGC (camera pre-processing)
CCD
JPEG field memory
Lens driver
CCD driver
Camera DSP processing
Camera DSP SDRAM
Digital Video Camera
V850E/SV2
LCD panel S1 video input Mike Mike
System controller & servo control microcontroller LCD controller
V850E/SV2
OSD
;; ;;
Still picture and moving picture processing block
MPEG4
USB2.0
USB
JPEG
Card Interface
SD memory, etc.
JPEG SDRAM
IEEE1394
Moving picture processing DV processing IEEE1394
DV processing SDRAM Video head
M
Head amplifier Audio & video I/O interface
Loading
M
s Power meter
Power Meter
V850ES/PM1
3-phase 3-wire
; ;; ;;; ;; ;; ;; ;;
Motor driver (motor control)
Drum
M
Capstan
System control/servo control block
V850ES/PM1
ROM
RAM
LCD display
16-bit A/D
32bit RISC CPU Timers PMWs WDT RTC CSI CSI UART
On-chip LCD C/D 8-bit microcontroller
EEPROM
Communication function block
Main clock 20 MHz
Subclock 32 kHz
Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
V850/SV1 V850 23 MIPS (@ 20 MHz) 20 MHz 384 KB/256 KB 384 KB/256 KB/192 KB 16 KB/8 KB 3.1 V to 3.6 V @ 20 MHz 2.7 V to 3.6 V @ 16 MHz Address: Multiplexed Data: 16 bits 24-bit x 2 ch, 16-bit x 2 ch 8-bitx8ch, WDT x 1 ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I 2 C x 2 ch* 10-bit x 16 ch 6 ch (internal RAM-on-chip peripheral I/O) ROM correction function, dedicated PWM output x 4, Hsync/Vsync separation circuit 151 82 mW (20 MHz @3.3 V) 176-pin LQFP (24 x 24 mm) 180-pin FBGA (13 x 13 mm)
V850E/SV2 V850E1 55 MIPS (@ 40.5 MHz) 40.5 MHz 512 KB 512 KB 24 KB 2.3 V to 2.7 V (internal) 2.7 V to 3.6 V (external) Address: Multiplexed/separate Data: 8/16 bits 32-bit x 1 ch, 16-bit x 12 ch 8-bit x 12 ch, WDT x 1 ch CSI x 5 ch, CSI/UART x 1 ch, UARTx1 ch, I 2 C x 1 ch* 10-bit x 24 ch 4 ch On-chip debugging function, boundary scan function ROM correction function, dedicated PWM output: 5 ch 195 134 mW (40.5 MHz @ 2.5 V) 257-pin FBGA (14 x 14 mm)
V850ES/PM1 V850ES 29 MIPS (@20 MHz) 20 MHz 128 KB/ROM-less 10 KB 3.0 V to 3.6 V @ 20 MHz, 2.7 V to 3.6 V @ 10 MHz, 2.2 to 3.6 V @ 32.768 kHz Address : Separate Data : 8/16 bits 16-bit x 6 ch, 8-bit x 2 ch WDT x 1 ch CSI x 2 ch, UART x 2 ch 16-bit x 6 ch ROM correction function, dedicated PWM output: 4 ch Real-time counter (watch function) 80 81 mW (20 MHz @3.3 V) 100-pin LQFP (14 x 14 mm)
* : Only Y products have an on-chip I2C interface.
Pamphlet U15412EJ4V1PF
15
Product Lineup
ASSP Lineup (2)
Field-specific lineups
V850/DB1
On-chip meter driver, On-chip DCAN, On-chip LCD driver, In mass production Under development Under planning
Dashboard control
On-chip meter driver On-chip LCD driver
V850ES/FE2
FF2
80-pin
FG2
100-pin
FJ2
144-pin
Body control
On-chip CAN
64-pin Large-capacity internal flash, on-chip aFCAN, on-chip LIN, POC/LVI
V850/SC2
5 V low-power version 19 MHz, 144-pin, IEBus
Larger capacity
V850ES/SJx
Car audio control
V850ES/SJ2
3 V low-power version 20 MHz, 144-pin, On-chip aFCAN/On-chip IEBus
V850/SC3
5 V low-power version 16 MHz, 144-pin, FCAN
V850ES/SGx
Peripheral function/ memory capacity Optimization
Larger capacity
V850/SF1
5 V low-power version 16 MHz, 100-pin, FCAN
On-chip CAN/ On-chip IEBus Low noise
V850/SB2
5 V low-power version 19 MHz, 100-pin, IEBus
V850ES/SG2
3 V low-power version 20 MHz, 100-pin, On-chip aFCAN/On-chip IEBus
V850ES/SGx
Features
V850/DB1
sFor automotive electronics (body control applications) sROM/RAM : 128 KB/6 KB sOn-chip DCAN controller (2 ch max.) s18 MIPS @ 16 MHz, 4.0 to 5.5 V operation s128-pin QFP
V850ES/FE2, FF2, FG2, FJ2
sFor automotive electronics (body control applications) sOn-chip large-capacity single-power-supply flash memory sROM/RAM: 512 KB/20 KB, 384 KB/16 KB, 256 KB/12 KB,
128 KB/6 KB
sOn-chip aFCAN controller (4 ch max.), LIN function
compatible UART, POC/LVI
s29 MIPS @ 20 MHz, 4.0 to 5.5 V operation
V850ES/SG2, SJ2
sFor car audio sOn-chip large-capacity single-power-supply flash memory sROM/RAM : 640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB, 256 KB/24 KB (SG2 only) sOn-chip IEBus controller (1 ch), on-chip aFCAN controller (2 ch max.) s29 MIPS @ 20 MHz, 2.85 to 3.6 V operation s5 V withstand voltage ports incorporated, and 5 V output is possible
by setting the N-ch open-drain output
s64-pin TQFP (FE2)/80-pin TQFP (FF2)/100-pin LQFP
(FG2)/144-pin LQFP (FJ2)
V850/SF1
sFor car audio sLow EMI noise sOn-chip FCAN controller (2 ch max.) sROM/RAM: 256 KB/16 KB, 128 KB/12 KB s100-pin LQFP/100-pin QFP
sOn-chip debugging function s100-pin LQFP/100-pin QFP (SG2), 144-pin LQFP (SJ2) Product specifications
Item
FE2 FF2
CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
128 KB/64 KB 128 KB/64 KB 6 KB/4 KB
256 KB/128 KB 256 KB/128 KB 12 KB/6 KB
V850ES/Fx2 FG2 V850ES 29 MIPS (@ 20 MHz) 20 MHz 384 KB/256 KB/128 KB 256 KB/128 KB 16 KB/12 KB/6 KB 4.0 V to 5.5 V -
FJ2
384 KB/256 KB 16 KB/12 KB
512 KB 20 KB
16-bit x 6 ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, LIN-compatible UART x 2 ch 10-bit x 10 ch aFCAN x 1 ch 51 64-pin TQFP (10 x 10 mm) 67 155 mW (20 MHz @ 5 V) 80-pin TQFP (12x12 mm) 10-bit x 12 ch
16-bit x 7 ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, LIN-compatible UART x 3 ch 10-bit x 16 ch -
Address: Multiplexed bus Data: 8/16 bits 16-bit x 8 ch WDT x 1 ch, watch timer x 1 ch CSI x 3 ch, LIN-compatible UART x 3 ch CSI x 3 ch, LIN-compatible UART x 4 ch 10 bit x 24 ch 4 ch
POC/LVI function, clock monitor function, RAM hold flag aFCAN x 2 ch 84 200 mW (20 MHz @ 5 V) 100-pin LQFP (14 x14 mm)
aFCAN x 4 ch 128 144-pin LQFP (20 x 20 mm)
16
Pamphlet U15412EJ4V1PF
V850/SB2
Low EMI noise Large-capacity memory and large memory selection ROM/RAM:512K/24KB, 384KB/24KB, 256KB/16KB, 128KB/8KB On-chip IEBus controller (1 ch) 100-pin QFP/100-pin LQFP
V850/SC2,SC3
Low EMI noise Large-capacity memory (ROM/RAM: 512 KB/24 KB) Enhanced peripheral functions for SB1 On-chip IEBus controller (V850/SC2 : 1 ch) , On-chip FCAN controller (V850/SC3 : 2 ch max.) 144-pin LQFP
Application examples
Dashboard
Integrated body control unit
Battery voltage (12 V) Power supply unit
V850ES/Fx2
Dashboard
Input interface
CPU General-purpose I/O 10-bit A/D converter
V850ES/Fx2
Serial I/O Interrupt controller LIN controller CAN controller
External I/O interface
Switch inputs * Mirror fold-in switch * Left-right switching switch * Ignition switch * Light control switch * Courtesy lamp switch * Door lock switch
Timer unit
General-purpose I/O
Output interface
Internal memory ROM/RAM
* Headlamp control * Tail lamp control * Warning indicator * Power window (passenger seat) control * Power window (rear right seat) control * Power window (rear left seat) control * Lighting equipment control * Dashboard control module * Driver seat door module * Passenger seat door
Analog input * Sensor inputs
Car audio
Antenna
speaker
Tuner unit
PLL CD unit
Microcontroller (CD control)
MPX
Audio DSP (or electronic volume)
Power amplifier
Power supply block
Regulator
Car Audio
V850ES/Kx1 PD703229
RF
Battery (continuous power supply) ACC (power supply when engine on) Display unit Driver
Microcontroller (CD control)
Power supply detection IC
V850/SF1
Driver
DAC servo
ASSP for CD PD63761
DSP MP3,WMA
V850/SBx, SF1,SCx V850ES/Sx2
CAN, IEBus driver
Microcontroller
(Display/key control)
V850E/ MA1,MA3
KEY
MD unit
4/8 stage LCD
Automotive communication (CAN, IEBus, etc.) CD (MD) changer unit
Power supply system signal Audio system signal
Item CPU core Performance Maximum operating frequency Internal flash memory Internal mask ROM Internal RAM Power supply voltage External bus Timer/counter Serial interface A/D converter D/A converter DMA controller Other peripheral functions I/O Power consumption (mask ROM version, Typ.) Package
V850/SB2 SC2 V850 22 MIPS (@ 19 MHz) 19 MHz/13 MHz (main clock) 32.768 kHz (subclock) 512 KB/384 KB/256 KB 512 KB/384 KB/256 KB/128 KB 24 KB/16 KB/8 KB 4.0 V to 5.5 V Address: Multiplexed/separate Data: 16-bits 16-bit x 2 ch, 8-bit x 6 ch WDT x 1 ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I2C x 2 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) IEBus x 1 ch ROM correction function 83 125 mW (19 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm)
V850/SCx SC3 V850 21 MIPS (@ 19 MHz) 19 MHz (main clock) 32.768 kHz (subclock) 18MIPS (@ 16 MHz) 16 MHz (main clock) 32.768 kHz (subclock)
V850/SF1 V850 18 MIPS (@ 16 MHz) 16 MHz 256 KB 256 KB/128 KB 16 KB/12 KB 3.5 V to 5.5 V (mask version), 4.0 V to 5.5 V (flash version) 3.5 V to 5.5 V @ 32.768 kHz Address: Multiplexed Data: 16-bit 16-bit x 8ch WDT x 1ch, watch timer x 1 ch CSI x 1 ch, CSI/UART x 2 ch CSI/I2C x 1 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) FCAN x 2 ch, ROM correction function 84 75 mW (16 MHz @ 5 V) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm)
V850/DB1 V850 18 MIPS (@ 16MHz) 16 MHz 128 KB 128 KB 6 KB 4.0 V to 5.5 V 16-bit x 3 ch, 8-bit x 2 ch WDT x 1 ch, watch timer x 1 ch CSI x 3 ch, UART x 2 ch 10-bit x 8 ch meter controlPWM (8-bit) x 24 ch DCAN x 2 ch (flash version)/1 ch (mask version) 107 120mW (16 MHz @ 5V) 128-pin QFP (20 x 20 mm)
512 KB 512 KB 24 KB 3.5 V to 5.5 V (mask version) 4.0 V to 5.5 V (flash version) Address: Multiplexed Address: Multiplexed/separate Data: 16-bit Data: 16-bits 16-bit x 10ch WDT x 1 ch, watch timer x 1 ch CSI x 2 ch, CSI/UART x 2 ch UART x 2 ch, CSI/I2C x 2 ch 10-bit x 12 ch 6 ch (internal RAM-on-chip peripheral I/O) FCAN x 2 ch IEBus x 1 ch ROM correction function ROM correction function 124 110 mW (16 MHz @ 5 V) 120 mW (19 MHz @ 5V) 144-pin LQFP (20 x 20 mm)
Pamphlet U15412EJ4V1PF
17
Product Lineup
; ; ; ; ; ; ; ; ; ; ; ;
640K 512K 384K 256K 192K 128K 96K
Memory Lineup
Flash memory version Mask ROM version Mask ROM/flash memory version
SJ2* SJ2 SG2* SG2 MA3* FJ2* SV2 SC3 SC2 SC1 SB2 SB1 SV1 FG2* FJ2* SV1 SA1 V853 MA1 IA1 IA4 IA3 KF1+* KF1* FJ2* FG2* FF2* MA3* SA3 SA2 KJ1+* KJ1* KG1+* KG1* SV1 SF1 SB2 SB1 SV1 MA1 MS1 KE1+* KE1 SA1 V853 IK1* IA4 IA3 IA2 KJ1+* KJ1 KG1+* KG1 KF1+* KF1 DB1 FE2* FF2* FG2* MS1 KG1 KF1 V853 KJ1 SB2 SB1 SA2 MA1 PM1 SF1 SG2* SB2 SB1 SJ2* SJ2 SG2 3229Y MA3* MA3* MA3 SJ2* SG2*
; ; ;
64K ROM less
18
IK1* KF1 KG1 SA1 FE2* MS1 MS2 MA1 MA2 PM1 ME2
Instruction RAM : 128KB
ST2*
ROM Size (bytes)
4K
RAM size (bytes)
6K
8K
10K
12K
16K
20K
24K
32K
40K
48K
* : Under development
Pamphlet U15412EJ4V1PF
Package Lineup
No. of pins Type Size Pitch Thickness Mounted products
121 pins FBGA (F1) 12x12 mm 0.8 mm 1.13 mm SA1, SA3
No. of pins Type Size Pitch Thickness Mounted products
64 pins LQFP (GB) 10x10 mm 0.5 mm 1.4 mm KE1, KE1+
No. of pins Type Size Pitch Thickness Mounted products
161 pins FBGA (F1) 13x13 mm 0.8 mm 1.13 mm MA1, MA3
No. of pins Type Size Pitch Thickness Mounted products
64 pins TQFP (GB) 10x10 mm 0.5 mm 1.0 mm FE2
No. of pins Type Size Pitch Thickness Mounted products
100 pins LQFP (GC) 14x14 mm 0.5 mm 1.4 mm
KG1, KG1+, SA1, SB1, SB2, SF1, SG2, PM1, FG2, MS2, MA2, IA2, IA4, V853, PD70F3229Y, 703229Y
No. of pins Type Size Pitch Thickness Mounted products
180 pins FBGA (F1) 13x13 mm 0.8 mm 1.13 mm SV1
No. of pins Type Size Pitch Thickness Mounted products
64 pins TQFP (GK) 12x12 mm 0.65 mm 1.0 mm KE1, KE1+
No. of pins Type Size Pitch Thickness Mounted products
120 pins TQFP (GC) 14x14 mm 0.4 mm 1.0 mm ST2
No. of pins Type Size Pitch Thickness Mounted products
157 pins FBGA (F1) 14x14 mm 0.8 mm 0.96 mm MS1
No. of pins Type Size Pitch Thickness Mounted products
80 pins TQFP (GK) 12x12 mm 0.5 mm 1.0 mm KF1, KF1+, FF2
No. of pins Type Size Pitch Thickness Mounted products
100 pins QFP (GF) 14x20 mm 0.65 mm 1.4 mm KG1, KG1+, SB1, SB2, SF1, SG2, IA2, IA4
No. of pins Type Size Pitch Thickness Mounted products
257 pins FBGA (F1) 14x14 mm 0.65 mm 1.13 mm SV2
No. of pins Type Size Pitch Thickness Mounted products
64 pins LQFP (GC) 14x14 mm 0.8 mm 1.4 mm IK1
No. of pins Type Size Pitch Thickness Mounted products
128 pins QFP (GJ) 20x20 mm 0.5 mm 1.4 mm DB1
No. of pins Type Size Pitch Thickness Mounted products
240 pins FBGA (F1) 16x16 mm 0.8 mm 1.13 mm ME2
No. of pins Type Size Pitch Thickness Mounted products
80 pins QFP (GC) 14x14 mm 0.65 mm 1.4 mm KF1, KF1+, IA3
No. of pins Type Size Pitch Thickness Mounted products
144 pins LQFP (GJ) 20x20 mm 0.5 mm 1.4 mm
KJ1, KJ1+, SC1, SC2, SC3, SJ2, ST2, FJ2, MS1, MA1, MA3, IA1
No. of pins Type Size Pitch Thickness Mounted products
100 pins TQFP (GC) 14x14 mm 0.5 mm 1.0 mm SA2
No. of pins Type Size Pitch Thickness Mounted products
176 pins LQFP (GM) 24x24 mm 0.5 mm 1.4 mm SV1, ME2
Pamphlet U15412EJ4V1PF
19
CPU Roadmap
Performance range of 20 to over 300 MIPS with single instruction set
V850E2 CPU cores
V850E2 CPU cores 400 MHz V850E2 CPU cores 266 MHz V850E2 CPU cores 200 MHz
1000 800 to S MIP
* Utilization of existing software resources * Maintenance of real-time performance * Pursuit of low power consumption
V850E1 CPU cores
215 MIPS @ 150 MHz
Under planning Under development In mass production
143 MIPS @ 100 MHz
96 MIPS @ 66 MHz
43 MIPS @ 32 MHz 38 MIPS @ 33 MHz 29 MIPS @ 20 MHz 23 MIPS @ 20 MHz
V850 CPU cores
V850ES CPU cores
CPU Core Function Comparison
CPU Core Function
Maximum operating frequency Instructions Maximum program memory space Maximum data memory space Higher performance
V850
20/33 MHz 47 16 MB 16 MB 5-stage pipeline Harvard architecture
V850ES
20/32 MHz 80 16 MB 16 MB
V850E1
66100150 MHz 80 64 MB 256 MB
V850E2
200266400 MHz 89 512 MB (internal 128 MB) 4 GB
* 7-stage pipeline
Simultaneous execution of 2 instructions with 3 pipelines that can operate independently from each other
Improved pipeline * Non-blocking load/store instructions - Parallel instruction execution (instruction execution in internal ROM) * Addition of branching/load pipe * Shift to 3-operand manipulations in 1 slot Addition of C language compatible instructions (Switch instruction, Callt instruction, data conversion instruction, Prepare/Dispose instruction)
High code efficiency
2-byte instructions CISC instructions
32-bit relative branch instruction 3-operand instruction Sum-of-products instruction Bit search instruction
Multiplier
16x16 bits32 bit multiplication
16x16 bits32-bit operation 16x16 bits 32-bit operation 32x32 bits64-bit operation 32x32 bits64-bit operation (32-bit multiply instruction support) 4 to 10 clocks
Interrupt responsiveness
11 to 18 clocks
20
Pamphlet U15412EJ4V1PF
System LSI Support
Use of same development methods for standard V850 Series products, ASIC microcontrollers
Quick market introduction of standard products System optimization through shift to system LSIs
CPU core development considering system LSIs
Release of cores that support on-chip debugging 2-stage structure consisting of 32-bit sync system bus & 16-bit async peripheral function bus Large choice of peripheral function macros
;;;;;;;; ;;;;;;; ;;;;;;;;;;; ;;;;;;;; ;;;;
0.35m CB-9VX/VM 0.25m CB-10VX 0.18m CB-12L 0.18m CB-12M 0.13m CB-130L
V850E1 system configuration example
NPB: Peripheral I/O bus VSB: System bus VFB: Internal instruction bus VDB: Internal data bus
Many supported processes and large range of required performance, and power consumption
V850E1 system
NBU85ET Instruction Cache interface cache Instruction memory Data memory
VFB
TIMER
NPB
NPB I/F CPU Core VSB I/F DMAC DCU INTC
VSB
PWM CSI
MEMC NBT85E500
UART PORT etc ...
VDB
JTAG
User circuit (UDL)
External bus
UDL1 JTAG IE Flash memory UDL2
IP RAM
SRAM
I/O
V850E2 system configuration example
NPB: Peripheral I/O bus VSB: System bus iLB: Internal instruction bus dLB: Internal data bus
Instruction memory Data memory iLB
V850E2 system
NBA85E2S NPB I/F CPU core INTC I/F VSB I/F DCU
JTAG
Instruction cache
TIMER
NPB
PWM Arbiter CSI UART PORT etc ...
dLB
INTC QL85E70x
VSB
RCU
Data cache
MEMC NBT85E535
DMAC NBA85E300
User circuit (UDL) External bus UDL1 JTAG IE Flash memory UDL2 IP RAM
SDRAM
SRAM
I/O
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21
V850 Series Common Architecture
The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following features.
5-stage pipeline processing 2-byte basic instruction set 32-bit barrel shifter
Harvard architecture Support of CISC-like instructions
32 general-purpose registers Multi-status flags
Simple addressing DSP function
5-stage pipeline processing
The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock.
Internal system clock
Instruction1 Instruction2 Instruction3 Instruction4 Instruction5 Instruction6 IF ID EX MEM WB
IF
ID IF
EX ID IF
MEM EX ID IF
WB MEM EX ID IF WB MEM EX ID IF
Instruction1 completion Instruction2 completion
WB MEM EX ID
Instruction3 completion
WB MEM EX
Instruction4 completion
WB MEM
Instruction5 completion
WB
Instruction6 completion
: Instruction fetch : Instruction decode : Instruction execution : Memory access to target address : Write execution result to register
An instruction is executed each clock
Harvard architecture
The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely independently from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution.
CPU Instruction fetch Instruction bus
BCU
In the case of an architecture other than the Harvard architecture, the MEM stage of instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2 and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the pipeline operation to become disordered and lowers the instruction execution speed.
Pipeline Operation of Non-Harvard Architecture Internal ROM External memory Operand data access Data bus On-chip peripheral I/O
Instruction1 Instruction2 Instruction3 Instruction4 Instruction5 ---:Idles inserted due to bus wait
IF
ID IF
EX ID IF
MEM
-----
WB EX ID IF MEM
-----
WB EX ID IF MEM EX ID WB MEM EX WB MEM WB
Internal RAM
22
Pamphlet U15412EJ4V1PF
32 general-purpose registers
The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the development environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency and execution performance.
Comparison of Performance/Object Efficiency According to Number of Registers
Byte count (bytes) 4000 Execution time (s) 12
For example, looking at the program execution time and code size changes when the number of registers used by the compiler is changed using the servo control module, we can see that the larger the number of registers, the better the program execution speed and the smaller the code size. However, from about 26 registers, the improvement in terms of execution speed and code size becomes smaller, and in the neighborhood of 32 registers, there are no more changes. This is why the V850 Series has been provided with 32 registers as the strict minimum requirement.
3000
9
2000
6
1000
3
0
16
18
20
22
24 Byte count
26
28
30
32
0
Used C program: Servo control module
Execution time
Number of registers
Software register bank
The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs. Unused registers can be used as a software register bank for which save and restore processing is not required during interrupt servicing or task switching, which increases the processing speed.
Register bank interrupt Program execution Interrupt servicing instruction execution Actual interrupt servicing time Program execution
Save the program counter, etc., to a save register. Execute the interrupt restore instruction. Restore the program counter value, etc., from the save register.
Program execution
Normal interrupt
Program execution
Interrupt servicing instruction execution Actual interrupt servicing time User interrupt servicing routine execution time Total interrupt servicing time
Save general-purpose registers to stacks. Restore general-purpose registers from stacks.
General-purpose register configuration
31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 31 PC 0 Zero Register Reserved for Address Generation Stack Pointer(SP) Global Pointer(GP) Text Pointer(TP)
Name Application Operation
System register configuration
No. 0 1 2 3 System Register Name EIPC EIPSW FEPC FEPSW ECR PSW CTPC CTPSW DBPC DBPSW CTBP Reserved x x x Operand Specification LDSR STSR Register for saving status during interrupt Register for saving status during NMI Interrupt source register Program status word Register for saving status during CALLT execution Register for saving status during exception/debug trap CALLT base pointer Application
r0 r1
Zero register Assembler reservation
Always holds "0" Used as working register for address generation
r2
Address/data variable register (If real-time OS being used does not use r2)
r3
Stack pointer Global pointer Text pointer
Used for stack frame generation during function call Used when accessing global variables in the data area Used as register for specifying the beginning of the text area (program code allocation) Supported by other than V850 CPU core products
4 5 16 17 18 19 20 6-15, 21-31
r4 r5
r6-r29
Element Pointer(EP) Link Pointer(LP) 0 Program Counter
Address/data variable register Element pointer Used as base pointer for address generation during memory access Used during function call by compiler
r30
x : Access prohibited : Access enabled
LDSR: Instruction to load general-purpose register contents to system register STSR: Instruction to store system register contents to general-purpose register
r31 PC
Link pointer
Program counter Holds instruction addresses during program execution
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Simple addressing
The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline operation. As a result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the performance becomes difficult. The V850 Series avoids this problem by supporting only simple addressing.
Pipeline Processing Time and CPU Operating Frequency
In case of excessive addressing In case of simple addressing
Pipeline processing sequence Instruction fetch Address calculation Operating frequency held back by slow processing Execution Memory access Writeback All processing is standardized and efficient
Processing time
Processing time
Addressing mode
Instruction addresses
*Relative addressing (PC dependent)
Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter.
31 0 26 25 PC 0
Operand addresses
*Register addressing
Addressing that accesses the general-purpose register specified by the general-purpose specification field or a system register as an operand.
*Immediate addressing
Addressing of 5-bit data or 16-bit data for manipulation in the instruction code.
0 disp22
31 Signed extension
22 21
*Based addressing
31 0 26 25 PC Memory subject to manipulation 0
31 reg1 31 Signed extension 16 15 disp16
0
Addressing that accesses memory, with the sum of the contents of the generalpurpose register (reg1) and 16-bit displacement (disp16) as the operand address.
0
Memory subject to manipulation
*Register addressing (register indirect)
Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC).
31 26 25 reg1 0
*Bit addressing
Addressing that accesses 1 bit of 1 byte of the memory space, with the sum of the contents of the generalpurpose register (reg1) and 16-bit displacement (disp16) that has been sign extended to word length as the operand address.
31 reg1
0
31 Signed extension
16 15 disp16
0
Memory subject to manipulation
31 0
26 25 PC
0 Memory subject to manipulation
2-byte basic instruction set
The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent to 16-bit CISC microcontrollers.
*Improved object efficiency through ROMization programming
Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/ logic operations, and branching.
Object Code Size Comparison (Dhrystone 1.1/Large model)
16-bitV(CISC) 78K4(CISC) V850(RISC) VR/MIPSTM32(RISC)
1.00
*To realize ease of use, restrictions on 16-bit fixed-length instructions are partially removed through incorporation of 32-bit instructions. *Bit manipulation instructions, etc.
1.03
1.02 1.48
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Pamphlet U15412EJ4V1PF
CISC-like instructions for embedding (bit manipulation instructions)
The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in embedding control.
* Improvement of operability of memory mapped I/ Os for control purposes * Manipulation of any 1 bit of byte data in the memory space * Provision of test (tst1)/set (set1)/clear (clr1)/invert (not1) * Effective for reducing object size and execution time since flags can be manipulated in 1-bit units with 1 instruction Example: Setting (1) bit 6 of ASIM00 register
Item Coding example
Bit Manipulation Instruction set1
When Used
6, ASIM00[r0] ld.b ori st.b ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0]
When Not Used
add st.w ld.b ori st.b ld.w add -4, sp Save r20 r20, 0[sp] ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] 0[sp], r20 Restore r20 4, sp
Object size Execution time
4 bytes 4 clocks
12 bytes 4 clocks
24 bytes 8 clocks
Multi-status flags
In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC microcontrollers.
Example: Program that branches to positive/negative/zero according to register contents
CISC Microcontroller cmp jz jgt jmp ax, 0 ZERO PLUS MINUS cmp bz bgt br V850 0, r10 ZERO PLUS MINUS Other Manufacturer's RISC Microcontroller cmp/eq bt cmp/pl bt bra nop #0, r10 ZERO r10 PLUS MINUS ;For delay branching
* Easy recording with assembler * Improved object efficiency and execution speed
ZERO : Zero processing PLUS : Positive processing MINUS : Negative processing
DSP function
The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital signal processing such as image and speech processing.
* Direct data handling via general-purpose registers * Realization of digital signal processing through generalpurpose CPU * High-speed 16-bit (V850, V850ES CPU), 32-bit (V850E1 CPU) multiply/sum-of-products (Multiply: 1 to 2 clocks, sum-of-products: 3 clocks) * Effective for filter operations and matrix operations for feedback calculations in speed, position, and other servo control.
CPU SAT flag MUL ALU INT
V850
General-purpose register CPU
CPU+DSP
DSP
MUL ALU
Memory
32-bit barrel shifter
V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock.
* Shifting of any number of bits (0 to 31) executable in 1 instruction per clock Improved execution speed/object efficiency Effective for extracting arbitrary bit lengths of image data and signed data (extracting code during MH/MR/MMR encoding, etc.) Example: 27-bit logical right shift
Other manufacturer's V850 RISC microcontroller Processing sequence SHR16 SHR8 SHR2 SHR 4 4 Rn Rn Rn Rn Number of instructions 1 SHR 27, Rn
Number of execution clocks 1
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V850E1, V850ES Architecture
The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following improvements to the V850 CPU core.
Non-blocking load/store
* Improved bus use efficiency * Shorter interrupt insensitivity period
Addition of branch/load pipes
* 2-clock branching * Parallel execution of instructions
Shift to 3-operand manipulations in 1 slot
* Improved absolute performance * Example: Synchronous processing of mov + add
Addition of high-level language-compatible instructions
* Improved code efficiency * 10 to 15% improvement in object efficiency mainly when C compiler used
Pipeline configuration
Master Pipeline (V850 CPU compatible) ID IF br/sld Pipeline ID Address calculation stage EX DF WB
Non-blocking load/store
Conventional (V850 CPU) Pipeline is stopped until MEM stage complete Load instruction ADD instruction Next instruction V850E1 CPU Load instruction ADD instruction Next instruction IF ID IF EX ID IF MEM (external memory) T1 T2 T3 EX ID WB (MEM) EX WB MEM WB
Async WB Pipeline MEM WB
Load, store buffer (1 stage each)
Effective pipeline processing that uses the Async WB Pipeline when appropriate, according to the instruction. IF ID IF EX ID IF MEM (external memory) T1 T2 EX ID DF EX WB WB MEM WB
IF (Instruction fetch) ID (Instruction decode) EX (ALU, multiplier, barrel shifter execution) MEM (Memory access) WB (Writeback) DF (data fetch)
: Fetches instructions and increments the fetch pointer. : Decodes instructions, creates immediate data, and reads registers. : Executes decoded instructions. : Accesses memory of corresponding addresses. : Writes execution results to registers. : Transfers execution data to WB stage.
Addition of branch/load pipes
*Pipeline operation with branch instruction
Conventional (V850 CPU) Branch instruction Branch destination determined in EX stage
*Parallel instruction execution (when executed by internal ROM)
Conventional (V850 CPU) ADD instruction (16-bit length) Branch instruction (16-bit length) Next instruction IF ID EX ID (MEM) EX WB MEM IF WB ID EX MEM
IF
ID
EX
MEM
WB
Branch destination instruction
IF
ID
EX
MEM
WB
Branch destination determined in ID stage
V850E1 CPU
V850E1 CPU 1-clock reduction Branch instruction
ADD instruction IF ID ID EX MEM IF DF WB ID
2-clock reduction WB
IF
ID
MEM
WB
Branch instruction
Branch destination instruction
IF
ID
EX
MEM
WB
Next instruction EX MEM WB
* The next branch instruction code is also fetched due to the internal 32-bit bus.
Shift to 3-operand manipulations in 1 slot
Conventional (V850 CPU)
mov add r20(src2), r22(src2), r21(dst) r21(dst)
Addition of high-level language compatible instructions
The V850E1 and V850ES cores have enhanced the instruction set of the V850 core as follows.
switch (2 bytes)
* C language switch statement processing converted into instruction
* Sequence from mov to arithmetic instruction is detected in the ID stage, and if dst is the same, the next manipulation is performed. src1 src2 dst : Replace with src2 of mov : src2 of arithmetic instruction : As is
mov imm32, reg (6 bytes/2 clocks)
* Reduction of address setting code
mul/mulu (4 bytes)
* Reduction of array address calculation * Improvement of sum-of-products performance
* mov + add instructions executable in 1 clock V850E1 CPU add r22(src2), r20(src1), r21(dst)
callt (2 bytes)/ctret (4 bytes)
* Table-reference branching * Reducing size of call code that frequently appears
Other
* Bit manipulation (register indirect bit specification) * cmov (Conditional Move), divide (div/divu/ divhu) * sasf, endian conversion
Data conversion instructions (2 bytes)
* char, short type cast executed with 1 instruction * sxh, sxb, zxb, and zxh instructions
prepare/dispose (4 bytes)
* Function start/end processing executed in 1 instruction
unsigned Load
* Reduction of unsigned manipulation code
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Pamphlet U15412EJ4V1PF
V850E2 Architecture
V850E2 core features
Real-time performance of 250 MIPS
- Operation at over 200 MHz
V850E2 core Main added functions
32-bit relative branch instruction
- Support of program space expansion - Long-distance branching performance, elimination of code efficiency losses
Inheritance of V850E1 performance and features
- Upward instruction compatibility with V850E1 and V850ES cores at object level - Use of 7-stage pipeline - Parallel pipeline configuration (2 parallel superscalar) - 128-bit instruction fetch bus
3-operand instructions (addition of target operations)
- Higher speed processing of operations such as multiplex add/subtract (64-bit operation, saturate operation) and bit shift, contributing to higher code efficiency
Sum-of-products instruction
- Higher speed 32-bit sum-of-products operation (32 x 32 + 64 64 bits)
Support of expanding application software sizes
- Address space (program/data) expansion - Strengthened cache memory support
Bit search instruction
- Bit row change point search for run length measurement, contributing to increased speed of conversion from integers to floating decimals, etc.
V850E2 core CPU pipeline configuration
2 instructions simultaneously executable using 2 instruction execution units
Instruction execution pipeline right (Rpipe)
Instruction fetch pipeline (Fpipe)
Instruction decode unit R
BSFT unit
Instruction fetch unit (Bpipe)
ALU unit
Instruction buffer
MUL unit
Instruction execution pipeline left (Lpipe)
Instruction decode unit L
ALU unit
MEM unit
Instruction memory, instruction cache
Data memory, data cache
V850E2 core CPU pipeline operation
Execution of up to 2 instructions/clock possible (dependent on instruction set)
Time flow Internal system clock Processing simultaneously performed by CPU Instruction1 ......
IF DP ID EX ID IF DP ID EX ID IF DP ID EX ID IF DP ID EX ID IF DP ID EX ID IF DP ID EX
WB WB WB WB WB WB
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
<12>
ID
EX
AT
DF
WB
Instruction2 ...... Instruction3 ................. Instruction4 ................. Instruction5 ............................ Instruction6 ............................ Instruction7 ...................................... Instruction8 ...................................... Instruction9 ................................................. Instruction10 .................................................
EX
AT
DF
WB
EX
AT
DF
WB
EX
AT
DF
WB
EX
AT
DF
WB
Instruction11 ............................................................ IF : Instruction fetch DP : Dispatch ID : Instruction decode EX : Instruction execution AT : Address transfer DF : Data fetch WB : Writing execution result to register Instruction12 ............................................................
EX
AT
DF
WB
Instruction 2 Instruction 4 Instruction 1 Instruction 3 Instruction 5 Instruction 7 Instruction 9 Instruction 11 completion completion Instruction 6 Instruction 8 Instruction 10 Instruction 12 completion completion completion completion completion completion
Instructions executed at each clock
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Write back unit
Dispatch unit
Register file
27
Memory Access Functions
SDRAM controller
Products: V850E/MA1, MA2, MA3, ME2 SDRAM connectable without external circuit CAS latency: 2, 3 supported CBR (automatic) refresh: Self refresh supported
DMA controller (provided in V850E products)
Products: V850E/MA1, MA2, MA3, MS1, MS2, IA1, IA2, IA3, IA4, ME2, SV2 Transfer targets: Memory-peripheral I/O, memorymemory Transfer mode: Single, single step, block transfer Transfer units: 8/16 bits Transfer type: 1-cycle transfer, 2-cycle transfer Number of transfers: 65536 Max.
A1-A12 A21, A22Note D0-D15 SDCLK SDCKE CSn SDRAS SDCAS LDQM UDQM WE V850E/MA1
A0-A11 A12, A13 DQ0-DQ15 CLK CKE CS RAS CAS LDQM UDQM WE 64 Mb SDRAM (1 Mword x 16 bits x 4 banks)
CPU core External I/O DMA
Internal RAM On-chip peripheral I/O
Bus interface
Data control Address control Count control Channel control
External RAM 8/16 bit bus External ROM
Note The address signal used differs depending on the SDRAM product.
DMA controller (provided in V850ES products)
Products: V850ES/SA2, SA3, SG2, SJ2, KG1+, KJ1+, FG2, FJ2 PD703229Y, 70F3229Y Transfer targets: Memory-peripheral I/O, memory-memory Transfer mode: Single Transfer units: 8/16 bits Transfer type: 2-cycle transfer Number of transfers: 65536 Max.
DMA controller (provided in V850/Sxx products)
Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3 Transfer targets: Internal RAM-on-chip peripheral I/O Transfer mode: Single Transfer units: 8/16 bits Transfer clock: 4 clocks Min. Number of transfers: 256 Max.
On-chip peripheral bus
CPU core External I/O DMA
Bus interface
On-chip peripheral I/O
CPU core
Internal bus
Internal RAM
Data control Address control Count control Channel control
On-chip peripheral I/O
Internal RAM DMA Transfer source address Transfer destination address Number of transfers 8/16bit-data
External RAM 8/16 bit bus External ROM
28
Pamphlet U15412EJ4V1PF
Analog Circuits
A/D converter
Products: V850ES/PM1 High-accuracy 16-bit resolution Sampling frequency selector (4.340 kHz/2.170 kHz) Support of up to 3 lines and 4 phases through multiple input channels
High-speed A/D converter
Products: V850E/IA3, IA4 Simultaneous 10-bit A/D converter sampling for 2 circuits On-chip operational amplifier (2.5 x/5 x) for input level amplification On-chip overvoltage detection comparator
AVDD Input circuit
CPU
AVREFIN
AVREFOUT
Selector
;; ; ;; ;; ; ;; ;
AVDD AVSS
Analog block
modulator
Digital block
Internal bus
ANI00 ANI01 ANI20 ANI21 ANI40 ANI41 ANI10 ANI11 ANI30 ANI31 ANI50 ANI51
Register & selector
ANIn0
AMP
Selector
Sample & hold circuit
ANIn1
AMP
Digital filter (LPF)
Digital filter (HPF)
Voltage comparator Array
ANIn2
INTAD Internal reset signal Internal system clock
AMP
modulator
ANIn3
CMP
Successive approximation register (SAR)
CMP
INTCMPn
AVSS
VREF buffer
CMPREF
CMP
Reference generator
ADTRGn TTRGn0 TTRGn1
Edge detection/noise elimination circuit
Control circuit
INTADn
A/Dn conversion result register m (ADAnCRm/ADAnCRmH)
A/D converter (multi-stage buffer type)
Products: V850E/MA1, MA3, ME2, IA1, IA2, MS1, SV2, V850/SV1, V853, etc. Conversion startable by software or hardware 8 on-chip conversion result registers (24 for SV2) Select/scan mode switching possible
D/A converter
Products: V850ES/KG1, KJ1, KG1+, KJ1+, SA2, SA3, SG2, SJ2, V850E/MA3, V853 R-2R ladder method (except for V850ES/SA2, SA3) R string method (V850ES/SA2, SA3 only) 8-bit resolution Operation mode: Normal mode/real-time output mode
ANI0
Selector
Conversion value setting register 0 Tap selector Resistor string
AVREF
ANIn Successive approximation register
AVSS
AVREF1 R-2R ladder or R string ANO0
ADTRG
Conversion control circuit
INTAD
AVSS
Conversion result register 0 Conversion result register 1 Conversion result register 2 Conversion result register 3 Conversion result register 4 Conversion result register 5 Conversion result register 6 Conversion result register 7
Conversion value setting register 1
R-2R ladder or R string
ANO1
Pamphlet U15412EJ4V1PF
29
Timer/Counter
Timer configuration during inverter control
Products: V850E/IA3, IA4, MA3, V850ES/IK1 0% and 100% output and 6-phase PWM output with deadtime possible Switchable anytime/batch overwrite for compare register A/D converter conversion start trigger generator
Up/down counter
Products: V850E/IA1, IA2, IA3, IA4, MA3, ME2 16-bit 2-phase encoder input possible Compare registers: 2 Capture/compare registers: 2
TMQ
INTOVF Clear
TMQOP
16-bit counter
Interrupt signal
Output control
Output period generation
16-bit capture/compare
TM output control
Interrupt signal
U U
Capture/compare register INTCC0 Capture/compare register TCLR INTCC1
16-bit capture/compare
Timer Output
Interrupt signal
Output duty generation
16-bit capture/compare
Timer Output
Interrupt signal
6-phase PWM output controller
V V
16-bit capture/compare
Timer Output
W W
control
A/D capture timing generation
TMP
Sync start supported
A/D operation trigger control
A/D trigger
TCUD Edge detection circuit
Selector
16-bit up/down counter timer
CLR circuit
Output control Compare register TIUD Compare register
TO
INTCM0
INTCM1
32-bit servo timer
Products: V850E/SV2 32-bit timer unit for servo control Capture registers: 12 Compare registers: 2 External input detection circuit with 1 to 256 dividers On-chip 8-bit mask timers: 2
Real-time counter
Products: V850ES/SA2, SA3, PM1 On-chip week, day, hour, minute, second counters Counting up to 4095 periods Support of interval interrupt generation at fixed intervals selectable from: 0.015625 s, 0.03125 s, 0.0625 s, 0.125 s, 0.25 s, 0.5 s, 1 s, 1 mn, 1 hr, 1 day
TI3
Edge detection fxx-fxx/8 (4)
Selector
Noise elimination TI3
Clear & count control
SLCLK
Selector 1s Second count register (6 bits) 1 mn Minute count register (6 bits) 1 hr Hour count register (5 bits) 1 day Day count register (3 bits) Week count register (12 bits) Second count specification register Minute count specification register Hour count specification register Day count specification register Week count specification register Internal bus
fxx
INTTI3
0.015625 s/0.03125 s/0.0625 s/0.125 s/0.25 s/0.5 s 6 Count clock = 32.768 kHz Selector Subcount register (15 bits) INTRTC
Clear
{
TM3 (32-bit)
INTOV3
fXT
2ch (x=0-1)
ICP3x
2ch (y=2-3)
Noise elimination TRGx Edge detection Noise elimination TRGy Edge detection Noise elimination TRGz Edge detection
Divider
EDVCMx
Mask CPTTRGx timer
CP3x (32-bit)
Capture
INTCP3x
Prescaler fBRG 3
INTROV
ICP3y
8ch (z=4-11)
Divider
EDVCMy
CP3y (32-bit)
Capture
INTCP3y
Count enable/ disable circuit
ICP3z
CP3z (32-bit)
Capture
INTCP3z
CM30 (32-bit)
Match
INTCM30
CM31 (32-bit)
Match
INTCM31
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Pamphlet U15412EJ4V1PF
Serial Interface
Serial interface with automatic send/receive function
Products: V850E/SV2, V850ES/KF1, KG1, KJ1, KF1+, KG1+, KJ1+ 32-byte internal buffer RAM Automatic send/receive function *1 to 32 bytes of transfer bytes specifiable *Transfer interval specifiable (0 to 63 clocks) *Single transfer/repeated transfer specifiable
Internal bus
LINBus
Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2 Low-cost 1-line network bus Sync break field (SBF) send/receive possible through hardware (Send: 13 bits SBF 20 bits; Receive: SBF 11 bits) Also generally usable as UART
Port configuration for LIN reception
SBF automatic detection Timer output selectable as source clock Any baud rate selectable
DIRn
Buffer RAM (32 bytes)
Automatic data transfer address point specification register
Automatic data transfer address count register
LIN reception pin
Reception circuit
Timer
SIAn
Serial I/O shift register
External interrupt pin
Selector Flag
Timer input pin
Edge detection interrupt
Wakeup detection
SOAn
Internally connectable by software, so external connection not required! Capture input Baud rate error detection through capture timer
Selector
Serial clock counter Interrupt generator INTCSIAn
Flag
SCKAn
Serial transfer control circuit
Selector
fxx/6-fxx/256
LIN transmission circuit
SBF automatic transmission
LIN transmission pin
MASTERn 6-bit counter
Transmission circuit Timer
Selector
Able to invert output
Flag
Automatic data transfer interval specification register
Timer output selectable as source clock Any baud rate selectable!!
CAN
Products: V850ES/SG2, SJ2, FE2, FF2, FG2, FJ2, V850E/IA1, V850/SF1, SC3, DB1 CAN protocol ver. 2.0 Part B (send/receive of standard and extended frames) Max. transfer rate: 500 kbps (V850/DB1 only) 1 Mbps 32 message buffer
IEBus controller
Products: V850ES/SG2, SJ2, V850/SB2, SC2 Communication mode 1 supported Max. transfer bytes: 32 bytes/frame Max. transfer speed: Approx. 17 kbps
CAN module
Register block
CTXD CRXD
CAN protocol transfer block
MAC (Message Access Controller)
Control circuit
Interrupt request
IETX
Transmission block Reception block Bit controller Field controller
IERX
CAN RAM (message buffer)
Control block
Interrupt request
Pamphlet U15412EJ4V1PF
31
Other
USB
Products: V850E/ME2 Compliant with Universal Serial Bus Specification Support of 12 Mbps (full speed) transfer Many endpoint configurations
SSCG function (Spread spectrum Frequency Synthesizer Clock Generator)
Products: V850E/ME2 EMI peak noise reduction through input frequency modulation Large reduction in noise countermeasure time and cost possible Frequency modulation rate and modulation period changeable by register setting
USB
Control transfer: Endpoint0R (64 bytes)/Endpoint0W (64 bytes) Bulk transfer 1: Endpoint1 (64 bytes x 2)/Endpoint2 (64 bytes x 2) Bulk transfer 2: Endpoint3 (64 bytes x 2)/Endpoint4 (64 bytes x 2) Interrupt transfer1/2: Endpoint7 (8 bytes)/Endpoint8 (8 bytes)
UFDRQn DMAAKn TCn
Selector
I/O Buffer SIE UDM UDP
Modulation period With frequency modulation rate of -3% Modulation period: 13 to 27 kHz Without frequency modulation
USBSP2B USBSP4B INTUSB0B INTUSB1B INTUSB2B INTRSUM fUSB(48 MHz) Remark n = 0 to 3 RSUM_OUT
Frequency modulation rate
Improvement of 10 dB or more
USB function 0 DMA channel select register (UF0CS)
Endpoint
USB function 0 buffer control register (UF0BC)
ROM correction function
Products: V850 core :V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 V850E, V850ES cores :V850ES/SA2, SA3, SG2, SJ2, KE1, KF1, KG1, KJ1, KE1+, KF1+, KG1+, PM1, IK1, PD703229Y, 70F3229Y, V850E/MA3, SV2, IA3, IA4 Instructions of address to be modified inserted to replace DBTRAP instruction (JMP r0 instruction in case of V850 core), branching to 0060H (0000H in case of V850 core) Program modification following switch to mask ROM possible Modified addresses: 4 points, 8 pointsNote
Note V850E/SV2
Explanation of ROM correction operation
RESET
Internal ROM
Normal flow
ROM correction request flag = 0?
No ROM correction request flag clear
ROM correction flow
Yes Download modification program Initialization Jump to modification program
Internal RAM
Modification program execution Return to internal ROM
Modification program download
External ROM, EEPROM, etc.
Instruction address bus ROM correction address register
Correction address enable setting information
Read modification program to RAM
Correction address = XXXX ROM correction enable flag = 1
Correction address setting ROM correction enable
Replace DBTRAP instructionNote
Internal ROM Comparator
DBTRAP generation block instructionNote
Correction point
Next processing...
Main routine
Output trigger control circuit
Instruction replacement part
Note JMP r0 instruction in case of V850 core
Instruction data bus
Note JMP r0 instruction for the V850 core
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Pamphlet U15412EJ4V1PF
Low-voltage detection circuit (LVI)
Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1 Detection voltage level changeable by software Usable instead of reset IC, contributing to lower system cost Detection voltage not changeable after mode transition (security protection)
Clock monitor function
Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2, PD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1 Monitors abnormal stops of main clock with internal Ring- Oscillator During abnormal stop, entire system can be set to reset status Prevention of destruction due to system deadlock or runaway
VDD
Main clock
reset
Internal reset signal
Resistor
Detection level selection
VDD
Resistor
Selector
Reset signal
Ring oscillator clock enable
Interrupt signal
Resistor
+ ---
Reference voltage Flag
Flag
Main clock oscillation monitoring
Reset upon abnormal stop
Run/stop settable by software
On-chip debugging function
Products: V850E/ME2Note, V850E/MA3, IA4, SV2, V850ES/KJ1, KJ1+, SG2, SJ2, FE2, FF2, FG2, FJ2, PD70F3229Y Realization of on-chip debugging of microcontroller with DCU (Debug Control Unit) Compact and low-cost PC card-type emulator Flash programmer function Integrated debugger (ID850) supported
Note Trace function support is possible by using the RTE-2000-TP made by Midas Lab Co., Ltd., or PARTNER-ET II, PARTNER-J made by Kyoto Micro Computer Co., Ltd.
Boundary scan function
Products: V850E/SV2 Use of JTAG (Joint Test Action Group) communication specifications, IEEE1149.1 compliant Progressive scan of device's external I/O pins, test data input/ output possible Connection check of devices soldered on user board possible
: Boundary scan target pin : JTAG interface pin : Boundary scan cell
Boundary scan register
I/O I/O
Internal logic
I/O I/O
On-chip debug emulator
Target system
Bypass register
*Break function *Execute function Notebook PC *Pin mask function *Flash programmer function *Execution time measurement *Non-use of user resources
V85
ries 0 Se h Flas
Selector
Decoder
Selector
N-Wire CARD (IE-V850E1-CD-NW)
TDO
TDI
Instruction register
TCS TMS TRST
TPA controller
Pamphlet U15412EJ4V1PF
33
V850 Series Benchmark
The V850 Series realizes high speed, high performance, and high code efficiency.
Minimum instruction execution time
Cycle time 0.2 s 0.4 s 32-bit RISC V850ES/Kxx 0.05
V850 Series performance
Performance comparison
V850ES-20 MHz 4.1 1.7 1.0 3.6
0 1 2 3 4 5 (Relative comparison)
16-bit CISC 78K4 0.125 8-bit CISC 78K0/Kx1 0.20 0.24
A 16bit 20 MHz A 16bit 16 MHz B 32bit 50 MHz
Code size comparison
78K0
V850ES-20 MHz A 16bit 20 MHz
0.97 1.00 1.37 1.18
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 (Relative comparison)
78K0S : 12 MHz (0.168 s) supported for some products : 10 MHz (0.2 s) supported for some products
0.40
A 16bit 16 MHz B 32bit 50 MHz
* NEC Electronics measurement results using sample program
Low Power Consumption
Thanks to thorough energy-saving design, a superior current/performance ratio of 1.1 to 0.7 mA/MIPS is realized, particularly for V850ES and V850/Sxx products. As a result, a reduction in power consumption to 1/5 or less compared to 16-bit CISC microcontrollers of similar performance is realized. Lower system power consumption and higher performance are simultaneously realized through this extremely high power performance.
Power performance
mA/MIPS 10 Realization of low consumption current that is 1/5 or less compared to 16-bit CISC of similar performance
8-bit CISC
Consumption current/performance
9.2 mA/MIPS
16-bit CISC
5
7.3 mA/MIPS
1.1 mA/MIPS 1.1 mA/MIPS
V850/SV1
V850/SB1
0.9 mA/MIPS
V850/SA1
0
Clock gear function
Consumption current
Reduction to 1/5th through clock gear (1/8)
Standby mode
Normal operation mode
HALT mode
Reduction to 1/10th through clock gear (1/32)
Approx. 1/10 IDLE mode
;; ;;
0.7 mA/MIPS
V850ES/SA2, 3
CPU
Peripheral Watch Oscillation circuit function timer Main Sub
Approx. 1/2
Sub normal operation mode
Reduction to 1/400 through switch from main clock to subclock
Approx. 1/400
or
Sub IDLE mode Approx. 1/4000
or
STOP mode (sub operation)
Approx. 1/4000
fxx Operating frequency (20 MHz)
fxx/8 (2.5 MHz)
fxx/32 (625 kHz)
fXT (32.768 kHz)
STOP mode (sub stop)
Approx. 1/15000 Consumption current Operating Stopped
34
Pamphlet U15412EJ4V1PF
Low Noise Countermeasures
Minimizing the influence of electromagnetic interference (EMI) emitted from the microcontroller and the influence of noise applied to the microcontroller (EMS) is a high priority, particularly for AV equipment such as car audio systems, and thus superior noise performance is required of microcontrollers. Various noise countermeasures are implemented in the V850 Series, and noise performance equivalent or superior to that of 16-bit products has been realized.
EMS countermeasures
Use of PLL for oscillation circuit Voltage control oscillator Phase comparator Oscillation circuit Divider LPF VCO To CPU peripheral functions
EMS measurement results (power supply coupling measurement)
Noise application voltage
0 kV 1.0 kV 2.0 kV or higher
V850ES/KJ1 Existing V850 products (PLL-less products)
V850ES/KJ1 (flash version)
VDD=5 V Resonator: 4 MHz Internal operation frequency: 16 MHz (PLL = ON)
Existing V850 products
VDD=5 V Resonator: 16 MHz Internal operation frequency: 16 MHz
High-frequency noise cut through PLL filter
EMI noise countermeasures: Power supply circuit countermeasures
CPU power supply separation Insertion of capacitance between VDD and GND
Vport
Port power supply separation
Vcpu
Reg. (OFF setting possible)
I/O PORT
CPU
OSC AMP
GNDport GNDcpu
Due to the relation between the power supply and GND pad positions and the lead frame, placement is done so as to lower the power supply impedance.
EMS noise measurement results
0 -10 -20 -30 -40
Noise [dBm]
Power supply voltage Operating frequency
5V 78K0 V850ES/KJ1
10MHz 16MHz
Existing 78K0
-50 -60 -70 -80 -90
V850ES/KJ1
70 75 80 85 90 95 100 Frequency [MHz] 105 110 115 120
Pamphlet U15412EJ4V1PF
35
V850 Series Middleware List
Middleware plays a major role for maximizing processor performance and realizing high-speed processing of complex data with flexibility and ease. NEC Electronics offers a large array of middleware that is optimized for the CPU architecture and importantly contributes to shortening development time, while also facilitating additions and changes to dedicated functions whose implementation as hardware for devices, etc., used to have high cost and time requirements, and the creation of user-friendly interfaces.
Middleware merits:
Dedicated device development not required Shortening of development time Reduction in development cost
Shift to middleware accelerating deployment to optimum processors
An increasing number of processors optimized for various systems and based on NEC Electronics' original technology and the superb technology of third parties, as well as other technologies that have been established as standards, are being deployed from. Customers Planning
System proposal Demo systems Evaluation systems
Realization of latest technology and functions Maximization of system added value Easy performance enhancement and function expansion Easy creation of user-friendly interface Multimedia processing realizable just with CPU Realization of higher reliability and quality
Development support system Original NEC technologies
Middleware development Solution development
IP vendors Standards
System design
Consultation Performance verification
Development
Integration Customization
V850 Series Mass production
Maintenance
RISC
Next-generation processors
Middleware product list
V850 Series V850 Series
Category Image Speech
Middleware JPEG MPEG-4/H.263 Video Text To Speech Speech CODEC
Category Recognition Speech recognition
Middleware Japanese (large vocabulary) Japanese (small vocabulary) Chinese (small vocabulary) English (small vocabulary) Japanese (input frame required) Japanese (input frame not required) CIPERUNICORN
Sound
Japanese G.723.1 Annex A/C G.726 (ADPCM) G.729 Annex A/B AMR MPEG-4 CELP Acoustic echo canceller (for hands-free operation) AEC Noise suppressor 3GPP-NS Audio decoder AAC MP3 WMA Sound generator for cellular phone ringer melody
Handwriting recognition Security Internet Storage Encryption Fingerprint recognition TCP/IP PC-compatible file system
: Development completed
Middleware performance list
Middleware JPEG G.726 (ADPCM) Speech recognition (small vocabulary) Performance QVGAx24 : Enc0.32s/Dec0.24s 32Kbps, 16Kbps 0.4s Power (MIPS) --Enc8/Dec8.2 19 (20 words) 63 (100 words) ROM 17.5 KB 9 KB 82 KB RAM 15 KB 80 B 3.5 KB (15 words)
36
Pamphlet U15412EJ4V1PF
Platforms
Speech Recognition
Speech recognition is realized on a single chip using the memory and peripheral I/Os in the V850 Series. Ideal for applications such as games and home appliances that must feature speech recognition but are subject to large restrictions.
*Realization of speech recognition with memory and peripheral I/Os contained in V850 Series *Expansion of number of recognized words
Recognized number of words: 30 words (in case of V850/SA1, 20 MHz)
V850 Series Speech recognition system configuration example
*Realization of speech recognition using only memory and peripheral I/Os contained in V850 Series *Expansion of number of recognized words
Expansion of number of recognized words Memory capacity
Main dictionary Sub dictionary 1
ROM/RAM ROM Data
Description Program
Capacity 26 KB 40 KB 0.5 KB 3.4 KB 0.3 KB
Friend Company Reservation
Jim, Marc, Sally
Sub dictionary 2
V850/SA1 (Internal 20 MHz)
LPF
. . .
Smith, Jones, Brown
Sub dictionary 3
ROM/RAM mix Recognition dictionary (in case of 15 words) RAM Work area (in case of 15 words) Stack
ANA, JAL, ticket
Recognition dictionary and work vary depending on the number of recognized words.
Internal ROM Internal RAM Mike amp
*Speech recognition evaluation system
NEC Electronics provides an environment allowing easy evaluation for the introduction of speech recognition. For details and the purchasing method, consult your NEC Electronics sales representative.
A/D (1 ch)
JPEG
Text to Speech (for Japanese Text)
*Conforms to JPEG international standard *Versatile compression and decompression processing
Conforms to DCT baseline process (non-reverse coding) *User-customizable VRAM input module *User-specified Huffman and quantization tables *APPn marker insertion *Compression suspend function *User-customizable VRAM output module *Support of various JPEG markers (DRI, RSTn, DNL) *Decompression suspend function
JPEG performance
Processing Time
CPU V850E/MS1 (33MHz)Note
*Speech synthesized from Japanese Kana and Kanji text (SJIS code) *Versatile speech synthesis
Synthesis of female voices possible
*Rhythm of synthesized speech (pitch, phoneme duration) can
be designed (Speech Designer compatible)
Various adjustable parameters such as intonation and reading speed
*Support of special characters (Reading of special characters settable in user dictionaries) Synthesis speed *
ROM/RAM
Decompression
0.97 s
Speech synthesis using natural rhythm possible (synthesis of more natural sounding speech)
Works also with V850/SA1 (20 MHz). (However, text is placed in internal ROM.)
Description Program Data Dictionary data (approx. 80,000 words) Phoneme data 126 KB 35 KB 1.2 MB
Capacity
Sample Ratio
4:1:1 (Quality75)
QVGA (320x240x24)
VGA (640x480x24)
Compression
0.32 s
Decompression
0.24 s
Compression
1.3 s
ROM
Note Programs are placed in internal ROM, and stack and (some) work areas are placed in internal RAM. The data and other works are placed in external RAM.
Memory
ROM RAM
567 KB (8 kHz sampling) 684 KB (11 kHz sampling)
Compression
10 KB
Decompression
7.5 KB
Compression
5 KB
Decompression
10 KB
RAM
Work Stack Speech output buffer
160 KB 508 bytes 12 KB
Pamphlet U15412EJ4V1PF
37
Features
Flash microcontroller lineup
To answer the need for shorter development time and maintenance after shipping, NEC Electronics offers microcontrollers with on-chip flash memory available in a large range of capacities from 64 KB to 640 KB as part of the V850 Series. NEC Electronics' flash memory microcontrollers offer the following features.
Flash capacity 64 to 640 KB Overwrite unit Entire memory at one time, or block units Rewrite method Serial communication with dedicated flash memory programmer (on-board, off-board) Self-flash programming Rewrite voltage Single-power-supply flash: Operation voltage Dual-power-supply flash: Operation voltage 7.8 V/10.3 V Rewrite count: 100 times
Flash Memory Size (bytes) RAM size (bytes) V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 V850ES/KE1+* V850ES/KF1+* V850ES/KG1+* V850ES/KJ1+* V850ES/SG2 V850ES/SJ2
64K
128K
192K
256K
384K
512K
640K
4K
4K
6K
8K
12K
16K
8K
10K
12K
16K
16K
24K
32K
20K
24K
32K
48K
/ / /
PD70F3229Y
V850ES/SA2,SA3 V850/SA1 V850/SB1 V850/SB2 V850/SC1,SC2,SC3 V850E/MA3 V850E/MA1 V850E/MS1 V853 V850E/IA3, IA4 V850E/IA2 V850E/IA1 V850ES/IK1* V850ES/FE2* V850ES/FF2* V850ES/FG2* V850ES/FJ2* V850E/SV2 V850/SV1 V850/SF1 V850/DB1 : Single power supply : Dual power supply : Single power supply/dual power supply *: Under development
/
Rewrite Modes
To enable integrated use ranging from development to mass production and maintenance, the V850 Series supports a programmer rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites flash memory with user programs.
On-board programming mode This programming mode is used to rewrite the flash memory mounted on the target system using a dedicated flash memory programmer. Off-board programming mode This programming mode is used to rewrite flash memory using a dedicated flash memory programmer and dedicated program adapter (FA SeriesNote 1). Self-programming mode This programming mode is used to rewrite flash memory by executing the user program written beforehand to the flash memory using on-board/ off-board programming.Note 2
Notes 1. The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd. 2. Since instruction fetch and data access cannot be performed from the internal flash memory area during self-programming, a program for rewriting internal RAM or external memory must be transferred in advance.
Programmer program (on-board/off-board)
CSI communication method
FLMD0 FLMD1 VDD GND RESET SO SI SCK FLMD0 Note 1 Note 2 FLMD1 or VSS VDD VSS RESET SI0 SO0 Example: V850ES/SA2 SCK0
Handshake-compatible CSI communication method
FLMD0 FLMD1 VDD GND RESET SO SI SCK HS FLMD0 Note 2 FLMD1 or VSS VDD VSS RESET SI0 SO0 Example: V850ES/SA2 SCK0 PDH0
Note 1
UART communication method
FLMD0 FLMD1 VDD GND RESET TxD Dedicated flash RxD memory programmer (PG-FP4, etc.) FLMD0 Note 2 FLMD1 or VSS VDD VSS RESET RXD0 TXD0 Example: V850ES/SA2
Note 1
Dedicated flash memory programmer (PG-FP4, etc.)
Dedicated flash memory programmer (PG-FP4, etc.)
Note 1. In the case of dual-power-supply flash, VPP
Note 2. In the case of dual-power-supply flash, don't connect.
Pamphlet U15412EJ4V1PF
38
Self-programming mode (single-power-supply method)
Flash memory can be erased and rewritten using a self-programming library from a program placed in an area outside the flash memory.
Self-programming flow
Flash memory operation
Flash environment initialization processing
* Access to flash area prohibited * Stop instruction execution prohibited * Clock stop prohibited
Normal operation mode
Flash memory 3FFFFH
Self-programming mode
Flash memory
Erase processing
Library initialization processing
3FFFFH Block 7(60KB)
Write processing
Flash information setting processing
Block 6(60KB) Self-programming Library (Erase/Write routine execution) Block 5(60KB) Block 4(60KB) Block 3(4KB) Block 2(4KB) Block 1(4KB) Block 0(4KB)
Internal verify processing
256 KB Library end processing
All blocks completed? YES
NO
Boot area replacement processing
00000H
00000H
Flash environment end processing
Caution The number of blocks and block capacity differ depending on the products. (Example: V850ES/SA2)
Processing end
Flash Specifications List
Category Part No. Flash Memory Capacity Max. Operating Frequency Rewrite Voltage Rewrite Mode On-Board/Off-Board Programming
VPP --------10.3 V ----10.3 V ----10.3 V ------------------------------------7.8 V 7.8 V 7.8 V ----7.8 V 7.8 V 7.8 V 10.3 V --------7.8 V 7.8 V ------------------------7.8 V 7.8 V 7.8 V 7.8 V 7.8 V 7.8 V CSI UART CSI+HS ---- ---- ---- ---- ---- 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 20 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
SelfProgramming
Rewrite Count (Times)
Low end
V850ES/KE1 V850ES/KF1 V850ES/KF1 V850ES/KG1 V850ES/KG1 V850ES/KJ1 V850ES/KJ1 V850ES/KE1+* V850ES/KF1+* V850ES/KG1+* V850ES/KJ1+*
128 KB 256 KB/128 KB 128 KB 256 KB/128 KB 128 KB 256 KB/128 KB 128 KB 128 KB 256 KB/128 KB 256 KB/128 KB 256 KB/128 KB 640 KB/384 KB 640 KB/384 KB 384 KB 256 KB 256 KB 256 KB/128 KB 512 KB/384 KB/256 KB 512 KB 512 KB 256 KB 128 KB 128 KB 256 KB/128 KB 256 KB 256 KB 128 KB 256 KB 128 KB 512 KB 128 KB/64 KB 256 KB/128 KB 384 KB/256 KB/128 KB 512 KB/384 KB/256 KB 384 KB/256 KB 512 KB/384 KB/256 KB 512 KB 512 KB 256 KB 128 KB
20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 80 MHZ 50 MHZ 33 MHZ 33 MHZ 33 MHZ 64 MHZ 64 MHZ 40 MHZ 50 MHZ 32 MHZ 40.5 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 20 MHZ 19 MHZ 20 MHZ 20 MHZ 16 MHZ 16 MHZ
VDD 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.85 V to 3.6 V 2.85 V to 3.6 V 3.5 V to 5.5 V 2.2 V to 2.7 V 2.2 V to 2.7 V 3.0 V to 3.6 V 4.0 V to 5.5 V 3.5 V to 5.5 V 2.3 V to 2.7 V (internal) 3.0 V to 3.6 V (external) 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) 4.5 V to 5.5 V 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) 2.3 V to 2.7 V (internal) 4.5 V to 5.5 V (external) 4.5 V to 5.5 V 3.0 V to 3.6 V (internal) 4.5 V to 5.5 V (external) 4.5 V to 5.5 V 2.3 V to 2.7 V (internal) 2.7 V to 3.6 V (external) 4.0 V to 5.5 V 4.0 V to 5.5 V 4.0 V to 5.5 V 4.0 V to 5.5 V 3.1 V to 3.6 V 4.0 V to 5.5 V 3.5 V to 5.5 V 3.5 V to 5.5 V 3.5 V to 5.5 V 4.0 V to 5.5 V
Middle range
V850ES/SG2 V850ES/SJ2 PD70F3229Y V850ES/SA2 V850ES/SA3 V850/SA1 V850/SB1 V850/SC1
High end
V850E/MA3 V850E/MA1 V850E/MS1 V850E/MS1 V853 V850E/IA4 V850E/IA3 V850E/IA2 V850E/IA1 V850ES/IK1* V850E/SV2 V850ES/FE2* V850ES/FF2* V850ES/FG2* V850ES/FJ2* V850/SV1 V850/SB2 V850/SC2 V850/SC3 V850/SF1 V850/DB1
ASSP
*
: Under development Pamphlet U15412EJ4V1PF
39
Flash Memory Programmers
NEC Electronics flash memory programmer: PG-FP4
[Features] Supports write to all NEC Electronics microcontrollers with internal flash memory. USB support through host machine interface Allows verification of various types of information, including programmer setting information, error messages, and check-sum, even in stand-alone configuration, from the main unit's LCD. Enables downloading of two types of user code and selecting of valid code Device-specific information required for writing automatically settable with parameter files Supports both on-board programming and program adapter programming. Easy-to-carry A5 size Simple operation either on stand-alone basis and on WindowsTM 95/Windows 98/Windows Me/ Windows 2000/Windows XP, Windows NTTM 4.0 using a dedicated application (Flashpro4)
*
Flash memory programmer configuration
PG-FP4 allows single-microcontroller programming when used with a program adapter (FA Series of Naito Densei Machida Mfg. Co., Ltd.). Onboard programming can also be performed. A sample rewrite environment when using the program adapter is shown below. Rewrite environment example
Flash memory program (PG-FP4) Target system Power-supply unit Host machine interface (USB) To host machine Cautions 1. Install the PG-FP4 control software and target device parameter file in the host machine. *PG-FP4 control software: Bundled with PG-FP4 *PG-FP4 parameter file: Distributed via online delivery service 2. In addition to programming using the program adapter, on-board programming on the target system is also possible.
*
Third-party flash memory programmers (1/2)
Programming system Y1000-8
[Manufacturer/Distributor] Wave Technology Co., Ltd. [Target Devices] V850/SV1, SB1 (PD70F3032B, 70F3033B), SB2 (70F3035B, 70F3037H), V850E/IA1 (70F3116), MA1 [Features] Gang programmer enabling simultaneous programming and verification of up to 8 devices Enables reading of master data directly from floppy disk to internal memory Data dump display and editing functions Master data storable on internal hard disk Designed for simple and comfortable operation via touch panel, and superior operability via PASS/FAIL display, check-sum display, and task count display supporting sockets. [Additional information] TEL : +81-3-5304-1885 FAX : +81-3-5304-1886 E-mail : sales@y1000.com Website: http://www.y1000.com/index_e.html
40
Pamphlet U15412EJ4V1PF
*
Third-party flash memory programmers (2/2)
FlashPRO IV: FL-PR4
[Manufacturer/Distributor] Naito Densei Machida Mfg. Co. [Target Devices] V850 Series [Features] Supports writing to all NEC Electronics microcontrollers with internal flash memory. USB support through host machine interface Allows verification of various types of information, including programmer setting information, error messages, and check-sum, even in stand-alone configuration, from the main unit's LCD. Enables downloading of two types of user code and selecting of valid code Device-specific information required for writing automatically settable with parameter files Supports both on-board programming and program adapter programming. Easy-to-carry A5 size Simple operation either on stand-alone basis and on Windows 95/Windows 98/Windows Me/ Windows 2000/Windows XP, Windows NT 4.0 using a dedicated application (Flashpro4) [Additional information] TEL : +81-45-475-4191 FAX : +81-45-475-4091 E-mail : info@ndk-m.co.jp Website: http://www.ndk-m.co.jp/asmis/eng/index.html
*
NET IMPRESS
[Manufacturer/Distributor] Yokogawa Digital Computer Corporation [Target Devices] V850/SB1 (PD70F3033B), SB2(70F3037H), SA1(70F3017A), SC3(70F3089Y), V853(70F3003A, 70F3025A), V850E/MS1(70F3102A), MA1(70F3107), IA1, IA2(70F3114), V850ES/KF1(70F3210), FE2, FF2, FG2, FJ2, SG2, SJ2 [Features] Enables programming of flash memory microcontrollers of various writing specifications solder mounted on user system boards. One control module is the key to this product's versatility. Microcontrollers of the same family are supported by changing parameters, and microcontrollers of different families are supported by purchasing the required license for the descriptor part. Can be used on standalone basis as well as via a host machine. Rich lineup of downloadable freeware [Additional Information] TEL : Japan +81-42-333-6224 U.S.A +408-941-0132 (Yokogawa Corporation of America) Europe +44-1256-811998 (Ashling Microsystems Limited) Korea +82-2-785-3929 (KM DATA INC.) South East Asia +65-6563-2082 (Unidux Electronics Pte Ltd.) FAX : Japan +81-42-352-6109 U.S.A +408-941-0121 (Yokogawa Corporation of America) Europe +44-1256-811761 (Ashling Microsystems Limited) Korea +82-2-785-3117 (KM DATA INC.) South East Asia +65-6569-4661 (Unidux Electronics Pte Ltd.) Website: http://www.ydc.co.jp/micom/index_E.htm
*
Flash Burner Forward FL-S01, Flash Gang Forward FL-G01
[Manufacturer] Forward Electric Co., Ltd. (Hong Kong) [Distributor] Application Co., Ltd. [Target Devices] V850/SB1(70F3033A), V850E/MA1 [Features] Host machine interface supports USB. Easy operation and rich array of GUI software provided Low cost from development to mass production Compact and easy to carry (FL-S01) Gang programmer enabling simultaneous programming of up to 8 devices (FL-G01) Can be used on standalone basis using compact flash (FL-G01). Programming adapter board (option) usable in common for FL-S01 and FL-G01. [Additional Details] TEL : +81-42-732-1377 FAX : +81-42-732-1378 Website:http://www.apply.co.jp/index_eng.html
FL-S01
FL-G01
Pamphlet U15412EJ4V1PF
41
Low-End Lineup (1/2)
Item Part No.
V850ES/KE1
PD703207/3207Y PD70F3207H/F3207HY PD703208/3208Y
V850ES/KF1 PD703209/3209Y PD703210/3210Y PD70F3210/F3210Y PD70F3210H/F3210HY PD703211/3211Y PD70F3211H/F3211HY
CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 128 KB (mask)
V850ES 29 MIPS (@20 MHz: 5 MHz x 4) 128 KB (flash) 4 KB - - - - - 25 (Y products: 26) 8 (8)Note 1 16-bit timer/event counter (TM0) x 1 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch 2 ch CSI x 2 ch UART x 2 ch I2Cx1 chNote 2 25 (Y products: 26) 64 KB (mask) 4 KB 96 KB (mask)
V850ES 29 MIPS (@20 MHz: 5 MHz x 4) 128 KB (mask) 128 KB (flash) 6 KB Multiplexed 16 bits 8/16 bits 2 SDRAM, etc. 28 (Y products: 29) 8(8)Note 1 16-bit timer/event counter (TM0) x 2 ch 16-bit timer/event counter (TMP) x 1 chNote 3 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch 2 ch CSI with automatic transfer function (32-byte buffer) x 1 ch CSI x 2 ch UART x 2 ch I2C x 1 chNote 2 10 bits x 8 ch - - 59 8
-
256 KB (mask) 256 KB (flash) 12 KB
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions Operating frequency I/O Input
10-bitx8 ch - - 43 8 - Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 2.7 to 5.5 V 200 mW (128 KB mask products: 20 MHz @5 V operation) 39.6 mW (128 KB mask products: 10 MHz @3.3 V operation) 64-pin TQFP (12 x 12 mm) 64-pin LQFP (10 x 10 mm) -40 to +85C
Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz
Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. 3. PD703211, 703211Y, 70F3211H, 70F3211HY only
2.7 to 5.5 V 150 mW (128 KB mask products: 20 MHz @5 V operation) 29.7 mW (128 KB mask products: 10 MHz @3.3 V operation) 80-pin TQFP (12 x 12 mm) 80-pin QFP (14 x 14 mm) -40 to +85C
Item Part No.
V850ES/KG1
PD703212/3212Y PD703213/3213Y PD703214/3214Y PD703215/3215Y PD703216/3216Y PD70F3214/F3214Y PD70F3215H/F3215HY PD70F3214H/F3214HY
V850ES/KJ1
PD703217/3217Y PD70F3217/F3217Y PD70F3217H/F3217HY
V850ES 29 MIPS (@ 20 MHz: 5 MHz x 4) 256 KB (mask) 256 KB (flash) 16 KB 6 KB Multiplexed/separate 24 bits 8/16 bits 4 SRAM, etc. 33 (Y products : 34) 38(Y products : 40) 41(Y products : 43) 8(8)Note 1 16-bit timer/event counter (TM0) x 6 ch 16-bit timer/event counter (TMP) x 1 chNote 3 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch 2 ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 3 ch UART/I2C x 1 chNote 4 UART x 2 ch I2C x 1 chNote 4 10-bit x 16 ch 8-bit x 2 ch - 112 16 - Provided(RUN/break) Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 2.7 V to 5.5 V 150 mW (128 KB mask products: 20 MHz @ 5 V operation) 29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 144-pin LQFP (20 x 20 mm) -40 to +85C 96 KB (mask) 128 KB (mask) 128 KB (flash) 16 KB 256 KB (flash)
PD70F3218H/F3218HY
CPU core CPU performance Internal ROM Internal RAM External bus interface 64 KB (mask) 4 KB Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 30 (Y products : 31) 96 KB (mask)
V850ES 29 MIPS (@ 20 MHz: 5 MHz x 4) 128 KB (mask) 128 KB (flash) 6 KB Multiplexed/separate 22 bits 8/16 bits 2 SRAM, etc. 8(8)Note 1 16-bit timer/event counter (TM0) x 4 ch 16-bit timer/event counter (TMP) x 1 chNote 2 8-bit timer/event counter (TMH) x 2 ch 8-bit timer/event counter (TM5) x 2 ch 8-bit interval timer (BRG) x 1 ch 2ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 2 ch UART x 2 ch 2 I C x 1 chNote 4 10-bit x 8 ch 8-bit x 2 ch - I/O Input 76 8 - Watch timer: 1 ch, ROM correction function: 4 points, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 2.7 V to 5.5 V 150 mW (128 KB mask products: 20 MHz @ 5 V operation) 29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40 to +85C
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions Operating frequency Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. PD703215, 703215Y, 70F3215H, 70F3215HY only 3. PD70F3218H, 70F3218HY only 4. Only Y products have an on-chip I2C interface.
42
Pamphlet U15412EJ4V1PF
Low-End Lineup (2/2)
Item Part No.
V850ES/KE1+
PD703302/3302Y
V850ES 29 MIPS (@20 MHz: 5 MHz x 4) 128 KB (mask) 4 KB Bus type Address bus Data bus Chip select signal - - - - - Internal External 26 (Y products: 27) 9(9)Note 1 16-bit timer/event counter (TM0) x 1 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 2 ch CSI x 2ch UART x 1ch UART (LIN compatible) x 1 ch I2C x 1 chNote 2 10-bit x 8 ch - - I/O Input 43 8 - Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output Using main clock: 2 to 20 MHz Using subclock: 32.768 kHz Ring-OSC: 240 kHz 2.7 to 5.5V 200 mW (128 KB mask products: 20 MHz @ 5 V operation) 39.6 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 64-pin TQFP (12 x 12 mm) 64-pin LQFP (10 x 10 mm) -40C to +85C 128 KB (flash) 128 KB (flash) 6 KB
V850ES/KF1+
PD70F3306/F3306Y
V850ES 29 MIPS (@20 MHz: 5 MHz x 4) 256 KB (mask) 256 KB (flash) 12 KB Multiplexed 16 bits 8/16 bits 2 SRAM, etc. 29 (Y products: 30) 9(9)Note 1 16-bit timer/event counter (TM0) x 2 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 2 ch CSI with automatic transfer function (32-byte buffer) x 1 ch CSI x 2 ch UART x 1 ch UART (LIN compatible) x 1 ch I2C x 1 chNote 2 10-bit x 8 ch - - 59 8 - Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output Using main clock: 2 to 20 MHz Using subclock: 32.768 kHz Ring-OSC: 240 kHz 2.7 to 5.5V 220 mW (256 KB mask products: 20 MHz @ 5 V operation) 42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation) 80-pin TQFP (12 x 12 mm) 80-pin QFP (14 x 14 mm) -40C to +85C
PD70F3302/F3302Y
PD703308/3308Y PD70F3308/F3308Y
CPU core CPU performance Internal ROM Internal RAM External bus interface
Memory controller Interrupt sources Timer/counter
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions Operating frequency
Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
Item Part No.
V850ES/KG1+
PD70F3311/F3311Y PD703313/3313Y PD70F3313/F3313Y
V850ES/KJ1+
PD70F3316/F3316Y PD70F3318/F3318Y
CPU core CPU performance Internal ROM Internal RAM External bus interface 128 KB (flash) 6 KB Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Internal External Timer/counter
V850ES 29 MIPS (@ 20 MHz : 5 MHz x 4) 256 KB (mask) 256 KB (flash) 16 KB Multiplexed/separate 22 bits 8/16 bits 2 SRAM, etc. 41 (Y products: 42) 9 (9)Note 1 16-bit timer/event counter (TM0) x 4 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 2ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 1 ch UART/CSI x 1 ch UART x 1 ch UART (LIN compatible) x 1 ch I2C x 1 chNote 2 128 KB (flash) 6 KB
V850ES 29 MIPS (@ 20 MHz : 5 MHz x 4) 256 KB (flash) 16 KB Multiplexed/separate 24 bits 8/16 bits 4 SRAM, etc. 46 (Y products: 48) 9 (9)Note 1 16-bit timer/event counter (TM0) x 6 ch 16-bit timer/event counter (TMP) x 1 ch 8-bit timer (TMH) x 2 ch, 8-bit timer/event counter (TM5) x 2 ch, 8-bit interval timer (BRG) x 1 ch 2ch CSI with automatic transfer function (32-byte buffer) x 2 ch CSI x 2 ch UARTNote3/CSI x 1 ch UARTNote3/I2C x 1 chNote2 UART (LIN compatible) x 1 ch UARTx 1 ch, I2C x 1 chNote 2 10-bit x 16 ch 8-bit x 2 ch 4 ch 112 16 - Provided (RUN/break) When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 240 kHz 2.7 to 5.5 V 275 mW (256 KB flash products: 20 MHz @ 5 V operation) 59.4 mW (256 KB flash products: 10 MHz @ 3.3 V operation) 144-pin LQFP (20 x 20 mm) -40C to +85C Watch timer: 1 ch, POC/LVI/clock monitor, real-time output
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions Operating frequency I/O Input
10-bit x 8 ch 8-bit x 2 ch 4 ch 76 8 - Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 240 kHz 2.7 to 5.5 V 220 mW (256 KB mask products: 20 MHz @ 5 V operation) 42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C
Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface. 3. These UARTs are the identical and the number of channels in KJ1+ totals 3 channels.
Pamphlet U15412EJ4V1PF
43
Middle-Range Lineup (1/3)
Item Part No. Without IEBus, aFCAN On-chip IEBus On-chip aFCAN CPU core CPU performance Internal ROM Internal RAM External bus interface
PD703260/3260Y PD703270/3270Y PD703280/3280Y
PD703261/3261Y PD703271/3271Y PD703281/3281Y
PD70F3261/F3261Y PD70F3271/F3271Y PD70F3281/F3281Y
V850ES/SG2
PD703262/3262Y PD703272/3272Y PD703282/3282Y
PD703263/3263Y PD703273/3273Y PD703283/3283Y
PD70F3263/F3263Y PD70F3273/F3273Y PD70F3283/F3283Y
V850ES 29 MIPS (@ 20 MHz) 256 KB (mask) 24 KB Bus type Address bus Data bus Chip select signal Internal External 384 KB (mask) 32 KB 384 KB (flash) 512 KB (mask) 40 KB Multiplexed/separate 22 bits 8/16 bits - 640 KB (mask) 48 KB 640 KB (flash)
Memory controller Interrupt sources Timer/counter
SRAM, etc. 47Note 1/52Note 2 9(9)Note 1 16-bit interval timer(TMM) x 1 ch 16-bit timer/event counter(TMP) x 6 ch 16-bit timer/event counter(TMQ) x 1 ch 1 ch CSI x 3 ch UART(LIN compatible)/CSI x 1 ch CSI/I2C x 1 chNote 4 UART(LIN compatible)/I2C x 2 chNote 4 10-bit x 12 ch 8-bit x 2 ch
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions
I/O Input - Provided (RUN/break)
4 ch 84 - - Provided (RUN/break) Watch timer: 1 ch IEBus controller x 1 chNote 5 aFCAN controller x 1 chNote 6 ROM correction function : 4 points Real-time output LVI/clock monitor When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 200 kHz 2.85 to 3.6 V (@ 20 MHz) 82.5 mW(3.3 V,@ 20 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C
Notes4.Only Y products have an on-chip I2C interface. 5.PD703270 (Y)/3271 (Y)/F3271 (Y)/3272 (Y)/3273 (Y)/F3273 (Y) 6.PD703280 (Y)/3281 (Y)/F3281 (Y)/3282 (Y)/3283 (Y)/F3283 (Y)
Operating frequency
Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes1.Only products without IEBus or aFCAN 2.Only products with IEBus or aFCAN 3.Number of external interrupts that can be used to release STOP mode
59.4 mW(3.3 V,@ 20 MHz)
59.4 mW(3.3 V,@ 20 MHz)
89.1 mW(3.3 V,@ 20 MHz)
Item Part No. Without IEBus, aFCAN On-chip IEBus On-chip aFCAN CPU core CPU performance Internal ROM Internal RAM External bus interface
PD703260/3260Y PD703270/3270Y PD703280/3280Y
PD703261/3261Y PD703271/3271Y PD703281/3281Y
PD70F3261/F3261Y PD70F3271/F3271Y PD70F3281/F3281Y
V850ES/SG2
PD703262/3262Y PD703272/3272Y PD703282/3282Y
PD703263/3263Y PD703273/3273Y PD703283/3283Y
PD70F3263/F3263Y PD70F3273/F3273Y PD70F3283/F3283Y
V850ES 29 MIPS (@ 20 MHz) 256 KB (mask) 24 KB Bus type Address bus Data bus Chip select signal Internal External 384 KB (mask) 32 KB 384 KB (flash) 512 KB (mask) 40 KB Multiplexed/separate 22 bits 8/16 bits - 640 KB (mask) 48 KB 640 KB (flash)
Memory controller Interrupt sources Timer/counter
SRAM, etc. 47Note 1/52Note 2 9(9)Note 1 16-bit interval timer(TMM) x 1 ch 16-bit timer/event counter(TMP) x 6 ch 16-bit timer/event counter(TMQ) x 1 ch 1 ch CSI x 3 ch UART(LIN compatible)/CSI x 1 ch CSI/I2C x 1 chNote 4 UART(LIN compatible)/I2C x 2 chNote 4 10-bit x 12 ch 8-bit x 2 ch
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions
I/O Input - Provided (RUN/break)
4 ch 84 - - Provided (RUN/break) Watch timer: 1 ch IEBus controller x 1 chNote 5 aFCAN controller x 1 chNote 6 ROM correction function : 4 points Real-time output LVI/clock monitor When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz Ring-OSC: 200 kHz 2.85 to 3.6 V (@ 20 MHz) 82.5 mW(3.3 V,@ 20 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C
Notes 5. Only Y products have an on-chip I2C interface. 6. PD703274(Y)/F3274(Y)/3275(Y)/3276(Y)/F3276(Y) 7. PD703284(Y)/F3284(Y)/3285(Y)/3286(Y)/F3286(Y) 8. PD703287(Y)/3288(Y)/F3288(Y)
Operating frequency
Power supply voltage Power consumption (Typ.) Package Operating ambient temperature
Notes 1. Only products without IEBus or aFCAN 2. Only products with IEBus or aFCAN 3. Only products with two aFCAN channels 4. Number of external interrupts that can be used to release STOP mode
59.4 mW(3.3 V,@ 20 MHz)
59.4 mW(3.3 V,@ 20 MHz)
89.1 mW(3.3 V,@ 20 MHz)
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Pamphlet U15412EJ4V1PF
Middle-Range Lineup (2/3)
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Internal External Timer/counter 128 KB (mask) 8 KB 256 KB (mask) 16 KB Multiplexed/separate 22 bits 16 bits - SRAM, etc. 31 (Y products: 32) 8(6)Note 1 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 6 ch 8-bit timer x 2 ch 1 ch CSI x 1 ch CSI/I2C x 2 chNote 2 CSI/UART x 2 ch 10-bit x 12 ch - 6 ch (dedicated internal RAM I/O Input Debug control unit Other peripheral functions Operating frequency 71 12 - ROM correction function:4 points, watch timer: 1 ch When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) on-clip peripheral I/O) 256 KB (flash)
V850/SB1
PD703031B/3031BY PD703033B/3033BY PD70F3033B/F3033BY PD703030B/3030BY PD70F3030B/F3030BY PD703032B/3032BY PD70F3032B/F3032BY
V850 23 MIPS (@20 MHz) 384 KB (mask) 384 KB (flash) 24 KB 512 KB (mask) 512 KB (flash)
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
Power supply voltage
Power consumption (Typ.)
125 mW (5 V, @ 20 MHz)
165 mW (5 V, @ 20 MHz)
125 mW (5 V, @ 20 MHz)
185 mW (5 V, @ 20 MHz)
125 mW (5 V, @ 20 MHz)
210 mW (5 V, @ 20 MHz)
Package
100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40 to +85C
100-pin QFP (14 x 20 mm)
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External
PD703229Y
PD703229Y PD70F3229Y
V850ES 29 MIPS (@ 20 MHz) 384 KB (mask) 32 KB Multiplexed 18 bits 8/16 bits 2 SRAM, etc. 38 sources 9 (9)Note 16-bit internal timer (TMM) x 1 ch 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 1 ch 1 ch UART (LIN compatible) x 3 ch CSI x 1 ch CSI/I2C x 1 ch 384 KB (flash)
V850/SC1
PD703068Y
V850/SC2
PD703069Y
V850
V850/SC3
PD703088Y PD703089Y
V850/SC1,V850/SC2,V850/SC3
PD70F3089Y
23 MIPS (@ 20 MHz)
21 MIPS (@ 19 MHz) 512 KB (mask) 24 KB
18 MIPS (@ 16 MHz)
23 MIPS (@ 20 MHz) 512 KB (flash)
Multiplexed (can be separated only for V850/SC1, V850/SC2) 22 bits 16 bits - SRAM, etc. 42 44 46 11 (9)Note 16-bit timer/event counter x 10 ch 49
Watchdog timer Serial interface
1ch CSI x 2 ch CSI/I C x 2 ch
2
CSI/UART x 2 ch UART x 2 ch
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions Operating frequency I/O Input -
10-bit x 12 ch - 4 ch 84 - Provided (RUN, break)
10-bit x 12 ch - 6 ch (dedicated internal RAM 112 12 - on-chip peripheral I/O)
ROM correction function : 4 points, watch timer: 1 ch, LVI/clock monitor ROM correction function : 4 points, watch timer: 1 ch, IEBus controller : 1 ch (V850/SC2 only), FCAN controller : 2 ch (1 ch : PD703088Y only) (V850/SC3 only) When using main clock: 2.5 to 20 MHz When using subclock: 32.768 kHz During Ring OSC operation: 200 kHz When using main clock: 4 to 20 MHz (@5 V) When using main clock: 4 to 19 MHz (@5 V) When using main clock: 4 to 16 MHz (@5 V) When using main clock: 4 to 20 MHz (@5 V)
When using subclock: 32.768 kHz When using subclock: 32.768 kHz Power supply voltage Power consumption (Typ.) 3.5 to 5.5V 100 mW (5 V, @ 20MHz) 145 mW (5 V, @ 20MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C 125 mW (5 V, @ 20 MHz)
When using subclock: 32.768 kHz
When using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) 150 mW (5 V, @ 20 MHz)
3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 120 mW (5 V, @ 19 MHz) 110 mW (5 V, @ 16 MHz) 144-pin LQFP (20 x 20 mm) -40 to +85C
Package Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ4V1PF
45
Middle-Range Lineup (3/3)
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type 128 KB (mask) 8 KB 256 KB (mask)
V850ES/SA2
PD703200/3200Y PD703201/3201Y PD70F3201/F3201Y
V850ES 29 MIPS (@ 20 MHz) 256 KB (flash) 16 KB Multiplexed/separate 256 KB (mask)
V850ES/SA3
PD703204/3204Y PD70F3204/F3204Y
V850ES/ST2
PD703220
V850ES - 256 KB (flash) ROM-less 48 KB Separate/multiplexed (selectable only for CS1)
Address bus Data bus Chip select signal Memory controller Interrupt sources Internal External Timer/counter
22 bits 8/16 bits 4 SRAM, etc. 30 (Y products: 31) 8 (8)Note1 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch 1 ch CSI x 2 ch CSI/UART x 1 ch CSI/I2C x 1 chNote 2 UART x 1 ch
24 bits
22 bits 8/16 bits 4 SRAM, etc.
31 (Y products: 32)
28 9 16-bit interval timer (TMM) x 1 ch 16-bit timer/event counter (TMP) x 6 ch 1 ch
Watchdog timer Serial interface
CSI x 3 ch
CSI x 1 ch CSI/UART x 1 ch UART x 1 ch
A/D converter D/A converter DMA controller Ports I/O Input Debug control unit Other peripheral functions Operating frequency
10-bit x 12 ch 8-bit x 2 ch 4 ch 68 14 - ROM correction function : 4 points, real-time counter (watch timer): 1 ch When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 2.2 to 2.7 V
10-bit x 16 ch
10-bit x 8 ch 8-bit x 2 ch -
84 18
57 8 - Real-time output 20 to 34 MHz
Power supply voltage
3.0 to 3.6 V
Power consumption (Typ.) Package
38 mW (2.5 V, @ 20 MHz) 100-pin TQFP (14 x 14 mm)
46 mW (2.5 V, @ 20 MHz)
38 mW (2.5 V, @ 20 MHz)
46 mW (2.5 V, @ 20 MHz)
T.B.D. 120-pin TQFP (14 x 14 mm) 144-pin LQFP (20 x 20 mm) -40C to +85C
121-pin FBGA (12 x 12 mm)
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
-40C to +85C
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Internal External Timer/counter 64 KB (mask) 4 KB
PD703014A/3014AY PD703014B/3014BY PD703015A/3015AY PD703015B/3015BY PD70F3015B/F3015BY
V850 23 MIPS (@ 20 MHz) 128 KB (mask) 128 KB (flush)
V850/SA1
PD703017A/3017AY PD70F3017A/F3017AY
256 KB (mask) 8 KB
256 KB (flash)
Multiplexed/separate 22 bits 16 bits - SRAM, etc. 24 8 (5)Note 1 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch 1ch CSI x 1 ch, CSI/I2C x 1 chNote 2 CSI/UART x 1 ch UART x 1ch 10-bit x 12 ch - 3 ch (dedicated internal RAM on-chip peripheral I/O)
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports I/O Input Debug control unit Other peripheral functions Operating frequency
72 13 - Watch timer: 1 ch When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 3.0 to 3.6 V (@20 MHz) 2.7 to 3.6 V (@17 MHz) 66 mW (3.3 V, @ 20 MHz) 56 mW (3.0 V, @ 17 MHz) 105 mW (3.3 V, @ 20 MHz) 99 mW (3.0 V, @ 17 MHz) 66 mW (3.3 V, @ 20 MHz) 56 mW (3.0 V, @ 17 MHz) 105 mW (3.3 V, @ 20 MHz) 99 mW (3.0 V, @ 17 MHz)
Power supply voltage
Power consumption (Typ.)
Package
121-pin FBGA (12 x 12 mm) 100-pin LQFP (14 x 14 mm) 121-pin FBGA (12 x 12 mm)
100-pin LQFP (14 x 14 mm)
100-pin LQFP (14 x 14 mm) 121-pin FBGA (12 x 12 mm)
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
-40C to +85C
46
Pamphlet U15412EJ4V1PF
ASSP Lineup (1/3)
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 128 KB (mask) 6 KB - - - - - 53 8 (7) Note 16-bit timer/event counter (TMQ) x 2 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 2 ch 16-bit timer/event counter (TMP) x 2 ch 16-bit timer/counter (TMP) x 2 ch 16-bit interval timer (TMM) x 1 ch
V850E/IA4
PD703185 PD703186
V850E1 82 MIPS (@ 64 MHz) 256 KB (mask) 12 KB 256 KB (flash)
V850E/IA3
PD70F3186 PD703183
V850E1 82 MIPS (@ 64 MHz) 128 KB (mask) 6 KB - - - - - 49 7 (6) Note 16-bit timer/event counter (TMQ) x 1 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 1 ch 16-bit timer/event counter (TMP) x 2 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit timer/counter (TMP) x 2 ch 16-bit interval timer (TMM) x 1 ch 256 KB (flash) 12 KB
V850E/IA1
PD703116 PD70F3116
V850E1 67 MIPS (@ 50 MHz) 256 KB (mask) 10 KB Multiplexed 24 bits 8/16 bits 8 SRAM, etc. 45 20(14) Note 16-bit 3-phase sinusoidal PWM timer x 2 ch 16-bit encoder counter/timer x 2 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch 256 KB (flash)
V850E/IA2
PD703114
V850E1 54 MIPS (@ 40 MHz) 128 KB (mask) 6 KB Multiplexed 22 bits 8/16 bits - SRAM, etc. 42 16(12) Note 16-bit 3-phase sinusoidal PWM timer x 2 ch 16-bit encoder counter/timer x 1 ch 16-bit timer/counter x 2 ch 16-bit timer/event counter x 1 ch 16-bit interval timer x 1 ch 128 KB (flash)
PD70F3184
PD70F3114
Watchdog timer Serial interface
1 ch CSI x 1 ch UART x 1 ch CSI/UART x 1 ch 10-bit x 4 ch, 2 units (conversion time: 2 s) 8/10-bit x 8 ch - 4 ch
1 ch CSI x 1 ch UART x 1 ch CSI/UART x 1 ch 10-bit x 4 ch, 10-bit x 2 ch (conversion time: 2 s) 8/10-bit x 6 ch - 4 ch 44 6 Provided (RUN/break) - 0.5 to 64 MHz 2.5 V (internal), 5 V (A/D converter) 5 V (external) 175 mW (internal 2.5 V, @ 64 MHz) 80-pin QFP (14 x 14 mm) -40C to +85C
- CSI x 2 ch UART x 3 ch 10-bit x 8 ch, 2 units - 4 ch 75 8 - FCAN controller x 1 ch 4 to 50 MHz 3.3 V (internal), 5 V (A/D converter) 5 V (external) 630 mW (internal 3.3 V, external 5 V, @ 50 MHz operation) 144-pin LQFP (20 x 20 mm) -40C to +85C (Provided 110C products)
- CSI x 1 ch CSI/UART x 1 ch UART x 1 ch 10-bit x 6 ch (A/D converter 0) 10-bit x 8 ch (A/D converter 1) - 4 ch 47 6 - - 4 to 40 MHz 5 V (3.3 V (internal), 5 V (A/D converter)) 5 V (external) (on-chip regulator) 440 mW (5 V, @ 40 MHz operation) 100-pin QFP (14 x 20 mm) 100-pin LQFP (14 x 14 mm) -40C to +85C
A/D converter
D/A converter DMA controller Ports I/O Input Debug control unit Operating frequency Power supply voltage -
56 8
Other peripheral functions ROM correction function : 4 points, operational amplifier, comparator, software pull-up function ROM correction function : 4 points, operational amplifier, comparator, software pull-up function 0.5 to 64 MHz 2.5 V (internal), 5 V (A/D converter) 5 V (external) 175 mW (internal 2.5 V, @ 64 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C
Power consumption (Typ.) Package
Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode.
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Internal Interrupt sources External Timer/counter
PD703327
V850ES/IK1
V850ES
PD703329 PD70F3329
PD703034B/3034BY
PD703035B/3035BY PD70F3035B/F3035BY
V850/SB2
V850
PD703036H/3036HY PD70F3036H/F3036HY
PD703037H/3037HY PD70F3037H/F3037HY
41MIPS (@ 32 MHz) 64 KB (mask) 4 KB - - - - - 36 7 (6)Note 1 16-bit timer/event counter (TMQ) x 1ch (inverter timer support possible) 16-bit timer/event counter (TMP) x 1 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit timer counter (TMP) x 3 ch 16-bit interval timer (TMM) x 1 ch 128 KB (mask) 128 KB (flash) 6 KB 8 KB 128 KB (mask)
15 MIPS (@ 13 MHz) 256 KB (mask) 256 KB (flash) 16 KB Multiplexed/separate 22 bits 16 bits - SRAM, etc. 33 (Y products : 34) 8 (6)Note 1 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 4 ch 8-bit timer x 2 ch 384 KB (mask) 384 KB (flash)
22MIPS (@ 19 MHz) 512 KB (mask) 512 KB (flash) 24 KB
Watchdog timer Serial interface
1 ch CSI x 1 ch UART x 2 ch
2
1 ch CSI x 1 ch CSI/I C x 2 chNote 2 CSI/UART x 2 ch 10-bit x 12 ch - 6 ch (dedicated internal RAM 71 12 - ROM correction function : 4 points, watch timer x 1 ch, IEBus controller (simple version) : 1 ch When using main clock: 2 to 13 MHz (@ 5 V) When using subclock: 32.768 kHz 4.0 to 5.5 V (A/D converter : 4.5 to 5.5 V) 75 mW (mask ROM version : @ 5 V, 13 MHz) 125 mW (flash memory version : @ 5 V, 13 MHz) 100-pin LQFP (14 x 14mm) 100-pin QFP (14 x 20mm) -40C to +85C 125 mW (mask ROM version : @5 V, 19 MHz) 125 mW (mask ROM version : @ 5 V, 19 MHz) 185 mW (flash memory version : @ 5 V, 19 MHz) 210 mW (flash memory version : @ 5 V, 19 MHz) 100-pin QFP (14 x 20 mm) When using main clock: 2 to 19 MHz (@ 5 V) When using subclock: 32.768 kHz 0n-chip peripheral I/O)
A/D converter D/A converter DMA controller Ports I/O Input Debug control unit Operating frequency Power supply voltage
10 bits x 4 ch, 2 units (conversion time 2 s) - - 39 - - 20 to 32 MHz 3.5 to 5.5 V (A/D converter : 4.5 to 5.5 V) T.B.D. 64-pin LQFP (14 x 14 mm) -40C to +85C
Other peripheral functions ROM correction function : 4 points, software pull-up function, POC/LVI/clock monitor
Power consumption (Typ.) Package
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode. 2. Only Y products have an on-chip I2C interface.
Pamphlet U15412EJ4V1PF
47
ASSP Lineup (2/3)
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 64 KB (mask) 4 KB - - - - - 44 9(9)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TQM) x 1 ch 16-bit interval timer (TMM) x 1 ch 1 ch CSI x 2 ch UART (LIN compatible) x 2 ch 10-bit x 10 ch - - I/O Input Debug control unit Other peripheral functions Operating frequency - 51 - Provided (RUN, break) - Provided (RUN, break) - Provided (RUN, break)
V850ES/FE2
PD703230 PD70F3230
V850ES 29 MIPS (@20 MHz) 64 KB (flash) 128 KB (mask) 6 KB 128 KB (flash) 128 KB (mask) 6 KB
V850ES/FF2
PD70F3231 PD703232 PD70F3232
V850ES 29 MIPS (@20 MHz) 128 KB (flash) 256 KB (mask) 12 KB - - - - - 44 9(9)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 1 ch 16-bit interval timer (TMM) x 1 ch 1 ch CSI x 2 ch UART (LIN compatible) x 2 ch 10-bit x 12 ch - - 67 - - Provided (RUN, break) 256 KB (flash)
PD703231
PD703233
PD70F3233
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch When using main clock: 16 to 20 MHz
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch When using main clock: 16 to 20 MHz
Power supply voltage Power consumption (Typ.) 155 mW (@5.0 V, 20 MHz)
4.0 to 5.5V 170 mW (@5.0 V, 20 MHz) 155 mW (@5.0 V, 20 MHz) 170 mW (@5.0 V, 20 MHz) 155 mW (@5.0 V, 20 MHz)
4.0 to 5.5V 170 mW (@5.0 V, 20 MHz) 155 mW (@5.0 V, 20 MHz) 170 mW (@5.0 V, 20 MHz)
Package
64-pin TQFP (10 x 10 mm)
80-pin TQFP (12 x 12mm)
Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
-40C to +85C, -40C to +110C
-40C to +85C, -40C to +110C
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 128 KB (mask) 6 KB 128 KB (flash)
V850ES/FG2
PD703234 PD70F3234 PD703235
V850ES 29 MIPS (@ 20 MHz) 256 KB (mask) 12 KB - - - - - 62 12 (12)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 2 ch 16-bit interval timer (TMM) x 1 ch 1 ch CSI x 2 ch UART (LIN compatible) x 3 ch 10-bit x 16 ch - 4 ch I/O Input - 84 - Provided (RUN, break) - Provided (RUN, break) 256 KB (flash) 384 KB (flash) 16 KB
PD70F3235
PD70F3236
PD70F3237
V850ES/FJ2
PD70F3238
V850ES 29 MIPS (@ 20 MHz)
PD70F3239
256 KB (flash) 12 KB - - - - - 73
384 KB (flash) 16 KB
512 KB (flash) 20 KB Multiplexed 16 bits 8/16 bits 4 SRAM, etc. 83
16 (16)Note 16-bit timer/event counter (TMP) x 4 ch 16-bit timer/event counter (TMQ) x 3 ch 16-bit interval timer (TMM) x 1 ch 1ch CSI x 3 ch UART (LIN compatible) x 3 ch 10-bit x 24 ch - 4 ch 128 - Provided (RUN, break) Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag aFCAN controller: 2 ch aFCAN controller: 4 ch CSI x 3 ch UART (LIN compatible) x 4 ch
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
Debug control unit Other peripheral functions
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 2 ch
Operating frequency
When using main clock: 16 to 20 MHz
When using main clock: 16 to 20 MHz
Power supply voltage
4.0 to 5.5V
4.0 to 5.5V
Power consumption (Typ.)
155 mW (@ 5.0 V, 20 MHz)
170 mW (@ 5.0 V, 20 MHz)
155 mW (@ 5.0 V, 20 MHz) 100-pin LQFP (14 x 14 mm)
170 mW (@ 5.0 V, 20 MHz)
200 mW (@ 5.0 V, 20 MHz) 144-pin LQFP (20 x 20 mm)
Package
Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
-40C to +85C, -40C to +110C
-40C to +85C, -40C to +110C
48
Pamphlet U15412EJ4V1PF
ASSP Lineup (3/3)
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt Internal sources External Timer/counter 512 KB (mask) 24 KB Multiplexed/separate 26 bits 8/16 bits 8 SRAM, etc. 75 (Y products : 76) 12(12)Note 1 32-bit timer/event counter x 1 ch 16-bit timer/event counter x 6 ch 16-bit interval timer x 6 ch 8-bit timer/event counter x 12 ch 1 ch CSI with automatic transfer function x 2 ch CSI x 3 ch UART/CSI x 1 ch UART x 1 ch I2C x 1 chNote 2 10-bit x 24 ch - 4 ch I/O Input Debug control unit Other peripheral functions Operating frequency Power supply voltage Power consumption (Typ.) Package Operating ambient temperature 171 24 Provided (RUN, break) Boundary scan function, 12- to 16-bit PWM output : 5 ch, real-time output, ROM correction function : 8 points 10 to 40.5 MHz 2.3 to 2.7 V (internal) 2.7 to 3.6 V (external) 134 mW (@ 2.5 V, 40.5 MHz) 159 mW (@ 2.5 V, 40.5 MHz) 176-pin LQFP (24 x 24 mm) 82 mW (@ 3.3 V, 20 MHz)
V850E/SV2
PD703166/3166Y PD70F3166/F3166Y PD703041/3041Y PD703039/3039Y PD703040/3040Y
V850E1 55 MIPS (@ 40.5 MHz) 512 KB (flash) 192 KB (mask) 8 KB 256 KB (mask)
V850/SV1
PD70F3040/F3040Y
V850 23 MIPS (@ 20 MHz) 256 KB (flash) Multiplexed 22 bits 16 bits - SRAM, etc. 45 (Y products: 46) 9(6)Note1 24-bit timer/event counter x 2 ch 16-bit timer/event counter x 2 ch 8-bit timer/event counter x 8 ch 384 KB (mask) 16 KB 384 KB (flash)
PD703038/3038Y
PD70F3038/F3038Y
Watchdog timer Serial interface
1 ch CSI x 1 ch CSI/I2C x 2 chNote 2 CSI/UART x 2ch
A/D converter D/A converter DMA controller Ports
10-bit x 16 ch - 6 ch (dedicated internal RAM 135 16 - Watch timer: 1 ch, 12- to 16-bit PWM output : 4 ch, Vsync/Hsync separator, ROM correction function : 4 points When using main clock: 4 to 20 MHz When using subclock: 32.768 kHz 3.1 to 3.6 V (@ 20 MHz) 2.7 to 3.6 V (@ 16 MHz) 148 mW (@ 3.3 V, 20 MHz) 82 mW (@ 3.3 V, 20 MHz) 148 mW (@ 3.3 V, 20 MHz) internal peripheral I/O)
257-pin FBGA (14 x 14 mm) -10C to +70C
176-pin LQFP (24 x 24 mm) 180-pin FBGA (13 x 13 mm) -40C to +85C
180-pin FBGA (13 x 13 mm)
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 35 38 128 KB (mask) 12 KB
V850/SF1
PD703075AY PD703076AY PD703078AY
V850 18 MIPS (@ 16 MHz) 256 KB (mask) 16 KB Multiplexed 22 bits 16 bits - SRAM, etc. 35 8 (6)Note 16-bit timer/event counter x 8 ch 38 44 7 (7)Note 1 256 KB (flash) 128 KB (flash)
V850/DB1
PD703079AY PD70F3079AY PD70F3080
V850 18 MIPS (@ 16 MHz) 128 KB (mask) 6 KB - - - - - 40 7 (7)Note 1
V850ES/PM1
PD703081 PD703228
V850ES 29 MIPS (@ 20 MHz) 128 KB (mask)/ROM-less 10 KB Separate 19 bits 8/16 bits 3 SRAM, etc. 28 4 (4)Note 1 16-bit timer/event counter (TM1) x 6 ch 8-bit timer/event counter (TM2) x 2 ch 1 ch CSI x 2 ch UART x 2ch 16-bit x 6 ch (12 inputs) - - 68 - - Real-time counter (watch timer) : 1 ch ROM correction function : 4 points 8- to 12-bit PWM output : 4 ch
16-bit timer/event counter (TMG) x 1 ch 16-bit timer/event counter (TM0) x 2 ch 8-bit timer/event counter (TM5) x 2 ch
Watchdog timer Serial interface
1 ch CSI x 1 ch CSI/I2C x 1 ch CSI/UART x 2 ch 10-bit x 12 ch - 6 ch (dedicated internal RAM I/O Input 72 12 - Watch timer: 1 ch FCAN controller : 1 ch ROM correction function : 4 points Watch timer: 1 ch FCAN controller : 2 ch ROM correction function : 4 points Watch timer: 1 ch FCAN controller : 1 ch ROM correction function : 4 points Watch timer: 1 ch FCAN controller : 2 ch ROM correction function : 4 points internal peripheral I/O)
1 ch CSI x 3 ch UART x 2 ch 10-bit x 8 ch - - 99 (Including 16 output-only) 8 - Watch timer: 1 ch,16-bit PWM output: 6 ch 8-bit PWM output: 2 ch, meter control PWM: 24 ch DCAN controller: 2 ch Watch timer: 1 ch, 16-bit PWM output: 6 ch 8-bit PWM output: 2 ch, meter control PWM: 24 ch DCAN controller: 1 ch
A/D converter D/A converter DMA controller Ports Debug control unit Other peripheral functions
Operating frequency Power supply voltage
When using main clock: 4 to 16 MHz When using subclock: 32.768 kHz 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V)
When using main clock: 4 to 16 MHz 4.0 to 5.5 V
When using main clock: 2 to 20 MHz When using subclock: 32.768 kHz 3.0 to 3.6 V (@ 20 MHz) 2.7 to 3.6 V (@ 10 MHz) 2.2 to 3.6 V (@ 32.768 kHz) 81 mW (@ 3.3 V, 20 MHz) 100-pin LQFP (14 x 14 mm) -40C to +85C
Power consumption (Typ.) Package Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
75 mW (@ 5 V, 16 MHz) 100-pin LQFP (14 x 14 mm) 100-pin QFP (14 x 20 mm) -40C to +85C
125 mW (@ 5 V, 16 MHz)
180 mW (@ 5 V, 16 MHz)
120 mW (@ 5 V, 16 MHz)
128-pin QFP (20 x 20 mm) -40C to +85C
Pamphlet U15412EJ4V1PF
49
High-End Lineup (1/2)
Item Part No.
V850E/MA3
PD703131A/3131AY PD703132A/3132AY PD703133A/3133AY PD703134A/3134AY PD70F3134A/F3134AY
V850E1 106 MIPS (@ 80 MHz) 256 KB (mask) 16 KB Bus type Address bus Data bus Chip select signal 32 KB 16 KB Multiplexed/separate 26 bits 8/16 bits 8 SDRAM, SRAM, etc. Internal External 41 26(26)Note 1 16-bit interval timer (TMD) x 4 ch 16-bit timer/event counter (TMP) x 3 ch 16-bit timer/event counter (TMQ) x 1 ch (inverter timer support possible) 16-bit encoder counter/timer (TMENC) x 1 ch 1 ch CSI/UART x 3 ch UART/I2C x 1 chNote 2 512 KB (mask) 32 KB 512 KB (flash)
V850E/ME2
PD703111A
V850E1 215 MIPS (@ 150 MHz) ROM-less (instruction cache : 8 KB) Instruction: 128 KB; Data: 16 KB Separate 26 bits 8/16/32 bits 8 SDRAM, SRAM, etc. 59 40(32)Note 1 16-bit timer/event counter (TMC) x 6 ch 16-bit interval timer (TMD) x 4 ch 16-bit encoder counter/timer (TMENC) x 2 ch
CPU core CPU performance Internal ROM Internal RAM External bus interface
Memory controller Interrupt sources Timer/counter
Watchdog timer Serial interface
- CSI (with FIFO) x 1 ch CSI (with FIFO)/UART x 1 ch UART x 1 ch 10-bit x 8 ch - 4 ch 77 1 Provided (RUN, break, trace) USB (function) x 1 ch, SSCG 16-bit PWM output x 2 ch 10 to 150 MHz
A/D converter D/A converter DMA controller Ports I/O Input Debug control unit Other peripheral functions Operating frequency
10-bit x 8 ch 8-bit x 2 ch 4 ch 101 11 Provided (RUN, break) ROM correction function : 4 points 5 to 80 MHz
Power supply voltage
2.3 to 2.7 V (internal)/3.0 to 3.6 V (external)
1.35 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 133 MHz) 1.40 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 150 MHz) 575 mW (@2.5 V, 80 MHz) 200 mW (@ 1.5 V, 150 MHz) 176-pin LQFP (24 x 24 mm) 240-pin FBGA (16 x 16 mm) -40C to +85C (@133MHz), -40 toC +70C (@150MHz)
Power consumption (Typ.) Package
T.B.D. 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm) -40C to +85C
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C interface.
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External - ROM-less 4 KB
PD703103A
PD703105A
V850E/MA1 PD703106A
V850E1 67 MIPS (@ 50 MHz)
PD703107A
PD70F3107A
V850E/MA2 PD703108
V850E1 -
128 KB (mask)
256 KB (mask) 10 KB Separate 26 bits 8/16 bits 8
256 KB (flash)
ROM-less 4 KB Separate 25 bits 8/16 bits 4 SDRAM, SRAM, etc. 23 8 (4)Note 16-bit timer/event counter (TMC) x 2 ch 16-bit interval timer (TMD) x 4 ch - CSI/UART x 2 ch
SDRAM, SRAM, etc. 33 25 (17)Note 16-bit timer/event counter (TMC) x 4 ch 16-bit interval timer (TMD) x 4 ch - CSI x 1 ch CSI/UART x 2 ch UART x 1 ch 10-bit x 8 ch - 4 ch I/O Input 106 9 - 12-bit PWM output x 2ch 4 to 50 MHz 3.0 to 3.6 V
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
10-bit x 4 ch - 4 ch - 74 5 - - 4 to 40 MHz 3.0 to 3.6 V
Debug control unit Other peripheral functions Operating frequency Power supply voltage
Power consumption (Typ.) Package
528 mW (@ 3.3 V, 50 MHz) 144-pin LQFP (20 x 20 mm)
627 mW (@ 3.3 V, 50 MHz) 144-pin LQFP (20 x 20 mm) 161-pin FBGA (13 x 13 mm)
416 mW (@ 3.3 V, 40 MHz) 100-pin LQFP (14 x 14 mm)
Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
-40C to +85C
-40C to +85C
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Pamphlet U15412EJ4V1PF
High-End Lineup (2/2)
Item Part No.
V850E/MS1
External 3.3V External 5V PD703100A-33/-40 PD703100-33/-40
- ROM-less 96 KB (mask) 4 KB Bus type Address bus Data bus Chip select signal Separate 24 bits 8/16 bits 8 EDO DRAM, SRAM, etc. Internal External 47 25 (1)Note1 16-bit timer/event counter x 6 ch 16-bit interval timer x 2 ch - CSI x 2 ch CSI/UART x 2 ch 10-bit x 8 ch - 4ch I/O Input 122 9 - - 2 to 40 MHz (-40 product) 2 to 33 MHz (-33 product) 3.0 to 3.6 V (internal, external) (A products) 3.0 to 3.6 V (internal)/4.5 to 5.5 V (external) (Products without A) 272 mW (@ 3.3 V, 33 MHz) 430 mW (@ 5 V, 33 MHz) 144-pin LQFP (20 x 20 mm) 157-pin FBGA (14 x 14 mm)Note2 -40C to +85CNote3 294 mW (@ 3.3 V, 33 MHz) 515 mW (@ 5 V, 33 MHz)
V850E/MS2
PD703102A-33 PD703102-33 PD70F3102A-33 PD70F3102-33
V850E1 47 MIPS (@ 33 MHz) 128 KB (mask) 128 KB (flash) - ROM-less 4 KB Separate 24 bits 8/16 bits 4 EDO DRAM, SRAM, etc. 35 10 (1)Note1 16-bit timer/event counter x 4 ch 16-bit interval timer x 2 ch - CSI/UART x 2ch 10-bit x 4 ch - 4 ch 52 5 - - 10 to 33 MHz
PD703101A-33 PD703101-33
V850E1
PD703130
CPU core CPU performance Internal ROM Internal RAM External bus interface
Memory controller Interrupt sources Timer/counter
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
Debug control unit Other peripheral functions Operating frequency
Power supply voltage
3.0 to 3.6 V (internal)/ 4.5 to 5.5 V (external) 218 mW (@ 3.3 V, 33 MHz)
Power consumption (Typ.)
Package
100-pin LQFP (14 x 14 mm)
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode 2. PD703100A-33, 703101A-33, 703102A-33, and 70F3102A-33 only 3. PD703100-40, 703100A-40 : -40C to +70C Others : -40C to +85C
-40C to +85C
Item Part No. CPU core CPU performance Internal ROM Internal RAM External bus interface Bus type Address bus Data bus Chip select signal Memory controller Interrupt sources Timer/counter Internal External 128 KB (mask) 4 KB 96 KB (mask) PD703003A PD703004A
V853
PD703025A V850 38 MIPS (@ 33 MHz) 256 KB (mask) 8 KB Multiplexed 20 bits 16 bits - SRAM, etc. 32 17(1)Note 16-bit timer/event counter x 4 ch 16-bit interval timer x 1 ch - CSI x 2 ch CSI/UART x 2 ch 10 bits x 8 ch 2 ch - I/O Input 67 8 - 12-bit PWM output x 2 ch 2 to 33 MHz 128 KB (flash) 4 KB 256 KB (flash) 8 KB PD70F3003A PD70F3025A
Watchdog timer Serial interface
A/D converter D/A converter DMA controller Ports
Debug control unit Other peripheral functions Operating frequency
Power supply voltage
4.5 to 5.5V
Power consumption (Typ.)
365 mW (@ 5 V, 33 MHz)
450 mW (@ 5 V, 33 MHz)
425 mW (@ 5 V, 33 MHz)
480 mW (@ 5 V, 33 MHz)
Package
100-pin LQFP (14 x 14 mm)
Operating ambient temperature
Note Number of external interrupts that can be used to release STOP mode
-40C to +85C
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V850 Series Development Environment
The V850 Series development environment consists of tools designed to make the development of application systems using the V850 Series of highperformance microcontrollers made by NEC Electronics more pleasant, faster, and more accurate. Each one of these development tools features functions to fully exploit the performance of the V850 Series.
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Pamphlet U15412EJ4V1PF
Low-Priced Development Environment Lineup
Price
Emulator and evaluation board available at low prices
Low-priced full-function emulator IECUBE
* Low prices 1/3 or 1/4 the price of conventional emulators * Connectable to PC via USB * Enhanced real-time RAM monitor and time measuring function * On-chip self-diagnosis function * Debugger and simple programmer provided * Palm size
Ultra-low-priced on-chip emulator N-Wire CARD
* Ultra low price 1/10 the price of conventional emulators * Connectable to PC via PCMCIA * Writing to the microcontroller on-chip flash memory possible * Debugger provided
Starter kit for simple evaluation TK-850 Series
* Evaluation kit enabling easy performance testing * Lineup for V850ES/Kx1, V850ES/SA2, and V850ES/SG2 * Debugger, compiler, and circuit diagrams provided as standard
Function
* For details, refer to V850 Series Development Environment Pamphlet (U15763E)
Pamphlet U15412EJ4V1PF
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Development Flow
Product planning
System design
PM plus
Hardware design
Software design RX850, RX850 Pro Coding
Fabrication Compiling/ assembly Standalone testing Debugging CA850
SM850, SM plus +RD850, +RD850 Pro +AZ850, +TW850 ID850, ID850NW, ID850QB DF703xxx
System debugging
IE, IECUBE Hardware tools
System evaluation
Commercialization
Software tools
Development Tools (1/3)
Software tools
Product Name Software package C compiler Device file Project Manager Integrated debugger System simulator Real-time OS Task debugger System performance analyzer Middleware Performance analysis tool SP850 CA850Note 1 DF703xxxNote 2 PM plusNotes 1, 3 ID850Note 1, ID850NWNote 1, ID850QBNote 4 SM850Note 1, SM plusNote 5 RX850, RX850 Pro RD850, RD850 ProNote 6 AZ850Note 6 AP703000-Bxxx, AP703100-Bxxx TW850Note 1
Notes 1. Packaged in SP850 2. Download from the NEC Electronics Website. (URL: http://www.necel.com/micro/index_e.html) 3. Included with CA850 4. Included with IECUBE and IE-V850E1-CD-NW. 5. Instruction simulation version: Included with SP850. Instruction + peripheral simulation version: Only the SM plus for the PD70F3261Y is included with SP850. 6. Included with RX850, RX850 Pro Remark For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
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Development Tools (2/3)
Hardware tools (when using IECUBE)
Target Device V850ES/SG2, V850ES/SJ2 V850E/IA3, V850E/IA4, V850ES/IK1 V850ES/KE1, V850ES/KE1+, V850ES/KF1, V850ES/KF1+, V850ES/KG1, V850ES/KG1+, V850ES/KJ1, V850ES/KJ1+ V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, PD703229Y, 70F3229Y QB-V850ESSX2-ZZZ QB-V850EIA4-ZZZ QB-V850ESKX1H-ZZZ QB-V850ESFX2-ZZZ In-Circuit Emulator
Remarks 1. A separate socket is required for each above emulator. 2. A power supply, a USB interface cable, a debugger, and a simple programmer are included. A PC interface board is not required. 3. For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
Hardware tools (when using N-Wire CARD)
Target Device V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2, V850ES/SJ2, V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, V850ES/KJ1, V850ES/KJ1+, PD70F3229Y
Remarks 1. A target connection cable, a connector conversion board, a target connector, and a debugger are included. A power supply and a PC interface board are not required. 2. For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
On-Chip Debug Emulator IE-V850E1-CD-NW
Hardware tools (using other emulators)
Target Device Main Unit V850ES/SA2, V850ES/SA3 V850ES/KF1, V850ES/KG1, V850ES/KJ1 V850ES/SG2, V850ES/SJ2 V850ES/PM1 V850ES/FE2, V850/FF2, V850ES/FG2, V850ES/FJ2, PD703229Y, 70F3229Y V850ES/ST2 V850E/SV2 V850E/MA1, V850E/MA2 V850E/IA1 V850E/IA2 V850E/MS1 (5V), V850E/MS2 (5V) V850E/MS1 (3.3V) V850/SA1 V850/SB1, V850/SB2 V850/SV1 V850/SF1 V850/SC1, V850/SC2, V850/SC3 V853
Notes 1. A separate socket and probe are required for connection to the target system. The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part. 2. A separate socket is required for connection to the target system. The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part. 3. Depending on the target device package, a separate socket and probe may be required. The following items are required as common items. * PC interface board: IE-70000-PCI-IF-A or IE-70000-CD-IF-A * Power supply: IE-70000-MC-PS-B Remark For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
In-Circuit Emulator Emulation Board IE-703204-G1-EM1Note 1 IE-703217-G1-EM1Note 2 IE-V850ES-G1 IE-703288-G1-EM1Note 2 IE-703228-G1-EM1Note 2 IE-703239-G1-EM1Note 2 IE-703220-G1-EM1Note 2 IE-V850E-MC-A IE-V850E-MC IE-703102-MC IE-703166-MC-EM1 IE-703107-MC-EM1Note 3 IE-703116-MC-EM1 IE-703114-MC-EM1 IE-703102-MC-EM1Note 3 IE-703102-MC-EM1-A IE-703017-MC-EM1Note 3 IE-703037-MC-EM1Note 3 IE-703002-MC IE-703040-MC-EM1Note 3 IE-703079-MC-EM1Note 3 IE-703089-MC-EM1 IE-703003-MC-EM1
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Development Tools (3/3)
*
IECUBE configuration example
*
N-Wire CARD configuration example
In-circuit emulator (IECUBE) AC adapter (provided with ) USB interface cable (provided with ) Extension probe Note Exchange adapter (provided with ) Note Target connector (provided with ) Mount adapter Note If ordering the in-circuit emulator ( ), if the part number ends in "-ZZZ", the above exchange adapter ( ) and target connector ( ) are not provided.
Host machine (with PCMCIA slot) On-chip emulator IE-V850E1-CD-NW In-circuit emulator connection cable Connector conversion board In-circuit emulator connector
*
IE-V850ES-G1 configuration example
*
IE-V850E-MC, IE-V850E-MC-A, IE-703102-MC, IE-703002-MC configuration example
In-circuit emulator (main unit) Emulation board (connected inside main unit) Emulation probe Conversion adapter/conversion socket PC interface cable (provided with ) Power supply cable (provided with )
In-circuit emulator (main unit) Option board Power supply unit Conversion adapter/conversion socket (provided with PC interface cable (provided with ) )
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V850 Series Development Environment (1/2)
Development environment using in-circuit emulator, N-Wire emulator
Real-time OS Task debugger
Compiler
Debugger Analyzer
Integrated development environment
In-circuit emulator N-Wire emulator
RX850 RX850 Pro RD850 Note RD850 Pro Note
CA850
ID850 AZ850 Note TW850 ID850 CATS ZIPC850
IE-703002-MC IE-703102-MC IE-V850E-MC IE-V850E-MC-A IE-V850ES-G1 QB-V850ESSX2-ZZZ QB-V850EIA4-ZZZ QB-V850ESKX1H-ZZZ QB-V850ESFX2-ZZZ IE-V850E1-CD-NW IE-70000-MC-NW-A
Refer to Development Tools Hardware tools (when using N-Wire CARD) (p. 55)
Refer to Development Tools Hardware tools (when using IECUBE) (p. 55)
Refer to Development Tools Hardware tools (when using N-Wire CARD) (p. 55)
Nx85ET V852 V853, V853A V850/SA1 V850/SB1, V850/SB2 V850E/MA1 V850E/ IA1 Nx85ET Nx85ET, V850E/ME2, V850E/MA3, NA85E2, AS85EP2 V850E/MA3 V853, V853A V850/SV1 V850/SA1 V850/SB1, V850/SB2 V850E/MS1 V850E/MA1 Nx85ET, Nx85E V850E/IA1 V850ES/KF1, V850ES/KG1, V850ES/KJ1 V850E/ME2 V850ES/SG2, V850ES/SJ2, V850ES/Fx2, V850ES/Kx1+, V850ES/Kx1, V850ES/IK1, V850E/IA3, V850E/IA4
YDC
ID850NW
GHS ATI
Midas Lab
Nucleus PLUS
CCV850 CCV850E
Metrowerks
ID850QB AZ850 TW850
GHS
MULTI AZ850
KMC
RTE-V852-IE RTE-V853-IE RTE-V850/SA1-IE RTE-V850/SB1-IE RTE-V850E/MA1-IE RTE-V850E/IA1-IE RTE-1000-TP RTE-2000-TP KIT-V850E/MA3-IE UniSTAC V853 UniSTAC V850/SV1 UniSTAC V850/SA1 UniSTAC V850/SB1 UniSTAC V850E/MS1 UniSTAC V850E/MA1 UniSTAC Nx85ET UniSTAC V850E/IA1 UniSTAC V850ES/Kx1 UniSTACII/J V850E/ME2 IECUBE
CodeWarrior
Mispo
Sophia Systems
NORTi
Red Hat
PARTNER AZ850
Sophia Systems
GNU
KMC
exeGCC
GAIO
WATCHPOINT AZ850
GAIO
G-OS Native-G
XCC-V XASS-V
YDC
micro VIEW-G micro VIEW-PLUS
advice advice advice advice advice advice advice advice advice advice advice
V853 V850/SA1 V850/SB1 V850E/MS1 V850E/MA1 Nx85ET V850E/IA1 V850E/ME2 V850ES/KF1 V850ES/KG1 V850ES/KJ1
KMC
V853 V850/SA1 V850/SB1 V850E/MS1 V850E/MA1 Nx85ET V850E/IA1 V850E/ME2 V850ES/KF1 V850ES/KG1 V850ES/KJ1
PARTNER-ET II PARTNER-J PARTNER-Jet
Nx85ET, V850E/ME2 Nx85ET, V850E/ME2 Nx85ET, V850E/ME2
Note The RD850, RD850 Pro, and AZ850 can be used with the ID850, ID850QB, MULTI, PARTNER, and WATCHPOINT.
ATI CATS GAIO GHS KMC Metrowerks :Accelerated Technology, Inc. :Communication and Technology Systems, Inc. :Gaio Technology Co., Ltd. :Green Hills Software, Inc. :Kyoto Microcomputer Corporation :Metrowerks Corporation Midas Lab Mispo Red Hat Sophia Systems YDC Unmarked :Midas Lab Co., Ltd. :MiSPO, Inc. :Red Hat Corporation :Sophia Systems Co., Ltd. :Yokogawa Digital Computer Corporation :NEC Electronics
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V850 Series Development Environment (2/2)
Development environment using ROM emulator, evaluation board
Real-time OS Task debugger
Compiler
Debugger Analyzer
ROM emulator
Evaluation board Low-cost evaluation board (limited functions) Evaluation board
Cosmo
CA850 RX850 RX850 Pro
KMC KMC
CEB-V850/SA1 CEB-V850/SB1 exeGCC PARTNER AZ850 Note
V850/SA1 V850/SB1
RD850 Note RD850 Pro Note
CEB-V850E/MS1 CEB-V850E/MA1
V850E/MS1 V850E/MA1
GHS
CCV850 CCV850E
Midoriya
CEB-V850E/MA3 CEB-V850E/IA1 CEB-V850ES/FJ2 CEB-V850ES/SJ2
V850E/MA3 V850E/IA1 V850ES/FJ2 V850ES/SJ2
EMUSE-GII
ATI KMC Metrowerks GHS
Nucleus PLUS
PARTNER-ET II
Midoriya
Midas Lab
Code Warrior
MULTI AZ850 EMUSE
RTE-V852-PC RTE-V853-PC
V852 V853
Mispo
Red Hat
Lightwell
NORTi
GNU
MDX700
RTE-V850E/MS1-PC RTE-V850E/MA1-CB RTE-V850E/ME2-CB RTE-V850ES/SA3-CB
V850E/MS1 V850E/MA1 V850E/ME2 V850ES/SA3
APPLY
TK-850/KG1 CA850
GAIO GAIO
V850ES/KG1
Monitor version ID850
GAIO APPLY
G-OS Native-G
XCC-V XASS-V
XDEB-V SystemSimulator
TK-850/SA2
V850ES/SA2
APPLY
TK-850/SG2
V850ES/SG2
SG-703107-1 SG-703111-1
V850E/MA1 V850E/ME2
Note RD850, RD850 Pro, and AZ850 can be used with MULTI, PARTNER. APPLY ATI Cosmo Red Hat GAIO GHS KMC Lightwell :Application Corporation :Accelerated Technology, Inc. :Cosmo Co., Ltd. :Red Hat Corporation :Gaio Technology Co., Ltd. :Green Hills Software, Inc. :Kyoto Microcomputer Corporation :Lightwell Co., Ltd. Metrowerks Midas Lab Midoriya Mispo WRS eSOL Unmarked :Metrowerks Corporation :Midas Lab, Co., Ltd. :Midoriya Electric Co., Ltd. :MiSPO, Inc. :Wind River Systems, Inc. :eSOL Co., Ltd. :NEC Electronics
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Pamphlet U15412EJ4V1PF
Software Product
Software package (SP850)
Product configuration
The SP850 software package consists of the following software development tools. *C compiler (CA850) *Project Manager (PM plus) *Integrated debugger (ID850, ID850NW) (to be packaged) *System simulator (SM850, SM plus) (to be packaged) *Performance analysis tuning tool (TW850) *Device file (DF703xxx)
C compiler (CA850)
Features
*Complies with ANSI-C, a C language standard. *Supports libraries for embedded systems *Compact code size and faster execution speed can be realized through powerful optimization *Utilities useful for embedded systems (ROMization processor, etc.) *Description of embedded systems in C language (specification of memory allocation and I/O register access) is possible.
System simulator (SM850, SM plus)
Features
*Same operability as debugger *Target-less evaluation prior to target completion possible *In addition to the operation of the CPU itself, target system operation including on-chip peripheral unit and interrupt servicing can also be simulated. *Pseudo-target system construction and I/O operation are possible through external parts. *Data generated by 0/1 logic and timing charts can be input to the program being simulated. *Larger number of events than in-circuit emulator *Execution speed estimates can be done on the host machine to accurately simulate pipeline operationNote. *Construction by user target system users is possible through user open interface. *A peripheral I/O register status can be specified and when this status occurs, the system can be made to output an interrupt at the desired timing or transfer data to memory (peripheral I/O register event & action function). Note The pipeline mode is supported by the V853.
Project manager (PM plus)
Features
*Project management (management of target chip, source, and environment during debugging is possible.) *Supports wizard function during project creation *Automation of series of operations consisting of edit, build, and debug *Integration of Help function
Target devices
V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850/SC1, V850/SC2, V850/SC3, V850E/MS1, V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2, V850ES/SA2, V850ES/SA3, V850ES/KF1, V850ES/ KG1, V850ES/KJ1, V850ES/SG2Note, V850ES/SJ2Note, V850ES/FE2Note, V850ES/FF2Note, V850ES/FG2Note, V850ES/FJ2Note Note Only SM plus is supported
N-Wire card (IE-V850E1-CD-NW)
Features
*Supports V850E and V850ES *Emulator for on-chip debugging *Enables realization of low-cost development environment *Compact PC card type *Function for download to internal flash ROM *Same ease of operation as ID850
Target Devices
V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2, V850ES/SJ2, V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, V850ES/KJ1, V850ES/ KJ1+, PD70F3229Y
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Integrated debugger (ID850, ID850NW, ID850QB)
Features
*Supports object files *Debugging at source level *Debugging using target resources *Real-time execution on target *Event setting according to complex software operation *Online help function
Task debuggers (RD850, RD850 Pro)
Features
*Display detailed information on OS resources such as tasks. *Display source of referenced tasks. *Included with real-time OS (RX850, RX850 Pro)
Real-time OSs (RX850, RX850 Pro)
Features
*Comply with global standard (ITRON 3.0 specifications). *Support power management function. *Enable embedding of required functions only (selection of system calls to be used). *Support sophisticated task development through task debugger (RD). *Support application operation analysis through system performance analyzer (AZ) *Inherit attributes of real-time OS of 16-bit V Series and 78K Series
TCP/IP software library (RX-NET) for V850E products
Product configuration
*TCP/IP protocol stack *Applications *LAN control driver
Features
*RFC-compliant *Support of numerous socket interfaces/libraries *Support of applications as option products *Provided device driver *Support of NEC Electronics real-time OS (RX850 Pro)
System performance analyzer (AZ850)
Features
*Detection of bugs through system timing errors *Detection of bugs due to simultaneous operation of complex tasks *Detection/analysis of real-time system execution performance *Operation linked to various debuggers
Target devices
V850E products
Performance analysis tuning tool (TW850)
Features
*Performance analysis changing the internal ROM size, instruction cache size, etc., is possible. *Display of inter-function call relationships, call count information, function execution time information, and cache mishit information *Functions optimally placed to reduce cache mishit count *Functions causing bottlenecks placed into internal ROM or other high-speed access memory
In-circuit emulator (IE, IECUBE)
Features
*Emulator functions loaded in dedicated chip to realize high equivalence *Connectable to variety of computers *Large array of emulation functions *Realization of maximum operating frequency equivalent to that of device
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OSEK/VDX specifications compliant OS (RX-OSEK850)
Features
* Kernel Compliant with OSEK/VDX OS Ver. 2.0 specifications Supports 4 conformance classes: BCC1, BCC2, ECC1, and ECC2. * Configurator Configurator (OIL850) allowing easy system information creation provided as standard. Configuration files support formats compatible with OIL Ver. 2.0. * Task debugger (RD-OSEK850) Task debugger effective for application debugging using RX-OSEK850 provided as standard
RISC microcontroller reference platform (SolutionGearTM)
Features
* * * * * * * General-purpose evaluation boards available as RISC microcontroller software development platform Target CPU: V850E/MA1, V850E/ME2 Industry standard PC-compatible interfaces including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB, provided CPU independent motherboards and CPU boards used combined Bundled real-time OS, middleware, and sample drivers MULTI-PARTNER remote monitor version can be used Reference design information provided
Actually tested
Circuit diagrams attached
This board usable for comparison purposes Not working properly. Is the cause hardware or software?
I want to measure Is it possible to realize CPU performance. such a function?
First time I use this device, please provide sample circuits.
Device selection
S/W
Software design/ development
Debug
H/W
Board design/ development
Time
I would like to use OS/middleware. Bundle OS/ middleware
I want to start software development prior to the board. Various peripheral devices are mounted, so debugging can be started from device-independent parts
Likely to be a long time until OS/middleware are ready
Provide user-own coding block as sample according to this board
At such times, RISC microcontroller reference platform
Cooperation with third parties
By deepening cooperation with third-party companies and forming an array of tools combining NEC Electronics-made tools and third-party-made tools, NEC Electronics offers development environments that support the diverse needs of users.
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V850 Series Website
Information about V850 microcontrollers and V850 microcontroller development environment can be viewed at the NEC Electronics Microcomputer website.
http://www.necel.com/micro/index_e.html
Microcontroller Search Tool
* * *
Facility for searching for V850 Series microcontrollers by function
Product Lineup
Microcontroller product information
Document Download
Microcontroller, development environment, and middleware documents can be downloaded from this area. http://www.necel.com/micro/english/document/index.html
Development Tool Download
*
V850 Series development tools can be downloaded from this area. Customers who are registered users receive upgrade information by email. http://www.necel.com/micro/ods/eng/index.html
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Microcontroller Search Tool
Facility for searching V850 Series microcontrollers by function.
Specify search condition(s) here.
The corresponding NEC Electronics development environment documents can be searched from here with a single link.
Development Tool List
Document Information List
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Product Lineup
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MEMO
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MEMO
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Pamphlet U15412EJ4V1PF
EEPROM, IEBus, IECUBE, SolutionGear, and VR are trademarks of NEC Electronics Corporation. MIPS is a trademark of MIPS Technologies, Inc. in the United States. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. JAVA and all trademarks and logos related to JAVA are either registered trademarks or trademarks of Sun Microsystems, Inc. in the United States and/or other countries. Ethernet is a trademark of Xerox Corporation. TRON stands for The Real-time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. ITRON is an abbreviation of Micro Industrial TRON. TRON, ITRON, and ITRON do not refer to specific products or product groups. All other marks or trademarks in this document are property of their respective holders. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of September, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
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Pamphlet U15412EJ4V1PF
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For further information, please contact:
NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [North America] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.necelam.com/ [Europe] NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.ee.nec.de/ Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Succursale Francaise 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven The Netherlands Tel: 040-2445845 Tyskland Filial P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 [Asia & Oceania] NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311
Document No. U15412EJ4V1PF00 (4th edition) Date Published January 2005 N CP(K)
C
G04.1
2002, 2004
Printed in Japan

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