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| www..com DOC Title EK7603 Data Sheet DOC NO REV Page / Revision History / / Revise item / Content New Issue P.5 . OSEL = H or open H OSEL = L L or open 2. When EDGSL = L L or open 0.2 / TPL7603-0 REV. 0. 0.2 REV Date 2003/ /27 2003/6/5 Eff. Date 2003/3/20 2003/6/ 7 REV. Page .com DataShee ON C .com DataSheet 4 U .com EN ID F L IA T www..com Eureka Microelectronics, Inc. EK7603 t4U.com .com DataShee 402/480-Output TFT LCD Analog Source Driver 6F, NO.12, INNOVATION 1 . RD., SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU CITY, TAIWAN, R.O.C. http://www.eureka.com.tw ON C EN ID F ST L IA T .com DataSheet 4 U .com www..com EUREKA Table of Contents EK7603 Page 1.GENERAL DESCRIP TION... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .3 ... ... ... ... ..... ...... .3 2.FEATURES... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 3.BLOCK DIAGRAM... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... .4 4.PIN FUNCTION DESCRIPTIONS... ... ... ... ... ... ... ... ... ... ... ... ... ......5 ... ... ... ... ...... 5.FUNCTION OPERATIONS... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...7 5.1 5.2 5.3 5.4 5.5 Operation timing Number of output selection Sampling modes Color mode selection Relationship between OE and output waveform 6.ABSOLUTE MAXIMUM RATINGS... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..... ... ... ... 11 6.1 Absolute maximum ratings 6.2 Recommended operating conditions t4U.com .com 7.ELECTRICAL CHARACTERISTICS ... ... ... ... ... ... ... ... ... ... ... ... ...... ... ... ... .... 12 ... 7.1 DC characteristics 7.2 AC characteristics 7.3 Timing chart DataShee 8.DEFINITIONS ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..15 ... ... ... ... ... ... ... ... ... 8.1 Data sheet status and application information 8.2 Life support application June 2003 2 ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 402/480- Output TFT LCD Analog Source Driver EK7603 1. GENERAL DESCRIPTION The EK7603 is an analog, fully color, source driver for TFT LCD panels designed for camera, TV etc. Analog R, G and B signal are applied directly on the chip. For each of the 402/480 outputs, the voltage is sampled and buffered to the panel. With a double sample and hold circuit a new voltage can be sample whereas the previous sample voltage is applied to the panel. According to different modes, the 3 input voltages (VA, VB, VC) can be applied on different output to support various pixel array types. The 3 input voltages (VA, VB, VC) can be sampled simultaneously or sequentially to have a better flexibility with the input voltage. Using enable signal (STHx), several chips can be cascaded for large panel. 2. FEATURES 402/480 analog source driver outputs (OSEL) High frequency Sampling 10MHz Automatic low power consumption mode after data capture (gated clock) Bi-directional shift capability (L/R) Simultaneous or Sequential RGB acquisition mode (MODE) RGB color selection to match different types of color filters (Q1H, Q2H) Output enable signal edge selectable (EDGSL) Logic power supply voltage VDD : 2.7V - 5.25V LCD power supply voltage AVDD: 4.5V - 5.5V Output dynamic range AV SS+0.2V to AV DD -0.2V Bare chip with gold bumper for COG application t4U.com .com DataShee June 2003 3 ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 3. BLOCK DIAGRAM EK7603 t4U.com .com DataShee Fig. 1 Block diagram Clock MUX Selects if the sampling is simultaneous or sequential. Also gates the clock. 3 x 134/160-bit bi-directional shift register Generates enable signals for sequential sampling 134/160 groups of 3 input colors. Line control Select sample circuit SHA or SHB and the high impedance output state SH control MUX Select which sample and hold circuit samples the analog input value. AMUX According to the controls signals, selects which input color goes to which group of outputs. Sample and hold Circuit (SHA, SHB) Sample the input voltage when the enable signal of the shift register is generated and hold this value until it is stored on the panel. Buffers Drive the sample grayscale voltage on the panel. June 2003 -4- ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 4. PIN FUNCTION DESCRIPTION Pin description Pin Type Output Table 1. Signal Name Qa1 to Qa160 Qb1 to Qb160 Qc1 to Qc160 VA VB VC L/R EK7603 Function Liquid-crystal application voltages Each QaX, QbX or QcX correspond to one of the analog sample input signal VA, VB or VC. Video input signal Analog video input signal that is sampled internally and applied to the panel. Controls the display data shift direction L/R = H : STH1 input, Qa1Qc160, STH2 output. L/R = L : STH2 input, Qc160 Qa1, STH1 output. Right shift start pulse L/R = H : Becomes the start pulse input pin L/R = L : Becomes the start pulse output pin Left shift start pulse L/R = H : Becomes the start pulse output pin L/R = L : Becomes the start pulse input pin Sampling clock input Refers to the analog data-sampling clock. The sampling starts at the first rising edge of CPH1 when STH1 (L/R = H) is activated. The sampling can be simultaneous or sequential. When in simultaneous mode (MODE = H), the sampling is .com made during CPH1 period for all output, but CPH2 and CPH3 must be fixed to VDD or VSS. When in sequential mode (MODE = L, L/R = H), the sampling is made according the table below: CPH1 control the sampling for Qa1Qa160 CPH2 control the sampling for Qb1Qb160 CPH3 control the sampling for Qc1 Qc160 When in sequential mode (MODE = L, L/R = L), the sampling is made according the table below: CPH1 control the sampling for Qc160Qc 1 CPH2 control the sampling for Qb160Qb1 CPH3 control the sampling for Qa160Qa1 Load line The sampled voltages are connecting to the panel at the rising/falling edge (EDGSL) of OE. The outputs of SHA(B) that was in sample mode are applied to the panel, whereas the SHB(A) becomes ready to sample new values. Number of output selection OSEL = H : 402 output mode OSEL = L or open : 480 outputs mode Output pins Qx68 Qx93 are invalid in 402-output mode. Output enable signal edge select. When EDGSL = H, OE will be active at falling edge. When EDGSL = L or open, OE will be active at rising edge. Sampling mode selection MODE = H: Simultaneous sampling MODE = L or open: Sequentially sampling -5- Input Input STH1 Bi-direction STH2 Bi-direction CPH1 CPH2 CPH3 Input t4U.com DataShee OE Input OSEL Input (Pull-down) EDGSL Input (Pull-down) Input (Pull-down) MODE June 2003 ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA Q1H Q2H V DD V SS AVDD AVSS Input (Pull-down) Power Power Power Power EK7603 Color selection input Q1H and Q2H select which input voltage (VA, VB, VC) correspond to QaX, QbX, QcX outputs. Logic part power supply Logic part ground Analog part power supply Analog part ground t4U.com .com DataShee June 2003 -6- ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 5. FUNCTIONAL DESCRIPTION 5.1 Operation Timing EK7603 t4U.com .com DataShee Fig. 2 Operation timing diagram The start condition is initiated by applying a start pulse to the enable input pin (STH1 when L/R = H) at the beginning of each line on the first chip. During the next 134/160 CPH1 rising edges, this source driver sample 134/160 times 3 display input voltage (3 RGB dot x 134/160 pixels). After sampling the 134/160th group of input voltages, it activates the enable output signal (STH2 when L/R= H) to enable the following chip. As soon as the loading of the input voltage is achieved for a complete line, the controller activates the OE signal to force the 402/480 output buffers in a high impedance state. Then the outputs of SHA(B) that were in sample mode are applied to the output buffers, whereas the SHB(A) becomes ready to sample new values. Finally, at the rising edge of OE, the 402/480 output buffers drive the sample voltages to the panel. June 2003 -7- ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 5.2 Number of output selection EK7603 Fig. 3 402-output mode timing diagram The OSEL pin allows using the chip as a 402-output or a 480-output driver. When 402 -output mode is selected, outputs Qa68 to Qc93 are unavailable and the sampling pass from Qa67 to Qa94, Qb67 to Qb94 t4U.com and Qc67 to Qc94. Then the sampling of the whole chip is made in 134 CPH1 periods. .com DataShee 5.3 Sampling modes Fig. 4 Simultaneous sampling mode June 2003 -8- ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA Each input is sampled simultaneously synchronised with CPH1 rising edge. th EK7603 STH2 signal is generated at the falling edge of the 134/160 period of CPH1 since the start pulse. t4U.com Fig. 5 Sequential sampling mode .com DataShee Each input is sampled sequentially synchronised with the associated rising edge of the corresponding clock. CPH1 controls the sample for QAx outputs, CPH2 controls the sample for QBx outputs and CPH3 controls the sample for QCx outputs. STH2 signal is generated at the falling edge of the 134/160 period of CPH1 since the start pulse. th 5.4 Color mode selection The Q1H and Q2H control the color selection to match various color filters in shown as following table. Table 2. Color mode selection table Q1H L L H Q2H L H X QA VA VC VB QB VB VA VC QC VC VB VA June 2003 -9- ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 5.5 Relationship between OE and output waveform EK7603 Fig. 6 OE timing diagram At OE rising/falling edge, the sample voltages are output on the panel. As long as OE is active, the 402/480 output buffers are forced in a high impedance state. t4U.com .com DataShee June 2003 - 10 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 6. ABSOLUTE MAXIMUM RATINGS 6.1 Absolute maximum ratings Table 3. Absolute maximum ratings (VSS = AV SS = 0 V) Parameter Logic Part Supply Voltage Analog Part Supply Voltage Logic Part Input Voltage Video Input Voltage Logic Part Output Voltage Driver Part Output Voltage Storage Temperature EK7603 Symbol VDD AVDD VI1 VI2 VO1 VO2 TSTG Rating -0.5 to +7.0V -0.5 to +7.0V -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to AVDD + 0.5 -55 to +125 Unit V V V V V V C Caution: If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum rating, therefore, specify the values exceeding which the product may be physically damaged. Be t4U.com .com sure to use the product within the range of the absolute maximum rating. DataShee 6.2 Recommended operating range Table 4. Recommended operating range (VSS = AV SS = 0 V) Parameter Logic Part Supply Voltage Analog Part Supply Voltage Video Input Voltage Operating Ambient Temperature Maximum Clock Frequency OE period Symbol VDD AVDD VVIDEO TA FCPH TOE Conditions MIN 2.7 4.5 AVSS + 0.2 -30 TYP MAX 5.25 5.5 AVDD - 0.2 75 10 Unit V V V C MHz s 64 200 June 2003 - 11 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 7. ELECTRICAL CHARACTERISTICS 7.1 DC characteristics Table 5. DC characteristics EK7603 (TA= -30 to +75C, V DD = 2.7V to 5.25V, AV DD = 4.5V to 5.5V, VSS=AVSS=0V) Parameter Logic High-level Input Voltage Logic Low-level Input Voltage Logic Input Leakage Current Video Input Leakage Current Logic High-level Output Voltage Logic Low-level Output Voltage Output Voltage Range Output Voltage Deviation Symb ol VDIH VDIL ILIL IVIL VOH VO L V0 V0 IDD IADD Note 1 Note 2 Note 3 Condition MIN. 0.7*VDD 0.0 TYP. MAX. VDD 0.3*VDD 1.0 1.0 Unit V V A A V STH1(STH2), IOH=-400A STH1(STH2), IOL=+400A VDD - 0.4 0.4 0.2 AVDD - 0.2 20 TBD TBD TBD TBD V V mV mA mA t4U.com Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption .com DataShee Note 1: Deviation between input voltage and output value. Voltage on the output pin 30us after the rinsing edge of OE. VVIDEO= 0.2V to AV DD -0.2V. Note 2: FCPH1=10MHz,In Simultaneous Clock Mode, TOE=63s, TIWL = 5us, No load. Note 3: Video input = AVDD /2, No Load. June 2003 - 12 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 7.2 AC characteristics Table 6. AC characteristics (TA= -30 to +75C, V DD = 2.7V to 5.25V, VSS=AVSS=0V, TR = TF = 5.0ns) Parameter Clock Period Clock high-level width Clock low-level width Delay time Between Clocks STH Setup Time STH Hold Time OE high-level width OE low-level width OE -STH Timing STH Pulse Delay Time EK7603 Symbol TCP TCWH TCWL TC12, TC23 TSS TSH TIWH TIWL TOE-STH TSD TDD Condition MIN. 100 40 40 15 10 10 30 160 TBD TYP. MAX. Unit ns ns ns 1/2*TCP ns ns ns s ns ns C L =20pF 20 12 20 ns s t4U.com .com Driver Output Delay Time C L =25pF, R L=25k DataShee June 2003 - 13 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 7.3 Timing chart Unless otherwise specified, the input level is defined to VIH = 0.7 VDD , VIL = 0.3 V DD EK7603 t4U.com .com DataShee Fig. 7 Timing June 2003 - 14 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com www..com EUREKA 8. DEFINITIONS 8.1 Date sheet status and application information Data sheet status EK7603 Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. 8.2 Life support application These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Eureka customers using or selling these products for use in such applications do so at their own risk and agree to fully inde mnify Eureka for any damages resulting from such improper use or sale. t4U.com .com June 2003 - 15 - ON C EN ID F L IA T Preliminary Rev. 0.2 .com DataSheet 4 U .com |
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