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CMOS IC
LC863364B/56B/48B/40B/32B/28B/24B/20B/16B 8-Bit Single Chip Microcontroller
Under Development
LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
8-bit Single Chip Microcontroller with on-chip 64K/56K/48K/40K/32K/28K/24K/20K/16K-byte ROM, on-chip 640/512-byte RAM and 352x9 bit OSD RAM
Overview
The LC863364/56/48/40/32/28/24/20/16B are 8-bit single chip microcontrollers with the following on-chip functional blocks: - CPU : Operable at a minimum bus cycle time of 0.424s - On-chip ROM capacity Program ROM : 64K/56K/48K/40K/32K/28K/24K/20K/16K bytes CGROM : 16K bytes - On-chip RAM capacity : 640/512 bytes - OSD RAM : 352 x 9 bits - Five channels x 8-bit AD Converter - Three channels x 7-bit PWM - Two 16-bit timer/counters, 14-bit base timer - 8-bit synchronous serial interface circuit - IIC-bus compliant serial interface circuit (Multi-master type) - ROM correction function - 15-source 9-vectored interrupt system - Integrated system clock generator and display clock generator X ' tal oscillator (32.768kHz) for PLL reference is used for TV control. All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please
notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation.
Ver:0.93 62102
System Business Division Micon Business Unit ogawa 1/22
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
Features
(1) Read-Only Memory (ROM) : 65536 40960 24576 16128 512 384 128 352 x x x x x x x x 8 8 8 9 8 8 8 8 bits bits bits bits / 57344 x 8 bits / 49152 x 8 bits / / 32768 x 8 bits / 28672 x 8 bits / / 20480 x 8 bits / 16384 x 8 bits for program for CGROM
(2) Random Access Memory (RAM) :
bits bits bits bits
(working area) : LC863364/56/48/40B (working area) : LC863332/28/24/20/16B (working or ROM correction function) (for CRT display)
(3) OSD functions - Screen display : 36 characters x 16 lines (by software) - RAM : 352 words (9 bits per word) Display area : 36 words x 8 lines Control area : 8 words x 8 lines - Characters Up to 252 kinds of 16 x 32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts : a 16 x 17 dot and 8 x 9 dot character font - Various character attributes Character colors : 16 colors Character background colors : 16 colors Fringe / shadow colors : 16 colors Full screen colors : 16colors Rounding Underline Italic character (slanting) - Attribute can be changed without spacing - Vertical display start line number can be set for each row independently (Rows can be overlapped) - Horizontal display start position can be set for each row independently - Horizontal pitch (bit 9 - 16) *1 and vertical pitch (bit-32) can be set for each row independently - Different display modes can be set for each row independently Caption * Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode - Ten character sizes *1 Horez. x Vert. = (1 x 1), (1 x 2), (2 x 2), (2 x 4), (0.5 x 0.5) (1.5 x 1), (1.5 x 2), (3 x 2), (3 x 4), (0.75 x 0.5) - Shuttering and scrolling on each row - Simplified Graphic Display *1 Note : range depends on display mode : refer to the manual for details. (4) Bus Cycle Time / Instruction-Cycle Time Bus cycle time 0.424s 7.5s 183.1s Instruction cycle time 0.848s 15.0s 366.2s System clock oscillation Internal VCO (Ref : X ' tal 32.768kHz) Internal RC Crystal Oscillation Frequency 14.156MHz 800kHz 32.768kHz Voltage 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V
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(5) Ports - Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually: 4 ports (20 terminals) - Input port : 1 port (1 terminal) (6) AD converter - 5 channels x 8-bit AD converters (7) Serial interfaces - IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. be connected internally. - Synchronous 8-bit serial interface (8) PWM output - 3 channels x 7-bit PWM (9) Timer - Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. - Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode0/1,the resolution of Timer1/PWM is 1 tCYC In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC - Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 (10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows
The two data lines and two clock lines can
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(12) ROM correction function Max 128 bytes / 2 addresses (13) Interrupts - 15 sources 9 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H,T1L 7. SIO0 8. Vertical synchronous signal interrupt ( VS ), horizontal line ( HS ), AD 9. IIC, Port 0 - Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. (14) Sub-routine stack level - A maximum of 128 levels (stack is built in the internal RAM) (15) Multiplication/division instruction - 16 bits x 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (16) 3 oscillation circuits Built-in RC oscillation circuit used for the system clock Built-in VCO circuit used for the system clock and OSD X ' tal oscillation circuit used for base timer, system clock and PLL reference
(17) Standby function - HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. - HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X ' tal oscillations. This mode can be released by the following conditions. * Pull the reset terminal ( RES ) to low level. * Feed the selected level to either P70/INT0 or P71/INT1. * Input the interrupt condition to Port 0. (18) Package - DIP42S - QIP48E
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(19) -
Development tools Flash EEPROM: Evaluation chip: Emulator:
LC86F3364A LC863096 EVA86000 (main) + ECB863200* or ECB863200A (evaluation chip board) + POD863300 (pod: DIP42S) or POD863301 (pod: QIP48E) * This product is no longer available
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System Block Diagram
Interrupt Control
IR
PLA
Standby Control
ROM
RC VCO
Clock Generator
X'tal
PC PLL
IIC
ROM Correct Control
ACC
SIO0
XRAM
B Register
Timer 0
Bus Interface
C Register
Timer 1
Port 1 ALU
Base Timer
Port 6
ADC
Port 7
PSW
INT0-3
Noise Rejection Filter
Port 8
RAR
PWM
CGROM
RAM OSD Control Circuit
Stack Pointer VRAM Port 0
Watch Dog Timer
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
Pin Assignment
* DIP42S
P10/SO0 P11/SI0 P12/SCK0 P13/PWM1 P14/PWM2 P15/PWM3 P16 P17/PWM VSS XT1 XT2 VDD P84/AN4 P85/AN5 P86/AN6 P87/AN7 RES FILT P83/AN3 VS HS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0 I BL B G R
Package Dimension (unit : mm)
SANYO : DIP-42S(600mil) * QIP48E
P14/PWM2 P13/PWM1 P12/SCK0 P10/SO0
P11/SI0
P07
P06
P05
P04 38
48
47
46
45
44
43
42
41
40
39
37
P03
NC
NC
P15/PWM3 P16 P17/PWM VSS XT1 XT2 VDD NC P84/AN4 P85/AN5 P86/AN6 P87/AN7
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 12
36 35 34 33 32 31 30 29 28 27 26 25
P02 P01 P00 NC
Package Dimension (unit : mm)
P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P63/SCLK1 P62/SDA1 P61/SCLK0 P60/SDA0
BL
G
R
B
I
P83/AN3
FILT
RES
NC
NC
VS
HS
SANYO : QIP-48E
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Pin Description
Pin Description Terminal VSS XT1 XT2 VDD
RES
FILT
VS HS
R G B I BL Port 0 P00 - P07
Table I/O I O I O I I O O O O O
I/O
Port 1 P10 - P17
I/O
Function Description Negative power supply Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Intensity ( I ) output terminal of RGB image output Fast blanking control signal Switch TV image signal and OSD image signal *8-bit input/output port, Input/output can be specified in nibble unit *Other functions HOLD release input Interrupt input *8-bit input/output port Input/output can be specified in a bit *Other functions P10 SIO0 data output P11 SIO0 data input / bus input/output P12 SIO0 clock input/output P13 PWM1 output P14 PWM2 output P15 PWM3 output P17 Timer1 (PWM) output *4-bit input/output port Input/output can be specified for each bit *Other functions P60 IIC0 data I/O P61 IIC0 clock output P62 IIC1 data I/O P63 IIC1 clock output
Option
Pull-up resistor provided/not provided Output Format CMOS/Nch-OD Output Format CMOS/Nch-OD
Port 6 P60 - P63
I/O
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Terminal Port 7 P70 P71 - P73
I/O I/O
Port 8 P83 P84-P87 NC
I I/O -
Function Description *4-bit input/output port Input or output can be specified for each bit *Other function P70 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses rising falling rising/ H level L level vector falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH *1-bit input port 4-bit input/output port Input or output can be specified for each bit *Other function AD converter input port (5 lines) unused terminal Leave open
Option
* Output form and existence of pull-up resistor for all ports can be specified for each bit. * Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. * Port status in reset Terminal Port 0 Port 1 I/O I I Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF
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1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Parameter Supply voltage Input voltage Output voltage Input/output voltage High Peak level output output current current Total output current Low level output current Peak output current Total output current Maximum power dissipation Operating temperature range Storage temperature range Symbol VDDMAX VI(1) VO(1) VIO IOPH(1) IOPH(2) IOAH(1) IOAH(2) IOAH(3) IOPL(1) IOPL(2) IOPL(3) IOAL(1) IOAL(2) IOAL(3) Pdmax Pins VDD * RES , HS , VS , P83 R, G, B, I, BL, FILT *Ports 0, 1, 6, 7, 84-87 *Ports 0, 1, 7, 84-87 R, G, B, I, BL *Ports 0, 1 Ports 7, 84-87 R, G, B, I, BL Ports 0, 1, 6, 84-87 Port 7 R, G, B, I, BL Ports 0, 1 Ports 6, 7, 84-87 R, G, B, I, BL DIP42S QIP48E Conditions Ratings unit typ. max. V +7.0 VDD+0.3 VDD+0.3 VDD+0.3 mA
VDD[V]
min. -0.3 -0.3 -0.3 -0.3
*CMOS output *For each pin. *CMOS output *For each pin. Total of all pins. Total of all pins. Total of all pins. For each pin. For each pin. For each pin. Total of all pins. Total of all pins. Total of all pins. Ta=-10 to +70C
-4 -5 -20 -10 -15 20 15 5 40 40 15 690 370 -10 +70
mW C
Topr
Tstg
-55
+125
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2. Recommended Operating Range at Ta=-10C to +70C, VSS=0V
Parameter Operating supply voltage range Hold voltage Symbol VDD(1) VDD(2) VHD VDD VDD Pins Conditions 0.844s tCYC 0.852s 4s tCYC 400s RAMs and the registers data are kept in HOLD mode. Output disable Output disable Ratings typ. unit V
VDD[V]
min. 4.5 4.5 2.0
max. 5.5 5.5 5.5
High level input voltage
VIH(1) VIH(2)
Port 0 (Schumitt) *Ports 1,6 (Schumitt) *Port 7 (Schumitt) port input/ interrupt * HS , VS , RES (Schumitt) Port 70 Watchdog timer input *Port 8 port input Port 0 (Schumitt) *Ports 1,6 (Schumitt) *Port 7 (Schumitt) port input/ interrupt * HS , VS , RES (Schumitt) Port 70 Watchdog timer input Port 8 port input
4.5 - 5.5 0.6VDD 4.5 - 5.5 0.75VDD
VDD VDD
VIH(3)
Output disable
4.5 - 5.5 VDD-0.5
VDD
VIH(4) Low level input voltage VIL(1) VIL(2)
Output disable Output disable Output disable
4.5 - 5.5 0.7VDD 4.5 - 5.5 4.5 - 5.5 VSS VSS
VDD 0.2VDD 0.25VDD
VIL(3)
Output disable
4.5 - 5.5
VSS
0.6VDD
VIL(4) Operation cycle time tCYC(1) tCYC(2)
Output disable *All functions operating *AD converter operating *OSD is not operating *OSD and AD converter are not operating Internal RC oscillation
4.5 - 5.5 4.5 - 5.5 4.5 - 5.5
VSS 0.844 0.844 0.848
0.3VDD 0.852 30 s
tCYC(3)
4.5 - 5.5
0.844
400
Oscillation frequency range
FmRC
4.5 - 5.5
0.4
0.8
3.0
MHz
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3. Electrical Characteristics at Ta=-10C to +70C, VSS=0V
Parameter High level input current Symbol IIH(1) Pins Ports 0, 1, 6, 7, 8 Conditions *Output disable *Pull-up MOS Tr. OFF *VIN=VDD (including the off-leak current of the output Tr.) *VIN=VDD *Output disable *Pull-up MOS Tr. OFF *VIN=VSS (including the off-leak current of the output Tr.) VIN=VSS Ratings typ. unit A
VDD[V] 4.5 - 5.5
min.
max. 1
IIH(2) Low level input current IIL(1)
* RES * HS , VS Ports 0, 1, 6, 7, 8
4.5 - 5.5 4.5 - 5.5 -1
1
IIL(2) High level output voltage Low level output voltage VOH(1)
VOH(2) VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) Rpu
Pull-up MOS Tr. resistance Bus terminal RBS short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis VHIS voltage Pin capacitance CP
* RES * HS , VS *CMOS output of IOH=-1.0mA ports 0,1,71-73, 84-87 R, G, B, I, BL IOH=-0.1mA Ports 0,1,71-73, IOL=10mA 84-87 Ports 0,1,71-73, IOL=1.6mA 84-87 *R, G, B, I, BL IOL=3.0mA *Port 6 Port 6 IOL=6.0mA Port 70 IOL=1mA *Ports 0, 1, 7, VOH=0.9VDD 84-87 *P60-P62 *P61-P63
4.5 - 5.5 4.5 - 5.5
-1 VDD-1 V
4.5 - 5.5 VDD-0.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5
1.5 0.4 0.4 0.6 0.4 80 300
13
38 130
k
*Ports 0, 1, 6, 7 * RES * HS , VS All pins
Output disable
4.5 - 5.5
0.1VDD
V
*f=1MHz *Every other terminals are connected to VSS. *Ta=25C
4.5 - 5.5
10
pF
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4. Serial Input/Output Characteristics at Ta=-10C to +70C, VSS=0V
Parameter Input clock Cycle Low Level pulse width High Level pulse width Cycle Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK SI0 *SCK0 *SCLK0 *Use pull -up resistor (1k) when Nch opendrain output. *Refer to figure 4. *Data set-up to SCK0. *Data hold from SCK0. *Refer to figure 4. *Data hold from SCK0. *Use pull-up resistor (1k) when Nch opendrain output. *Refer to figure 4. 4.5 - 5.5 Pins *SCK0 *SCLK0 Conditions Refer to figure 4. VDD[V] 4.5 - 5.5 min. 2 1 1 2 1/2tCKCY 1/2tCKCY 4.5 - 5.5 0.1 s Ratings typ. max. unit tCYC
Serial clock Serial input
Low Level pulse width High Level pulse width Data set up time
Data hold time
Output clock
tCKI
0.1
Output delay time (Using external clock) Output delay time (Using internal clock)
tCKO(1)
SO0
4.5 - 5.5
Serial output
7/12tCYC +0.2 1/3tCYC +0.2
tCKO(2)
SO0
4.5 - 5.5
5. IIC Input/Output Conditions at Ta=-10C to +70C, VSS=0V
Parameter SCL Frequency BUS free time between stop - start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition (Note) Symbol Standard min. max. 0 100 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 4.0 High speed min. max. 0 400 1.3 0.6 1.3 0.6 0.6 0 0.9 100 20+0.1Cb 300 20+0.1Cb 300 0.6 unit kHz s s s s s s ns ns ns s
fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Refer to figure 9 Cb : Total capacitance of all BUS (unit : pF)
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6. Pulse Input Conditions at Ta=-10C to +70C, VSS=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins *INT0, INT1 *INT2/T0IN INT3/T0IN (1tCYC is selected for noise rejection clock.) INT3/T0IN (16 tCYC is selected for noise rejection clock.) INT3/T0IN (64 tCYC is selected for noise rejection clock.)
RES HS , VS
Conditions *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable
VDD[V] 4.5 - 5.5 4.5 - 5.5
min. 1 2
Ratings typ. max.
unit tCYC
tPIH(3) tPIL(3)
*Interrupt acceptable *Timer0-countable
4.5 - 5.5
32
tPIH(4) tPIL(4)
*Interrupt acceptable *Timer0-countable
4.5 - 5.5
128
tPIL(5) tPIH(6) tPIL(6)
Rising/falling time
tTHL tTLH
HS
Reset acceptable *Display position controllable *The active edge of HS and VS must be apart at least 1 tCYC. *Refer to figure 6. Refer to figure 6.
4.5 - 5.5 4.5 - 5.5
200 8
s
4.5 - 5.5
500
ns
7. AD Converter Characteristics at Ta=-10C to + 70C, VSS=0V
Parameter Resolution Absolute precision Conversion time Analog input voltage range Analog port input current Symbol N ET tCAD VAIN AN3 - AN7 Pins Conditions (Note 3) ADCR2=0 (Note 4) ADCR2=1 (Note 4) VSS 16 32 VDD Ratings typ. 8 unit bit LSB tCYC V A
VDD[V] 4.5 - 5.5
min.
max. 1.5
IAINH IAINL
VAIN=VDD VAIN=VSS
1 -1
(Note 3) Absolute precision does not include quantizing error (1/2LSB). (Note 4) Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent.
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8. Sample Current Dissipation Characteristics at Ta=-10C to +70C, VSS=0V
The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation during basic operation (Note 5) Symbol IDDOP(1) Pins VDD Conditions *FmX'tal=32.768kHz X'tal oscillation *System clock : VCO *VCO for OSD operating *Internal RC oscillation stops *HALT mode *FmX'tal=32.768kHz X'tal oscillation *System clock : VCO *VCO for OSD stops *Internal RC oscillation stops *HALT mode *FmX'tal=32.768kHz X'tal oscillation *VCO for system stops *VCO for OSD stops *System clock : Internal RC *HALT mode *FmX'tal=32.768kHz X'tal oscillation *VCO for system stops *VCO for OSD stops *System clock : X'tal *HOLD mode *All oscillation stops. Ratings typ. 12 unit mA
VDD[V] 4.5 - 5.5
min.
max. 25
Current dissipation in HALT mode (Note 5)
IDDHALT(1) VDD
4.5 - 5.5
4
10
mA
IDDHALT(2) VDD
4.5 - 5.5
300
1000
A
IDDHALT(3) VDD
4.5 - 5.5
35
200
Current dissipation in HOLD mode (Note 5)
IDDHOLD
VDD
4.5 - 5.5
0.05
20
A
(Note 5) The currents through the output transistors and the pull-up MOS transistors are ignored.
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Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: * Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. * Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70C) Operating Oscillation Notes Recommended circuit Frequency Manufacturer Oscillator supply stabilizing parameters voltage range time C1 C2 Rf Rd typ. max 32.768kHz Seiko C-002RX 18pF 18pF OPEN 390k 4.5 - 5.5V 1.0S 1.5S Epson Notes The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. * Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. * The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10C to +70C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. * When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. * The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. * The capacitors' VSS should be allocated close to the microcontroller's GND terminal and be away from other GND. * The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf Rd C1 X'tal C2
Figure 1
Recommended oscillation circuit.
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Power supply
VDD VDD limit 0V Reset time
RES
Internal RC resonator oscillation
XT1,XT2 tmsVCO VCO for system stable
Operation mode
Unfixed
Reset
Instruction execution mode

HOLD release
Valid
Internal RC resonator oscillation
XT1,XT2 tmsVCO VCO for system stable
Operation mode
HOLD
Instruction execution mode

Figure 2
Oscillation stabilizing time
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VDD
RRES
RES CRES
(Note)
Determine the CRES, RRES value to generate more than 200s reset time.
Figure 3
Reset circuit
0.5VDD

tCKCY tCKL SCK0 tICK SI0 tCKO SO0 SB0 50pF tCKI tCKH
VDD
1K
< Timing >
< Test load >
Figure 4
Serial input / output test condition
18/22
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
TPIL (1)-(5)
TPIH (1)-(4)
Figure 5
Pulse input timing condition - 1
tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6)
more than 1tCYC
Figure 6
Pulse input timing condition - 2
LC863364B 10k HS HS C536
Figure 7
Recommended Interface circuit
19/22
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
100 FILT + 2.2F -
1M
33000pF
Figure 8 (Note)
FILT recommended circuit
Place FILT parts on board as close to the microcontroller as possible.
P
S
Sr
P
SDA
tBUF tHD;STA tR tF tHD;STA tsp
SCL
tLOW tHD;DAT
tHIGH tSU;DAT tSU;STA tSU;STO
S : start condition P : stop condition Sr : restart condition
tsp : Spike suppression
Standard mode : not exist High speed mode : less than 50ns
Figure 9
IIC timing
20/22
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
memo:
PS 21/22
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LC863364B/56B/48B/40B/32B/28B/24B/20B/16B
This catalog provides information as of July 2002. Specifications and information herein are subject to change without notice
PS 22/22

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