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UL
(R)
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
RBIAS V DD (+V ) V SS (-V ) A 1 2 3 4
LS7183N LS7184N
(631) 271-0400 FAX (631) 271-0405
April 2009
PIN ASSIGNMENT - TOP VIEW
A3800
QUADRATURE CLOCK CONVERTER
FEATURES: * x1, x2 and x4 resolution * Programmable output pulse width (200ns to 140s) * Excellent regulation of output pulse width * TTL and low voltage CMOS compatible I/Os * +3V to +12V operation (VDD - VSS) * LS7183N, LS7184N (DIP); LS7183N-S, LS7184N-S (SOIC) - See Figure 1 Applications: * Interface incremental encoders to Up / Down Counters (See Figure 6A and Figure 6B) * Interface rotary encoders to Digital Potentiometers (See Figure 7) DESCRIPTION: The LS7183N and LS7184N are CMOS quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7183N / LS7184N, are converted to strings of Up Clocks and Down Clocks (LS7183N) or to a Clock and an Up/Down direction control (LS7184N). These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. INPUT/OUTPUT DESCRIPTION: RBIAS (Pin 1) Input for external component connection. A resistor connected between this input and VSS adjusts the output clock pulse width (Tow). VDD (Pin 2) Supply Voltage positive terminal. VSS (Pin 3) Supply Voltage negative terminal. A, B (Pin 4, Pin 5) Quadrature Clock inputs A and B. Directional output pulses are generated from the A and B clocks according to Fig. 2. A and B inputs have built-in immunity for noise signals less than 50ns duration (Validation delay, TVD). The A and B inputs are inhibited during the occurrence of a directional output clock (UPCK or DNCK), so that spurious clocks resulting from encoder dither are rejected. MODE (Pin 6) MODE is a 3-state input to select resolution x1, x2 or x4. The input quadrature clock rate is multiplied by factors of 1, 2 and 4 in x1, x2 and x4 mode, respectively, in producing the output UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic levels are as follows: Mode = 0 : x1 selected Mode = 1 : x2 selected Mode = Float : x4 selected
8 7
UPCK DNCK MODE B
LSI LS7183N
6 5
RBIAS V DD (+V ) V SS (-V ) A
1 2 3 4
8 7 6 5 FIGURE 1
CLK UP/DN MODE B
LS7183N - DNCK (Pin 7) In LS7183N, this is the DOWN Clock Output. This output consists of low-going pulses generated when A input lags the B input. LS7184N - UP/DN (Pin 7) In LS7184N, this is the count direction indication output. When A input leads the B input, the UP/DN output goes high indicating that the count direction is UP. When A input lags the B input, UP/DN output goes low, indicating that the count direction is DOWN. LS7183N - UPCK (Pin 8) In LS7183N, this is the UP Clock output. This output consists of low-going pulses generated when A input leads the B input. LS7184N - CLK (Pin 8) In LS7184N, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is indicated by the UP/DN output (Pin 7). NOTE: For the LS7184N, the timing of CLK and UP/DN requires that the counter interfacing with LS7184N counts on the rising edge of the CLK pulses.
LSI LS7184N
7183N/84N-042709-1
ABSOLUTE MAXIMUM RATINGS: PARAMETER DC Supply Voltage Voltage at any input Operating temperature Storage temperature SYMBOL VDD - VSS VIN TA TSTG VALUE 16.0 VSS - 0.3 to VDD + 0.3 -20 to +85 -55 to +150 UNITS V V C C
DC ELECTRICAL CHARACTERISTICS: (Unless otherwise specified VDD = 3V to 12V and TA = -20C to +85C) PARAMETER Supply Voltage Supply current MODE input: Logic 0 Logic 1 Logic float Logic 0 input current Logic 1 input current Vml Vmh Vmf Iml Iml Iml Imh Imh Imh VABl VABh IABlk RB VDD - 0.5 (VDD /2) - 0.5 0.7VDD 2k VDD /2 2.2 3.5 8.3 -2.0 -3.4 -8.2 0 0.5 (VDD /2) + 0.5 4.2 6.9 16.2 -9.8 -6.6 -16 0.25VDD 10 10M V V V A A uA A A A V V nA Ohm SYMBOL VDD IDD MIN 3.0 TYP 185 MAX 12 200 UNITS V A CONDITON VDD = 12V, All input frequencies = 0Hz and RBIAS = 2M VDD = 3V VDD = 5V VDD =12V VDD = 3V VDD = 5V VDD = 12V -
A, B inputs: Logic 0 Logic 1 Input current RBIAS input: External resistor All outputs: Sink current Source current
Iol Iol Iol Ioh Ioh Ioh
-
-3.4 -4.8 -7.2 1.7 2.2 3.1
-
mA mA mA mA mA mA
Vo = 0.5V, VDD = 3V Vo = 0.5V, VDD = 5V Vo = 0.5V, VDD = 12V Vo = 2.5V, VDD = 3V Vo = 4.5V, VDD = 5V Vo = 11.5V, VDD = 12V
TRANSIENT CHARACTERISTICS (TA = -20C to +85C) PARAMETER Output Clock Pulse Width A, B inputs: Validation Delay SYMBOL TOW TVD TVD TVD TPS TPW fA, B TDS TDS TDS MIN 190 TVD + TOW 2TPS TYPE 50 25 11 213 133 78 MAX 100 50 21 Infinite Infinite 1/(2TPW) 270 150 63 UNITS ns ns ns ns s s Hz ns ns ns CONDITON See Fig. 2 VDD = 3V VDD = 5V VDD = 12V VDD = 3V VDD = 5V VDD = 12V
Phase Delay Pulse Width Frequency Inupt to Output Delay
7183N/84N-040609-2
FORWARD A TPW TPS TPS TDS 4 1 TOW 2 2 4 1 4 2 2 4 2
REVERSE
B UPCLK (7183N) DNCLK (7183N) CLK (7184N) UP/DN (7184N)
4 4
1 1
4 4
2 2
NOTE: Output clocks labeled 1, 2 and 4 have the following interpretations. 1: Generated in x1, x2 and x4 modes 2: Generated in x2 and x4 modes only 4: Generated in x4 mode only FIGURE 2. LS7183N, LS7184N INPUT/OUTPUT TIMING
A
4
FILTER INHIBIT LOGIC
DIRECTION MUX AND BUFFER 8 UPCK or CLK
B
5
FILTER
7 1 CURRENT MIRROR PULSE
V DD 1M
DNCK or UP/DN
RBIAS
MODE
6
1M
MODE DECODE
V DD V SS
2 3
FIGURE 3. LS7183N, LS7184N BLOCK DIAGRAM
The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
7183N/84N-121508-3
25 V DD = 3V 20 15 10 5 0 V DD = 5V V DD = 9V V DD = 12V
300 250 200 150 100 50
0 200 400 600 800
V DD = 3V
TOW, us
V DD = 5V V DD = 9V V DD = 12V
0
0
5
10
Figure 4. TOW vs RBIAS (R in k )
+V 6 MODE A CLOCK 4 ENCODER B CLOCK 5 A B 2 V DD UPCK LS7183N DNCK 8 5 +V 16 VDD
Figure 5. TOW vs RBIAS (R in M )
SPDT (On - Off - On) +V +V 6 2 V DD CLK LS7184N UP/DN 8 15 CK UP/DN 4516 Vss 3 Vss 8 16 V DD
CK-UP 40193 CK-DN Vss 8
RB A CLOCK ENCODER B CLOCK 4 5 A B
MODE
7
4
7
10
1 RB
RBIAS
Vss 3
1
RBIAS
FIGURE 6A. TYPICAL APPLICATION FOR LS7183N in x4 MODE
FIGURE 6B*. TYPICAL APPLICATION FOR LS7184N WITH MODE SELECTION *See NOTE at bottom right of Page 1
+5V DIGITAL POTENTIOMETER CLK U/D A1 GND V DD CS B1
A1 10k 10k 100k 1 RBIAS 2 3 A GND 10k 10k V DD V SS CLK U/D MODE B LS7184N 0.01uF Part Number: RE11CT-V1Y12-EF2CS 0.01uF 8 7 6 5 1 2 3 4
8 7 6 B1 W1
ROTARY ENCODER
B
4A
W1 5
AD5220
FIGURE 7. Rotary Encoder Control of Digital Potentiometer
7183N/84N-042709-4

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