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K4B1G04(08/16)46C
1Gb DDR3 SDRAM
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1Gb C-die DDR3 SDRAM Specification
Revision 1.0
June 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Page 1 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
1Gb DDR3 SDRAM
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Revision History
Revision 0.0 0.1 1.0 Month January June June Year 2007 2007 2007 - Revision 0.0 release - Deleted 800Mbps 5-5-5 speed - Timing Parameters by Speed Grade (13.0) - Input/Output Capacitance (11.0) - Revision 1.0 specification release. History
Page 2 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
1Gb DDR3 SDRAM
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Table Contents
1.0 Ordering Information ....................................................................................................................................................4 2.0 Key Features .................................................................................................................................................................4 3.0 Package pinout/Mechanical Dimension & Addressing .............................................................................................5 3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) ..........................................5 3.2 x8 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) ..........................................6 3.3 x16 Package Pinout (Top view) : 112ball FBGA Package(96balls + 16 balls of support balls) ......................................7 3.4 FBGA Package Dimension (x4) ...................................................................................................................................8 3.5 FBGA Package Dimension (x8) ...................................................................................................................................9 3.6 FBGA Package Dimension (x16) ...............................................................................................................................10 4.0 Input/Output Functional Description ........................................................................................................................11 5.0 DDR3 SDRAM Addressing .........................................................................................................................................12 6.0 Absolute Maximum Ratings .......................................................................................................................................14 6.1 Absolute Maximum DC Ratings ................................................................................................................................14 6.2 DRAM Component Operating Temperature Range ....................................................................................................14 7.0 AC & DC Operating Conditions .................................................................................................................................14 7.1 Recommended DC operating Conditions (SSTL_1.5) .................................................................................................14 8.0 AC & DC Input Measurement Levels .........................................................................................................................15 8.1 AC and DC Logic input levels for single-ended signals .............................................................................................15 8.2 Differential swing requirement for differntial signals ................................................................................................16 8.2.1 Single-ended requirements for differential signals ............................................................................................17 8.3 AC and DC logic input levels for Differential Signals .................................................................................................18 8.4 Differential Input Cross Point Voltage .......................................................................................................................18 8.5 Slew rate definition for Single Ended Input Signals ...................................................................................................19 8.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) ...............................................................19 8.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) ..................................................................19 8.6 Slew rate definition for Differential Input Signals ......................................................................................................19 9.0 AC and DC Output Measurement Levels .................................................................................................................. 20 9.1 Single Ended AC and DC Output Levels ....................................................................................................................20 9.2 Differential AC and DC Output Levels .......................................................................................................................20 9.3.Single Ended Output Slew Rate ................................................................................................................................ 21 9.4 Differential Output Slew Rate ....................................................................................................................................21 9.5 Reference Load for AC Timing and Output Slew Rate ................................................................................................22 9.6 Overshoot/Undershoot Specification ........................................................................................................................23 9.6.1 Address and Control Overshoot and Undershoot specifications .......................................................................23 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications ..........................................................23 9.7 34 ohm Output Driver DC Electrical Characteristics ..................................................................................................24 9.7.1 Output Drive Temperature and Voltage sensitivity ............................................................................................25 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..........................................................................................25 9.8.1 ODT DC electrical characteristics .....................................................................................................................26 9.8.2 ODT Temperature and Voltage sensitivity ......................................................................................................... 27 9.9 ODT Timing Definitions ............................................................................................................................................ 28 9.9.1 Test Load for ODT Timings ............................................................................................................................... 28 9.9.2 ODT Timing Definition ......................................................................................................................................28 10.0 Idd Specification Parameters and Test Conditions ...............................................................................................31 10.1 IDD Measurement Conditions .................................................................................................................................31 10.2 IDD Specifications ..................................................................................................................................................41 11.0 Input/Output Capacitance ........................................................................................................................................43 12.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ................................................................44 12.1 Clock specification .................................................................................................................................................44 12.2 Clock Jitter Specification ........................................................................................................................................45 12.3 Refresh Parameters by Device Density ...................................................................................................................46 12.4 Standard Speed Bins ..............................................................................................................................................46 13.0 Timing Parameters by Speed Grade ....................................................................................................................... 48
Page 3 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 1.0 Ordering Information
[ Table 1 ] Samsung DDR3 ordering information table Organization 256Mx4 128Mx8 64Mx16 DDR3-800 (6-6-6) K4B1G0446C-ZCF7 K4B1G0846C-ZCF7 K4B1G1646C-ZCF7 DDR3-1066 (7-7-7/8-8-8) K4B1G0446C-CF8/G8 K4B1G0846C-CF8/G8 K4B1G1646C-CF8/G8
1Gb DDR3 SDRAM
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DDR3-1333 (8-8-8/9-9-9) K4B1G0446C-ZCG9/H9 K4B1G0846C-ZCG9/H9 K4B1G1646C-ZCG9/H9
Package 94 FBGA 94 FBGA 112 FBGA
Note : 1. Speed bin is in order of CL-tRCD-tRP. 2. x4/x8/x16 Package - including 16 support balls
2.0 Key Features
[ Table 2 ] 1Gb DDR3 C-die Speed bins Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) DDR3-800 6-6-6 2.5 6 15 15 37.5 52.5 7 13.125 13.125 37.5 50.625 7-7-7 1.875 8 15 15 37.5 52.5 8 12 12 36 48 DDR3-1066 8-8-8 8-8-8 1.5 9 13.5 13.5 36 49.5 DDR3-1333 9-9-9 Unit ns tCK ns ns ns ns
* JEDEC standard 1.5V 0.075V Power Supply * VDDQ = 1.5V 0.075V * 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin * 8 Banks * Posted CAS * Programmable CAS Latency: 5, 6, 7, 8, 9, 10, (11 for high density only) * Programmable Additive Latency: 0, CL-2 or CL-1 clock * Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) * 8-bit pre-fetch * Burst Length: 8 (Interleave without any limit, sequential with starting address "000" only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] * Bi-directional Differential Data-Strobe * Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) * On Die Termination using ODT pin * Average Refresh Period 7.8us at lower than TCASE 85xC, 3.9us at 85xC < TCASE < 95 xC * Asynchronous Reset * Package : 94 balls FBGA - x4/x8 (with 16 support balls) 112 balls FBGA - x16 (with 16 support balls) * All of Lead-free products are compliant for RoHS Note : 1. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. 2. 1066Mbps CL7 doesn't have back-ward compatibility with 800Mbps CL5 The 1Gb DDR3 SDRAM C-die is organized as a 32Mbit x 4/16Mbit x 8/ 8Mbit x 16 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR31333) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V 0.075V power supply and 1.5V 0.075V VDDQ. The 1Gb DDR3 device is available in 94ball FBGAs(x4/x8) and 112ball FBGA(x16)
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in "DDR3 SDRAM Device Operation & Timing Diagram".
Page 4 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 3.0 Package pinout/Mechanical Dimension & Addressing
1Gb DDR3 SDRAM
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3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls)
1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC NC NC NC VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 NC VDDQ VSS VDD CS BA0 A3 A5 A7 RESET NC DQ0 DQS DQS NC RAS CAS WE BA2 A0 A2 A9 A13 NC DM DQ1 VDD NC CK CK A10/AP A15 A12/BC A1 A11 NC VSS VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA BA1 A4 A6 A8 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC
Note1: A1,A2,A4,A8,A10,A11,D1,D11,T1,T11,W1,W2,W4,W8,W10 and W11 balls indicate mechanical support balls with no internal connection
1
2
3
4
5
6
7
8
9
10 11
Ball Locations (x4)
A B C
Populated ball Ball not populated
D E F G H
Top view (See the balls through the Package)
J K L M N P R T U V W
Page 5 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
1Gb DDR3 SDRAM
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3.2 x8 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls)
1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC NC NC NC VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC
Note1: A1,A2,A4,A8,A10,A11,D1,D11,T1,T11,W1,W2,W4,W8,W10 and W11 balls indicate mechanical support balls with no internal connection
1
2
3
4
5
6
7
8
9
10 11
Ball Locations (x8)
A B C
Populated ball Ball not populated
D E F G H
Top view (See the balls through the Package)
J K L M N P R T U V W
Page 6 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
1Gb DDR3 SDRAM
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3.3 x16 Package Pinout (Top view) : 112ball FBGA Package(96balls + 16 balls of support balls)
1 A B C D E F G H J K L M N P R T U V W Y AA AB NC NC NC NC NC NC NC NC VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP A15 A12/BC A1 A11 NC VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T U V W NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC
Note1: A1,A2,A4,A8,A10,A11,D1,D11,W1,W11,AB1,AB2,AB4,AB8,AB10 and AB11 balls indicate mechanical support balls with no internal connection 1 A 2 3 4 5 6 7 8 9 10 11
Ball Locations (x16)
B C D E
Populated ball Ball not populated
F G H J K
Top view (See the balls through the Package)
L M N P R T U V W Y AA AB
Page 7 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
3.4 FBGA Package Dimension (x4)
11.00 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK
1Gb DDR3 SDRAM
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11 10 9 8 7 6 5 4 3 2 1 (Datum A)
A B C D E F (Datum B) G H J K L M N P R T U V W
7.20 0.80 x 18 = 14.40
94 - 0.45 Solder ball 0.2 M A B
MOLDING AREA
BOTTOM VIEW
0.10MAX 18.00 0.10 1.10 0.10 0.50 0.05 0.35 0.05
#A1
11.00 0.10
TOP VIEW
0.80
0.80
18.00 0.10
Page 8 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
3.5 FBGA Package Dimension (x8)
11.00 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK
1Gb DDR3 SDRAM
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11 10 9 8 7 6 5 4 3 2 1 (Datum A)
A B C D E F (Datum B) G H J K L M N P R T U V W
7.20 0.80 x 18 = 14.40
94 - 0.45 Solder ball 0.2 M A B
MOLDING AREA
BOTTOM VIEW
0.10MAX 18.00 0.10 1.10 0.10 0.50 0.05 0.35 0.05
#A1
11.00 0.10
TOP VIEW
0.80
0.80
18.00 0.10
Page 9 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
3.6 FBGA Package Dimension (x16)
11.00 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK
1Gb DDR3 SDRAM
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11 10 9 8 7 6 5 4 3 2 1 A B C D E F G (Datum B) H J K L M N P R T U V W Y AA AB (Datum A)
8.40 0.80 x 21 = 16.80
MOLDING AREA 112 - 0.45 Solder ball 0.2 M A B
BOTTOM VIEW
0.10MAX 18.00 0.10 1.10 0.10 0.50 0.05 0.35 0.05
#A1
11.00 0.10
TOP VIEW
0.80
0.40
18.00 0.10
Page 10 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 4.0 Input/Output Functional Description
[ Table 3 ] Input/Output function description Symbol CK, CK Type Input Function
1Gb DDR3 SDRAM
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Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. No Connect: No internal electrical connection is present. DQ Power Supply: 1.5V +/- 0.075V DQ Ground Power Supply: 1.5V +/- 0.075V Ground Reference voltage for DQ Reference voltage for CA Reference Pin for ZQ calibration
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE DM (DMU), (DML)
Input Input
BA0 - BA2
Input
A0 - A12
Input
A10 / AP
Input
A12 / BC
Input
RESET DQ DQS, (DQS)
TDQS, (TDQS)
Input Input/Output Input/Output
Output
NC VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ Supply Supply Supply Supply Supply Supply Supply
Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
Page 11 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 5.0 DDR3 SDRAM Addressing 512Mb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size
*1
1Gb DDR3 SDRAM
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128Mb x4 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9,A11 A12/BC 1 KB
64Mb x 8 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9 A12/BC 1 KB
32Mb x16 8 BA0 - BA2 A10/AP A0 - A11 A0 - A9 A12/BC 2 KB
* Reference Information : The following tables are address mapping information for other densitites
1Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size
*1
256Mb x4 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9,A11 A12/BC 1 KB
128Mb x 8 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 1 KB
64Mb x16 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9 A12/BC 2 KB
2Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 512Mb x4 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9,A11 A12/BC 1 KB 256Mb x 8 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 1 KB 128Mb x16 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 2 KB
4Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 1Gb x4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 1 KB 512Mb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 1 KB 256Mb x16 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 2 KB
Page 12 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C
8Gb
Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 2Gb x4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11,A13 A12/BC 2 KB 1Gb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 2 KB
1Gb DDR3 SDRAM
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512Mb x16 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 2 KB
Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG 8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
Page 13 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 6.0 Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -55 to +100
1Gb DDR3 SDRAM
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Units V V V C
Notes 1,3 1,3 1
[ Table 4 ] Absolute Maximum DC Ratings Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6xVDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
Symbol TOPER Parameter Normal Operating Temperature Range Extended Temperature Range (Optional) rating 0 to 85 85 to 95 Unit C C Notes 1,2 1,3
[ Table 5 ] Temperature Range Note : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.
7.0 AC & DC Operating Conditions
7.1 Recommended DC operating Conditions (SSTL_1.5)
Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V Notes 1,2 1,2
[ Table 6 ] Recommended DC Operating Conditions Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Page 14 of 63
Rev. 1.0 June 2007
K4B1G04(08/16)46C 8.0 AC & DC Input Measurement Levels
8.1 AC and DC Logic input levels for single-ended signals
Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VREFDQ(DC) VREFCA(DC) Parameter dc input logic high dc input logic low ac input logic high ac input logic low I/O Reference Voltage(DQ) I/O Reference Voltage(CMD/ADD) DDR3-800/1066/1333 Min. VREF + 100 VSS VREF + 175 0.49*VDDQ 0.49*VDDQ
1Gb DDR3 SDRAM
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Max. VDD VREF - 100 VREF - 175 0.51*VDDQ 0.51*VDDQ
Unit mV mV mV mV V V
Notes 1 1 1,2 1,2 3,4 3,4
[ Table 7 ] Single Ended AC and DC input levels Note : 1. For DQ and DM, VREF = VREFDQ . For input only pins except RESET, or VREF = VREFCA 2. See 9.6 "Overshoot and Undershoot specifications" on page 23. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference : approx. 15mV) 4. For reference : approx. VDD/2 15mV
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in above table. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than 1% VDD.
voltage
VDD
VRef(DC) VRef ac-noise VRef(DC) VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef" shall be understood as VRef(DC), as defined in Figure 1. This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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8.2 Differential swing requirement for differntial signals
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Figure 2 : Definition of differntial ac-swing and "time above ac level tDVAC
tDVAC VIHdiff(ac) min VIHdiff min VIHdiff(dc) min 0.0 VIHdiff(ac) max VIHdiff max VIHdiff(dc) max differential voltage time half cycle time tDVAC CK - CK DQS - DQS
[ Table 8 ] Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
Symbol VIHdiff VILdiff VIHdiff(ac) VIHdiff(ac)
Parameter differential input high differential input low differential input high ac differential input low ac
DDR3-800 & 1066 & 1033 & 1600 min +0.2 note 3 2 x (VIH(ac)-Vref) note 3 max note 3 -0.2 note 3 2 x (Vref - VIL(ac))
unit V V V V
Note 1 1 2 2
Notes: 1. used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
[ Table 9 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0
tDVAC [ps] @ |VIH/Ldiff(ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max -
tDVAC [ps] @ |VIH/Ldiff(ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max -
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8.2.1 Single-ended requirements for differential signals
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Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(ac) / VIL(ac) ) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(ac) / VIL(ac) ) for DQ signals) in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g. if VIH150(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2 CK or DQS VSEL max
VSS or VSSQ
VSEL time
Figure 3: Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode charateristics of these signals.
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8.3 AC and DC logic input levels for Differential Signals
[ Table 10 ] Differential DC and AC input levels Symbol VIHdiff VILdiff Parameter Differential input logic high Differential input logic low DDR3-800/1066/1333 Min + 200 Max - 200
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Unit mV
Notes 1
Note : 1. Refer to "Overshoot and Undershoot specifications" on page 23.
8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS.
VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Figure 4. Vix Definition [ Table 11 ] Cross point voltage for differential input signals (CK, DQS) Symbol VIX Parameter Differential input Cross point voltage relative to VDD/2 DDR3-800/1066/1333/1600 Min -150 Max 150 Unit mV Notes
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8.5 Slew rate definition for Single Ended Input Signals
8.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
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Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL(AC)max.
8.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge Vref Vref Vil(DC)max Vih(DC)min Measured From To Vih(AC)min Vil(AC)max Vref Vref Defined by Vih(AC)min-Vref Delta TRS Vref-Vil(AC)max Delta TFS Vref-Vil(DC)max Delta TFH Vih(DC)min-Vref Delta TRH Applicable for
Setup (tIS,tDS)
Hold (tIH,tDH)
[ Table 12 ] Single Ended Input Slew Rate definition Notes: This nominal slew rate applies for linear signal waveforms.
VDDQ VIH(ac) min VSWING(MAX) VIH(dc) min VREF VIL(dc) max VIL(ac) max VSSQ delta TFS delta TRS delta TFH delta TRH VSWING(MAX) VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSSQ
< Figure : Input slew rate for setup>
< Figure : Input slew rate for Hold>
Figure 5. Input Nominal Slew Rate definition for Singel ended Signals
8.6 Slew rate definition for Differential Input Signals
Description Measured From To VIHdiffmin VILdiffmax Defined by VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff
Differential input slew rate for rising edge (CKVILdiffmax CK and DQS-DQS) Differential input slew rate for falling edge (CKVIHdiffmin CK and DQS-DQS) [ Table 13 ] Differential input slew rate definition
Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
VDDQ VIHdiffmin VSWING(MAX) VREF VILdiffmax VSSQ delta TFdiff delta TRdiff
Figure 6. Differential Input Slew Rate definition for DQS, DQS and CK, CK
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9.1 Single Ended AC and DC Output Levels
[ Table 14 ] Single Ended AC and DC output levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR)
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DDR3-800/1066/1333/1600 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ
Units V V V V V
Notes
1 1
Note : 1. The swing of +/-0.1xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 34ohms and an effective test load of 25ohms to VTT=VDDQ/2.
9.2 Differential AC and DC Output Levels
Symbol VOHdiff(AC) VOLdiff(DC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800/1066/1333/1600 +0.2 x VDDQ -0.2 x VDDQ Units V V Notes 1 1
[ Table 15 ] Differential AC and DC output levels Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 34ohms and an effective test load of 25ohms to VTT=VDDQ/2 at each of the differential outputs
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9.3.Single Ended Output Slew Rate
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With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and figure 7. [ Table 16 ] Single Ended Output slew rate definition Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Measured From VOL(AC) VOH(AC) DDR3-800 Min 2.5 Max 5 To VOH(AC) VOL(AC) DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 Defined by VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC) Delta TFse DDR3-1600 Min TBD Max 5 Units V/ns
Parameter Single ended output slew rate
Symbol SRQse
[ Table 17 ] Single Ended Output slew rate Note : Output slew rate is verified by design and characterization, and may not be subject to production test. For Ron=RZQ/7 setting
VDDQ VOH(AC) VREF VOL(AC) VSSQ delta TFS delta TRS
Figure 7. Single Ended Output Slew Rate definition
9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown inTable 18 and figure 8. [ Table 18 ] Differential Output slew rate definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge Measured From VOLdiff(AC) VOHdiff(AC) DDR3-800 Min 5 Max 10 To VOHdiff(AC) VOLdiff(AC) DDR3-1066 Min 5 Max 10 Defined by VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC) Delta TFdiff DDR3-1333 Min 5 Max 10 DDR3-1600 Min TBD Max 10 Units V/ns
Parameter Single ended output slew rate
Symbol SRQse
[ Table 19 ] Differential Output slew rate Note : Output slew rate is verified by design and characterization, and may not be subject to production test. For Ron=RZQ/7 setting
VDDQ VOHdiff(AC) VREF VOLdiff(AC) VSSQ delta TFdiff delta TRdiff
Figure 8. Differential Output Slew Rate definition
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9.5 Reference Load for AC Timing and Output Slew Rate
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Figure 9 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment of a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK/CK
DUT
DQ DQS DQS
VTT = VDDQ/2 25
Reference Point
Figure 9. Reference Load for AC Timing and Output Slew Rate
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9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications AC Overshoot/Undershoot Specification for Address and Control Pins
(A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 8) Maximum peak amplitude allowed for undershoot area (See Figure 8) Maximum overshoot area above VDD (See Figure 8) Maximum undershoot area below VSS (See Figure 8)
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Specification DDR3-800 0.4V 0.4V 0.67V-ns 0.67V-ns DDR3-1066 0.4V 0.4V 0.5V-ns 0.5V-ns DDR3-1333 0.4V 0.4V 0.4V-ns 0.4V-ns DDR3-1600 0.4V 0.4V 0.33V-ns 0.33V-ns
[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins
Maximum Amplitude
Overshoot Area
Volts (V)
VDD VSS
Maximum Amplitude Time (ns)
Undershoot Area
Figure 10. Address and Control Overshoot and Undershoot definition
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins
(DQ, DQS, DQS, DM, CK, CK) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 9) Maximum peak amplitude allowed for undershoot area (See Figure 9) Maximum overshoot area above VDDQ (See Figure 9) Maximum undershoot area below VSSQ (See Figure 9) Specification DDR3-800 0.4V 0.4V 0.25V-ns 0.25V-ns DDR3-1066 0.4V 0.4V 0.19V-ns 0.19V-ns DDR3-1333 0.4V 0.4V 0.15V-ns 0.15V-ns DDR3-1600 0.4V 0.4V 0.13V-ns 0.13V-ns
[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask
Maximum Amplitude
Overshoot Area
Volts (V)
VDDQ VSSQ
Maximum Amplitude Time (ns)
Undershoot Area
Figure 11. Clock, Data, Strobe and Mask Overshoot and Undershoot definition
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9.7 34 ohm Output Driver DC Electrical Characteristics
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A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON34 = RZQ/7 (Nominal 34ohms +/- 10% with nominal RZQ=240ohm) The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows VDDQ-Vout RONpu = l Iout l Vout RONpd = l Iout l under the condition that RONpu is turned off under the condition that RONpd is turned off
Output Driver : Definition of Voltages and Currents Output Driver VDDQ Ipu
To other circuity
RON
Pu
DQ RON Ipd Iout Vout VSSQ
Pd
Figure 12. Output Driver : Definition of Voltages and Currents
[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240 ohms ; entire operating temperature range; after proper ZQ calibration RONnom Resistor RON34pd 34Ohms RON34pu Mismatch between Pull-up and Pull-down, MMpupd Vout VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOMdc = 0.5 x VDDQ Min 0.6 0.9 0.9 0.9 0.9 0.6 -10 Nom 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 10 Units RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 % Notes 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,4
Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ 4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ: RONpu - RONpd MMpupd = RONnom x 100
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9.7.1 Output Drive Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ *dRONdT and dRONdV are not subject to production test but are verified by design and characterization [ Table 23 ] Output Driver Sensitivity Definition Min RONPU@VOHDC RON@VOMDC RONPD@VOLDC 0.6 - dRONdTH * |T| - dRONdVH * |V| 0.9 - dRONdTM * |T| - dRONdVM * |V| 0.6 - dRONdTL * |T| - dRONdVL * |V| Max
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Units RZQ/7 RZQ/7 RZQ/7
1.1 + dRONdTH * |T| + dRONdVH * |V| 1.1 + dRONdTM * |T| + dRONdVM * |V| 1.1 + dRONdTL * |T| + dRONdVL * |V|
[ Table 24 ] Output Driver Voltage and Temperature Sensitivity Min dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH 0 0 0 0 0 0 Max 1.5 0.15 1.5 TBD 1.5 TBD Units
%/C
%/mV
%/C
%/mV
%/C
%/mV
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DQ, DQS/DQS and TDQS,TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as follows :
VDDQ-Vout RTTpu = l Iout l Vout RTTpd = l Iout l under the condition that RTTpu is turned off
under the condition that RTTpd is turned off
On-Die Termination : Definition of Voltages and Currents Output Driver VDDQ Ipu
To other circuitry like RCV, ...
Iout=Ipd-Ipu
Pu
RTT
DQ RTT Ipd Iout
Pd
Vout VSSQ
Figure 13. On-Die Termination : Definitionof Voltages and Currents
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9.8.1 ODT DC electrical characteristics
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Table # provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines:. MR1 (A9,A6,A2) RTT RESISTOR Vout 0.2XVDDQ RTT120pd240 0.5XVDDQ 0.8XVDDQ (0,1,0) 120 ohm RTT120pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT120 MIN 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 -5 NOM 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 MAX 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 UNIT RZQ RZQ RZQ RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % NOTES 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,5,6
VIL(AC) TO VIH(AC)
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ
RTT60pd240
(0,0,1)
60 ohm RTT60pu240
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60
VIL(AC) TO VIH(AC)
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ
RTT40pd240
(0,1,1)
40 ohm RTT40pu240
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT40
VIL(AC) TO VIH(AC)
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ
RTT60pd240
(1,0,1)
30 ohm RTT60pu240
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60
VIL(AC) TO VIH(AC)
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ
RTT60pd240
(1,0,0)
20 ohm RTT60pu240
0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60
VIL(AC) TO VIH(AC)
Deviation of VM w.r.t VDDQ/2, VM
[ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operating temperature range; after proper ZQ calibration
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Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ. 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) perspectively
VIH(ac) - VIL(ac) RTT = I(VIH(ac)) - I(VIL(ac))
6. Measurement definition for VM and VM : Measure voltage (VM) at test pin (midpoint) with no load
VM =
2 x VM VDDQ
-1
x 100
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition Min RTT 0.9 - dRTTdT * |T| - dRTTdV * |V| Max 1.6 + dRTTdT * |T| + dRTTdV * |V| Units RZQ/2,4,6,8,12
[ Table 27 ] ODT Voltage and Temperature Sensitivity Min dRTTdT dRTTdV 0 0 Max 1.5 0.15 Units
%/C
%/mV
These parameters may not be subject to production test. They are verified by design and characterization.
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9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 14.
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VDDQ
CK,CK
DUTDQ, DM
DQS , DQS TDQS , TDQS
VTT= VSSQ RTT =25 ohm
VSSQ
Timing Reference Points
BD_REFLOAD_ODT
Figure 14. ODT Timing Reference Load
9.9.2 ODT Timing Definition Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table28 and subsequent figures. Measurement reference settings are provided in Table29.
[ Table 28 ] ODT Timing Definitions Symbol Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 of ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figute Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
tAON tAONPD tAOF tAOFPD tADC
[ Table 29 ] Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RTT_Wr Setting NA NA NA NA NA NA NA NA RZQ/2 VSW1[V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20 VSW2[V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 Note
tAON tAONPD tAOF tAOFPD tADC
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Begin point : Rising edge of CK - CK defined by the end point of ODTLon
CK VTT CK
tAON
TSW2
DQ, DM DQS , DQS TDQS , TDQS
TSW1 VSW2 VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ
Figure 15. Definition of tAON
Begin point : Rising edge of CK - CK with ODT being first registered high
CK VTT CK
tAONPD
TSW2
DQ, DM DQS , DQS TDQS , TDQS
TSW1 VSW2 VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ
Figure 16. Definition of tAONPD
Begin point : Rising edge of CK - CK defined by the end point of ODTLoff
CK VTT CK
tAOF
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom
TSW2
VSW2 VSW1
TSW1
VSSQ
TD_TAON_DEF
Figure 17. Definition of tAOF
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Begin point : Rising edge of CK - CK with ODT being first registered low
CK VTT CK
tAOFPD
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom
TSW2
VSW2 VSW1
TSW1
VSSQ
Figure 18. Definition of tAOFPD
Begin point : Rising edge of CK - CK defined by the end point of ODTLcnw
Begin point : Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8
CK VTT CK
tADC tADC
VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS
End point Extrapolated point at VRTT_Nom
TSW21 TSW11 VSW1 VSW2
VRTT_Nom
TSW22 TSW12
End point Extrapolated point at VRTT_Nom
VRTT_Wr
End point Extrapolated point at VRTT_Wr
VSSQ
Figure 19. Definition of tADC
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K4B1G04(08/16)46C 10.0 Idd Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
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Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: [ Table 30 ] Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Table number Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Measurement Conditions IDD0 and IDD1 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) IDD3N and IDD3P IDD4R, IDD4W, IDD7 IDD7 for different speed grades and different tRRD, tFAW conditions IDD5B IDD6, IDD6ET
Within the tables about IDD measurement conditions, the following definitions are used: * LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.); * STABLE is defined as inputs are stable at a HIGH or LOW level * FLOATING is defined as inputs are VREF = VDDQ / 2 * SWITCHING is defined as described in the following 2 tables. [ Table 31 ] Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: Address (Row, Column): If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax ..... please see each IDDx definition for details If not otherwise mentioned the bank addresses should be switched like the row/ column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE } := {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE } := {HIGH, HIGH,HIGH,HIGH} Command (CS, RAS, CAS, WE): Define Command Background Pattern = D D D D D D D D D D D D ... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R) the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples.
Bank address:
[ Table 32 ] Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data (DQ) Data Masking (DM) Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. NO Switching; DM must be driven LOW all the time
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Timing parameters are listed in the following table: [ Table 33 ] For IDD testing the following parameters are utilized. Parameter tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) tRFC(IDD) - 1Gb x4/x8 x16 x4/x8 x16 Bin DDR3-800 6-6-6 2.5 6 15 52.5 37.5 15 40 50 10 10 110 7 13.13 50.63 37.5 13.13 37.5 50 7.5 10 110 7-7-7 1.875 8 15 52.50 37.5 15 37.5 50 7.5 10 110 8 12 48 36 12 30 45 6.0 7.5 110 DDR3-1066 8-8-8 8-8-8 1.5 9 13.5 49.5 36 13.5 30 45 6.0 7.5 110 ns ns ns ns ns ns ns ns 110 DDR3-1333 9-9-9 Unit ns
The following conditions apply: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric test conditions. 3. IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12).
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[ Table 34 ] IDD Measurement Conditions for IDD0 and IDD1 Current Operating Current 0 -> One Bank Activate -> Precharge IDD0
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IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Figure 1 HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) n.a. n.a. n.a. n.a. HIGH between. Activate and Precharge Commands SWITCHING as described in Table 2; only exceptions are Activate and Precharge commands; example of IDD0 pattern: HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) n.a. CL(IDD) 0 HIGH between Activate, Read and Precharge SWITCHING as described in Table 2; only exceptions are Activate, Read and Precharge commands; example of IDD1 pattern: A0 D D D D R0 D D D DD D D DD D P0 (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (R)ead to bank 0 ; Definition of D and D: see Table 2) Definition of D and D: See table ##.
Name
Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS
Command Inputs (CS, RAS, CAS, WE)
A0 D D D D D D D D D D D P0 (DDR3-800: tRAS = 37.5ns between (A)ctivate and (P)recharge to bank 0 ; Definition of D and D: see Table 2) Definition of D and D: See table ##.
Row, Column Addresses Bank Addresses
Row addresses SWITCHING as described in Table 2; Row addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! Address Input A10 must be LOW all the time! bank address is fixed (bank 0) bank address is fixed (bank 0) Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". When there is no read data burst from DRAM the DQ I/O should be FLOATING. off / 1 disabled 8 fixed / MR0 Bits [A1, A0] = {0,0} one ACT-RD-PRE loop all other n.a.
Data I/O
SWITCHING as described in Table 3
Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WR Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit 12
off / 1 disabled n.a. one ACT-PRE loop all other n.a.
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T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
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T14 T15 T16 T17 T18
BA[2:0]
000
ADDR_a[9:0]
000
3FF
000
3FF
000
ADDR_b[10]
ADDR_c[13:11]
000
111
000
111
000
CS
RAS
CAS
WE
CMD
ACT
D
D
D
D
RD
D
D
D
D
D
D
D
D
D
PRE
D
D
D
DQ
0
0
1
1
0
0
1
1
DM IDD1 Measurement Loop
Figure 20. IDD1 Example (DDR3-800-666, 1Gb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 ="1") to achieve Iout = 0mA. Address inputs are split into 3 parts.
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[ Table 35 ] IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Current IDD2N Precharge Standby Current IDD2P(1) a Precharge Power Down Current Fast Exit MRS A12 Bit = 1
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IDD2P(0) Precharge Power Down Current Slow Exit MRS A12 Bit = 0 IDD2Q Precharge Quiet Standby Current
Name
Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Bank Address, Row Addr. and Command Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a Figure 2 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING off / 1 disabled n.a. none all LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. none all Fast Exit / 1 (any valid command after tXP1) LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH STABLE FLOATING off / 1 disabled n.a. none all Slow Exit / 0 Slow exit (RD and ODT commands must satisfy tXPDLL-AL) LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. none all
n.a.
n.a.
Note : 1. In DDR3 the MRS Bit 12 defines DLL on/off behavior ONLY for precharge power down. There are 2 different Precharge Power Down states possible : one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). 2. Because it is an exit after precharge power down the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh.
T0 CK BA[2:0] ADDR[13:0] CS RAS CAS WE CMD DQ[7:0] DM D 0 0000
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
7 3FFF
0 0000
D
D
D
D
D
D
D
D
D
D
FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00
IDD2N /IDD3N Measurement Loop
Figure 21. IDD2N /IDD3N Example (DDR3-800-666, 1Gb X8)
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[ Table36 ] IDD Measurement Conditions for IDD3N and IDD3P(fast exit) Current Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a Figure 2 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING as described in Table 3 off / 1 disabled n.a. all none n.a. IDD3N Active Standby Current
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IDD3P Active Power-Down Currenta Always Fast Exit
LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. all none n.a. (Active Power Down Mode is always "Fast Exit" with DLL on
Note : 1. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit A12 will be used to switch between two different precharge power down modes.
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[ Table 37 ] IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Figure 3 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0
HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: R0DDDR1DDDR3DDDR3DDDR4 ..... Rx = Read from bank x; Definition of D and D: see Table 2 column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! bank address cycling (0 ->1 -> 2 -> 3 ...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". off / 1
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IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD7 All Bank Interleave Read Current
HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0
HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: W0DDDW1DDDW2DDDW3DDD W4 ... Wx = Write to bank x; Definition of D and D: see Table 2 column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! bank address cycling (0 ->1 -> 2 -> 3 ...) Seamless Write Data Burst (BL8): input data switches every clock, which means that Write data is stable during one clock cycle. DM is low all the time.
HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) tRRDmin(IDD) CL(IDD) tRCDmin-1tCK
HIGH btw. valid cmds
Command Inputs (CS, RAS, CAS, WE)
For patterns see Table 9
Row, Column Addresses
STABLE during DESELECTs bank address cycling (0 ->1 -> 2 -> 3 ...), see pattern in Table 9 Read Data (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". off / 1
Bank Addresses
DQ I/O
Output Buffer DQ,DQS / MR1 bit A12
off / 1
Rtt_NOM, Rtt_WE Burst length Active banks Idle banks
Precharge Power Down Mode / Mode Register Bit
disabled
8 fixed / MR0 Bits [A1, A0] = {0,0}
disabled
8 fixed / MR0 Bits [A1, A0] = {0,0}
disabled
8 fixed / MR0 Bits [A1, A0] = {0,0}
all none
n.a.
all none
n.a.
all none
n.a.
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T0 CK BA[2:0] ADDR_a[9:0] 000 000 001 3FF 010 000 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
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T11 T12 T13
001 3FF
ADDR_b[10] ADDR_c[13:11]
000
111
000
111
CS RAS CAS WE CMD[2:0] DQ[7:0] DM Start of Measurement Loop RD D D RD D D D RD D D D D RD D
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00
Figure 22 IDD4R Example (DDR3-800-666,1Gb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12="1") to achieve Iout = 0mA. Address inputs are split into 3 parts.
[ Table 38 ] IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Speed Mb/s all 800 all all 1066 all all 1333 all all 1600 all x16
40 32 7.5 6
Bin
Org. x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8
tFAW [ns] 40 50 37.5
50 30 45 30
tFAW [CLK] 16 20 20
27 20 30 24
tRRD [ns] 10 10 7.5
10 6 7.5 6
tRRD [CLK] 4 4 4
6 4 5 5
IDD7 Patterna A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D A4 RA4 D D D D A5RA5 D D D D A6 RA6 D D D D A7 RA7 D D D DD D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D D D D D D D A4 RA4 D D DA5 RA5 D D D A6 RA6 D D D A7 RA7 D D D DD D D D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D A4 RA4 D D D A5 RA5 D DD A6 RA6 D D D A7 RA7 D D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D D D D D D A4 RA4D D D D A5 RA5 D D D D A6 RA6 D D D D A7RA7 D D D D D D D D DDDD
Note : 1. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect
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[ Table 39 ] IDD Measurement Conditions for IDD5B Current Name Measurement Condition CKE External Clock tCK tRC tRAS tRCD tRRD tRFC CL AL CS Addr. and cmd Inputs
Data inputs Output Buffer DQ,DQS / MR1 bit A12
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IDD5B Burst Refresh Current HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. tRFCmin(IDD) n.a. n.a.
HIGH btw. valid cmds SWITCHING SWITCHING off / 1
Rtt_NOM, Rtt_WE Burst length Active banks Idle banks
Precharge Power Down Mode / Mode Register Bit
disabled n.a. Refresh command every tRFC=tRFCmin none
n.a.
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[ Table 40 ] IDD Measurement Conditions for IDD6 and IDD6ET Current Name Measurement Condition Temperature Auto Self Refresh(ASR) / MR2 Bit A6 Self Refresh Temperature Range (SRT) / MR2 Bit A7 CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS, RAS, CAS, WE)
Row, Column Addresses Bank Addresses Data I/O Output Buffer DQ,DQS / MR1 bit A12
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IDD6 Self-Refresh Current Normal Temperature Range TCASE = 0 .. 85C TCASE = 85C Disabled / "0" Normal / "0" LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING
off / 1
IDD6ET Self-Refresh Current Extended Temperature Range a TCASE = 0 .. 95C TCASE = 95C Disabled / "0" Enabled / "1" LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING
off / 1
Rtt_NOM, Rtt_WR Burst length Active banks Idle banks
Precharge Power Down Mode / Mode Register Bit 12
disabled n.a. all during self-refresh actions all btw. Self-Refresh actions
n.a.
disabled n.a. all during self-refresh actions all btw. Self-Refresh actions
n.a.
Note : 1 .Users should refer to the DRAM supplier datasheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options referred to in this material
[ Table 41 ] IDD6 current definition Symbol IDD6 IDD6ET Parameter/Condition Normal Temperature Range Self-Refresh Current : CKE< 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable for MR2 setting A6=0 and A7=0. Extended Temperature Range SElf-Refresh Current: CKE<0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable for MR2 settings A6=0 and A7=1.
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10.2 IDD Specifications
(IDD values are for full operating range of Voltage and Temperature)
Symbol Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
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Units
Notes
IDD0
mA
IDD1
Operating one bank active-read-precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Extended Temperature Range Self-Refresh Current; CK and CK at 0V; CKE 0.2V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled, Applicable for MR2 setting A6=0 and A7=1 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA
IDD3P
mA
IDD3N
mA
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD6ET
mA
IDD7
= tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
mA
[ Table 42 ] IDD Specification
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1Gb DDR3 SDRAM E-die IDD Spec Table
256Mx4 (K4B1G0446C) Symbol IDD0 IDD1 IDD2P-F IDD2P-S IDD2N IDD2Q IDD3P-F IDD3N IDD4R IDD4W IDD5 IDD6 IDD6ET IDD7 800Mbps 6-6-6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 7-7-7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1066Mbps 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
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1333Mbps 9-9-9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
128Mx8 (K4B1G0846C) Symbol IDD0 IDD1 IDD2P-F IDD2P-S IDD2N IDD2Q IDD3P-F IDD3N IDD4R IDD4W IDD5 IDD6 IDD6ET IDD7 800Mbps 6-6-6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 7-7-7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1066Mbps 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1333Mbps 9-9-9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit Notes
64Mx16 (K4B1G1646C) Symbol IDD0 IDD1 IDD2P-F IDD2P-S IDD2N IDD2Q IDD3P-F IDD3N IDD4R IDD4W IDD5 IDD6 IDD6ET IDD7 800Mbps 6-6-6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 7-7-7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1066Mbps 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 8-8-8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1333Mbps 9-9-9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit Notes
[ Table 43 ] IDD Specification for 1Gb DDR3 C-die
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K4B1G04(08/16)46C 11.0 Input/Output Capacitance
Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta (All control input-only pins) Input capacitance delta (all ADD and CMD input-onlypins) Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS) Input/output capacitance of ZQ pin [ Table 44 ] Input / Output Capacitance Symbol CIO CCK CDCK CI CDDQS CDI_CTRL CDI_ADD_CMD CDIO CZQ DDR3-800 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1066 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1333 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 -
1Gb DDR3 SDRAM
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DDR3-1600 Min TBD 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max TBD 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3
Max 2.5 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3
Units pF pF pF pF pF pF pF pF pF
Notes 1,2,3 2,3,5 2,3,4 2,3,6 2,3,12 2,3,7,8 2,3,9,10 2,3,11 2, 3, 13
Note : 1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK# 5. Absolute value of CIO(DQS)-CIO(DQS#) 6. CI applies to ODT, CS#, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CDI_CTRL applies to ODT, CS# and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK#)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS#, CAS# and WE# 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#))
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1Gb DDR3 SDRAM
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12.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
12.1 Clock specification
Parameter Average clock period Clock period Symbol tCK(avg) DDR3-800 min 2500 max 3333 DDR3-1066 min 1875 max 3333 DDR3-1333 min 1500 max 3333 DDR3-1600 min 1250 max 3333 Units ps
tCK(abs)
tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max tCK(avg)min tCK(avg)max + + + + + + + + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max
ps
[ Table 45 ] Clock specification Add note fot tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge.
N
tCKj
j=1
N
N=200
Add note fot tCK(abs) tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge.
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12.2 Clock Jitter Specification
Parameter Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across n cycles Average high pulse width Average low pulse width Duty cycle jitter [ Table 46 ] Clock Jitter specification Symbol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(nper) tCH(avg) tCL(avg) tJIT(duty) TBD 0.47 0.47 -100 DDR3-800 min -100 -90 200 180 TBD 0.53 0.53 100 TBD 0.47 0.47 -75 max 100 90 DDR3-1066 min -90 -80 180 160 TBD 0.53 0.53 75 TBD 0.47 0.47 -60 max 90 80 DDR3-1333 min -80 -70 160 140
1Gb DDR3 SDRAM
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DDR3-1600 min -70 -60 140 120 TBD 0.53 0.53 60 TBD 0.47 0.47 -50 TBD 0.53 0.53 50 max 70 60
max 80 70
Units ps ps ps ps ps tCK(avg) tCK(avg) ps
Note : The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device.
Add note for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
j=1
N
tCHj
N x tCK(avg)
N=200
j=1
N
tCLj
N x tCK(avg)
N=200
Add note for tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH form tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg) tJIT(duty) = min/max of {tJIT(CH), tJIT(CL)}, where: tJIT(CH) = {tCHi-tCH(avg) where i=1 to 200}, tJIT(CL) = {tCLi-tCL(avg) where i=1 to 200},
Add note for tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing Add note for tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi} tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing Add note for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). This definition is TBD.
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12.3 Refresh Parameters by Device Density
1Gb DDR3 SDRAM
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Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval tREFI
Symbol tRFC 0 C TCASE 85C 85 C < TCASE 95C
512Mb 90 7.8 3.9
1Gb 110 7.8 3.9
2Gb 160 7.8 3.9
4Gb 300 7.8 3.9
8Gb 350 7.8 3.9
Units ns s s
[ Table 47 ] Refresh parameters by device density
12.4 Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 48 ] DDR3-800 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 / CWL = 5 CL = 6 / CWL = 5 Supported CL Settings Supported CWL Settings Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) 2.5 6 5 min 15 15 15 52.5 37.5 Reserved 3.3 DDR3-800 6-6-6 max 20 9*tREFI ns ns ns ns ns ns ns nCK nCK 8 1,2,3,4 1,2,3 Units Note
[ Table 49 ] DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CL = 7 CL = 8 Supported CL Settings Supported CWL Settings CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 2.5 Reserved Reserved 1.875 1.875 6,7,8 5,6 <2.5 <2.5 Reserved min 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 3.3 2.5 Reserved Reserved Reserved Reserved 1.875 6,8 5,6 <2.5 DDR3-1066 7-7-7 max 20 9*tREFI min 15 15 15 52.5 37.5 Reserved Reserved 3.3 DDR3-1066 8-8-8 max 20 9*tREFI ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 8 1,2,3,4,6 4 1,2,3,6 1,2,3,4 4 1,2,3,4 4 1,2,3 Units Note
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[ Table 50 ] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6,7 CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5,6 CWL = 7 CWL = 5,6 CL = 10 Supported CL Settings Supported CWL Settings CWL = 7 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.5 1.5 1.5 2.5 Reserved Reserved Reserved 1.875 <2.5 Reserved Reserved 1.875 <2.5 <1.875 Reserved <1.875 Reserved <1.875 5,6,7,8,9 5,6,7 1.5 6,8,9 5,6,7 (Optional) 1.5 min 12 12 12 48 36 2.5 Reserved 3.3 2.5 Reserved Reserved Reserved Reserved Reserved Reserved 1.875 DDR3-1333 8-8-8 max 20 9*tREFI 3.3 min 13.5 13.5 13.5 49.5 36 Reserved Reserved
1Gb DDR3 SDRAM
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DDR3-1333 9 -9 - 9 max 20 9*tREFI ns ns ns ns ns ns ns 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 8 1,2,3,4,7 4 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 1,2,3,4, 4 1,2,3,7 1,2,3,4, 4 1,2,3,4 4 1,2,3 5 Units Note
<2.5
Reserved Reserved <1.875 Reserved <1.875 (Optional)
NOTES: Absolute Specification (TOPER;VDDQ=VDD=1.5V +/- 0.075V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfiled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next 'Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the next valid speed bin limit (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. 'Reserved' settings are not allowed. User must program a different value. 5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. tREFI depends on TOPER
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K4B1G04(08/16)46C 13.0 Timing Parameters by Speed Grade
[ Table 51 ] Timing Parameters by Speed Bin
Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 ... 49, 50 cycles Absolute clock HIGH pulse width Absolute clock Low pulse width Data Timing DQS,DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac) levels Data Strobe Timing DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS rising edge output access time from rising CK, CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/ 2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS,DQS faling edge setup time to CK, CK rising edge DQS,DQS faling edge hold time to CK, CK rising edge tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH 0.9 0.3 0.38 0.38 0.9 0.3 -400 -800 0.4 0.4 -0.25 0.2 0.2 NOTE1 400 400 400 0.6 0.6 0.25 0.9 0.3 0.38 0.38 0.9 0.3 -300 -600 0.4 0.4 -0.25 0.2 0.2 NOTE1 300 300 300 0.6 0.6 0.25 tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) 0.38 -800 75 150 200 400 400 0.38 -600 25 100 150 300 300 tCK(DLL_OFF) tCK(avg) tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) 0.43 0.43 - 147 - 175 - 194 - 209 - 222 - 232 - 241 - 249 - 257 - 263 - 269 8 8 Symbol MIN DDR3-800 MAX MIN DDR3-1066 MAX
1Gb DDR3 SDRAM
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DDR3-1333 MIN MAX
Units
Note
8
-
ns ps ps tCK(avg) tCK(avg) ps ps ps ps
6 f
See Speed Bins Table tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max 0.47 0.47 -100 -90 200 180 147 175 194 209 222 232 241 249 257 263 269 - 132 - 157 - 175 - 188 - 200 - 209 - 217 - 224 - 231 - 237 - 242 0.53 0.53 100 90 0.47 0.47 -90 -80 180 160 132 157 175 188 200 209 217 224 231 237 242 - 118 - 140 - 155 - 168 - 177 - 186 - 193 - 200 - 205 - 210 - 215 0.53 0.53 90 80 0.47 0.47 -80 -70 160 140 118 140 155 168 177 186 193 200 205 210 215 0.53 0.53 80 70
f f
ps ps ps ps ps ps ps ps ps ps PS
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max 0.43 0.43 0.43 0.43 tCK(avg) tCK(avg) 25 26
0.38 -500 -10 65
125 250 250
ps tCK(avg) ps ps ps ps
12,13 12,13 13,14, a 13,14, a d, 17 d, 17
-
-
-
0.9 0.3 0.4 0.4 0.9 0.3 -255 -500 0.4 0.4 -0.25 0.2 0.2
NOTE1 255 250 250 0.6 0.6 0.25 -
tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK tCK tCK(avg) tCK(avg) tCK(avg)
13, 19, b 11, 13, b 13, b 13, b 1 1 12,13 12,13,14 12,13,14
c c c
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[ Table 51 ] Timing Parameters by Speed Bin (Cont.)
Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Refresh Timing 512Mb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 1Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 2Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 4Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval 8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0C TCASE 85 C) Average periodic refresh interval (85C TCASE 95 C) Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) Valid Clock Requirement before Self Refresh Exit (SRX) tXS tXSDLL tCKESR tCKSRE tCKSRX max(5tCK,tRFC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5tCK,10ns) max(5tCK,10ns) max(5tCK,tRFC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5tCK,10ns) max(5tCK,10ns) tXPR max(5tCK, tRFC + 10ns) max(5tCK, tRFC + 10ns) tZQinitI tZQoper tZQCS 512 256 64 512 256 64 tRFC tRFC tRFC tRFC tRFC tREFI tREFI 90 110 160 300 350 7.8 3.9 90 110 160 300 350 7.8 3.9 tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW tIS(base) tIH(base) 1 37.5 max (4tCK,10ns) max (4tCK,10ns) 40 50 200 275 70,000 512 max (4tCK,7.5ns) max (4tCK,7.5ns) 15 4 max (12tCK,15ns) 4 512 max (4tCK,7.5ns) max (4tCK,7.5ns) 15 4 max (12tCK,15ns) 4 Symbol MIN DDR3-800 MAX MIN DDR3-1066 MAX
1Gb DDR3 SDRAM
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DDR3-1333 MIN MAX
Units
Note
512 max (4tCK,7.5ns) max (4tCK,7.5ns) 15 4 max (12tCK,15ns) 4
-
nCK e e,18 ns tCK(avg) e
nCK nCK
WR + roundup (tRP / tCK(AVG)) 1 37.5 max (4tCK,7.5ns) max (4tCK,10ns) 37.5 50 125 200 70,000 1 36 max (4tCK,6ns) max (4tCK,7.5ns) 30 45 65 140 70,000 -
nCK ns e e e ns ns ps ps e e b,16 b,16
-
-
90 110 160 300 350 7.8 3.9
-
ns ns ns ns ns us us
512 256 64
-
tCK tCK tCK 23
max(5tCK, tRFC + 10ns)
-
max(5tCK,tRFC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5tCK,10ns) max(5tCK,10ns)
tCK
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1Gb DDR3 SDRAM
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[ Table 51 ] Timing Parameters by Speed Bin (Cont.)
Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid command;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timing ODT high time without write command or with wirte command and BC4 ODT high time with Write command and BL8 Asynchronous RTT tum-on delay (Power-Down with DLL frozen) Asynchronous RTT tum-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed DQS/DQS delay after tDQS margining mode is programmed Setup time for tDQSS latch Hold time of tDQSS latch Write leveling output delay Write leveling output error tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE 40 25 325 325 0 0 9 2 40 25 245 245 0 0 9 2 40 25 195 195 0 0 9 2 tCK tCK ps ps ns ns 3 3 ODTH4 ODTH8 tAONPD tAOFPD tAON tAOF tADC 4 6 1 1 -400 0.3 0.3 9 9 400 0.7 0.7 4 6 1 1 -300 0.3 0.3 9 9 30 0.7 0.7 4 6 1 1 -250 0.3 0.3 9 9 250 0.7 0.7 nCK nCK ns ns ps tCK(avg) tCK(avg) 7,12 8,12 12 tXP tXPDLL tCKE tCPDED tPD tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN tREFPDEN tMRSPDEN max (3tCK,7.5ns) max (10tCK,24ns) max (3tCK,7.5ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK) WL + 4 +WR +1 WL + 2 +(tWR/ tCK) WL +2 +WR +1 1 tMOD(min) max (3tCK,7.5ns) max (10tCK,24ns) max (3tCK,5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK) WL + 4 +WR +1 WL + 2 +(tWR/ tCK) WL +2 +WR +1 1 tMOD(min) max (3tCK,6ns) max (10tCK,24ns) max (3tCK,5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK) WL + 4 +WR +1 WL + 2 +(tWR/ tCK) WL +2 +WR +1 1 tMOD(min) Symbol MIN DDR3-800 MAX MIN DDR3-1066 MAX MIN DDR3-1333 MAX Units Note
9*tREFI -
9*tREFI -
9*tREFI tCK nCK nCK nCK nCK nCK tCK nCK nCK
2
15 20 20
9 10 9 10 20,21
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Jitter Notes
Specific Note a
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12
Specific Note b
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!) These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c
Specific Note d
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
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Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT turn-on time tAON see "Device Operation" 8. For definition of RTT turn-off time tAOF see "Device Operation". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles as programmed in MR0 11. The maximum postamble is bound by tHZDQS(max)
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12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD 13. Value is only valid for RON34 14. Single ended signal parameter. Refer to chapter for definition and measurement method. 15. tREFI depends on TOPER 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VrefDQ(DC). FOr input only pins except RESET, VRef(DC)=VRefCA(DC). See "Address/ Command Setup, Hold and Derating" on page 53. 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)= VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC). See "Data Setup, Hold and Slew Rate Derating" on page 59. 18. Start of internal write transaction is definited as follows ; For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL 19. The maximum preamble is bound by tLZDQS(max) 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. See "Device Operation". 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maxi-mum sensitivities specified in the 'Output Driver Voltage and Temperature Sensitivity' and 'ODT Voltage and Temperature Sensitivity' tables. The appropriate interval between ZQCS commands can be determined from these tables and other applicationspecific One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as: 0.5 (1.5 x 1) + (0.15 x 15) 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters. 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns]. = 0.133 ~ 128ms ~
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Address / Command Setup, Hold and Derating:
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For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table 53) to the tIS and tIH derating value (see Table 54) respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(dc) to ac region', use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 25). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded 'dc to VREF(dc) region', use nominal slew rate for derating value (see Figure 24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 26). For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 55). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in Table 54, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [ Table 53 ] ADD/CMD Setup and Hold Base-Values for 1V/ns [ps] tIS(base) tIH(base) tIS(base)-AC150 DDR3-800 200 275 DDR3-1066 125 200 DDR3-1333 65 140 65+125 DDR3-1600 TBD TBD TBD+125 reference VIH/L(ac) VIH/L(dc) VIH/L(ac)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns].
[ Table 54 ] Derating values DDR3-800/1066 tIS/tIH-ac/dc based tIS, tIH Derating [ps] AC/DC based AC175 Threshold -> VIH(ac) = VREF(dc) + 175mV, VIL(ac) = VREF(dc) - 175mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -60 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 96 67 8 6 2 -3 -9 -27 -54 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 104 75 16 14 10 5 -1 -19 -46 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 112 83 24 20 13 13 7 -11 -38 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 120 91 32 30 26 21 15 -2 -30 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 128 99 40 38 34 29 23 6 -22 tIH 100 74 50 46 40 34 24 10 -10
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[ Table 55 ] Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold
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tIS, tIH Derating [ps] AC/DC based Alternate AC150 Threshold -> VIH(ac) = VREF(dc) + 150mV, VIL(ac) = VREF(dc) - 150mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 70 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 83 58 8 8 8 8 7 -2 -17 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 91 66 16 16 16 16 15 6 -9 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 99 74 24 24 24 24 23 14 -1 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 107 82 32 32 32 32 31 22 7 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 115 90 40 40 40 40 39 30 15 tIH 100 84 50 46 40 34 24 10 -10
[ Table 56 ] Required time tVAC above VIH(ac) {blow VIL(ac)} for valid transition Slew Rate[V/ns] min
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 75 57 50 38 34 29 22 13 0 0
tVAC @175mV [ps] max
-
tVAC @50mV [ps] min
175 170 167 163 162 161 159 155 150 150
max
-
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
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CK DQS
DQS tDS VDDQ tDH tDS tVAC tDH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max tVAC
V SS
Delta TF Setup Slew Rate= VREF(dc) - Vil(ac)max Falling Signal Delta TF Delta TR Setup Slew Rate Vih(ac)min - VREF(dc) = Rising Signal Delta TR
Figure 21 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock).
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
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CK DQS
DQS VDDQ tDS tDH tDS tDH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate dc to VREF region nominal slew rate
VIL(ac) max
VSS Delta TR Hold Slew Rate VREF(dc) - Vil(dc)max Rising Signal = Delta TR Delta TF
Hold Slew Rate Vih(dc)min - VREF(dc) Falling Signal = Delta TF
Figure 22 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock).
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
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CK DQS
DQS VDDQ tDS tDH nominal line VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS tDS tVAC tDH
VIH(ac) min
Delta TR Setup Slew Rate tangent line[Vih(ac)min - VREF(dc)] Rising Signal= Delta TR
Delta TF
Setup Slew Rate tangent line[VREF(dc) - Vil(ac)max] Falling Signal = Delta TF
Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock)
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
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CK DQS
DQS tDS VDDQ tDH tDS tDH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line tangent line
nominal line
VIL(ac) max
VSS Delta TR Hold Slew Rate tangent line [ VREF(dc) - Vil(dc)max ] Rising Signal = Delta TR Hold Slew Rate tangent line [ Vih(dc)min - VREF(dc) ] Falling Signal = Delta TF Delta TF
Figure 24 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock)
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Data Setup, Hold and Slew Rate Derating:
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For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see Table 57) to the tDS and tDH (see Table 58) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max (see Figure 27). If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(dc) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 29). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc) (see Figure 28). If the actual signal is always later than the nominal slew rate line between shaded 'dc level to VREF(dc) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 30). For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 59). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization [ Table 57 ] Data Setup and Hold Base-Value [ps] tDS(base) tDH(base) DDR3-800 75 150 DDR3-1066 25 100 DDR3-1333 -10 65 DDR3-1600 TBD TBD reference VIH/L(ac) VIH/L(dc)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate) [ Table 58 ] Derating values DDR3-800/1066 tIS/tIH-ac/dc based tDS, tDH Derating [ps] AC/DC baseda DQS,DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 88 59 0 tDH 50 34 0 3.0 V/ns tDS 88 59 0 -2 tDH 50 34 0 -4 2.0 V/ns tDS 88 59 0 -2 -6 tDH 50 34 0 -4 -10 1.8 V/ns tDS 67 8 6 2 -3 tDH 45 8 4 -2 -8 1.6 V/ns tDS 16 14 10 5 -1 tDH 16 12 6 0 -10 1.4V/ns tDS 22 18 13 7 -11 tDH 20 14 8 -2 -16 1.2V/ns tDS 26 21 15 -2 -30 tDH 24 18 8 -6 -26 1.0V/ns tDS 29 23 6 -22 tDH 34 24 10 -10
Note : a. Cell contents shaded in red are defined as 'not supported'.
[ Table 59 ] Required time tVAC above VIH(ac) {blow VIL(ac)} for valid transition Slew Rate[V/ns]
>2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5
tVAC[ps] min
75 57 50 38 34 29 22 13 0 0
max
-
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
1Gb DDR3 SDRAM
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CK DQS
DQS tDS VDDQ tDH tDS tVAC tDH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max tVAC VSS
Delta TF Setup Slew Rate= VREF(dc) - Vil(ac)max Falling Signal Delta TF
Delta TR Setup Slew Rate Vih(ac)min - VREF(dc) Rising Signal = Delta TR
Figure 27 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock).
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
1Gb DDR3 SDRAM
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CK DQS
DQS VDDQ tDS tDH tDS tDH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate dc to VREF region nominal slew rate
VIL(ac) max
VSS Delta TR Hold Slew Rate VREF(dc) - Vil(dc)max Rising Signal = Delta TR Delta TF
Hold Slew Rate Vih(dc)min - VREF(dc) = Falling Signal Delta TF
Figure 28 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock).
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
1Gb DDR3 SDRAM
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CK DQS
DQS VDDQ tDS tDH nominal line VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS tDS tVAC tDH
VIH(ac) min
Delta TR Setup Slew Rate tangent line[Vih(ac)min - VREF(dc)] Rising Signal= Delta TR
Delta TF
Setup Slew Rate tangent line[VREF(dc) - Vil(ac)max] Falling Signal = Delta TF
Figure 29 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock)
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Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH
1Gb DDR3 SDRAM
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CK DQS
DQS tDS VDDQ tDH tDS tDH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line tangent line
nominal line
VIL(ac) max
VSS Delta TR Hold Slew Rate tangent line [ VREF(dc) - Vil(dc)max ] Rising Signal = Delta TR Hold Slew Rate tangent line [ Vih(dc)min - VREF(dc) ] Falling Signal = Delta TF Delta TF
Figure 30 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock)
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