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Advanced LCD Controller AL310 Data Sheets
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AL310
Amendments
99.10.04 02.12.17 Preliminary version Preliminary version A0.1: (1) Updated from Preliminary version A0.1 Version B1.0: (1) Updated from Preliminary version A0.2 (2) Add Register Description
03.05.23
THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE.
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Contents:
1. General Description ................................................................................................... 5 2. Function Block Diagram ............................................................................................ 6 3. Features ...................................................................................................................... 6 3.1 General Features .................................................................................................... 6 3.2 Feature Description: .............................................................................................. 7 4 5 6 7 Applications ................................................................................................................ 8 Application Example (Advanced LCD TV with PIP Function)................................. 9 Pin-Out Diagram ....................................................................................................... 10 Pin Definition and Description ................................................................................ 12 7.1 Input Format Table of AL310:.............................................................................. 12 7.2 The pin-out definitions are described as follows:............................................. 12 8 General Function Description ................................................................................. 18 8.1 Function Blocks ................................................................................................... 18 8.2 VIU (Video Input Unit)........................................................................................... 20 8.2.1 8.2.2 8.2.3 8.2.4 Input Data Format ......................................................................................... 20 Video Capture and Down Scale Engine ...................................................... 20 Automatic Positioning Registers................................................................. 22 PLL Programming for Memory and Display Clock..................................... 22
8.3 MIU (Memory Interface Unit)................................................................................ 22 8.3.1 8.3.2 DRAM Bandwidth Consideration ................................................................. 22 DRAM Input/Output Windows ...................................................................... 23
8.4 VPU (Video Processing Unit)............................................................................... 24 8.4.1 8.4.2 8.4.3 Video De-Interlaced with Film Detection and Motion Adaptive................. 24 Up Scale Engine............................................................................................ 24 Keystone Up Scale Engine........................................................................... 25
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8.5 VOU (Video Output Unit)...................................................................................... 26 8.5.1 8.5.2 8.5.3 8.5.4 PIP Overlaying............................................................................................... 27 OSD ................................................................................................................ 28 LUT (Look up table for Gamma Correction and Color Enhancement) ..... 29 Dithering ........................................................................................................ 29
8.6 BIU (Bus Interface Unit) ....................................................................................... 30 9 Register Definition & Description ........................................................................... 31 9.1 Register Set .......................................................................................................... 31 9.2 Register Description ............................................................................................ 40 10 Electrical Characteristics......................................................................................... 97 10.1 10.2 10.3 10.4 Absolute Maximum Ratings ............................................................................ 97 Recommended Operating Conditions............................................................ 97 DC Characteristics ........................................................................................... 97 AC Characteristics ........................................................................................... 98
11 Timing Diagrams ...................................................................................................... 99 12 Mechanical Drawing- BGA-308.............................................................................. 100
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1. General Description
AL310 is a highly integration LCD Controller which supports Triple-Port input with multiple graphics/video formats capable and mixing captured frames output with scaling, overlaying and alpha blending effects...etc. It can be used for most video conversion and processing applications. AL310 is equipped with a high-quality scaling engine that automatically maintains full screen output display, regardless of the resolution of the incoming signals. Applying AverLogic's proprietary scaling algorithm, the primary input graphics/video can be scaled up and scaled down independently in horizontal & vertical directions. It also provides film detection, advanced de-interlacing, filtering, and scaling which's able to convert and process the interlaced video to be displayed on progressive panels. The On Screen Display (OSD) window provides overlay of a control menu, text, or caption on the output display. It's built-in OSD generator with 2K Bytes programmable RAM fonts and supports optional external OSD ROM. AL310 is built-in 3-channel DAC for non-interlaced analog output and 48bit digital output. It's housed with 308-pin PBGA.
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2. Function Block Diagram
3. Features
3.1 General Features
Support Triple Digital RGB/YUV inputs and Non-interlaced RGB/YPbPr Analog and Digital outputs Triple Input ports for PIP overlaying (Video over Graphics or Video over Video) Film Detection with Inverse 3:2/2:2 Pull Down Advanced Motion Adaptive Deinterlacing AverLogic's Proprietary Scaling Algorithm for Scaling Up and Down Direct Video Memory Access for Graphic Data Processing Built-in 2K Bytes OSD RAM and support External OSD Font ROM Available in 308-pin PBGA 2.5V Core and 3.3V I/O power supplies with 5V input tolerant
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3.2 Feature Description:
Input Interface Input resolution up to 1280x1024 @60Hz Simultaneous Primary and Secondary input for PIP overlaying Input resolution support: VGA up to SXGA(RGB), SDTV, EDTV and HDTV Video interface ITU-R 656-8bit & 601-16bit, YUV422 supported Output Interface Output resolution up to 1280x1024 @60Hz Analog non-interlaced RGB/YPbPr and Digital RGB 48bit outputs supported SDRAM Interface Support maximum 48bit bus width SDRAM interface, two or three of SDRAM configuration up to 125 MHz supported Deinterlacing and Scan Rate Conversion DeInterlacing for Interlaced Video Input Advanced Motion Adaptive Deinterlacing Film Mode Detection with Inverse 3:2 & 2:2 pull down Frame Rate Conversion(FRC) from 50Hz up to 120Hz Scaling Engine and Video Processing Independent Scale Up and Down in both Horizontal and Vertical direction Keystone Correction for Front-Projection Systems Sharpness Control Built-in LUT for Gamma Correction and Color Adjustment Dithering Logic for Color Depth Enhancement Overlaying and Alpha Blending for PIP function Two input source overlaying for PIP display with Alpha Blending/Transparency effect I2C or Parallel Port Registers Access Registers can be accessed by serial I2C port or 8 bit parallel port for high speed registers data update
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On Screen Display (OSD) 2k Bytes Internal OSD RAM for fine bitmaps and text font Dual internal OSD windows support with Alpha Blending/Transparency effect Support up to 64k Bytes External ROM for font and bitmap data In ROM mode, 1.5k Bytes OSD RAM for Context RAM, 0.5k Bytes for Pre-fetch RAM Pre-fetch RAM supports different speed types of Font ROMs (EE-PROM, PROM or Mask-ROM) Other Features Primary input stream VBI pass through support Automatic screen positioning and phase adjustment support for LCD output display Frame capture Mirroring support in Horizontal or Vertical direction NTSC/PAL Video Input Auto-Detection support Power Saving support Slave mode support Operating Power 2.5V core and 3.3V I/O power supplies with 5V input tolerant Package 308-pin PBGA
4 Applications
PIP LCD TV & LCD Monitor with Video Input PIP PDP/Front Projection/Rear Projection/Progressive Scan TVs PIP HDTV/DTV Video Enhancer & Advanced TV Tuner Box Other PIP Flat Panel Displays
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5 Application Example (Advanced LCD TV with PIP Function)
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6 Pin-Out Diagram
PBGA-308 Package:
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11
RA2 RA0 VOUT33 OXIN2 VDD25
12
RA1 RDATA6 VOUT31 PDSDEN VDD25
13
RDATA7 RDATA4 VOUT29 VOUT30
14
RDATA5 RDATA2 OXIN1 VOUT1
15
RDATA3 RDATA0 DSCLK VOUT2
16
RDATA1 PHS VOUT25 VOUT7
17
SCLK PVS VOUT23 VOUT4 VOUT13 VOUT11 AVSS25
18
VOUT28 VOUT26 VOUT3 VOUT5 VOUT19 VOUT17 VOUT20 VOUT12 IOG MDATA35 MADDR8 MADDR4 MADDR1 MADDR0 MDATA30 MDATA29 MDATA41 MDATA43 MDATA18 MDATA13
19
VOUT27 VOUT22 VOUT6 VOUT15 VOUT10 VOUT18 VOUT9 COMP IOB MDATA34 MADDR11 MADDR9 MADDR5 MADDR2 MDATA31 MDATA27 MDATA39 MDATA20 MDATA17 MDATA16
20
VOUT24 VOUT21 VOUT0 VOUT14 VOUT16 VOUT8 VREFOUT VREFIN IOR MDATA33 MDATA32 MADDR10 MADDR6 MADDR3 PMXIN MDATA26 MDATA25 MDATA24 MDATA23 MDATA22
Coordinate
VSS33 H AVSS33R VSS25 H VSS25 VSS25 H VSS33
VSS33 AVDD33R VSS25 VSS25 VSS25 VSS33
AVDD33 AVDD33B VSS33 VSS33 VSS33 VSS33 AVSS33B AVSS33 AVDD33G AVSS33G
DVSS25 RSET MDATA36 MADDR7 AVDD25 DVDD25 VDD25 VDD25
VDD25 MDATA10 MDATA6 CSB MDATA5
VDD25 MDATA42 MDATA9 MDATA46 CLKE MDATA44 MDATA45 MDATA47 MDATA7 WEB MDATA40 MDATA11 MDATA8 MDATA14 MDATA12 RASB CLK MDATA15 MDATA38 BA1 CASB
MDATA28 MDATA21 MDATA37 MDATA19 BA0
A B C D E F G H J K L M N P R T U V W Y
Coordinate
11
12
13
14
15
16
17
18
19
20
: Input Interface : OSD ROM Interface : DAC Output Interface : Panel Interface : SDRAM Interface : HOST Interface : PLL Interface : Digital Power 2.5V : Digital Ground 2.5V : Digital Power 3.3V : Digital Ground 3.3V
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7 Pin Definition and Description
7.1 Input Format Table of AL310: VIN No. PC(V0) 55~48 47~40 39~32 31~24 23~16 R/Cr 15~8 G/Y Y V1 Cr Y Y V2 Y YCbCr CbCr Cb CbCr YCbCr 7~0 B/Cb CbCr YCbCr
7.2 The pin-out definitions are described as follows:
Pin Name Input Interface VIN[55:48] U2,T4,R4,R1,P3,P1, N1,M2 I For V2: YUV 4:2:2(16bit) : Y[7:0] Input Data YUV 4:2:2 (8 bit) : YCbCr[7:0] Input Data VIN[47:40] L4,L1,K2,K4,J2,H1, G1,G2 I For V1: YUV 4:4:4 For V2: YUV 4:2:2(16bit) : CbCr[7:0] Input Data VIN[39:32] G3,E1,D1,E2,D2,E3, C2,J5 I For V1: YUV 4:4:4 : Y[7:0] Input Data YUV 4:2:2(16bit) : Y[7:0] Input Data VIN[31:24] W5,V5,W4,V4,W3, V3,V2,W1 I For V1: YUV 4:4:4 : Cb[7:0] Input Data YUV 4:2:2(16bit) : CbCr[7:0] Input Data YUV 4:2:2 (8 bit) : YCbCr[7:0] Input Data VIN[23:16] V1,T3,U1,T2,R3,T1, R2,P4 I For PC RGB : RED[7:0] Input Data : Cr[7:0] Input Data Pin Number I/O type Description
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AL310 Pin Name Pin Number I/O type For V0: YUV 4:4:4 VIN[15:8] M4,M3,M1,L3,L2,K1 ,K3,J1 I For PC RGB For V0: YUV 4:4:4 : Y[7:0] Input Data YUV 4:2:2(16bit) : Y[7:0] Input Data VIN[7:0] J3,J4,H2,H3,F1,F2, F3,C1 I For PC RGB For V0: YUV 4:4:4 : Cb[7:0] Input Data YUV 4:2:2(16bit) : CbCr[7:0] Input Data YUV 4:2:2 (8 bit) : YCbCr[7:0] Input Data PCCLK PCHREFF PCHS PCVS V1CLK V1HREFF V1HS V1VS V2CLK V2HREFF V2HS V2VS OSD ROM Interface RDATA[7:0] A13,B12,A14,B13, A15,B14,A16,B15, RA[15:0] B3,A3,A4,A5,B6,A6, B7,A7,A8,A9,B9,A10 ,B10,A11,A12,B11 DAC Output Interface O ROM Address Bus Bit 15-0 I ROM Data Bus Bit 7-0 N2 N4 N3 P2 Y4 Y5 Y6 W7 V8 U6 W8 Y8 I I I I I I I I I I I I Reference Clock of PC or Video Port 0 HDE Input of PC or Video Port 0 HSYNC Input of PC or Video Port 0 VSYNC Input of PC or Video Port 0 Reference Clock of Video Port 1 HDE Input of Video Port 1 HSYNC Input of Video Port 1 VSYNC Input of Video Port 1 Reference Clock of Video Port 2 HDE Input of Video Port 2 HSYNC Input of Video Port 2 VSYNC Input of Video Port 2 : BLUE[7:0] Input Data : GREEN[7:0] Input Data : Cr[7:0] Input Data Description
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AL310 Pin Name AVDD33 AVSS33 AVDD25 AVSS25 AVDD33R AVSS33R AVDD33G AVSS33G AVDD33B AVSS33B DVDD25 DVSS25 IOR IOG IOB RSET COMP VREFIN VREFOUT Panel Interface VOUT[47:40] D4,B4,B5,C5,C6,D6, D5,B8 VOUT[39:32] D7,D9,C7,C10,C8, C9,C11,D10 VOUT[31:24] C12,D13,C13,A18, A19,B18,C16,A20 VOUT[23:16] C17,B19,B20,G18, E18,F19,F18,E20 VOUT[15:8] D19,D20,E17,H18, F17,E19,G19,F20, VOUT[7:0] D16,C19,D18,D17, C18,D15,D14,C20 O Digital Output Interface BLUE[7:0] Odd O Digital Output Interface GREEN[7:0] Odd O Digital Output Interface RED[7:0] Odd O Digital Output Interface BLUE[7:0] Even O Digital Output Interface GREEN[7:0] Even O Digital Output Interface RED[7:0] Even Pin Number H13 K16 M17 G17 J12 J11 L16 M16 J13 J16 N17 H17 J20 J18 J19 J17 H19 H20 G20 I/O type AP AG AP AG AP AG AP AG AP AG DP DG O O O I I I O Description 3.3v Analog Power for DAC Analog GND for DAC 2.5V Analog Power for DAC Analog GND for DAC 3.3 V Analog Power for Channel R Analog GND for Channel R 3.3 V Analog Power for Channel G Analog GND for Channel G 3.3 V Analog Power for Channel B Analog GND for Channel B 2.5V Digital Power for DAC Digital GND for DAC Channel R Current Output Channel G Current Output Channel B Current Output Full-Scale Adjust Resister Compensation Pin Voltage Reference Input Voltage Reference Output
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AL310 Pin Name SCLK DSCLK PDSDEN PHS PVS OXIN1 OXIN2 SDRAM Interface MDATA[47:0] W13,W12,V13,U13, V18,U12,U18,V14, U19,V16,V17,K17, K18,K19,K20,L20, R19,R18,T18,T17, T19,T20,U20,V20, W20,Y20,U17,V19, W17,W18,W19,Y19, U16,U15,Y18,V15, W14,U11,V12,Y14, Y13,V11,Y11,U8, W10,V10,W9,U9 MADDR[11:0] L19,M20,M19,L18, L17,N20,N19,M18, P20,P19,N18,P18 PMXIN BA[1:0] DQML DQMH WEB RASB CASB CLK CLKE R20 W16,Y17 U10 Y10 U14 W15 Y16 Y15 Y15 I O O O O O O O O SDRAM Read Data Input Sampling Clock SDRAM Bank Address Bit 0-1 SDRAM Low Byte Data Mask SDRAM High Byte Data Mask SDRAM Write Enable SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM reference Clock SDRAM Clock Enable O SDRAM Address Bit 11-0 I/O SDRAM Data Bus Bit 47-0 A17 C15 D12 B16 B17 C14 D11 Pin Number I/O type O O O I/O I/O I I Display Pixel Clock Display Pixel Clock Divided by 2 Display Data Enable Display HSYNC output / input for Slave Mode Display VSYNC output / input for Slave Mode Reference Clock 1 for Display Device Reference Clock 2 for Display Device Description
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AL310 Pin Name CSB Host Interface RSTB HOST_DB[7:0] C3 B2,V7,W6,V6,U5,Y3 ,Y2,W2 HOST_WRB HOST_RDB HOST_DENB HOST_MEMB HOST_RDYB IREQ GPO0 GPO1 GPO2 I2C_EN PLL Interface MXIN MXOUT P1VDD25 P1VSS25 P1AVDD25 P1AVSS25 P2VDD25 P2VSS25 P2AVDD25 P2AVSS25 B1 A1 L5 M5 K5 E4 F4 D3 G4 H4 I O DP DG AP AG DP DG AP AG Crystal Input (14.31818MHz) Crystal Output 2.5V Pad Ring Power for PLL1 Pad Ring GND for PLL1 Analog Power for PLL1 Analog GND for PLL1 2.5V Pad Ring Power for PLL2 Pad Ring GND for PLL2 Analog Power for PLL2 Analog GND for PLL2 A2 Y7 U7 V9 Y9 C4 U4 U3 Y1 D8 I I I I O O O O O I Reference Clock of Parallel Port Read/Write Strobe of Parallel Port Data Cycle of parallel Port Memory Access Cycle of Parallel Port Read Data Ready Output of Parallel Port Interrupt Output of Parallel Port General Output Port 0 General Output Port 1 General Output Port 2 I2C Enable I I/O Reset Host Data Bus Bit 7-0 of Parallel Port Pin Number W11 I/O type O Description SDRAM Chip Select
DIGITAL POWER / GROUND VDD25 E9,E10,E11,E12, P17,R17,T9,T10, T11,T12 VSS25 J9,J10,K9,K10,K11, K12,L9,L10,L11,L12 DG Digital Ground 2.5V DP Digital Power 2.5V
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AL310 Pin Name Pin Number ,M9,M10,M11,M12 VDD33 H8,H9,J8,K8,L8,M8, N8,N9 VSS33 H10,H11,H12,K13, L13,M13,N10,N11, N12,N13 Note: For I/O type, "I", "O", "AP", "AG", "DP", and "DG" stand for "Input", "Output", "Analog Power", "Analog Ground", "Digital Power", and "Digital Ground" respectively. DG Digital Ground 3.3V DP Digital Power 3.3V I/O type Description
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8 General Function Description
8.1 Function Blocks AL310 provide a fully programmable structure allowing video stream process more flexible. The AL310 data process is executed by parsing in the modules such as capture, down scale, memory, up scale and mixer. In each module, data will be manipulated corresponding to the setting of registers. Due to the lack of the number of registers, some registers require banking to other page for access. There are 4 group registers, base control registers, capture control registers, memory control registers and display control registers. The value of base register 0eh determines which group of registers is taken effect. If register 0eh is programmed to value 00, the group of base control registers is chosen; and the register 0eh with value 01 is for capture register group, value 02 is for memory register group and value 03 is for display register group. The register 0eh must be set to corresponding value before that group of register can be accessed.
Register
Group ID 00 <1:0> 01 10 11
Group register Description Access only base control registers Access capture and base control registers Access memory and base control registers Access display and base control registers
Symbol BAS# CAP# MEM# DIS#
Example BAS#16 CAP#20 MEM#20 DSP#20
0Eh
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PSCapHStart PSCapVStart
PSCapHSrcSize
SSCapHStart SSCapVStart
SSCapHSrcSize
PSCapVSrcSize
PS Capture Window
SSCapVSrcSize
SS Capture Window
Down Scale Engine (*Note)
Down Scale Engine
PSInputStride PSCapHDestSize PSInputStart PSInputSize SSInputStart
SSInputStride
SSCapHDestSize SSInputSize
PSCapVDestSize PSDisVSrcSize
PS DRAM Window
SSCapVDestSize
SS DRAM Window
DRAM
PSOutputStart
PSOutputSize PSOutputStride PSDisHSrcSize
SSOutputStart SSOutputStride
SSOutputSize
Up Scale Engine (*Note) Mixer (Overlay) PSHDEStart PSDisHDestSize VEnd VDEStart PSVDEStart OSD PS Output Window text SS Output Window PSVDEEnd VDEEnd SSVDEEnd SSHDEStart SSHDEEnd PSHDEEnd
OSD
VTotal
SSVDEStart
PSDisVDestSize
HDEStart HEnd HTotal * Note: Primary Stream process supports Down Scale or Up Scale, it can't do both at the same ti V t
HDEEnd
Primary Stream and Secondary Stream processing parse and defined registers
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8.2 VIU (Video Input Unit) AL310 supports triple input ports for PIP overlaying. Main-channel accepts RGB/YUV 24/16/8bit and Sub-channel accepts 16/8bit YUV 4:2:2 video data stream with ITU-R656/601 standards. Applying AverLogic Proprietary Scaling algorithm, the video stream can be scaled down to accommodate required output resolutions with high quality scaling effect. The high quality scaling engine also ensures full screen output display. For PC Graphics input, AL310 provides Auto-adjustment function to adjust Phase, and Position automatically.
8.2.1 Input Data Format The AL310 is an integrated video processor that automatically detects and converts multiple graphics & video formats. The AL310 recognized the input data streams as primary and secondary. The Index and Base registers provide user an expansion of the control registers, which implements easy control of the input and the desired output format. The Base registers control the input type and target format. The AL310 accepts four data formats: 24bit RGB, 8-bit ITU-R BT.656 (CCIR656), 16-bit CCIR601 422 and 24-bit CCIR601 444 data. The clock and sync signal pins separate for RGB or YUV while the YUV data share the same pins as RGB data. applications, please refer to AL310 Application Notes. 8.2.2 Video Capture and Down Scale Engine The AL310 has a high-quality scaling engine performing proprietary scaling operations independently in both Horizontal and Vertical direction with 4-line, high precision interpolation. For detailed
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8.2.3 Automatic Positioning Registers The AL310 can detect and report input capture timing for Auto-adjustment function. It detects the starting and ending positions of active video in both direction (Horizontal and Vertical) and ensures the output fit properly into the display region. The data threshold value defines the sensibility of valid data. The capture data will be sampled and qualified base upon the value of data threshold, so that it can determine the starting point and ending point of an active line or an active frame. 8.2.4 PLL Programming for Memory and Display Clock AL310 embedded 2 independent 200MHz PLL-Based Clock Generator. One is used to generate SDRAM clock (CLK, pin Y15), the other is for output clock (SCLK, pin A17). They are all reference input clock from XIN (generally 14.318MHZ). There are 3 operation modes in defined in PLL register: Power Down Mode, Bypass Mode and Normal Mode. Power Down Mode forces FOUT to low and PLL in low power consumption state (<10uW). Bypass Mode provides FOUT with the same frequency as FIN. Normal Mode synthesizes FOUT by programming suitable divider values. It needs a Tready time (Pull_in Time + Locking Time) for PLL to re-lock the FIN clock when PLL wakes up from Power Mode to Normal Mode. In general, it should be reserved a Tread time for re-locking when PLL is changed to Normal Mode from Power Mode or Bypass Mode, or when any divider setting is changed.
8.3 MIU (Memory Interface Unit) MIU supports SDRAM 48/32bit bus width interface. AL310 supports various SDRAM configurations, such as 1Mx16, 2ea or 3ea. It uses sequential Burst mode to control SDRAM memory that operates at minimum 100MHz of clock frequency. For detail operation of SDRAM, please reference memory specifications.
8.3.1 DRAM Bandwidth Consideration The AL310 uses external DRAMS for the purpose of frame rate conversion between the input video and the output video device. The frame rate conversion for video is done by
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double buffering. However, for graphics, double buffering is disabled for most of the time less motion happens in graphics. 8.3.2 DRAM Input/Output Windows The proceeding diagrams will describe the DRAM input control.
The DRAM input data size depends on the horizontal capture destination size. After the input data size has been defined, the memory address of input data can be determined by the register DRAM input stride. The DRAM input stride can be programmed to provide extra memory space for input data.
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8.4 VPU (Video Processing Unit) AL310 identifies video input sources including Progressive Film (24/25 fames/sec) and Interlaced Video (50/60 fields/sec) and selects appropriate de-interlacing algorithm for video enhancement. VPU supports Film Detection with Inverse 3:2 or 2:2 Pull Down and AverLogic Proprietary Deinterlacing. When AL310 detects the video source as Film, then progressive scan frames will be reassembled and output twice input rate such as 50/60 frame/sec. Otherwise, it will be taken as Interlaced Video Source, and processed by using Deinterlacing to reduce video artifacts. The scaling engine offers Scale-Up effect by applying AverLogic's proprietary scaling algorithm. It supports independent Scale-Up in both Horizontal and Vertical direction with 4-line, high precision interpolation. The Sharpness Control provides good effect for image enhancement. It also provides Keystone function for Projector application.
8.4.1 Video De-Interlaced with Film Detection and Motion Adaptive Video Processing unit equips a high quality deinterlacing algorithm to optimize the output progressive scan frame by recovering film sequence and compensating motion effect during the deinterlacing process. The motion estimation can evaluate both Y/C data or Y data by setting register. In Motion Adaptive process, the sensitivity of the data estimation can be adjusted by register for Luma and Chroma threshold. In film video, such as DVD movie, some duplicate fields are inserted into the interlaced video stream. Original film sequence detection and recovery can produce a smooth progressive scan frame transition after deinterlaced.
8.4.2 Up Scale Engine The Up Scale Engine can scale up Primary Stream to higher resolution in high quality for output display. The AL310 adapts FIR scaling engine that can do horizontal and vertical up scale independently. The primary stream picture can be either down scale to smaller size of picture or up scale to larger size of picture from original capture (input) picture for output, but it can not do both up and down scale process at the same time. Consider to capture full picture of input data if the output resolution of primary stream picture is going to be enlarged.
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Following block diagram illustrates the define registers of source primary stream window and destination up scale window.
8.4.3 Keystone Up Scale Engine The AL310 can scale up the image in dynamic ratio which is good for projector image correction. The projected images from the projector sometimes show as Figure due to the misalignment or cheap optics. The AL310 can up scale picture in dynamic ratios which are loaded from pre-stored at internal FIFO buffers. The keystone is designed to compensate the distortions, such as figures following.
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dis tortion 1
dis tortion 2
dis tortion 3
8.5 VOU (Video Output Unit) Two independent On-Screen-Display (OSD) windows provide overlay for a control menu, text, or caption on the output display. The AL310's OSD is very flexible in the way that the font, size, and display location are all programmable. The internal 2K byte SRAM provides storage for the OSD information. The OSD can be operated with only this internal SRAM or with an external ROM to store font tables or even larger bitmaps. Builtin 8bit Programmable Gamma Look-Up Table for each input color channel for Gamma Correction. It may be used for RGB Contrast, Brightness and Color Temperature adjustments. Dithering is performed to retain color resolution for LCD panels that support 18-bit color depths. AL310 provides Digital video output interface that can be directly connected to 24bit TFT LCD Panel or DVI/LVDS Transmitters. It also provides Analog video output which can support SXGA resolution.
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Horizontal Total (DSP:20h, DSP:21h)
Display HSYNC
H-SYNC End (DSP:22h DSP:23h)
Display HDE
Horizontal Display Start (DSP:24h, DSP: 25h) Horizontal Display End (DSP:26h, DSP: 27h)
Primary Stream Display Window
Secondary Stream Display Window
Primary Stream HDE
PS Horizontal Display Start (DSP:30h, DSP:31h) PS Horizontal Display End (DSP:32h, DSP:33h)
Secondary Stream HDE
SS Horizontal Display Start (DSP:38h, DSP:39h) SS Horizontal Display Start (DSP:3Ah, DSP:3Bh)
AL310 Output timing and display windows
8.5.1 PIP Overlaying In the primary stream, select either PS image or PS background color to show on the PS
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display region. In proportion to the SS image or SS background color show on the SS display region. On the overlay area of PS & SS is a blending region. If PS and SS don't fill up the display screen, the desktop color is showed on other areas. The Figure 3 Display Screen shows the location of different combination from input image or internal color generator.
Figure 3 Display Screen
8.5.2 OSD Two independent On-Screen-Display (OSD) windows provide overlay for a control menu, text, or caption on the output display. The AL310's OSD is very flexible in the way that the font, size, and display location are all programmable. The internal 2K byte SRAM provides storage for the OSD information. The OSD can be operated with only this internal SRAM or with an external ROM to store font tables or even larger bitmaps. Regarding the detailed usage, please refer to AL310's OSD Application Note.
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8.5.3 LUT (Look up table for Gamma Correction and Color Enhancement) Because of the different characteristics of TV's and PC monitors, direct color space conversion from TV to PC may not show the same color that the human eye sees from the original video on the TV. The contrast may not be sufficient, and the hue may not be accurate, so to resolve these issues the AL310 has a gamma correction internal LUT implemented. The AL310 provides programmable registers for implementing the LUT. The directly converted colors are sent to the LUT that then sends out the mapped, corrected colors. The user can program the LUT based on his/her own experiments on specific types of monitors. The typical input-output mapping curve is usually somewhat like the following:
Output Corrected Conversion Direct Conversion
Input
Figure 11 LUT Mapping
8.5.4 Dithering The AverLogic offers dithering technique that simulates display of colors that are not in the current color space of a particular image. The Dithering logic provides additional color depth enhancement to retain color resolution for LCD panels that support 18-bit color depth.
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8.5.5 Dual Output The AL310 supports both digital and analog output interfaces that provide flexible output mode selections according to different user desire.
8.6 BIU (Bus Interface Unit) It supports I2C serial and parallel port programming interfaces. I2C serial interface requires two wires to access while the parallel port interface needs 11 wires. The communication speed of proprietary parallel interface is much faster than I C serial interface. Regarding to the detailed usage, please refer to AL310's General Application Note.
2
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9 Register Definition & Description
Registers are provided to setup AL310. These registers can be programmed via host interface. The host interface protocol is illustrated in "Host Interface" paragraph. The application notes will describe more detailed settings about these registers. Upon request, AverLogic will provide the sample code or tool of host interface control software. 9.1 Register Set
Register Name Base Control Group Registers COMPANYID INTRMASK INTRSTATUS CAPCTRL DISCTRL1 DISCTRL2 POLARITYCTRL OTIMECTRL GROUPACCESS BOARDCFG INSRCFORMAT INPUTCTRL HREFDLY PSSSCTRL SSCTRL PSCTRL MEMACCR INVMSB PLLSETR MPLLNF MPLLNRO OPLLNF OPLLNRO 00h 02h 03h 06h 07h 08h 09h 0Ah 0Eh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Bh 1Ch 1Dh 1Eh 1Fh R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 46h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Company ID Interrupt Mask Interrupt Vector and Mode Capture Data Control Display Data Control 1 Display Data Control 2 Display Polarity Control Display Timing Control Group Access ID Board Configuration Input Video Source Format Input Control Horizontal Reference Delay PS and SS control SS input control PS input control Memory Access Control Inverted MSB of PS & SS PLL Setting for Memory and Display LSB of NF Value for Memory PLL MSB of NF/NR/NO Value for Memory PLL LSB of NF Value for Display PLL MSB of NF/NR/NO Value for Display PLL Address R/W Default Function
Capture Control Group Registers(Accessible when BAS#0E = 01h)
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AL310 Register Name PS Timing CAPPSHSTART CAPPSHSRCSIZE CAPPSHDESTSIZE CAPPSVSTART CAPPSVSRCSIZE CAPPSVDESTSIZE PSINTERLACECTRL PSHDNRATIO PSVDNRATIO VBI Input Timing VBIVSTART VBIVEND VBIHSTART VBIHSIZE ITU-656 Detection PS656HSTART PS656HEND PS656VSTART PS656VEND SS656HSTART SS656HEND SS656VSTART SS656VEND SS Input Timing CAPSSHSTART CAPSSHSRCSIZE CAPSSHDESTSIZE CAPSSVSTART CAPSSVSRCSIZE CAPSSVDESTSIZE SSINTERLACECTRL 41h & 40h 43h & 42h 45h & 44h 47h & 46h 49h & 48h 4Bh & 4Ah 4Eh R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h SS Horizontal Capture Start SS Horizontal Capture Source Size SS Horizontal Capture Destination Size SS Vertical Capture Start SS Vertical Capture Source Size SS Vertical Capture Destination Size SS Interface Control 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh R/W R/W R/W R/W R/W R/W R/W R/W 20h A0h 02h 04h 20h A0h 02h 04h PS ITU656 data Horizontal sync start PS ITU656 data Horizontal sync end PS ITU656 data Vertical sync start PS ITU656 data Vertical sync end SS ITU656 data Horizontal sync start SS ITU656 data Horizontal sync end SS ITU656 data Vertical sync start SS ITU656 data Vertical sync end 34h 35h 36h 37h R/W R/W R/W R/W 00h 00h 00h 00h VBI Vertical Capture Start VBI Vertical Capture End VBI Horizontal Capture Start VBI Horizontal Capture Size 21h & 20h 23h & 22h 25h & 24h 27h & 26h 29h & 28h 2Bh & 2Ah 2Eh 31h & 30h 33h & 32h R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h PS Horizontal Capture Start PS Horizontal Capture Source Size PS Horizontal Capture Destination Size PS Vertical Capture Start PS Vertical Capture Source Size PS Vertical Capture Destination Size PS Interlace Control PS Horizontal Scale Down Ratio PS Vertical Scale Down Ratio Address R/W Default Function
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AL310 Register Name SSDOWNHFILTER Position Detection POSDATATH POSHDESTART POSHDEEND POSVDESTART POSVDEEND Mode Detection CAPPSHTOTALCNT CAPPSVTOTALCNT CAPSSHTOTALCNT CAPSSVTOTALCNT PSDBUFFLAGNUML SSDBUFFLAGNUML DBUFFLAGNUMH TUNEPCCLK TUNEV1CLK TUNEV2CLK 63h & 62h 65h & 64h 67h & 66h 69h & 68h 70h 71h 72h 73h 74h 75h R R R R R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h PS Horizontal Total Counter PS Vertical Total Counter SS Horizontal Total Counter SS Vertical Total Counter PS Double Buffer Flag Number LSB SS Double Buffer Flag Number LSB PS & SS Double Buffer Flag Number MSB Tune Input PC Clock Timing Tune Input V1 Clock Timing Tune Input V2 Clock Timing 51h 5Bh & 5Ah 5Dh & 5Ch 5Fh & 5Eh 61h & 60h R/W R R R R 00h Data Threshold for Position Detection Horizontal Active Start Horizontal Active End Vertical Active Start Vertical Active End Address 4Fh R/W R/W Default 00h Function SS Scale Down Horizontal filter taps
Memory Control Group Registers(Accessible when reg.0Eh = 02h) DRAM Control DRAMACCESSCTRL DRAMWRITE FIFOCONTROL FIFOCONTROL DRAMMINREFRESH DRAMCTRL DRAMRADDR SKIPMODE DRAM Input Control DRAMPSISTART DRAMPSISTRIDE DRAMPSISIZE 33h 34h 35h R/W R/W R/W 10h 00h 00h PS DRAM Input Start PS DRAM Input Stride PS DRAM Input Size 20h 21h 22h 23h 28h 2Ah & 29h 2Dh ~ 2Bh 32h R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 10h DRAM Access control DRAM Write SS FIFO Control PS Input FIFO Control DRAM Minimum Refresh DRAM Control Register DRAM Read Address Skip Mode
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AL310 Register Name DRAMSSISTART DRAMSSISTRIDE DRAMSSISIZE DRAM Window Copy Control WCSRCSTART GSDRAMINPUTSTRIDE GSDRAMINPUTSIZE WCSTRIDE WCDESTSTART DASTART WCSIZE WCLINETOTAL DRAM Output Window Control DRAMPSOSTART DRAMPSOSTRIDE DRAMPSOSIZE DRAMSSOSTART DRAMSSOSTRIDE DRAMSSOSIZE VBISTART FRONTM TUNEMCLK TUNEPMCLK DRAM Data Port READSTATUS BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 60h 61h 62h 63h 64h 65h 66h R R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h Read Status Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 47h 48h 49h 4Ah 4Bh 4Ch 4Fh ~ 4Dh 50h 51h 52h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Tune Memory Write Clock Timing Tune Memory Read Clock Timing PS DRAM Output Start PS DRAM Output Stride PS DRAM Output Size SS DRAM Output Start SS DRAM Output Stride SS DRAM Output Size VBI Starting Address 3Bh ~ 39h 3Ch 3Dh 3Eh 41h ~ 3Fh 44h ~ 42h 45h 46h R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h Window Copy Source Start Window Copy Source Stride Window Copy HSize Direct Write Stride Window Copy Destination Start Direct Read/Write Address Window Copy Size Window Copy Line Total Address 36h 37h 38h R/W R/W R/W R/W Default 00h 00h 00h Function SS DRAM Input Start SS DRAM Input Stride SS DRAM Input Size
Display Control Group Registers (Accessible when reg.0Eh = 03h)
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AL310 Register Name Display Timing DISHTOTAL DISHSEND DISHDESTART DISHDEEND DISVTOTAL DISVSEND DISVDESTART DISVDEEND Window Output Timing DISPSHDESTART DISPSHDEEND DISPSVDESTART DISPSVDEEND DISSSHDESTART DISSSHDEEND DISSSVDESTART DISSSVDEEND Zoom In Control Registers DISPSHSRCSIZE DISPSHDESTSIZE DISPSVSRCSIZE DISPSVDESTSIZE PSZOOMFCTRL PSHUPRATIO DELTAHUPRATIO 41h & 40h 43h & 42h 45h & 44h 47h & 46h 48h 4Bh & 4Ah 4Bh & 4Ah R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h PS Horizontal Display Source Size PS Horizontal Display Destination Size PS Vertical Display Source Size PS Vertical Display Destination Size PS Zoom In Filter Control PS Horizontal Scale Up Ratio Delta PS Horizontal Scale Up Ratio Note: This definition is valid when DIS#CB<4> ='1' and used in Keystone PSVUPRATIO PSHPHASE PSVPHASE OUTPUTMODE 4Dh & 4Ch 4Fh & 4Eh 51h & 50h 54h R/W R/W R/W R/W 00h 00h 00h 00h PS Vertical Scale Up Ratio PS Horizontal Scale Up Initial Phase PS Vertical Scale Up Initial Phase Output Mode 31h & 30h 33h & 32h 35h & 34h 37h & 36h 39h & 38h 3Bh & 3Ah 3Dh & 3Ch 3Fh & 3Eh R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h PS Horizontal Display Start PS Horizontal Display End PS Vertical Display Start PS Vertical Display End SS Horizontal Display Start SS Horizontal Display End SS Vertical Display Start SS Vertical Display End 21h ~ 20h R/W 23h & 22h R/W 25h & 24h R/W 27h & 26h R/W 29h & 28h R/W 2Bh & 2Ah 2Dh & 2Ch 2Fh & 2Eh R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h Display Horizontal Total Display Horizontal Sync Horizontal Display Start Horizontal Display End Display Vertical Total Display Vertical Sync Vertical Display Start Vertical Display End Address R/W Default Function
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AL310 Register Name LUTINDEX LUTRED LUTGREEN LUTBLUE LUTCOLOR PATTERNGEN OSD Color Registers OSDRAMWADDR OSDRAMWDATA COLOR0RED COLOR0GREEN COLOR0RED COLOR1RED COLOR1GREEN COLOR1BLUE COLOR2RED COLOR2GREEN COLOR2BLUE COLOR3RED COLOR3GREEN COLOR3BLUE COLOR4RED COLOR0GREEN COLOR4BLUE COLOR5RED COLOR5GREEN COLOR5BLUE COLOR6RED COLOR6GREEN COLOR6BLUE COLOR7RED COLOR7GREEN 59h & 58h R/W 5Ah 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h OSD Write Address OSD Write Data Port Color 0 Red Color 0 Green Color 0 Blue Color 1 Red Color 1 Green Color 1 Blue Color 2 Red Color 2 Green Color 2 Blue Color 3 Red Color 3 Green Color 3 Blue Color 4 Red Color 4 Green Color 4 Blue Color 5 Red Color 5 Green Color 5 Blue Color 6 Red Color 6 Green Color 6 Blue Color 7 Red Color 7 Green Address 55h 5Ch 5Dh 5Eh 5Fh 56h R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h LUT Write Index LUT Red Color LSB LUT Green Color LSB LUT Blue Color LSB LUT Color MSB and Read/Write Trigger Pattern Generator and GPO Function
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AL310 Register Name COLOR7BLUE OSD Control Registers OSDCOLORSEL BLINKTIME OSDMODE FOREOP FOREOP FADEALPHA OSD1 Registers OSDCONTROL1 ROMSTARTADDR1 FONTADDRUNIT1 OSDHSTART1 OSDVSTART1 RAMADDRST1 RAMSTRIDE1 BMAPHSIZE1 BMAPHTOTAL1 BMAPVSIZE1 BMAPVTOTAL1 ICONHTOTAL1 ICONVTOTAL1 FONTLINESIZE1 OSD2 Registers OSDCONTROL2 ROMSTARTADDR2 FONTADDRUNIT2 OSDHSTART2 OSDVSTART1 RAMADDRST2 RAMSTRIDE2 BMAPHSIZE2 88h 89h 8Ah A0h A1h A2h 8Ch & A3h A5h & A4h R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h OSD2 Control OSD2 ROM Start Address OSD2 Font Address Unit OSD2 Horizontal Start OSD2 Vertical Start OSD2 RAM Start Address OSD2 RAM Horizontal Stride OSD2 Bitmap Horizontal Size 84h 85h 86h 90h 91h 92h 8Bh & 93h 95h & 94h 97h & 96h 99h & 98h 9Bh & 9Ah 9Ch 9Dh AEh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h OSD1 Control OSD1 ROM Start Address OSD1 Font Address Unit OSD1 Horizontal Start OSD1 Vertical Start OSD1 RAM Start Address OSD1 RAM Horizontal Stride OSD1 Bitmap Horizontal Size OSD1 Bitmap Horizontal Total Pixels OSD1 Bitmap Vertical Size OSD1 Bitmap Vertical total Lines OSD1 Icon Horizontal Total OSD1 Icon Vertical Total OSD1 Font Line Size 78h 79h 80h 81h 83h 82h R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h OSD Color Select OSD Blink Timer OSD Modes Logic Operation 1 Logic Operation 2 Fading Alpha Value Address 77h R/W R/W Default 00h Color 7 Blue Function
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AL310 Register Name BMAPHTOTAL2 BMAPVSIZE2 BMAPVTOTAL2L ICONHTOTAL2 ICONVTOTAL2 FONTLINESIZE2 Alpha Blending Registers MIXERCONFIG PSALPHA SSALPHA DESKR DESKG DESKB PSBACKR PSBACKG PSBACKB SSBACKR SSBACKG SSBACKB CHROMAR CHROMAG CHROMAB B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Mixer Configuration PS Alpha Value SS Alpha Value Desktop Color Component Red Desktop Color Component Green Desktop Color Component Blue PS Background Color Component Red PS Background Color Component Green PS Background Color Component Blue SS Background Color Component Red SS Background Color Component Green SS Background Color Component Blue Chroma Color Component Red Chroma Color Component Green Chroma Color Component Blue Address A7h & A6h A9h & A8h ABh & AAh ACh ADh AFh R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 00h 00h 00h 00h Function OSD2 Bitmap Horizontal Total Pixels OSD2 Bitmap Vertical Size OSD2 Bitmap Vertical Total Lines OSD2 Icon Horizontal Total OSD2 Icon Vertical Total OSD2 Font Line Size
Film Detection/ Motion Adaptive Registers MOTIONCNTTH LUMATH CHROMATH MCCTRL FILMCTRL PHASECTRL MVCNT Keystone Registers SHPKEYCTRL CBh R/W 00h Sharpness/Keystone Control Register C5h & C4h R/W C6h C7h C8h C9h CAh R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h Motion Counter Threshold Lumina(Y) Threshold Chroma(C) Threshold De-interlacing Control Register Film Detection Control Register Phase Detection Control Register Motion Pixel Numbers
CFh & CEh R/W
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AL310 Register Name MVCNTL MVCNTH Tri-Level Sync Registers TRISYNCA TRISYNCB TRISYNCD1 TRISYNCD2 TRISYNCBLANK TRISYNCLEVEL SS Border Registers SSLFSTART SSRTSTART SSTPSTART SSBTSTART SSBWIDTH SSBRED SSBGREEN SSBBULE Display Parameter Registers DISTUNEHS DISTUNESCLK DISTUNEDSCLK PHASECTRL DISHTOTAL DISVTOTAL PHASECNT COLORMANG BRIGHTNESS CONTRAST SATURATION C2h CCh CDh CAh D8h & D7h DAh & D9h DCh & DBh F0h F1h F2h F3h R/W R/W R/W R/W R R R R/W R/W R/W R/W 00h 80h 40h 40h Tune Display Horizontal Sync Phase Tune Display Pixel Clock Phase Tune Display Pixel Clock by 2 Phase Phase Detection Control Register Display Horizontal Total Display Vertical Total Phase Counter Enable Brightness/Contrast/Saturation Brightness Level Contrast Level Saturation Level E1h &E0h E3h &E2h E5h &E4h E7h &E6h E8h E9h EAh EBh W W W W W W W W SS Left Border Start SS Right Border Start SS Top Border Start SS Bottom Border Start SS Border Width SS Border Color Red SS Border Color Green SS Border Color Blue D0h D1h D2h D3h D4h D7h W W W W W W 00h 00h 00h 00h 00h 00h Tri-Level Sync Parameter Period a Tri-Level Sync Parameter Period b Tri-Level Sync Parameter Delta 1 Tri-Level Sync Parameter Delta 2 Tri-Level Sync Parameter Period Blank Tri-Level Sync Level Address C0h C1h R/W R/W R/W Default 00h 00h Function Keystone Parameters Address LSB Keystone Parameters Address MSB
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9.2 Register Description
Base Control Group Registers
INDEX (HEX) 00 Register Description Register Name BITS Function Description
Company ID (R) [COMPANYID] CompanyID <7:0> Company ID (46h)
02
Interrupt Mask (R/W) [INTRMASK] DVsyncIntMask <0> Display VSYNC interrupt mask 0 1 PSVsyncIntMask <1> 0 1 SSVsyncIntMask <2> 0 1 VBlMask <3> 0 1 FilmDetMask <4> 0 1 FullDetMask <5> 0 1 WCopyEndMask <6> Mask interrupt issued by VSYNC of display Interrupt issued when display VSYNC is activated Mask interrupt issued by VSYNC of PS Interrupt issued when VSYNC of PS is activated Mask interrupt issued by VSYNC of SS Interrupt issued when VSYNC of SS is activated Mask interrupt issued by display vertical blank Interrupt issued by display vertical blank Mask interrupt issued by film detection Interrupt issued when HW film detected Mask interrupt issued by FIFO full for directly write to SDRAM Interrupt issued by FIFO full for directly write to SDRAM Window copy finished interrupt mask 0 1 Mask interrupt issued by window copy Interrupt issued by window copy
Capture primary stream VSYNC interrupt mask
Capture secondary stream VSYNC interrupt mask
Display vertical blank interrupt mask
H/W Film detected finished interrupt mask
FIFO full for directly memory write Interrupt Mask
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AL310 FIFOFullMask <7> Arbiter FIFO full interrupt mask 0 1 03 Mask interrupt issued by FIFO index of arbiter Interrupt issued when FIFO is full
Interrupt Vector and Mode (R)(W) [INTRSTATUS] DVsyncInt (R) PSVsyncInt (R) SSVsyncInt (R) VBlInt (R) FilmDet (R) FullDet (R) WCopyEnd (R) FIFOFull (R) IntMode(W) <0> <1> <2> <3> <4> <5> <6> <7> <0> Display VSYNC interrupt Capture primary stream VSYNC interrupt Capture secondary stream VSYNC interrupt Display vertical blank interrupt H/W Film detected finished interrupt FIFO full for directly memory write interrupt Window copy finished interrupt Arbiter FIFO full interrupt 0 1 <1> 0 1 <7:2> Trigger mode Level mode High active Low active
Reserved
04~05: Reserved 06 Capture Data Control (R/W) [CAPCTRL] PSVScaleDn <0> Primary stream vertical scale down enable 0 1 SSVScaleDn <1> 0 1 PSMEM444En <2> 0 1 SSMEM444En <3> 0 1 Disable Enable Disable Enable 16-bit 4-2-2 format 24-bit 4-4-4 format 16-bit 4-2-2 format 24-bit 4-4-4 format
Secondary stream vertical scale down enable
Primary stream data format stored in frame buffer
Secondary stream data format stored in frame buffer
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AL310 Reserved SoGo DRAMBus <4> <5> <6> Tie to 0 Display timing strboe by PS capture VSYNC DRAM bus width 0 1 GO <7> 0 1 07 48-bit 32-bit Disable Enable
Capture timing enable
Display Data Control 1 (R/W) [DISCTRL1] PSDRAMByte <1:0> Primary stream data format stored in DRAM 00 01 10 11 Reserved PSCscEn <2> <3> Reserved 24-bit x 2, RGB888, YCbCr24 or YPbPr24 Reserved 16-bit x 2, RGB565, YCbCr16 or YPbPr16
Reserved Primary stream data color space conversion 0 1 Disable color space converter Enable color space converter Reserved 24-bit x 2, RGB888, YCbCr24 or YPbPr24 Reserved 16-bit x 2, RGB565, YCbCr16 or YPbPr16
SSDRAMByte
<5:4>
Secondary stream data format stored in DRAM 00 01 10 11
Reserved SSCscEn
<6> <7>
Reserved Secondary stream data color space conversion 0 1 Disable color space converter Enable color space converter
08
Display Data Control 2 (R/W) [DISCTRL2] PSUVFlip2Path <0> PS U/V flip in display data path 0 1 PSUVFlip2Mem <1> Disable Enable
PS U/V flipped in capture data path
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AL310 0 1 PSRGBEn <2> 0 1 PSYPbPrEn <3> 0 1 SSUVFlip2Path <4> 0 1 SSUVFlip2Mem <5> 0 1 SSRGBEn <6> 0 1 SSYPbPrEn <7> 0 1 09 Disable Enable YPbPr input RGB input YCbCr to RGB conversion YPbPr to RGB conversion Disable Enable Disable Enable YPbPr input RGB input YCbCr to RGB conversion YPbPr to RGB conversion
PS input data format, refer to BAS#16<4>
PS color space conversion, refer to BAS#07<3>
SS U/V flip in display path
SS U/V flipped in capture data path
SS input data format, refer to BAS#15<4>
SS color space conversion, refer to BAS#07<7>
Display Polarity Control (R/W) [POLARITYCTRL]
OClkSel
<0>
Output clock source selection as display clock, refer to BAS#09<7> 0 1 Select OXIN1 as display clock Select OXIN2 as display clock
ControlEn
<1>
Panel output data signals (clock, data, HSYNC, VSYNC and PDE) control enable 0 1 Disable output data signals to panel, all output data signals tie to low Enable panel output data signals Positive
HSyncPol
<2>
Output horizontal sync polarity 0
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AL310 1 BlankPol <3> 0 1 VSyncPol <4> 0 1 InvertOdd <5> 0 1 CSyncOut <6> 0 1 OPLLSel <7> 0 1 0A Negative Positive Negative Positive Negative Positive Negative Separate Composite From external pin (OXIN1/OXIN2) From PLL
Output horizontal blank polarity
Output vertical sync polarity
Invert odd field signal
Composite sync out
Display reference clock source, refer to BAS#09<0>
Display Timing Control (R/W) [OTIMECTRL] PSWinDisable <0> PS window diable 0 1 SSWinDisable <1> 0 1 SlaveMode <2> Enable Disable Enable Disable
SS window disable
Slave mode enable, refer to BAS#0A<3> 0 1 Output timing driven by internal registers Output timing driven by external device(capture or external display device)
SlaveType
<3>
Slave mode type, refer to BAS#0A<2> 0 1 Output timing is driven by capture timing Output timing is driven by external display device XOR AND
CSYNCType
<5:4>
Compsit SYNC type 00 01
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AL310 10 11 YPbPrAnalogOut <6> 0 1 YPbPrDigitalOut <7> 0 1 0E NXOR NAND RGB output YpbPr output RGB output YpbPr output
YPbPr analog output
YPbPr digital output
Group Access ID (R/W) [GROUPACCESS] GroupAccessID <1:0> Group register access control 00 01 10 11 Reserved <7:2> Access only Base control registers Access Capture and Base control registers Access Memory and Base control registers Access Display and Base control registers
Reserved
10
Board Configuration (R/W) [BOARDCFG] V1nConfig <1:0> Video1 data input pins configuration 00 01 10 11 Reserved <7:2> VIN pin 24 to pin 47 VIN pin 16 to pin 39 Reserved Reserved
Reserved
11
Input Video Source Format (R/W) [INSRCFORMAT] PCInFormat <1:0> Video 0 data input format 00 01 10 11 V1InFormat <3:2> 00 01 24-bit 16-bit 8-bit Reserved 24-bit 16-bit
Video 1 data input format
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AL310 10 11 V2InFormat <5:4> 00 01 10 11 TriPixPS TriPixSS 12 <6> <7> 8-bit Reserved 24-bit 16-bit 8-bit Reserved
Video 2 data input format
3 pixel per SDRAM cycle for PS 3 pixel per SDRAM cycle for SS
Input Control (R/W) [INPUTCTRL] Reserved HsPol <2:0> <3> Tie to "000" Enable HS polarity detection 0 1 VsPol <4> 0 1 Reserved <7:5> Disable, when turn on auto position function Enable Disable, when turn on auto position function Enable
Enable VS polarity detection
Reserved
13
Horizontal Reference Delay (R/W) [HREFDLY] PSHRefDly SSHRefDly <3:0> <7:4> Primary stream Capture HRef delay (Unit: psclk) Secondary stream Capture HRef delay (Unit: ssclk)
14
PS & SS control (R/W) [PSSSCTRL] PSHScaleDn Reserved PS656SyncSel <0> <1> <2> Enable primary stream scale down Reserved Primary stream SYNC source when ITU656 input 0 1 PSSoftRef <3> 0 1 SSHScaleDn <4> From external SYNC input pin From decoded ITU656 data From external HREF input pin Software programmable
Primary stream HREF source
Enable secondary stream scale down
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AL310 Reserved SS656SyncSel <5> <6> Reserved Secondary stream SYNC source when ITU656 input 0 1 SSSoftRef <7> 0 1 15 SS Input control (R/W) [SSCTRL] SSSrcSel <1:0> Select secondary stream input source / Position detection source 00 01 10 11 SSInvOddField Reserved SS444En <2> <3> <4> Video 0 (PC) Video 1 (V1) Video 2 (V2) Reserved From external SYNC input pin From decoded ITU656 data From external HREF input pin Software programmable
Secondary stream HREF source
Invert internal detected secondary stream odd field signal Reserved Input secondary stream data format, refer to BAS#08<4> 0 1 RGB/YPbPr input format YCbCr input format
SS656En SSDEdgeEn Reserved 16
<5> <6> <7>
Enable input secondary stream source is ITU656 format Double edge sampling for ITU656 input Reserved
PS Input control (R/W) [PSCTRL] PSSrcSel <1:0> Select primary stream input source 00 01 10 11 PSInvOddField Reserved PS444En <2> <3> <4> Video 0 (PC) Video 1 (V1) Video 2 (V2) Reserved, tie SYNC and clock signals to 0
Invert internal detected primary stream odd field signal Reserved Input primary stream data format, refer to BAS#08<2> 0 RGB/YPbPr input format
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AL310 1 PS656En PSDEdgeEn Reserved 17 <5> <6> <7> YCbCr input format
Enable input primary stream source is ITU656 format Double edge sampling for PS ITU656 input Reserved
Memory Access Control Register(R/W) [MEMACCR] MemWEn MemREn HostMode <0> <1> <2> Directly write enable Directly read enable Host data mode 0 1 HostBus <3> 0 1 PSOEn SSOEn WCopyEn <4> <5> <6> 2x16-bit per each host cycle 1x24-bit per each host cycle 32-bit Bus 8-bit Bus
Host data bus width, refer to MEM#61~66 port
Data output of directly memory via PS path Data output of directly memory via SS path Window copy enable 0 1 Disable window copy Enable window copy Memory clock from external PIN (XIN) Memory clock from internal PLL
MclkSel
<7>
Memory clock select 0 1
18
Inverted MSB of PS & SS (R/W) [INVMSB] InvPSBit7 InvPSBit15 InvPSBit23 Reserved InvSSBit7 InvSSBit15 InvSSBit23 Reserved <0> <1> <2> <3> <4> <5> <6> <7> Inverted bit 7 of PS input data Inverted bit 15 of PS input data Inverted bit 23 of PS input data Reserved Inverted bit 7 of SS input data Inverted bit 15 of SS input data Inverted bit 23 of SS input data Reserved
Note: Please refer to General Application Note
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AL310 PLL Registers 1B PLL Setting Register for Memory and Display(R/W) [PLLSETR] OPLLPd <0> Power Down for Display PLL 0 1 OPLLVon <1> 0 1 OPLLBp <2> 0 1 OPLLOe <3> 0 1 MPLLPd <4> 0 1 MPLLVon <5> 0 1 MPLLBp <6> 0 1 MPLLOe <7> 0 1 PLL normal Operation PLL Power Down PLL normal Operation Reset the PLL NF & NR Divider PLL normal Operation Bypass the PLL & FOUT=FIN FOUT= Fck/NO FOUT=0 PLL normal Operation PLL Power Down PLL normal Operation Reset the PLL NF & NR Divider PLL normal Operation Bypass the PLL & FOUT=FIN FOUT= Fck/NO FOUT=0
Reset for Display PLL
Bypass Mode for Display PLL
Output Control for Display PLL
Power Down for Memory PLL
Reset for Memory PLL
Bypass Mode for Memory PLL
Output control for memory PLL
Note: FOUT = FIN * NF/(NR*NO) = FVCO/NO, here FVCO is between 80MHz and 190Mhz Here, FIN is input clock (example:14.31818MHz XTAL) NF/NR, and NO are refer to BAS#1C~1F definition 1C LSB of NF Value for Memory PLL(R/W) [MPLLNF] MPLLNF <7:0> MPLLNF<7:0> Value for memory PLL
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AL310 Note: NF is MPLLNF+2 1D MSB of NF/NR/NO Value for Memory PLL(R/W) [MPLLNRO] MPLLNR MPLLNO MPLLNF <4:0> <6:5> <7> MPLLNR<4:0> value for memory PLL MPLLNO<1:0> value for memory PLL MPLLNF<8> Value for memory PLL
Note: NR is MPLLNR+2, NO is MPLLNO+1 1E LSB of NF Value for Display PLL(R/W) [OPLLNF] OPLLNF Note: NF is OPLLNF+2 1F MSB of NF/NR/NO Value for Display PLL(R/W) [OPLLNRO] OPLLNR OPLLNO OPLLNF <4:0> <6:5> <7> OPLLNR<4:0> value for display PLL OPLLNO<1:0> value for display PLL OPLLNF<8> Value for display PLL <7:0> OPLLNF<7:0> Value for display PLL
Note: NR is OPLLNR+2, NO is OPLLNO+1
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Capture Control Group Registers (Accessible when BAS#0E = 01h)
I. PS timing
INDEX (HEX) 20
Register Description Register Name BITS Function Description
PS Horizontal Capture Start LSB (R/W) [CAPPSHSTART] CapPSHStartL <7:0> Bits<7:0> of PS horizontal capture start position (Unit: 1 pixel)
21
PS Horizontal Capture Start MSB (R/W) [CAPPSHSTART] CapPSHStartH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal capture start position Reserved
22
PS Horizontal Capture Source Size LSB (R/W) [CAPPSHSRCSIZE] CapPSHSrcSizeL <7:0> Bits<7:0> of PS horizontal capture source size (Unit: 1 pixel)
23
PS Horizontal Capture Source Size MSB (R/W) [CAPPSHSRCSIZE] CapPSHSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal capture source size Reserved
24
PS Horizontal Capture Destination Size LSB (R/W) [CAPPSHDESTSIZE] CapPSHDestSizeL <7:0> Bits<7:0> of PS horizontal capture destination size (Unit: 1 pixel)
25
PS Horizontal Capture Destination Size MSB (R/W) [CAPPSHDESTSIZE] CapPSHDestSizeH <3:0> Reserved <7:4> Bits<11:8> of PS horizontal capture destination size Reserved
Note: CAPPSHSRCSIZE >= CAPPSHDESTSIZE 26 PS Vertical Capture Start (R/W) [CAPPSVSTART]
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AL310 CapPSVStartL <7:0> Bits<7:0> of PS vertical capture start position (Unit: 1 line) 27 PS Vertical Capture Start (R/W) [CAPPSVSTART] CapPSVStartH Reserved 28 <2:0> <7:4> Bits<10:8> of PS vertical capture start position Reserved
PS Vertical Capture Source Size LSB (R/W) [CAPPSVSRCSIZE] CapPSVSrcSizeL <7:0> Bits<7:0> of PS vertical capture source size (Unit: 1 line)
29
PS Vertical Capture Source Size MSB (R/W) [CAPPSVSRCSIZE] CapPSVSrcSizeH Reserved <2:0> <7:4> Bits<10:8> of PS vertical capture source size Reserved
2A
PS Vertical Capture Destination Size LSB (R/W) [CAPPSVDESTSIZE] CapVDestSizeL <7:0> Bits<7:0> of PS vertical capture destination size (Unit: 1 line).
2B
PS Vertical Capture Destination Size MSB (R/W) [CAPPSVDESTSIZE] CapPSVDestSizeH <2:0> Reserved <7:4> Bits<10:8> of PS vertical capture destination size Reserved
2E
PS Interlace Control (R/W) [PSINTERLACECTR] PSInterlaceEn PSFieldCap <0> <2:1> Enable PS interlace timing input PS field capture into memory 00 01 10 11 PSFieldoffset <7:4> Capture even and odd field into memory Capture odd field only Capture even field only Reserved
PS field capture offset
30
PS Horizontal Scale Down Ratio LSB (R/W) [PSHDNRATIO] PSHDnRatioL <7:0> Bits<7:0> of PS horizontal scale down ratio
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AL310 31 PS Horizontal Scale Down Ratio MSB (R/W) [PSHDNRATIO] PSHDnRatioH Reserved <0> <7:1> Bit<8> of PS horizontal scale down ratio Reserved
Note: PSHDNRATIO = CAPPSHDESTSIZE / CAPPSHSRCSIZE * 256 32 PS Vertical Scale Down Ratio LSB (R/W) [PSVDNRATIO] PSVDnRatioL 33 <7:0> Bits<7:0> of PS vertical scale down ratio
PS Vertical Scale Down Ratio MSB (R/W) [PSVDNRATIO] PSVDnRatioH Reserved <0> <7:1> Bit<8> of PS vertical scale down ratio Reserved
Note: PSVDNRATIO = CAPPSVDESTSIZE / CAPPSVSRCSIZE * 256
II. VBI Input timing: VBI captured data is always been stored in DRAM address, starting at 0. To Disable VBI capture, set VBIVStart > VBIVEnd, and VBIHStart > VBIHEnd 34 VBI Vertical Start (R/W) [VBIVSTART] VBIVStart 35 <7:0> VBI vertical capture start position
VBI Vertical End (R/W) [VBIVEND] VBIVend <7:0> VBI vertical capture end
36
VBI Horizontal Start (R/W) [VBIHSTART] VBIHStart <7:0> VBI horizontal capture start position
37
VBI Horizontal Size (R/W) [VBIVSIZE] VBIHSize <7:0> VBI horizontal capture size
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AL310 III. ITU-656 Detection:
38
PS ITU-656 Hsync Start (R/W) [PS656HSTART] PS656HStart <7:0> Primary stream ITU656data horizontal sync start position default value 20h
39
PS ITU-656 Hsync End (R/W) [PS656HEND] PS656HEnd <7:0> ITU656data horizontal sync end position default value a0h
3A
PS ITU-656 Vsync Start (R/W) [PS656VSTART] PS656VStart <7:0> ITU656data vertical sync start position default value 02h
3B
PS ITU-656 Vsync End (R/W) [PS656VEND] PS656VEnd <7:0> ITU656data vertical sync end position default value 04h
3C
SS ITU-656 Hsync Start (R/W) [SS656HSTART] SS656HStart <7:0> ITU656data horizontal sync start position default value 20h
3D
SS ITU-656 Hsync End (R/W) [SS656HEND] SS656HEnd <7:0> ITU656data horizontal sync end position default value a0h
3E
SS ITU-656 Vsync Start (R/W) [SS656VSTART] SS656VStart <7:0> ITU656data vertical sync start position default value 02h
3F
SS ITU-656 Vsync End (R/W) [SS656VEND] SS656VEnd <7:0> ITU656data vertical sync end position default value 04h
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IV. SS Input timing:
40
SS Horizontal Capture Start LSB (R/W) [CAPSSHSTART] CapSSHStartL <7:0> Bits<7:0> of SS horizontal capture start position (Unit: 1 pixel)
41
SS Horizontal Capture Start MSB (R/W) [CAPSSHSTART] CapSSHStartH Reserved <3:0> <7:4> Bits<11:8> of SS horizontal capture start position Reserved
42
SS Horizontal Capture Source Size LSB (R/W) [CAPSSHSRCSIZE] CapSSHSrcSizeL <7:0> Bits<7:0> of SS horizontal capture source size (Unit: 1 pixel)
43
SS Horizontal Capture Source Size MSB (R/W) [CAPSSHSRCSIZE] CapSSHSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of SS horizontal capture source size Reserved
44
SS Horizontal Capture Destination Size LSB (R/W) [CAPSSHDESTSIZE] CapSSHDestSizeL <7:0> Bits<7:0> of SS horizontal capture destination size (Unit: 1 pixel).
45
SS Horizontal Capture Destination Size MSB (R/W) [CAPSSHDESTSIZE] CapSSHDestSizeH <3:0> Reserved <7:4> Bits<11:8> of SS horizontal capture destination size Reserved
Note: CAPSSHSRCSIZE >= CAPSSHDESTSIZE 46 SS Vertical Capture Start LSB (R/W) [CAPSSVSTART] CapSSVStartL 47 <7:0> Bits<7:0> of SS vertical capture start position (Unit:1 line)
SS Vertical Capture Start MSB (R/W) [CAPSSVSTART] CapSSVStartH <2:0> Bits<10:8> of SS vertical capture start position
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AL310 Reserved 48 <7:3> Reserved
SS Vertical Capture Source Size LSB (R/W) [CAPSSVSRCSIZE] CapSSVSrcSizeL <7:0> Bits<7:0> of SS vertical capture source size (Unit:1 line)
49
SS Vertical Capture Source Size MSB (R/W) [CAPSSVSRCSIZE] CapSSVSrcSizeH Reserved <2:0> <7:3> Bits<10:8> of SS vertical capture source size Reserved
4A
SS Vertical Capture Destination Size LSB (R/W) [CAPSSVDESTSIZE] CapSSVDestSizeL <7:0> Bits<7:0> of SS vertical capture destination size (Unit:1 line).
4B
SS Vertical Capture Destination Size MSB (R/W) [CAPSSVDESTSIZE] CapSSVDestSizeH <2:0> Reserved <7:3> Bits<10:8> of SS vertical capture destination size Reserved
Note: CASSVSRCSIZE >= CAPSSVDESTSIZE 4E SS Interlace Control (R/W) [SSINTERLACECTRL] SSInterlaceEn SSFieldCap <0> <2:1> Enable SS interlace timing input SS field capture 00 01 10 11 SSFieldoffset 4F <7:4> Reserved Capture odd field only Capture even field only Reserved
SS field capture offset
SS Scale Down Horizontal Filter Taps (R/W) [SSDOWNHFILTER] SSHFltTaps <2:0> Secondary stream horizontal scale down filter taps 000 001 010 011 no filter 2-tap filter 4-tap filter 8-tap filter
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AL310 Reserved IV: Position Detection: 51 Data Threshold for Position Detection (R/W) [POSDATATH] PosDataTh <7:0> Luma(brightness) threshold value <7:3> Reserved
Note: CAP#51 is used to determine PS/SS non-blanking pixel for both horizontal and vertical direction. Any pixel luma value less than this value will be considered as blanking. 5A Horizontal Active Start LSB (R) [POSHDESTART] PosHDEStartL <7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel) 5B Horizontal Active Start MSB (R) [POSHDESTART] PosHDEStartH Reserved 5C <2:0> <7:3> Bits<10:8> of detected horizontal active start position Reserved
Horizontal Active End LSB (R) [POSHDEEND] PosHDEEndL <7:0> Bits<7:0> of detected horizontal active start position (Unit: 1 pixel)
5D
Horizontal Active End MSB (R) [POSHDEEND] PosHDEEndH Reserved <2:0> <7:3> Bits<10:8> of detected horizontal active end position Reserved
5E
Vertical Active Start LSB (R) [POSVDESTART] PosVDEStartL <7:0> Bits<7:0> of detected vertical active start line (Unit: 1 line)
5F
Vertical Active Start MSB (R) [POSVDESTART] PosVDEStartH Reserved <2:0> <7:3> Bits<10:8> of detected vertical active start line Reserved
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AL310 60 Vertical Active End LSB (R) [POSVDEEND] PosVDEEndL <7:0> Bits <7:0> of detected vertical active end line (Unit: 1 line) 61 Vertical Active End MSB (R) [POSVDEEND] PosVDEEndH Reserved <2:0> <7:3> Bits<10:8> of detected vertical active end line Reserved
V: Mode Detection: 62 PS Horizontal Capture Total Counter LSB (R) [CAPPSHTOTALCNT] CapPSHtotalCntL 63 <7:0> Bits<7:0> of PS horizontal total count value
PS Horizontal Capture Total Counter MSB (R) [CAPPSHTOTALCNT] CapPSHtotalCntH Reserved <2:0> <7:3> Bits<10:8> of PS horizontal total count value Reserved
64
PS Vertical Capture Total Counter LSB (R) [CAPPSVTOTALCNT] CapPSVtotalCntL <7:0> Bits<7:0> of PS vertical total count value
65
PS Vertical Capture Total Counter MSB (R) [CAPPSVTOTALCNT] CapPSVtotalCntH Reserved <2:0> <7:3> Bits<10:8> of PS vertical total count value Reserved
66
SS Horizontal Capture Total Counter LSB (R) [CAPSSHTOTALCNT] CapSSHtotalCntL <7:0> Bits<7:0> of SS horizontal total count value
67
SS Horizontal Capture Total Counter MSB (R) [CAPSSHTOTALCNT] CapSSHtotalCntH Reserved <2:0> <7:3> Bits<10:8> of SS horizontal total count value Reserved
68
SS Vertical Capture Total Counter LSB (R) [CAPSSVTOTALCNT] CapSSVtotalCntL <7:0> Bits<7:0> of SS vertical total count value
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SS Vertical Capture Total Counter MSB (R) [CAPSSVTOTALCNT] CapSSVtotalCntH Reserved <2:0> <7:3> Bits<10:8> of SS vertical total count value Reserved
70
PS Double Buffer Flag LSB (R/W) [PSDBUFFLAGNUM] PSDbufFlagNumL <7:0> Bits<7:0> of PS double buffer flag number
71
SS Double Buffer Flag LSB (R/W) [SSDBUFFLAGNUM] SSDbufFlagNumL <7:0> Bits<7:0> of SS double buffer flag number
72
PS & SS Double Buffer Flag MSB (R/W) [DBUFFLAGNUM] PSDbufFlagNumH SSDbufFlagNumH Reserved <2:0> <6:4> Bits<10:8> of PS double buffer flag number Bits<10:8> of SS double buffer flag number
<7><3> Reserved
73
Tune Input PC Clock Phase (R/W) [TUNEPCCLK] TunePCclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> PCclk PCclk + delay phase Inversed PCclk Inversed PCclk + delay phase
Reserved
74
Tune Input V1 Clock Phase (R/W) [TUNEV1CLK] TuneV1clk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> V1clk V1clk + delay phase Inversed V1clk Inversed V1clk + delay phase
Reserved
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AL310 75 Tune Input V2 Clock Phase (R/W) [TUNEV2CLK] TuneV2clk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> V2clk V2clk + delay phase Inversed V2clk Inversed V2clk + delay phase
Reserved
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Memory Control Group Registers (Accessible when BAS#0E = 02h)
I.DRAM control
INDEX (HEX) 20
Register Description Register Name BITS Function Description
DRAM Access control (R/W) [DRAMACCESSCTRL] PSInputEnable SSInputEnable PowerUp PSOutputEnable SSOutputEnable RefreshEnable PowerDown SetMode <0> <1> <2> <3> <4> <5> <6> <7> Enable PS input Enable SS input Enable power up Enable PS output Enable SS output Enable DRAM refresh Enable power down Enable DRAM setmode cycle
21
DRAM Write (R/W) [DRAMWRITE] PMCLKSel <0> Select DRAM read clock signal path 0 1 WriteMask1 WriteMask2 SoftRest DataDelay DataRdyDelay <1> <2> <3> <5:4> <7:6> Internal loop External loop from pad MCLK to PMCLK
Write mask of DRAM byte 0, 1 Write mask of DRAM byte 2 Software Reset DRAM data delay DRAM data ready delay
22
Output FIFO & SS Input FIFO Control (R/W) [FIFOCONTROL] OutputLevel SSInputLevel <3:0> <7:4> Stream output(PS and SS) FIFO level control SS input FIFO level control
23
PS Input FIFO Control (R/W) [FIFOCONTROL] PSInputLevel Reserved <3:0> <7:4> PS input FIFO level control Reserved
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Note: These are DRAM FIFO water mark, when FIFO reach this urgent level, the corresponding video source needs to be serviced(R/W or to/from DRAM) 24~27: Reserved 28 DRAM Minimum Refresh (R/W) [DRAMMINREFRESH] MinRefresh <7:0> Minimum refresh requirement within the period of a output VSYNC, usually 1/60 sec 29 DRAM Control 0 (R/W) [DRAMCTRL] TRAS <1:0> DRAM RAS control signal 00 01 01 11 TRC <4:2> 000 001 001 011 100 101 101 111 TRCD <5> 0 1 TRP <6> 0 1 TRPD <7> 0 1 5 memory clocks 6 memory clocks 7 memory clocks 8 memory clocks 7 memory clocks 8 memory clocks 9 memory clocks 10 memory clocks 11 memory clocks 12 memory clocks 13 memory clocks 14 memory clocks No delay Delay 1 memory clock No delay Delay 1 memory clock No delay Delay 1 memory clock
DRAM RC control signal
DRAM RCD control signals
DRAM RP control signal
DRAM RPD control signal
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2A
DRAM Control 1 (R/W) [DRAMCTRL] TWR <0> DRAM WR control signal 0 1 TCL <1> 0 1 TRW <2> 0 1 MemConfig <4:3> 00 01 10 11 BankConfig <5> 0 1 Reserved TXSR <6> <7> Tie to 1 DRAM XSR control signal No delay Delay 1 memory clock No delay Delay 1 memory clock No delay Delay 1 memory clock 16Mb 64Mb Reserved Reserved A22, 0-4M = bank 0, 4-8M = bank 1 A21, 4-6M = bank 0, 6-8M = bank 1
DRAM CL control signal
DRAM RW control signal
SDRAM Size
Bank selector
Note: MEM#29&2A is SDRAM timing parameters. Default value: MEM#29=ef, MEM#2A=4f 2B DRAM Read Address 0 (R/W) [DRAMRADDR] MemReadAddr0 2C <7:0> Bits<7:0> of DRAM read address. (unit: 2 pixels)
DRAM Read Address 1 (R/W) [DRAMRADDR] MemReadAddr1 <7:0> Bits<15:8> of DRAM read address
2D
DRAM Read Address 2 (R/W) [DRAMRADDR] MemReadAddr2 Reserved <4:0> <7:5> Bits<20:16> of DRAM read address Reserved
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AL310 30 XY Mirror Input (R/W) [XYMIRRORIN] PSInputFlipX PSInputFlipY SSInputFlipX SSInputFlipY GSInputFlipX GSInputFlipY WCInputFlipX WCInputFlipY <0> <1> <2> <3> <4> <5> <6> <7> Enable PS X mirror capture(horizontally captured in the reversed direction) Enable PS Y mirror capture(vertically captured in the reversed direction, i.e. up side down capture) Enable SS X mirror capture(horizontally captured in the reversed direction) Enable SS Y mirror capture(vertically captured in the reversed direction, i.e. up side down capture) Enable GS X mirror write(horizontally written in the reversed direction) Enable GS Y mirror capture(vertically written in the reversed direction, i.e. up side down written) Enable Window Copy X mirror copy-in (horizontally copyin in the reversed direction) Enable Window Copy Y mirror copy-in(vertically copy-in in the reversed direction, i.e. up side down copy-in) 31 XY Mirror Output (R/W) [XYMIRROROUT] PSOutputFlipX PSOutputFlipY SSOutputFlipX SSOutputFlipY WCOutputFlipX WCOutputFlipY Reserved 32 <0> <1> <2> <3> <4> <5> <7:6> Enable PS X mirror display(horizontally display in the reversed direction) Enable PS Y mirror display (vertically displayed in the reversed direction, i.e. up side down display) Enable SS X mirror display (horizontally displayed in the reversed direction) Enable SS Y mirror display (vertically displayed in the reversed direction, i.e. up side down display) Enable Window Copy X mirror copy-out (horizontally copy- out in the reversed direction) Enable Window Copy Y mirror copy- out (vertically copyout in the reversed direction, i.e. up side down copy- out) Reserved
Skip Mode (R/W) [SKIPMODE]
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AL310 PSInputSkip <1:0> PS DRAM input address pointer incremental unit 00 2 fields/1 frame stockpile even1, odd1, even1, odd1 ...., Note: Stride >= size 01 10 Reserved 4 fields/2frames stockpile F1(1),F2(1),F3(1),F4(1),F1(2),F2(2),F3(2)... Note: Stride >= size * 4 11 Reserved PSITwoField SSITwoField MemControlEn PSDbufferEn SSDbufferEn <2> <3> <4> <5> <6> <7> Reserved Reserved PSI two field mode SSI two field mode 0 1 Disable sdram controller Enable sdram controller
PS dobule buffering enable SS dobule buffering enable
II. DRAM input window control 33 PS DRAM Input Start (R/W) [DRAMPSISTART] DRAMPSIStart 34 <7:0> PS input DRAM address start (Unit: 8192 pixels)
PS DRAM Input Horizontal Stride (R/W) [DRAMPSIHSTRIDE] DRAMPSIHStride <7:0> PS input DRAM horizontal stride (Unit: 4/8/12 pixels)
Note: Set stride value at 64/128/256 boundary, will better ease DRAM timing. 35 PS DRAM Input Horizontal Size (R/W) [DRAMPSIHSIZE] DRAMPSIHSize <7:0> PS input DRAM horizontal size (Unit: 4/8/12 pixels)
Note: PS DRAM Input Horizontal Size should same as PS Horizontal Destination Size DRAMPSIHSIZE = CAPPSHDESTSIZE(CAP#25&24) / K, K= 4 or 8 or 12
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AL310 36 SS DRAM Input Start (R/W) [DRAMSSISTART] DRAMSSIStart 37 <7:0> SS input DRAM address start (Unit: 8192 pixels)
SS DRAM Input Horizontal Stride (R/W) [DRAMSSIHSTRIDE] DRAMSSIHStride <7:0> SS input DRAM horizontal stride (Unit: 4/8/12 pixels)
38
SS DRAM Input Horizontal Size (R/W) [DRAMSSIHSIZE] DRAMSSIHSize <7:0> SS input DRAM horizontal size (Unit: 4/8/16 pixels)
Note: SS DRAM Input Horizontal Size should same as SS Horizontal Destination Size DRAMSSIHSIZE = CAPSSHDESTSIZE(CAP#45&44) / K, III. DRAM window copy control 39 Window Copy Source Start LSB (R/W) [WCSRCSTART] GSInputStart1 <7:0> Bits<7:0> of GS input DRAM address start. (Unit: 8192 pixels) 3A Window Copy Source Start (R/W) [WCSRCSTART] GSInputStart2 3B <7:0> Bits<15:8> of GS input DRAM address start K= 4 or 8 or 12
Window Copy Source Start MSB (R/W) [WCSRCSTART] GSInputStart3 Reserved <3:0> <7:4> Bits<18:16> of GS input DRAM address start Reserved
3C
Window Copy Source Stride (R/W) [GSDRAMINPUTSTRIDE] GSIStride <7:0> GS input DRAM stride. (8 pixels)
3D
Window Copy Size (R/W) [GSDRAMINPUTSIZE] GSHSize <7:0> GS input DRAM size. (Unit: 8 pixels)
3E
Direct Write Stride (R/W) [WCSTRIDE] WCStride <7:0> DRAM window copy stride. (Unit: 8 pixels)
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AL310 3F Window Copy Destination Start LSB (R/W) [WCDESTSTART] WCSrcStart1 <7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8 pixels) 40 Window Copy Destination Start (R/W) [WCDESTSTART] WCDestStart2 41 <7:0> Bits<15:8> of DRAM window copy source address start
Window Copy Destination Start MSB (R/W) [WCDESTSTART] WCDestStart3 Reserved <3:0> <7:4> Bits<20:16> of DRAM window copy source address start Reserved
Note: After writing to MEM#41, the Window Copy operation will be carried out. 42 Direct Read/Write Address LSB (R/W) [DASTART] DAddrStart1 <7:0> Bits<7:0> of DRAM window copy source address start. (Unit: 8 pixels) 43 Direct Read/Write Address (R/W) [DASTART] DAddrStart2 44 <7:0> Bits<15:8> of DRAM window copy source address start
Direct Read/Write Address MSB (R/W) [DASTART] DAddrStart3 Reserved <3:0> <7:4> Bits<20:16> of DRAM window copy source address start Reserved
45
Window Copy Size (R/W) [WCSIZE] WCSize <7:0> DRAM Directly Write size. (Unit: 8 pixels) or DRAM window copy total lines [7:0] for Window Copy.
46
Window Copy Line Total (R/W) [WCLINETOTAL] WCLineTotal <7:0> DRAM window copy total lines[2:0]. (1 line)
IV. DRAM output window control
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AL310 47 PS DRAM Output Start (R/W) [DRAMPSOSTART] DRAMPSOStart 48 <7:0> PS output DRAM address start. (Unit: 8192 pixels)
PS DRAM Output Horizontal Stride (R/W) [DRAMPSOHSTRIDE] DRAMPSOHStride <7:0> PS output DRAM horizontal stride. (Unit: 4/8/12 pixels)
49
PS DRAM Output Horizontal Size (R/W) [DRAMPSOHSIZE] DRAMPSOHSize <7:0> PS output DRAM horizontal size. (Unit: 4/8/12 pixels)
Note: PS DRAM Output Horizontal Size should same as PS Horizontal Display Source Size DRAMPSOHSIZE = DISPSHSRCSIZE(DIS#41&40) / K, 4A SS DRAM Output Start (R/W) [DRAMSSOSTART] DRAMSSOStart 4B <7:0> SS output DRAM address start. (Unit: 8192 pixels) K= 4 or 8 or 12
SS DRAM Output Horizontal Stride (R/W) [DRAMSSOHSTRIDE] DRAMSSOHStride <7:0> SS output DRAM horizontal stride. (4/8/12 pixels)
4C
SS DRAM Output Horizontal Size (R/W) [DRAMSSOHSIZE] DRAMSSOHSize <7:0> SS output DRAM horizontal size. (4/8/12 pixels)
Note: SS DRAM Output Horizontal Size should same as SS Horizontal Display Size DRAMSSOHSIZE = [DISSSHDEEND(DIS#3B&3A) - DISSSHDESTART(DIS#39&38)] / K, K= 4 or 8 or 12 4D VBI Start Address LSB (R/W) [VBISTART] VBIAddrStart1 4E <7:0> Bit<7:0> of VBI starting address.
VBI Start Address (R/W) [VBISTART] VBIAddrStart2 <7:0> Bit<15:8> of VBI starting address.
4F
VBI Start Address MSB (R/W) [VBISTART] VBIAddrStart3 Reserved <3:0> <7:4> Bit<19:16> of VBI starting address. Reserved
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50
Front Motion Detect Control (R/W) [FRONTM] FrontMYth EnFrontM <6:0> <7> Y threshold Value for Front Motion Enable Front Motion Detection
51
Tune Memory Write Clock Phase (R/W) [TUNEMCLK] TuneMclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> Mclk Mclk + delay phase Inversed Mclk Inversed Mclk + delay phase
Reserved
52
Tune Memory Read Clock Phase (R/W) [TUNEPMCLK] TunePMclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> PMclk PMclk + delay phase Inversed PMclk Inversed PMclk + delay phase
Reserved
V. DRAM data port 60 Read Status (R) [READSTATUS] Status Reserved 61 <0> <7:1> Data Ready Reserved
Byte 0 (R)(W) [BYTE0] RByte0(R) WByte0(W) <7:0> <7:0> Bits<7:0> of DRAM for read-out Bits<7:0> of Pixel 0 for 16-bit mode Write, or Dummy field for 24-bit mode Write
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62
Byte 1 (R)(W) [BYTE1] RByte1(R) WByte1(W) <7:0> <7:0> Bits<15:8> of DRAM read-out Bits<15:8> of Pixel 0 for 16-bit mode Write, or Blue field for 24-bit mode Write
63
Byte 2 (R)(W) [BYTE2] RByte2(R) WByte2(W) <7:0> <7:0> Bits<23:16> of DRAM read-out Bits<7:0> of Pixel 1 for 16-bit mode Write, or Green field for 24-bit mode Write
64
Byte 3 (R)(W) [BYTE3] RByte3(R) WByte3(W) <7:0> <7:0> Bits<31:24> of DRAM read-out <15:8> of Pixel 1 for 16-bit mode Write, or Red field for 24-bit mode Write
65
Byte 4 (R) [BYTE4] RByte4 <7:0> Bits<39:32> of DRAM read-out
66
Byte5 (R) [BYTE5] RByte4 <7:0> Bits<47:40> of DRAM read-out
DRAM data read ports are defined in MEM#61~66. MemReadAddr is defined in MEM#42~44. After reading MEM#60, the read cycle will be strobe if bit-0 is 0. MEM#60 should be read until bit 0 is 1. Then, read MEM#61~66 for the data read from SDRAM.
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Display Control Group Registers (Accessible when BAS#0E = 03h)
I. Display Timing
INDEX (HEX) 20
Register Description Register Name BITS Function Description
Display Horizontal Total LSB (R/W) [DISHTOTAL] DisHTotalL <7:0> Bits<7:0> of display horizontal total (Unit: 1 pixel)
21
Display Horizontal Total MSB (R/W) [DISHTOTAL] DisHTotalH Reserved <3:0> <7:4> Bits<11:8> of display horizontal total Reserved
22
Display Horizontal Sync LSB (R/W) [DISHSEND] DisHSEndL <7:0> Bits<7:0> of display horizontal sync end (Unit: 1 pixel)
23
Display Horizontal Sync MSB (R/W) [DISHSEND] DisHSEndH Reserved <3:0> <7:4> Bits<11:8> of display horizontal sync end Reserved
Note: Horizontal sync start at position 1. 24 Horizontal Display Start LSB (R/W) [DISHDESTART] DisHDEStartL 25 <7:0> Bits<7:0> of horizontal display start (Unit: 1 pixel)
Horizontal Display Start MSB (R/W) [DISHDESTART] DisHDEStartH Reserved <3:0> <7:4> Bits<11:8> of horizontal display start Reserved
26
Horizontal Display End LSB (R/W) [DISHDEEND] DisHDEEndL <7:0> Bits<7:0> of horizontal display end (Unit: 1 pixel)
27
Horizontal Display End MSB (R/W) [DISHDEEND]
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AL310 DisHDEEndH Reserved 28 <3:0> <7:4> Bits<11:8> of horizontal display end Reserved
Display Vertical Total LSB (R/W) [DISVTOTAL] DisVTotalL <7:0> Bits<7:0> of display vertical total (Unit: 1 pixel)
29
Display Vertical Total MSB (R/W) [DISVTOTAL] DisVTotalH Reserved <3:0> <7:4> Bits <11:8> of display vertical total Reserved
2A
Display Vertical Sync LSB (R/W) [DISVSEND] DisVSEndL <7:0> Bits<7:0> of display vertical sync end (Unit: 1 pixel)
2B
Display Vertical Sync MSB (R/W) [DISVSEND] DisVSEndH Reserved <3:0> <7:4> Bits<11:8> of display vertical sync end Reserved
Note: Vertical sync start at line 1. 2C Vertical Display Start LSB (R/W) [DISVDESTART] DisVDEStartL 2D <7:0> Bits<7:0> of vertical display start (Unit: 1 pixel)
Vertical Display Start MSB (R/W) [DISVDESTART] DisVDEStartH Reserved <3:0> <7:4> Bits<11:8> of vertical display start Reserved
2E
Vertical Display End LSB (R/W) [DISVDEEND] DisVDEEndL <7:0> Bits<7:0> of vertical display end(Unit: 1 pixel)
2F
Vertical Display End MSB (R/W) [DISVDEEND] DisVDEEndH Reserved <3:0> <7:4> Bits<11:8> of vertical display end Reserved
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30
PS Horizontal Display Start LSB (R/W) [DISPSHDESTART] DisPSHDEStartL <7:0> Bits<7:0> of PS horizontal display start (Unit: 1 pixel)
31
PS Horizontal Display Start MSB (R/W) [DISPSHDESTART] DisPSHDEStartH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal display start Reserved
32
PS Horizontal Display End LSB (R/W) [DISPSHDEEND] DisPSHDEEndL <7:0> Bits<7:0> of PS horizontal display end(Unit: 1 pixel)
33
PS Horizontal Display End MSB (R/W) [DISPSHDEEND] DisPSHDEEndH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal display end Reserved
34
PS Vertical Display Start LSB (R/W) [DISPSVDESTART] DisPSVDEStartL <7:0> Bits<7:0> of PS vertical display start (Unit: 1 pixel)
35
PS Vertical Display Start MSB (R/W) [DISPSVDESTART] DisPSVDEStartH Reserved <3:0> <7:4> Bits<11:8> of PS vertical display start Reserved
36
PS Vertical Display End LSB (R/W) [DISPSVDEEND] DisPSVDEEndL <7:0> Bits<7:0> of PS vertical display end(Unit: 1 pixel)
37
PS Vertical Display End MSB (R/W) [DISPSVDEEND] DisPSVDEEndH Reserved <3:0> <7:4> Bits<11:8> of PS vertical display end Reserved
38
SS Horizontal Display Start LSB (R/W) [DISSSHDESTART] DisSSHDEStartL <7:0> Bits<7:0> of SS horizontal display start (Unit: 1 pixel)
39
SS Horizontal Display Start MSB (R/W) [DISSSHDESTART]
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AL310 DisSSHDEStartH Reserved 3A <3:0> <7:4> Bits<11:8> of SS horizontal display start Reserved
SS Horizontal Display End LSB (R/W) [DISSSHDEEND] DisSSHDEEndL <7:0> Bits<7:0> of SS horizontal display end (Unit: 1 pixel)
3B
SS Horizontal Display End MSB (R/W) [DISSSHDEEND] DisSSHDEEndH Reserved <3:0> <7:4> Bits<11:8> of SS horizontal display end Reserved
3C
SS Vertical Display Start LSB (R/W) [DISSSVDESTART] DisSSVDEStartL <7:0> Bits<7:0> of SS vertical display start (Unit: 1 pixel)
3D
SS Vertical Display Start MSB (R/W) [DISSSVDESTART] DisSSVDEStartH Reserved <3:0> <7:4> Bits<11:8> of SS vertical display start Reserved
3E
SS Vertical Display End LSB (R/W) [DISSSVDEEND] DisSSVDEEndL <7:0> Bits<7:0> of SS vertical display end (Unit: 1 pixel)
3F
SS Vertical Display End MSB (R/W) [DISSSVDEEND] DisSSVDEEndH Reserved <3:0> <7:4> Bits<11:8> of SS display vertical display end Reserved
III. Zoom In Control Registers 40 PS Horizontal Display Source Size LSB (R/W) [DISPSHSRCSIZE] DisPSHSrcSizeL <7:0> Bits<7:0> of PS horizontal display source size (Unit: 1 pixel) 41 PS Horizontal Display Source Size MSB (R/W) [DISPSHSRCSIZE] DisPSHSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal display source size Reserved
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42
PS Horizontal Display Destination Size LSB (R/W) [DISPSHDESTSIZE] DisPSHDestSizeL <7:0> Bits<7:0> of PS horizontal display destination size (Unit: 1 pixel).
43
PS Horizontal Display Destination Size MSB (R/W) [DISPSHDESTSIZE] DisPSHDestSizeH Reserved <3:0> <7:4> Bits<11:8> of PS horizontal display destination size Reserved
Note: DISPSHDESTSIZE >= DISPSHSRCSIZE 44 PS Vertical Display Source Size LSB (R/W) [DISPSVSRCSIZE] DisPSVSrcSizeL 45 <7:0> Bits<7:0> of PS vertical display source size (Unit:1 pixel)
PS Vertical Display Source Size MSB (R/W) [DISPSVSRCSIZE] DisPSVSrcSizeH Reserved <3:0> <7:4> Bits<11:8> of PS vertical display source size Reserved
46
PS Vertical Display Destination Size LSB (R/W) [DISPSVDESTSIZE] DisPSVDestSizeL <7:0> Bits<7:0> of PS vertical display source size (Unit:1 pixel)
47
PS Vertical Display Destination Size MSB (R/W) [DISPSVDESTSIZE] DisPSVDestSizeH Reserved <3:0> <7:4> Bits<11:8> of PS vertical display destination size Reserved
Note: DISPSVDESTSIZE >= DISPSVSRCSIZE 48 PS Zoom In Filter Control (R/W) [PSZOOMFCTRL] PSVZoomEn PSHZoomEn Reserved 4A <0> <1> <7:2> Enable PS vertical scale-up filtering Enable PS horizontal scale-up filtering Reserved
PS Horizontal Scale Up Ratio LSB (R/W) [PSHUPRATIO] PSHUpRatioL <7:0> Bits<7:0> of PS horizontal scale up ratio
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4B
PS Horizontal Scale Up Ratio MSB (R/W) [PSHUPRATIO] PSHUpRatioH <7:0> Bits<15:8> of PS horizontal scale up ratio
Note: PSHUPRATIO = DISPSHSRCSIZE / DISPSHDESTSIZE * 8192 4A Delta PS Horizontal Scale Up Ratio LSB (R/W) [PSDELTAHUPRATIO] PSDeltaHUpRatioL <7:0> Bits<7:0> delta of PS horizontal scale up ratio for Keystone 4B Delta PS Horizontal Scale Up Ratio MSB (R/W) [PSDELTAHUPRATIO] PSDeltaHUpRatioH <3:0> PSHDEStartInc <5:4> Bits<11:8> delta of PS horizontal scale up ratio for Keystone Delta of starting point of PS horizontal DE for Keystone 00 01 10 11 PSHDEEndInc <7:6> 00 01 10 11 Added by 0 Added by 1 Added by 0 Substrate by 1 Added by 0 Added by 1 Added by 0 Substrate by 1
Delta of Ending point of PS horizontal DE for Keystone
Note: This definition is valid when DIS#CB<4>='1' and used in Keystone 4C PS Vertical Scale Up Ratio LSB (R/W) [PSVUPRATIO] PSVUpRatioL 4D <7:0> Bits<7:0> of PS vertical scale up ratio
PS Vertical Scale Up Ratio MSB (R/W) [PSVUPRATIO] PSVUpRatioH <7:0> Bits<15:8> of PS vertical scale up ratio
Note: PSVUPRATIO = DISPSVSRCSIZE / PSDISVDESTSIZE * 8192
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AL310 4E PS Horizontal Scale Up Initial Phase LSB (R/W) [PSHPHASE] PSHUpPhaseL 4F <7:0> Bit<7:0> of PS horizontal scale up initial phase
PS Horizontal Scale Up Initial Phase MSB (R/W) [PSHPHASE] PSHUpPhaseH <7:0> Bit<15:8> of PS horizontal scale up initial phase
50
PS Vertical Scale Up Initial Phase LSB (R/W) [PSVPHASE] PSVUpPhaseL <7:0> Bit<7:0> of PS vertical scale up initial phase
51
PS Vertical Scale Up Initial Phase MSB (R/W) [PSVPHASE] PSVUpPhaseH <7:0> Bit<15:8> of PS vertical scale up initial phase
54
Output Mode (R/W) [OUTPUTMODE] OutputMode <1:0> Data pixel output mode 00 01 10 11 FlipOdd OffsetMode Reserved DitherMode <2> <3> <4> <5> 24-bit output Dual out Reserved Zero output
Dual RGB output data flip Dual RGB output data offset Reserved Enable dither output 0 1 No dither 8 bits to 6 bits
Reserved LutEn 55
<6> <7>
Reserved Enable built-in LUT look-up table
LUT Write Index (R/W) [LUTWINDEX] LUTWIndex <7:0> LUT access index
5C
LUT Red Color LSB (R/W) [LUTRED] LUTRed <7:0> LUT red color port
5D
LUT Green Color LSB (R/W) [LUTGREEN]
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AL310 LUTGreen 5E <7:0> LUT green color port
LUT Blue Color LSB (R/W) [LUTBLUE] LUTBlue <7:0> LUT blue color port
5F
LUT Read/Write Trigger (R/W) [LUTWEN] Reserved LUTWEn <5:0> <7:6> Reserved Write color field enable 00 01 10 11 Red, Green and Blue written into LUT Only Red is written into LUT Only Green written into LUT Only Blue written into LUT
56
Pattern Generator and GPO (R/W) [PATTERNGEN] PatternMode <1:0> 00 01 10 11 PatternEn GPO <4> <7:5> Fram line Color bar Gray level Line moier
Enable pattern generation General purpose output port
Note: Set register GPO(DIS#56<7:5>) value will effect pin GPO2~0 output status in phase
IV. OSD Color Registers 58 OSD Write Address LSB (R/W) [OSDRAMWADDR] OSDRamWAddrL 59 <7:0> Bit<7:0> of OSD ram write address
OSD Write Address MSB (R/W) [OSDRAMWADDR] OSDRamWAddrH Reserved <2:0> <7:3> Bit<10:8> of OSD ram write address Reserved
5A
OSD Write Data Port (W) [OSDRAMWDATA]
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AL310 OSDWData 60 <7:0> OSD ram write data port
Color 0 Red (R/W) [COLOR0RED] Color0Red <7:0> Color 0 Red Component
61
Color 0 Green (R/W) [COLOR0GREEN] Color0Green <7:0> Color 0 Green Component
62
Color 0 Blue (R/W) [COLOR0RED] Color0Blue <7:0> Color 0 Blue Component
63
Color 1 Red (R/W) [COLOR1RED] Color1Red <7:0> Color 1 Red Component
64
Color 1 Green (R/W) [COLOR1GREEN] Color1Green <7:0> Color 1 Green Component
65
Color 1 Blue (R/W) [COLOR1BLUE] Color1Blue <7:0> Color 1 Blue Component
66
Color 2 Red (R/W) [COLOR2RED] Color2Red <7:0> Color 2 Red Component
67
Color 2 Green (R/W) [COLOR2GREEN] Color2Green <7:0> Color 2 Green Component
68
Color 2 Blue (R/W) [COLOR2BLUE] Color2Blue <7:0> Color 2 Blue Component
69
Color 3 Red (R/W) [COLOR3RED] Color3Red <7:0> Color 3 Red Component
6A
Color 3 Green (R/W) [COLOR3GREEN] Color3Green <7:0> Color 3 Green Component
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6B
Color 3 Blue (R/W) [COLOR3BLUE] Color3Blue <7:0> Color 3 Blue Component
6C
Color 4 Red (R/W) [COLOR4RED] Color4Red <7:0> Color 4 Red Component
6D
Color 4 Green (R/W) [COLOR0GREEN] Color4Green <7:0> Color 4 Green Component
6E
Color 4 Blue (R/W) [COLOR4BLUE] Color4Blue <7:0> Color 4 Blue Component
6F
Color 5 Red (R/W) [COLOR5RED] Color5Red <7:0> Color 5 Red Component
70
Color 5 Green (R/W) [COLOR5GREEN] Color5Green <7:0> Color 5 Green Component
71
Color 5 Blue (R/W) [COLOR5BLUE] Color5Blue <7:0> Color 5 Blue Component
72
Color 6 Red (R/W) [COLOR6RED] Color6Red <7:0> Color 6 Red Component
73
Color 6 Green (R/W) [COLOR6GREEN] Color6Green <7:0> Color 6 Green Component
74
Color 6 Blue (R/W) [COLOR6BLUE] Color6Blue <7:0> Color 6 Blue Component
75
Color 7Red (R/W) [COLOR7RED] Color7Red <7:0> Color 7 Red Component
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AL310 76 Color 7 Green (R/W) [COLOR7GREEN] Color7Green 77 <7:0> Color 7 Green Component
Color 7 Blue (R/W) [COLOR7BLUE] Color7Blue <7:0> Color 7 Blue Component
V. OSD Control Register
78
OSD Color Select (R/W) [OSDCOLORSEL] Osd1ColorSel <1:0> OSD1 color selection, 8 colors only apply when Font2byte= '1' and PixDepth1= '1' 00 01 10 11 Osd2ColorSel <3:2> select OSD1 colors from index 3..0 select OSD1 colors from index 7..4 select OSD1 colors from index 7..0 Reserved
OSD2 color selection, 8 colors only apply when Font2byte= '1' and PixDepth2= '1' 00 01 10 11 select OSD2 colors from index 3..0 select OSD2 colors from index 7..4 select OSD2 colors from index 7..0 Reserved
Font2byte Reserved 79
<4> <7:5>
Two-byte font charter code mode, effective only when RomMode = '1' Reserved
Blink Time (R/W) [BLINKTIME] BlinkTimer BlinkType <6:0> <7> Blinking timing value 0 1 Reverse color Bypass
Note: OSD Blinking frequency = Vsync frequency / BlinkTimer 80 OSD Modes (R/W) [OSDMODE]
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AL310 RomMode <0> Enable ROM mode 0 1 Reserved Number <1> <7:2> Tie to 0 Adjust rom address width to access external rom data Internal RAM mode External ROM mode
Note: The method of select the Number value show on OSD application note 81 Logic Operation (R/W) [FOREOP] Color0Op <1:0> Logic operation between color 0 and video 00 01 10 11 Color1Op <3:2> 00 01 10 11 Color2Op <5:4> 00 01 10 11 Color3Op <7:6> 00 01 10 11 83 Logic Operation (R/W) [FOREOP] Color4Op <1:0> Logic operation between color 4 and video 00 01 NOP, show only OSD OR, video or color 4 NOP, show only OSD OR, video or color 0 AND, video and color 0 XOR, video xor color 0 NOP, show only OSD OR, video or color 1 AND, video and color 1 XOR, video xor color 1 NOP, show only OSD OR, video or color 2 AND, video and color 2 XOR, video xor color 2 NOP, show only OSD OR, video or color 3 AND, video and color 3 XOR, video xor color 3
Logic operation between color 1 and video
Logic operation between color 2 and video
Logic operation between color 3 and video
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AL310 10 11 Color5Op <3:2> 00 01 10 11 Color6Op <5:4> 00 01 10 11 Color7Op <7:6> 00 01 10 11 Note: Color 0 ~ 7 are defined in DIS#60~77. 82 Fading Alpha Value (R/W) [FADEALPHA] FadeAlpha Reserved <5:0> <7:6> The alpha factor for fading effect ranging Reserved AND, video and color 4 XOR, video xor color 4 NOP, show only OSD OR, video or color 5 AND, video and color 5 XOR, video xor color 5 NOP, show only OSD OR, video or color 6 AND, video and color 6 XOR, video xor color 6 NOP, show only OSD OR, video or color 7 AND, video and color 7 XOR, video xor color 7
Logic operation between color 5 and video
Logic operation between color 6 and video
Logic operation between color 7 and video
Note: FADEALPHA range from 00h to 20h, there is 33-level of fade-in/fade-out effect. Output = Image * FADEALPHA/32 + OSD * (1 - (FADEALPHA /32)) Show only OSD: FADEALPHA = "000000" --- minimum alpha value(00h) Show only Image: FADEALPHA = "100000" --- maximum alpha value(20h)
VI. OSD 1 Registers 84 OSD1 Control (R/W) [OSDCONTROL1] PixDepth1 <0> Number of bits per pixel of OSD1
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AL310 0 1 BlinkEn1 <1> 0 1 HZoom1 <3:2> 00 01 10 11 VZoom1 <5:4> 00 01 10 11 Reserved OsdEn1 <6> <7> One bit per pixel Two bits per pixel Disable blinking Enable blinking OSD1 pixel H size equals to 1X of video pixel OSD1 pixel H size equals to 2X of video pixel OSD1 pixel H size equals to 4X of video pixel OSD1 pixel H size equals to 8X of video pixel OSD1 pixel V size equals to 1X of video pixel OSD1 pixel V size equals to 2X of video pixel OSD1 pixel V size equals to 4X of video pixel OSD1 pixel V size equals to 8X of video pixel
OSD1 blinking enable, effective when RomMode = `1'
OSD1 horizontal zoom factor
OSD1 vertical zoom factor
Reserved OSD1 enable 0 1 Disable OSD1 Enable OSD1
85
OSD1 ROM Start Address (R/W) [ROMSTARTADDR1] RomStAddr1H <7:0> Bits<11:4> of OSD1 ROM start address (Unit: 16 bytes)
86
OSD1 Font Address Unit (R/W) [FONTADDRUNIT1] RomStAddr1L FontAddrUnit1 <3:0> <7:4> Bits<3:0> OSD1 ROM start address (Unit: 16 bytes) OSD1 font address unit (n), font address is multiple of 2(n+5) bytes, max. is 216
90
OSD1 Horizontal Start (R/W) [OSDHSTART1] OsdHStart1 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels)
91
OSD1 Vertical Start (R/W) [OSDVSTART1] OsdVStart1 <7:0> On Screen Display vertical start position (Unit: 4 video
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AL310 lines) 92 OSD1 RAM Start Address (R/W) [RAMADDRST1] RamAddrSt1 8B <7:0> OSD1 RAM start address (Unit: 8 bytes)
OSD1 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE1] RamStride1H Reserved <1:0> <7:2> Bits <9:8> of OSD1 RAM line stride (Unit: 1 bytes) Reserved
93
OSD1 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE1] RamStride1L <7:0> Bits<7:0> of OSD1 RAM line stride(Unit: 1 bytes)
94
OSD1 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE1] BmapHSize1L <7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel)
95
OSD1 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE1] BmapHSize1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal size Reserved
96
OSD1 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL1] BmapHTotal1L <7:0> Bits<7:0> of OSD1 bitmap horizontal total (Unit: 1 OSD pixel)
97
OSD1 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL1] BmapHTotal1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal total Reserved
98
OSD1 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE1] BmapVSize1L <7:0> Bits<7:0> of OSD1 bitmap vertical size(Unit: 1 OSD line)
99
OSD1 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE1] BmapVSize1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap vertical size Reserved
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9A
OSD1 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL1] BmapVTotal1L <7:0> Bits<7:0> of OSD1 bitmap vertical total(Unit: 1 OSD line)
9B
OSD1 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL1] BmapVTotal1H Reserved <1:0> <7:2> Bits<9:8> of OSD1 bitmap vertical total Reserved
9C
OSD1 Icon Horizontal Total (R/W) [ICONHTOTAL1] IconHtotal1 <7:0> OSD1 horizontal icon total (Unit: 1 icon)
9D
OSD1 Icon Vertical Total (R/W) [ICONVTOTAL1] IconVTotal1 <7:0> OSD1 vertical icon total (Unit: 1 icon)
AE
OSD1 Font Line Size (R/W) [FONTLINESIZE1] Fontlinesize1 <7:0> memory size of a line of font (Unit: 1 byte)
VII. OSD 2 Registers 88 OSD2 Control (R/W) [OSDCONTROL2] PixDepth2 <0> Number of bits per pixel of OSD2 0 1 BlinkEn2 <1> 0 1 Hzoom2 <3:2> 00 01 10 11 Vzoom2 <5:4> 00 One bit per pixel Two bits per pixel Disable blinking Enable blinking OSD pixel H size equals to 1X of video pixel OSD pixel H size equals to 2X of video pixel OSD pixel H size equals to 4X of video pixel OSD pixel H size equals to 8X of video pixel OSD pixel V size equals to 1X of video pixel
OSD2 blinking enable, effective when RomMode = `1'
OSD2 horizontal zoom factor
OSD2 vertical zoom factor
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AL310 01 10 11 Reserved OsdEn2 <6> <7> OSD pixel V size equals to 2X of video pixel OSD pixel V size equals to 4X of video pixel OSD pixel V size equals to 8X of video pixel
Reserved OSD2 enable 0 1 Disable OSD2 Enable OSD2
89
OSD2 ROM Start Address (R/W) [ROMSTARTADDR2] RomStAddr1H <7:0> Bits<11:4> of OSD2 ROM start address (Unit: 16 bytes)
8A
OSD2 Font Address Unit (R/W) [FONTADDRUNIT2] RomStAddr2L FontAddrUnit2 <3:0> <7:4> Bits<3:0> OSD2 ROM start address (Unit: 16 bytes) OSD1 font address unit (n), font address is multiple of 2(n+5) bytes, max. is 216
A0
OSD2 Horizontal Start (R/W) [OSDHSTART2] OsdHStart2 <7:0> On Screen Display horizontal start position (Unit: 8 video pixels)
A1
OSD2 Vertical Start (R/W) [OSDVSTART1] OsdVStart2 <7:0> On Screen Display vertical start position (Unit: 4 video lines)
A2
OSD2 RAM Start Address (R/W) [RAMADDRST2] RamAddrSt2 <7:0> OSD2 RAM start address (Unit: 8 bytes)
8C
OSD2 RAM Horizontal Stride MSB (R/W) [RAMSTRIDE2] RamStride2H Reserved <1:0> <7:2> Bits <9:8> of OSD2 RAM line stride (Unit: 1 bytes) Reserved
A3
OSD2 RAM Horizontal Stride LSB (R/W) [RAMSTRIDE2] RamStride2L <7:0> Bits<7:0> of OSD2 RAM line stride (Unit: 1 bytes)
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AL310 A4 OSD2 Bitmap Horizontal Size LSB (R/W) [BMAPHSIZE2] BmapHSize2L <7:0> Bits<7:0> of OSD1 horizontal bitmap size (Unit: 1 OSD pixel) A5 OSD2 Bitmap Horizontal Size MSB (R/W) [BMAPHSIZE2] BmapHSize2H Reserved A6 <1:0> <7:2> Bits<9:8> of OSD1 bitmap horizontal size Reserved
OSD2 Bitmap Horizontal Total Pixels LSB (R/W) [BMAPHTOTAL2] BmapHTotal2L <7:0> Bits<7:0> of OSD2 bitmap horizontal total (Unit: 1 OSD pixel)
A7
OSD2 Bitmap Horizontal Total Pixels MSB (R/W) [BMAPHTOTAL2] BmapHTotal2H Reserved <1:0> <7:2> Bits<9:8> of OSD2 bitmap horizontal total Reserved
A8
OSD2 Bitmap Vertical Size LSB (R/W) [BMAPVSIZE2] BmapVSize2L <7:0> Bits<7:0> of OSD2 bitmap vertical size(Unit: 1 OSD line)
A9
OSD2 Bitmap Vertical Size MSB (R/W) [BMAPVSIZE2] BmapVSize2H Reserved <1:0> <7:2> Bits<9:8> of OSD2 bitmap vertical size Reserved
AA
OSD2 Bitmap Vertical total Lines LSB (R/W) [BMAPVTOTAL2] BmapVTotal2L <7:0> Bits<7:0> of OSD2 bitmap vertical total(Unit: 1 OSD line)
AB
OSD2 Bitmap Vertical Total Lines MSB (R/W) [BMAPVTOTAL2] BmapVTotal2H Reserved <1:0> <7:2> Bits<9:8> of OSD2 bitmap vertical total Reserved
AC
OSD2 Icon Horizontal Total (R/W) [ICONHTOTAL2] IconHtotal2 <7:0> OSD2 horizontal icon total (Unit: 1 icon)
AD
OSD2 Icon Vertical Total (R/W) [ICONVTOTAL2]
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AL310 IconVTotal2 AF <7:0> OSD2 vertical icon total (Unit: 1 icon)
OSD2 Font Line Size (R/W) [FONTLINESIZE2] Fontlinesize2 <7:0> memory size of a line of font (Unit: 1 byte)
VIII. Alpha Blending Registers B0 Mixer Configuration (R/W) [MIXERCONFIG] MixerMode <1:0> Mixer Mode output 00 01 10 11 KeyType <3:2> 00 01 10 11 PSBackEn <4> 0 1 SSBackEn <5> 0 1 Reserved B1 <7:6> PS image output only SS image output only SS image on PS image output Mixing PS & SS (Enable Mixer block) PS output enable (pshde and psvde) SS output enable (sshde and ssvde) PS & Chroma compare SS & Chroma compare Image Background color Image Background color
Select alpha key type
Select image or background color on PS
Select image or background color on SS
Reserved
PS Alpha Value (R/W) [PSALPHA] PSAlpha <7:0> PS alpha value
B2
SS Alpha Value (R/W) [SSALPHA] SSAlpha <7:0> SS alpha value
B3
Desktop Color Component Red (R/W) [DESKR]
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AL310 DeskColorRed B4 <7:0> Desktop color red
Desktop Color Component Green (R/W) [DESKG] DeskColorGreen <7:0> Desktop color green
B5
Desktop Color Component Blue (R/W) [DESKB] DeskColorBlue <7:0> Desktop color blue
B6
PS Background Color Component Red (R/W) [PSBACKR] PSBackRed <7:0> PS background color red
B7
PS Background Color Component Green (R/W) [PSBACKG] PSBackGreen <7:0> PS background color green
B8
PS Background Color Component Blue (R/W) [PSBACKB] PSBackBlue <7:0> PS background color blue
B9
SS Background Color Component Red (R/W) [SSBACKR] SSBackRed <7:0> SS background color red
BA
SS Background Color Component Green (R/W) [SSBACKG] SSBackGreen <7:0> SS background color green
BB
SS Background Color Component Blue (R/W) [SSBACKB] SSBackBlue <7:0> SS background color blue
BC
Chroma Color Component Red (R/W) [CHROMAR] ChromaRed <7:0> Chroma red value
BD
Chroma Color Component Green (R/W) [CHROMAG] ChromaGreen <7:0> Chroma green value
BE
Chroma Color Component Blue (R/W) [CHROMAB] ChromaBlue <7:0> Chroma blue value
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IX. Film Detection/Motion Adaptive Registers C4 Motion Pixels Threshold LSB (R/W) [MOTIONCNTTH] MvCntThL C5 <7:0> Bit<7:0> of motion counter threshold
Motion Pixels Threshold MSB (R/W) [MOTIONCNTTH] MvCntThH <7:0> Bit<15:8> of motion counter threshold
C6
Lumina(Y) Threshold (R/W) [LUMATH] YThL Reserved <6:0> <7> Y threshold for film & motion adaptive Reserved
C7
Chroma(C) Threshold (R/W) [CHROMATH] CThH Reserved <6:0> <7> C threshold for film & motion adaptive Reserved
C8
Deinterlacing Control Register(R/W) [MCCTRL] MCEn <0> Motion Adaptive Deinterlacing Enable 0 1 MvMode <1> 0 1 Reserved TestMv Reserved <2> <3> <7:4> Field Merge Deinterlacing Mode Motion Adaptive Deinterlacing Mode Y/C Comparison Y Comparison Only
Motion Estimation Type
Reserved Display Motion Part Reserved
C9
Film Detection Control Register(R/W) [FILMCTRL] FilmDetEn <0> Film detection enable 0 1 ResetType <1> Disable Enable
Non-Film Detection Type
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AL310 0 1 FilmReset <2> 0 1 Reserved PdMatch CE <3> <7:4> H/W Auto Detection S/W Reset to Non-Film after Film Detected Disable Reset Reset when bit 1 is turn on
Reset Film Detection, depending on bit1
Reserved Number of film sequence matched
Motion Pixel Numbers LSB (R) [MVCNT] MvCountL <7:0> Bit<7:0> of pixels numbers of difference between 2field/frame
CF
Motion Pixel Numbers MSB (R) [MVCNT] MvCountH <7:0> Bit<15:8> of pixels numbers of difference between 2field/frame
X. Keystone/Sharpness Registers CB Keyston/Sharpness Control Register(R/W) [SHPKEYCTRL] ShapEn <0> Sharpness enable 0 1 KeyEn <4> 0 1 Interlace EvenField TriLevel C0 <5> <6> <7> Disable Enable Disable Enable
Keystone enable
Interlace output enable Even field mode Tri level analog data output enable
Keystone Parameters Address LSB (R/W) [KEYADDR] KeyAddrL <7:0> Bit<7:0> of keystone fifo address
C1
Keystone Parameters Address MSB (R/W) [KEYADDR]
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AL310 KeyAddrH Reserved KeyWriteEn <3:0> <6:4> <7> Bit<11:8> of keystone fifo address Reserved Keystone fifo write enable 0 1 Disable Enable
Note: Keystone parameter for each scan line is stored into 1280x32 SRAM inside AL310. KeyAddr is the address of read/write pointer of this SRAM.
XI. Tri-Level Sync Registers D0 Tri Level Sync Parameter (W) [TRISYNCA] PeriodA D1 <7:0> Tri level sync parameter Period_a
Tri Level Sync Parameter (W) [TRISYNCB] PeriodB <7:0> Tri level sync parameter Period_a
D2
Tri Level Sync Parameter (W) [TRISYNCD1] Delta1 Reserved <6:0> <7> Bit<6> is sign bit ex. 60h means from blank_level , - 32 every unit Reserved
D3
Tri Level Sync Parameter (W) [TRISYNCD2] Delta2 Reserved <6:0> <7> Bit<6> is sign bit ex. 20h means from sync_level, + 32 every unit Reserved
D4
Tri Level Sync Parameter (W) [TRISYNBLANK] BlankData <7:0> Data of blanking period
D7
Tri Level Sync Parameter (W) [TRISYNCLEVEL] SyncLevel <7:0> Sync level value
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XII. SS Border Registers
E0
SS Left Border Start LSB (W) [SSLFSTART] SSLFStartL <7:0> Bits<7:0> of SS left boder start position (Unit: 1 pixel)
E1
SS Left Border Start MSB (W) [SSLFSTART] SSLFStartH Reserved <3:0> <7:4> Bits<11:8> of SS left boder start position Reserved
E2
SS Right Border Start LSB (W) [SSRTSTART] SSRTStartL <7:0> Bits<7:0> of SS right boder start position (Unit: 1 pixel)
E3
SS Right Border Start MSB (W) [SSRTSTART] SSRTStartH Reserved <3:0> <7:4> Bits<11:8> of SS right boder start position Reserved
E4
SS Top Border Start LSB (W) [SSTPSTART] SSTPStartL <7:0> Bits<7:0> of SS top boder start position (Unit: 1 pixel)
E5
SS Top Border Start MSB (W) [SSTPSTART] SSTPStartH Reserved <3:0> <7:4> Bits<11:8> of SS top boder start position Reserved
E6
SS Bottom Border start LSB (W) [SSBTSTART] SSBTStartL <7:0> Bits<7:0> of SS bottom boder start position (Unit: 1 pixel)
E7
SS Bottom Border start MSB (W) [SSBTSTART] SSBTStartH Reserved <3:0> <7:4> Bits<11:8> of SS bottom boder start position Reserved
E8
SS Border width (W) [SSBWIDTH] SSBWidth <7:0> SS boder width (Unit: 1 pixel)
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AL310 E9 SS Border Color Red (W) [SSBRED] SSBRed EA <7:0> SS boder red color
SS Border Color Green (W) [SSBGREEN] SSBGreen <7:0> SS boder green color
EB
SS Border Color Blue (W) [SSBBULE] SSBBlue <7:0> SS boder blue color
XIII. Display Parameter Registers C2 Tune Display Horizontal Sync Phase (R/W) [DISTUNEHS] DisHsDelay CC <4:0> Output horizontal sync delay (Unit: 1 oclk)
Tune Display Pixel Clock Phase (R/W) [DISTUNESCLK] TuneSclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> Sclk Sclk + delay phase Inversed Sclk Inversed Sclk + delay phase
Reserved
CD
Tune Display Pixel Clock by 2 Phase (R/W) [DISTUNEDSCLK] TuneDSclk <2:0> <4:3> Phase delay number(8 steps) Phase delay types 00 01 10 11 Reserved <7:5> DSclk DSclk + delay phase Inversed DSclk Inversed DSclk + delay phase
Reserved
CA
Phase Detection Control Register(R/W) [PHASECTRL]
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AL310 PhaseEn <0> Phase detection Enable 0 1 PhaseMode <2:1> 00 01 10 11 Reserved D7 <7:3> Disable Enable 8-bit comparison 7-bit comparison 6-bit comparison 5-bit comparison
Phase detection precision
Tie to "00110"
Display Horizontal Total LSB (R) [DISHTOTAL] HTotalCntL <7:0> Bit<7:0> of display horizontal total count
D8
Display Horizontal Total MSB (R) [DISHTOTAL] HTotalCntH Reserved <2:0> <7:3> Bit<10:8> of display horizontal total count Reserved
D9
Display Vertical Total LSB (R) [DISVTOTAL] VTotalCntL <7:0> Bit<7:0> of display vertical total count
DA
Display Vertical Total MSB (R) [DISVTOTAL] VTotalCntH Reserved <2:0> <7:3> Bit<10:8> of display vertical total count Reserved
DB
Phase Counter LSB (R) [PHASECNT] PhaseCntL <7:0> Bit<7:0> of phase count value
DC
Phase Counter MSB (R) [PHASECNT] PhaseCntH Reserved <4:0> <7:5> Bit<12:8> of phase count value Reserved
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10 Electrical Characteristics
10.1 Absolute Maximum Ratings
(Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.)
Parameter VDD VP IO TAMB Tstg TVSOL Supply Voltage Input Pin Voltage Output Current Ambient Op. Temperature Storage Temperature Vapor Phase Soldering 3.3V Rating -0.3 ~ +3.8 -0.3 ~ +(VDD+0.3) -20 ~ +20 0 ~ +85 -40 ~ +125 220 Unit V V mA C C C
Temperature (15 Sec.)
10.2
Recommended Operating Conditions
3.3V Rating Min. Typical +3.3 Max. +3.6 VDD 0.3 VDD +70 V V V C
Parameter
Unit
VDD VIH VIL TAMB
Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Op. Temperature
+3.0 0.7 VDD 0 0
10.3
DC Characteristics
(VDD = 3.3V, Vss=0V. TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested)
Parameter Min. 3.3V Rating Typical Max. Unit
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Parameter Min. VIH VIL VOH VOL ILI ILO Hi-level Input Voltage Lo-level Input Voltage Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current Output Leakage Current 0.7 VDD 0 2.4 -5 -5
3.3V Rating Typical Max. VDD 0.3 VDD VDD +0.4 +5 +5
Unit
V V V V A A
10.4
AC Characteristics
(VDD = 3.3V, Vss=0V, TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested)
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11 Timing Diagrams
TBD.
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12 Mechanical Drawing- BGA-308
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BGA Family
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PACKAGE OFFERING & OUTLINE DIMENSION
Body Size D
14 17 23
Ball Count N
119 256 233, 241 376, 420, 456, 484 256, 272, 292, 308, 316, 320, 324, 328, 330, 336,
E
22 17 23
Ball Pitch e
1.27 1.00 1.27 1.00 1.27 1.00 1.27 1.00 1.00
Ball Dia. b
0.75 0.50 0.75 0.60 0.75 0.60 0.75 0.55 0.60
Package Thk. A
2.16 1.80 2.33 2.23 2.33 2.23 2.33 2.18 2.23
Stand Off A1
0.60 0.40 0.60 0.50 0.60 0.50 0.60 0.45 0.50
Body Thk. A2
1.56 1.21 1.73 1.73 1.73 1.73 1.73 1.73 1.73
Substrate Thk. c
0.56 0.36 0.56 0.56 0.56 0.56 0.56 0.56 0.56
27
27
348, 350, 352, 365, 376 484 304, 329, 345, 350, 385, 409, 457
31
31
556 560, 900 352, 387, 388, 400, 432, 436, 452, 456, 472, 476, 484, 492, 496, 502, 504,
1.27
0.75
2.33
0.60
1.73
0.56
35
35
505, 508, 510, 516, 524, 548, 556, 561, 637, 728 680, 700, 1156 1.00 1.27 1.27 0.60 0.75 0.75 2.23 2.33 2.33 0.50 0.60 0.60 1.73 1.73 1.73 0.56 0.56 0.56 (Unit: mm)
37.5 40
37.5 40
480, 576, 601, 618, 673 596
BGA Family
A-2
PBGA
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CONTACT INFORMATION
Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119, U.S.A. Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com
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