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| www..com VIS Description VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Selfrefresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII. Features * Single 5V or 3.3V only power supply * High speed tRAC access time: 50/60ns * Extended-data-out (EDO) page mode access * I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V) * 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh * Refresh interval: - RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms - Self-refresh: 1024 cycles * JEDEC standard pinout: 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII .com DataShee .com Document:1G5-0179 Rev.3 Page 1 DataSheet 4 U .com www..com VIS Pin Configuration 42-Pin 400mil SOJ 50(44)-Pin 400mil TSOPII VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 GND DQ15 DQ14 DQ13 DQ12 GND DQ11 DQ10 DQ9 DQ8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND t4U.com A0 A1 A2 A3 VCC NC NC WE OE RAS A9 NC A8 NC A7 A0 .com A1 A6 A2 A5 A3 A4 VCC VSS DataShee Pin Description Pin Name A0-A9 Function Address inputs - Row address: A0-A9 - Column address: A0-A9 - Refresh address: A0-A9 Data-in / data-out Row address strobe Column address strobe Write enable Output enable Power (+5 V or + 3.3V) Ground No connection DQ0~DQ15 RAS UCAS, LCAS WE OE Vcc Vss NC .com Document:1G5-0179 Rev.3 Page 2 DataSheet 4 U .com www..com VIS VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Block Diagram WE LCAS UCAS CAS CONTROL LOGIC DATA - IN BUFFER DQ1 . . DQ16 NO.2 CLOCK GENERATOR DATA - OUT BUFFER OE COLUMNADDRESS BUFFERS (10) A0 A1 t4U.com A2 A3 A4 A5 A6 A7 ROW DECODER COLUMN DECODER REFRESH CONTROLLER .com 1024 DataShee SENSE AMPLIFIERS I/0 GATING REFRESH COUNTER 1024x16 A8 A9 ROW ADDRESS BUFFERS (10) 1024 x 1024 x 16 MEMORY ARRAY 1024 RAS NO.1 CLOCK GENERATOR Vcc Vss .com Document:1G5-0179 Rev.3 Page 3 DataSheet 4 U .com www..com VIS TRUTH TABLE ADDRESSES FUNCTION RAS STANDBY READ : WORD READ : LOWER BYTE H L L LCAS H(R)X L L UCAS H(R)X L H WE X H H OE X L L ROW X ROW ROW COL X COL COL VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM DQS High-Z Data-Out Lower Byte: Data-Out Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-Out Data-In Notes READ: UPPER BYTE L H L H L ROW COL WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE : UPPER BYTE (EARLY) READ WRITE PAGE-MODE READ 1st Cycle 2nd Cycle PAGE-MODE WRITE 1st Cycle 2nd Cycle L L L L X ROW COL L L H L X ROW COL Lower Byte: Data-In Upper Byte: High-Z Lower Byte: High-Z Upper Byte: Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z 4 1,2 2 2 1 1 1,2 1,2 2 1,3 L H L L X ROW COL L L L L L L L L(R)H(R)L L(R)H(R)L L H(R)L L H(R)L H(R)L H(R)L H(R)L H(R)L H(R)L L L H L L H(R)L H(R)L H(R)L H(R)L H(R)L H(R)L L L H L H(R)L H H L L H(R)L H(R)L H L X H L(R)H L L X X L(R)H L(R)H L X X X ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X COL COL COL COL COL COL COL COL COL n/a X t4U.com PAGE-MODE READWRITE HIDDEN REFRESH 1st Cycle 2nd Cycle READ WRITE RAS-ONLY REFRESH CBR REFRESH .com DataShee Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). .com Document:1G5-0179 Rev.3 Page 4 DataSheet 4 U .com www..com VIS Absolute Maximum Ratings VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Parameter Voltage on an any pin relative to Vss 5V 3.3V Supply voltage relative to Vss 5V 3.3V Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC IOUT PD TOPT TSTG Value -1.0 to + 7.0 -0.5 to + 4.6 -1.0 to + 7.0 -0.5 to + 4.6 50 1.0 0 to + 70 -55 to + 125 Unit V V mA W C C Recommended DC Operating Conditions Parameter/Condition Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs Symbol VCC VIH VIL 5 Volt Version Min 4.5 2.4 -1.0 Typ 5.0 Max 5.5 VCC + 1.0 0.8 Min 3.15 2.0 -0.3 3.3 Volt Version Typ 3.3 Max 3.6 VCC + 0.3 0.8 Unit V V V t4U.com .com DataShee Capacitance Ta = 25C, VCC = 5V 10 % or 3.3V 10 %, f = 1MHz Parameter Input capacitance (Address) Input capacitance (RAS , LCAS , UCAS, OE, WE) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Max 5 7 7 Unit pF pF pF Note 1 1 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, LCAS and UCAS = VIH to disable Dout. .com Document:1G5-0179 Rev.3 Page 5 DataSheet 4 U .com www..com VIS DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 C, VCC= + 5V 10 %,VSS = 0V) Parameter Symbol Test Conditions VG26(S)18165 -5 Min Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min TTL interface RAS,LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS Vcc -0.2V Dout = High-Z RAS-only refresh current EDO page mode current CAS-before-RAS refresh current Self-refresh current ICC3 RAS cycling, LCAS / UCAS = VIH tRC = min tRC = min tRC = min RAS, LCAS / UCAS cycling t RAS 100ms 1 Max 160 Min -6 VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Unit Notes Max 1, 2 145 mA Standby current ICC2 2 - 2 mA 1 mA 1, 2 160 145 mA 1, 3 1, 2 ICC4 ICC5 ICC6 ILI ILO -5 90 160 500 5 -5 80 145 500 5 mA mA mA mA mA V V t4U.com Input leakage current Output leakage current .com 0V V IN V CC + 0.5V 0V V OUT V CC + 0.5V Dout = Disable IOH = - 5mA IOL = + 4.2mA DataShee -5 5 -5 5 Output high Voltage Output low voltage Notes: VOH VOL 2.4 - 0.4 2.4 - 0.4 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. .com Document:1G5-0179 Rev.3 Page 6 DataSheet 4 U .com www..com VIS DC Characteristics ; 3.3 - Volt Version (Ta = 0 to 70C, VCC = + 3.15V~3.6V , VSS = 0V) VG26V(S)18165 Parameter Symbol Test Conditions Min VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM -5 Max Min -6 Max Unit Notes Operating current ICC1 RAS cycling LCAS / UCAS cycling tRC = min LVTTL interface RAS, LCAS / UCAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC -0.2V Dout = High-Z - 160 - 145 mA 1, 2 Standby Current ICC2 - 2 - 2 mA - 0.5 - 0.5 mA RAS- only refresh current ICC3 RAS cycling LCAS / UCAS = VIH tRC = min tPC = min tRC = min RAS, LCAS / UCAS cycling t RASS 100ms - 160 - 145 mA 1, 2 EDO page mode current CAS- before- RAS refresh current ICC4 ICC5 - 90 160 - 80 145 mA mA 1, 3 1, 2 t4U.com Self- refresh current Input leakage current Output leakage current ICC6 ILI ILO VOH VOL .com -5 -5 450 5 5 -5 -5 450 5 5 mA mA mA V V DataShee 0V Vin V CC + 0.3V 0V Vout V CC + 0.3V Dout = Disable IOH = -2mA IOL = +2mA Output high Voltage Output low voltage 2.4 - 0.4 2.4 - 0.4 Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For ICC4, address can be changed once or less within one EDO page mode cycle time. .com Document:1G5-0179 Rev.3 Page 7 DataSheet 4 U .com www..com VIS Test conditions * Output load: two TTL Loads and 50pF (VCC = 5.0V 10 %); one TTL Load and 50pF (VCC = 3.15V~3.6V) * Input timing reference levels: VIH = 2.4V, VIL = 0.8V (VCC = 5.0V 10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.15V~3.6V) * Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VCC = 5.0V 10 %, 3.15V ~3.6V) VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM AC Characteristics(Ta = 0 to + 70C, Vcc = 5V 10 % or 3.15V~3.6V, Vss = 0V) *1, *2, *3, *4, *5 Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) VG26(V)(S) 18165 Parameter Symbol Min Random read or write cycle time RAS precharge time LCAS / UCAS precharge time in normal mode RAS pulse width tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tCRP tOED tT tREF tCLZ tDZC tDZO 50 8 0 8 0 8 12 10 25 8 38 5 20 1 0 0 0 10K 10K 37 25 50 16 60 10 0 10 0 10 14 12 30 10 40 5 20 1 0 0 0 10K 10K 45 30 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 12 11 9 10 8 6 7 tRC tRP tCPN 84 30 10 -5 Max Min 104 40 10 -6 Max ns ns ns Unit Notes t4U.com LCAS / UCAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to LCAS / UCAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time LCAS / UCAS hold time LCAS / UCAS to RAS precharge time OE to Din delay time Transition time (rise and fall) Refresh period LCAS / UCAS to output in Low- Z LCAS / UCAS delay time from Din OE delay time from Din .com DataShee .com Document:1G5-0179 Rev.3 Page 8 DataSheet 4 U .com www..com VIS Read Cycle VG26(V)(S)18165 Parameter Symbol Min Access time from RAS Access time from LCAS / UCAS Access time from column address Access time from OE Read command setup time Read command hold time to LCAS / UCAS Read command hold time to RAS Output buffer turn-off time Output buffer turn-off time from OE tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ 0 0 10 0 0 -5 Max 50 13 25 12 12 12 Min 0 0 10 0 0 -6 Max 60 15 30 15 15 15 VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM Unit Notes ns ns ns ns ns ns ns ns ns 13 14, 15 15, 16 8 11, 17 17 18 18 Write Cycle VG26(V)(S)18165 Parameter Symbol Min -5 Max Min 0 10 10 15 10 0 10 10 -6 Max ns ns ns ns ns ns ns ns 20 21 21 8, 19 Unit Notes t4U.com Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to LCAS / UCAS lead time Data-in setup time Data-in hold time WE to Data-in delay .com tWCS tWCH tWP tRWL tCWL tDS tDH tWED 0 8 8 13 8 0 8 10 DataShee Read- Modify- Write Cycle VG26(V)(S)18165 Parameter Symbol Min Read-modify- write cycle time RAS to WE delay time LCAS / UCAS to WE dealy time Column address to WE delay time OE hold time from WE tRWC tRWD tCWD tAWD tOEH 108 64 26 39 8 -5 Max Min 133 77 32 47 10 -6 Max ns ns ns ns ns 19 19 19 Unit Notes .com Document:1G5-0179 Rev.3 Page 9 DataSheet 4 U .com www..com VIS Refresh Cycle VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VG26(V)(S)18165 Parameter Symbol Min LCAS / UCAS setup time (CBR refresh) LCAS / UCAS hold time (CBR refresh) RAS precharge to CAS hold time RAS pulse width (self refresh) RAS precharge time (self refresh) LCAS / UCAS hold time (CBR self refresh) WE setup time WE hold time tCSR tCHR tRPC tRASS tRPS tCHS tWSR tWHR 5 8 5 100 90 -50 0 10 -5 Max Min 5 10 5 100 110 -50 0 10 -6 Max Unit ns ns ns ms ns ns ns ns 11 8 Notes EDO Page Mode Cycle VG26(V)(S)18165 Parameter Symbol Min EDO page mode cycle time tPC tCP 20 10 50 30 5 10 5 3 10 -5 Max 105 30 10 Min 25 10 60 35 5 10 5 3 10 -6 Max 105 35 10 ns ns ns ns ns ns ns ns ns ns 22 11, 15 Unit Notes t4U.com EDO page mode LCAS / UCAS precharge time EDO page mode RAS pulse width Access time from LCAS / UCAS precharge RAS hold time from LCAS / UCAS precharge OE high hold time from LCAS / UCAS high OE high pulse width Data output hold time after LCAS / UCAS low Output disable delay from WE WE pulse width for output disable when LCAS / UCAS high .com DataShee tRASP tCPA tCPRH tOEHC tOEP tCOH tWHZ tWPZ EDO Page Mode Read Modify Write Cycle VG26(V)(S)18165 Parameter EDO page mode read- modify- write cycle LCAS / UCAS precharge to WE delay time EDO page mode read- modify- write cycle time Symbol Min tCPW tPRWC 45 56 -5 Max Min 55 68 -6 Max ns ns 11 Unit Notes .com Document:1G5-0179 Rev.3 Page 10 DataSheet 4 U .com www..com VIS Notes : 1. AC measurements assume tT = 1ns. VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM 2. An initial pause of 100 ms is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. When both LCAS and UCAS go low at the same time, all 16-bits data are witten into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 6. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle. 7. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 8. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS . 9. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 10. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 11. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS . 12. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. t4U.com 13. Assumes that tRCD tRCD(max) and tRAD.com or tRAD is greater than the maximum tRAD(max). If tRCD recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that t RCD DataShee t RCD (max) and t RAD t RAD (max). t RAD (max). 15. Access time is determined by the maximum of tAA, tCAC, tCPA. 16. Assumes that t RCD t RCD (max) and t RAD 17. Either tRCH or tRRH must be satisfied for a read cycle. 18. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). tOFF is determined by the later rising edge of RAS or CAS. 19. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t RWD t CWD t RWD (min), t CWD (min), t AWD t AWD (min) and t CPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 20. tCWL shall be satisfied by both LCAS and UCAS. 21. These parameters are referenced to LCAS or LCAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 22. tRASP defines RAS pulse width in EDO page mode cycles. .com Document:1G5-0179 Rev.3 Page 11 DataSheet 4 U .com www..com VIS Timing Waveforms * Word Read Cycle VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CRP t CSH t RCD t T t RSH t CAS t CPN UCAS LCAS t RAD t RAL t ASR t RAH t ASC t CAH ADDRESS Row Column t4U.com .com t RRH DataShee t RCS t RCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ1~DQ16 t CLZ DOUT .com Document:1G5-0179 Rev.3 Page 12 DataSheet 4 U .com www..com VIS * Byte Read Cycle t RC t RAS t RP VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP UCAS (or LCAS) LCAS (or UCAS) t RAD t ASR t RAH Row t ASC t RAL t CAH t4U.com ADDRESS Column .com DataShee tRRH t RCS t RCH WE OE t OEA t CAC t AA t RAC t OEZ t OFF DQ9~DQ16 (or DQ1~DQ8) DOUT t CLZ DQ1~DQ8 (or DQ9~DQ16) High-Z .com Document:1G5-0179 Rev.3 Page 13 DataSheet 4 U .com www..com VIS * Word Early Write Cycle VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CSH t RCD t T t RSH t CAS t CRP UCAS LCAS t RAD t RAL t ASR t RAH Row t ASC t CAH Column ADDRESS t4U.com .com DataShee t WCS t WCH WE t DS t DH DQ1~DQ16 D IN .com Document:1G5-0179 Rev.3 Page 14 DataSheet 4 U .com www..com VIS * Byte Early Write Cycle VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RAS t RP RAS t CSH t RCD t T t RSH t CAS t CRP LCAS (or UCAS) LCAS (or UCAS) t RAD t ASR t RAH Row t ASC t RAL t CAH Column t4U.com ADDRESS .com DataShee t WCS t WCH WE t DS t DH DQ9~DQ16 DIN DQ1~DQ8 .com Document:1G5-0179 Rev.3 Page 15 DataSheet 4 U .com www..com VIS * Word Delayed Write Cycle t RC t RAS t RP VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CPN t CRP UCAS LCAS t ASR t RAH t ASC t CAH ADDRESS Row Column t4U.com .com t CWL t RWL DataShee t RCS t WP WE t OEH t OED OE t DS t DH DQ1~DQ16 OPEN D IN .com Document:1G5-0179 Rev.3 Page 16 DataSheet 4 U .com www..com VIS * Byte Delayed Write Cycle t RC t RAS t RP VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS t CSH t RCD t T t RSH t CAS t CRP LCAS (or UCAS) LCAS (or UCAS) t ASR t RAH t ASC t CAH t4U.com ADDRESS Row Column .com tCWL t RCS DataShee t RWL t WP WE t OEH tOED OE t DS t DH DQ9~DQ16 (or DQ1~DQ8) OPEN D IN DQ1~DQ8 (or DQ9~DQ16) .com Document:1G5-0179 Rev.3 Page 17 DataSheet 4 U .com www..com VIS * Word Read-Modify-Write Cycle t RWC t RAS VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t T t RCD t CAS t CRP t CPN UCAS LCAS t RAD t ASR t ASC t RAH t CAH ADDRESS Row Column t CWD t RCS t CWL t RWL t WP t4U.com t AWD .com t RWD DataShee WE t DS t DH DQ1~DQ16 OPEN D in t OED t OEH OE t OEA t CAC t AA t RAC t OEZ DQ1~DQ16 DOUT .com Document:1G5-0179 Rev.3 Page 18 DataSheet 4 U .com www..com VIS * EDO Page Mode Word Read-Modify-Write Cycle t RASP tCPRH VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t T t RCD t CAS t CP t PRWC t CAS tCP t CAS t CRP UCAS LCAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t RAL t ASC t CAH ADDRESS Row Column 1 Column 1 t RWD t AWD t CWD t CWL Column 2 t CPW t AWD t CWD t CWL Column N t t CWL CPW t AWD t CWD t RWL t RCS t4U.com WE WE t RCS t WP t DS .com t WP t DS tDH t DH t WP t DS t DH OPEN DataShee DQ1~DQ16 OPEN Din 1 OPEN Din 2 Din N tDZO tOED tOEH tOED tOEH tOED tOEH OE tOEA tCAC tRAC tAA t OEZ t OEA tCAC tAA tCPA tOEZ tCAC tAA tCPA tOEZ tOEA DQ1~DQ16 DOUT 1 DOUT 2 DOUT N .com Document:1G5-0179 Rev.3 Page 19 DataSheet 4 U .com www..com VIS * EDO Page Mode Word Read-Early-Write Cycle t RASP t CPRH VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP RAS t CRP t CSH t CRP t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CPN UCAS LCAS t CSH t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAL t RAL t CAH ADDRESS Row Column 1 Column 2 Column N Row t4U.com t RCS .com t RCH t WCS t WCH DataShee WE WE t OEA t WED OE OE t RAC t AA tCAC t COH OPEN Data Output 1 Data Output 2 Data Intput N t CPA t AA tCAC t WHZ t DH t DS DQ1~DQ16 .com Document:1G5-0179 Rev.3 Page 20 DataSheet 4 U .com www..com VIS * Read Cycle with WE Controlled Disable RAS VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t CSH t RCD t T t CAS UCAS LCAS t RAD t ASR t RAH t ASC t CAH ADDRESS Row Column t4U.com .com t RCH t WPZ DataShee t RCS WE t WHZ t OED OE t DS tOEA tCAC tAA tRAC tOEZ DQ1~DQ16 tCLZ DOUT .com Document:1G5-0179 Rev.3 Page 21 DataSheet 4 U .com www..com VIS RAS - Only Refresh Cycle t RC t RAS t RP VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM RAS tT t CRP tRPC tCRP UCAS LCAS tASR tRAH ADDRESS Row tOFF OPEN DQ1~DQ16 t4U.com CAS-Before-RAS Refresh Cycle .com DataShee tRC tRP tRC tRP tRAS t RP RAS tRAS tT tRPC t CSR t CHR tRPC tCSR tCHR tCRP UCAS LCAS tWSR tWHR tWSR tWHR WE tOFF OPEN DQ1~DQ16 .com Document:1G5-0179 Rev.3 Page 22 DataSheet 4 U .com www..com VIS * Hidden Refresh Cycle t RC tRAS (READ) VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RC t RP tRAS (REFRESH) t RC t RP tRAS (REFRESH) t RP RAS tT t CHR t RSH tRCD tCAS tCRP UCAS LCAS t RAD t ASR t RAH tASC t RAL tCAH ADDRESS Row Column t4U.com t RCS .com tRRH tRCH DataShee WE OE tORD t OEA t CAC t AA t RAC t OEZ t OFF t OFF DQ1~DQ16 D OUT .com Document:1G5-0179 Rev.3 Page 23 DataSheet 4 U .com www..com VIS * SELF REFRESH CYCLE (Addresses, WE and OE = DON'T CARE) VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM t RP tRASS t RPS RAS t RPC t CP t CHD t CSR t RPC t CP UCAS/LCAS DQ Open Don't Care t4U.com .com DataShee .com Document:1G5-0179 Rev.3 Page 24 DataSheet 4 U .com www..com VIS Ordering information Part Number VG26(V)(S)18165CJ-5 VG26(V)(S)18165CJ-6 VG26(V)(S)18165CT-5 VG26(V)(S)18165CT-6 Access time 50 ns 60 ns 50 ns 60 ns Package 400mil 42-Pin Plastic SOJ 400mil 50(44)-Pin TSOPII VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM VG26(V)(S)18165CJ-5 * VG * 26 *V * 18165 *C * VIS Memory Product * Technology * V: 3.3V Version; Non: 5V * Device Type and Configuation * Revision (C and D) * Package Type (J : SOJ, T : TSOP II) * Speed (5: 50 ns, 6: 60 ns) *J *5 t4U.com .com DataShee .com Document:1G5-0179 Rev.3 Page 25 DataSheet 4 U .com www..com VIS Package Information 42-pin SOJ D VG26(V)18165C 1,048,576 x 16 - Bit CMOS Dynamic RAM DIM A A1 A2 b b1 b2 c c1 e D E E1 E2 R1 q MILLIMETERS MIN. NOM. MAX. 3.25 3.51 3.76 2.08 ----2.79 REF. 0.38 --0.51 0.38 --0.46 0.66 0.71 0.81 0.18 --0.33 0.18 0.20 0.28 1.27 BASIC 27.18 27.31 27.43 11.05 11.18 11.30 10.03 10.16 10.29 9.40 BASIC 0.76 0.89 1.02 3 --16 INCHES MIN. NOM. MAX. 0.128 0.138 0.148 0.082 ----0.110 REF. 0.015 --0.020 0.015 --0.018 0.026 0.028 0.032 0.007 --0.013 0.007 0.008 0.011 0.050 BASIC 1.070 1.075 1.080 0.435 0.440 0.445 0.395 0.400 0.405 0.370 BASIC 0.030 0.035 0.040 3 --16 42 22 b b1 c1 E1 E c BASE METAL WITH PLATING SECTION B-B 1 21 q 0.025" MIN. A2 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025) BELOW b2 MIN. A b2 b e 0.007" M 0.004" B A1 E2 B RAD R1 SEATING PLANE t4U.com Package Information 50(44)-pin TSOPII .com DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1 MILLIMETERS MIN. --0.05 0.95 0.30 0.30 0.12 0.11 20.82 NOM. ----1.00 --------20.95 0.875 BASIC 0.80 BASIC 11.56 10.03 0.40 0.11 0.11 11.76 10.16 0.50 ----11.96 10.29 0.60 0.25 --0.455 0.395 0.016 0.004 0.004 MAX. 1.20 0.15 1.05 0.45 0.40 0.21 0.16 21.08 MIN. --0.002 0.037 0.012 0.012 0.005 0.0045 0.820 INCHES NOM. ----0.039 --------0.825 0.0344 BASIC 0.0315 BASIC 0.463 0.400 0.020 ----0.471 0.405 0.024 0.010 --D c1 c 1 11 15 25 b b1 MAX. 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.830 E1 A1 A2 RAD R1 RAD R B B 0 ~5 c 50 40 36 26 DETAIL A L SECTION B-B BASE METAL WITH PLATING NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. ZD A DETAIL A b 4-1.60 REF. 40 - e SEATING PLANE 0.100(0.004) E .com Document:1G5-0179 Rev.3 Page 26 DataSheet 4 U .com |
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