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| w DESCRIPTION WM8312 is an integrated power-management subsystem which provides a cost-effective, flexible, single-chip solution for power management, specifically targeted at the requirements of a range of low-power portable applications. WM8312 is specifically designed to operate as a system PMIC supporting a variety of industry standard processors and accessories in a wide range of applications. The start-up behaviour and configuration is fully programmable in an integrated OTP non-volatile memory. This highly flexible solution helps reduce time-to-market, as changing application requirements can be very easily accommodated in the OTP contents. The WM8312 power management subsystem comprises of four programmable DC-DC converters, eleven LDO regulators (four of which are low-noise for supplying sensitive analogue subsystems). The integrated OTP bootstrap circuitry controls the start-up sequencing and voltages of the converters and regulators as well as the sequencing of system clocks. WM8312 can be powered from a battery, a wall adaptor or from a USB power source. An on-chip regulator provides power for always-on PMIC functions such as register map and the RTC. The device provides autonomous backup battery switchover. A low-power LDO is included to support `Alive' processor power domains external to the WM8312. A linear on-chip battery charger supports trickle charging and constant current / constant voltage charging of single-cell lithium-ion / lithium-polymer batteries. The charge current, termination voltage, and charger time-out are programmable. WM8312 detects and handles battery fault conditions with a minimum of system software involvement. A 12-bit Auxiliary ADC supports a wide range of applications for internal as well as external analogue sampling, such as voltage detection and temperature measurement. The Touch Panel controller uses the same ADC on an interleaved basis. WM8312 includes a crystal oscillator, an internal RC oscillator and Frequency Locked Loop (FLL) to generate all clock signals for autonomous system start-up and processor clocking. A Secure Real-time Clock (S-RTC) and alarm function is included, capable of waking up the system from low-power modes. A watchdog function is provided to ensure system integrity. To maximise battery life, highly-granular power management enables each function in the WM8312 subsystem to be independently powered down through a control interface or alternatively through register and OTP-configurable GPIOs. The device offers a standby power consumption of <10uA, making it particularly suitable for portable applications. The WM8312 is supplied in a 7x7mm 169-ball BGA package, ideal for use in portable systems. The WM8312 forms part of the Wolfson series of audio and power management solutions. WM8312 Processor Power Management Subsystem FEATURES Power Management * 2 x DC-DC synch. buck converter (0.6V - 1.8V, 1.2A, DVS) * 1 x DC-DC synch. buck converter (0.85V - 3.4V, 1A) * * * * * * 1 x DC-DC boost converter (up to 30V, up to 40mA) 1 x LDO regulator (0.9V - 3.3V, 300mA, 1) 2 x LDO regulators (0.9V - 3.3V, 200mA, 1) 3 x LDO regulators (0.9V - 3.3V, 100mA, 2) 2 x Low-noise LDO regulators (1.0V - 3.5V, 200mA, 1) 2 x Low-noise LDO regulators (1.0V - 3.5V, 150mA, 2) * 1 x `Alive' LDO regulator (0.8V - 1.55V, up to 10mA) Backlight LED Current Sinks * 2 x programmable constant current sinks, suitable for multi-LED display backlight control Battery Charger * Programmable single-cell lithium-ion / lithium-polymer battery charger (1A max charge current) * Battery monitoring for temperature and voltage * Autonomous backup battery charging and switching System Control * * * * * * I2C or SPI compatible primary control interface Interrupt based feedback communication scheme Watchdog timer and system reset control Autonomous power sequencing and fault detection Intelligent power path and power source selection OTP memory bootstrap configuration function Additional Features * Auxiliary ADC for multi-function analogue measurement * Touch Panel interface controller (4-wire and 5-wire) * * * * 128-bit pseudo-random unique ID Secure Real-Time Clock with wake-up alarm 16 x configurable multi-function (GPIO) pins Comprehensive clocking scheme: low-power 32kHz RTC crystal oscillator, Frequency Locked Loop, GPIO clock output and 4MHz RC clock for power management System LED outputs indicating power state, battery charger or fault status * * Selectable USB current limiting up to 1.8A (in accordance with USB Battery Charging specification Rev 1.1) Package Options * 7x7mm, 169-ball BGA package, 0.5mm ball pitch APPLICATIONS * * * * * Portable Media Players Portable Navigation Devices Cellular Handsets Electronic Books Electronic Gaming Devices WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Pre-Production, December 2009, Rev 3.0 Copyright (c)2009 Wolfson Microelectronics plc WM8312 BLOCK DIAGRAM CIFMODE SDOUT1 SCLK1 SDA1 CS DC2VDD DC2LX DC2FB DC2GND DC3VDD DC3LX DC3FB DC3GND DC4VDD DC4LX DC4FB DC4GND DC1VDD DC1LX DC1FB DC1GND Pre-Production RESET IRQ SCLK2 SDA2 DBVDD DBGND PROGVDD Interrupt and Reset Controller Primary Control Interface Dynamic Bootstrap EEPROM Interface OTP NVM Bootstrap Config & Unique ID DC-DC1 Buck 0.6 to 1.8V 1.2A DVS DC-DC2 Buck 0.6 to 1.8V 1.2A DVS DC-DC3 Buck 0.85 to 3.4V 1A DC-DC4 Boost up to 30V, up to 40mA LED Sink GND PVDD LED1 LED2 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 ON TPVDD GPIO13 GPIO14 GPIO15 GPIO16 TPGND AUXADCIN1 AUXADCIN2 AUXADCIN3 AUXADCIN4 USBVMON SYSVMON BATTVMON NTCBIAS NTCMON XTO XTI XOSCGND CLKOUT CLKIN System Status LED Driver Register Map and Application Processor Interface ISINK1 ISINK2 ISINKGND LDO1VDD LDO1VOUT LDO2VDD LDO2VOUT LDO3VDD LDO3VOUT LDO4VDD LDO4VOUT LDO5VDD LDO5VOUT LDO6VDD LDO6VOUT LDO7VDD LDO7VOUT LDO8VDD LDO8VOUT LDO9VDD LDO9VOUT LDO10VDD LDO10VOUT LDO11VOUT LDO12VOUT LDO13VOUT SYSVDD LDO 1 Standard LDO 0.9 to 3.3V 300mA LDO 2 Standard LDO 0.9 to 3.3V 200mA MultiFunction Pin (GPIO) Controller Power Management Control 1 to 4MHz RC Oscillator W WM8312 LDO 3 Standard LDO 0.9 to 3.3V 200mA LDO 4 Standard LDO 0.9 to 3.3V 100mA LDO 5 Standard LDO 0.9 to 3.3V 100mA LDO 6 Standard LDO 0.9 to 3.3V 100mA LDO 7 Analogue LDO 1.0 to 3.5V 200mA LDO 8 Analogue LDO 1.0 to 3.5V 200mA PM SubSystem Monitoring AP Interface, GPIOs and PM Control 4/5-Wire Resistive Touch-Panel Interface LDO 9 Analogue LDO 1.0 to 3.5V 150mA LDO 10 Analogue LDO 1.0 to 3.5V 150mA LDO 11 Alive LDO 0.8 to 1.55V 10mA Aux ADC LDO 12 Internal LDO 2.1V 10mA LDO 13 Internal LDO 2.5V 50mA Supply Voltage and Battery Monitor WALLVDD 32.768kHz Oscillator Real-Time Clock Wake-Up Timer USBVDD Battery Charger 1A Backup Battery Charger References Power Management Power Path Management Switching Matrix BATTVDD BATTFETENA WALLVDD WALLFETENA BACKUPVDD VREFC IREFR REFGND FLL Auxiliary Functions w PP, December 2009, Rev 3.0 2 Pre-Production WM8312 TYPICAL APPLICATIONS The WM8312 is designed as a system PMIC device that manages multiple power supply paths (wall adapter, USB, battery) and generates configurable DC supplies to power processors and associated peripherals within a system. The WM8312 provides three step-down DC-DC converters and one step-up DC-DC converter. Eleven LDO regulators provide a high degree of flexibility to provide power to multiple devices, with the capability to power-up and power-down different circuits independently. Two of the DC-DC step-down converters are specifically designed to handle rapid changes in load current, as required by modern application processors; selectable operating modes allow the converters to be optimally configured for light, heavy or transient load conditions; they can also be tailored for minimum PCB area, maximum performance, or for maximum efficiency. The analogue LDOs provide low-noise outputs suitable for powering sensitive circuits such as RF / Wi-Fi / cellular handset applications. The WM8312 powers up the converters and LDOs according to a programmable sequence. A configurable `SLEEP' state is also available, providing support for an alternate configuration, typically for low-power / standby operation. The power control sequences and many other parameters can be stored in an integrated user-programmable OTP memory or may be loaded from an external memory. The WM8312 supports the programming and verification of the integrated OTP memory. The WM8312 provides power path management which seamlessly switches between wall adapter, USB and battery power sources according to the prevailing conditions. A backup battery supply is also supported in order to maintain the Real Time Clock (RTC) in the absence of any other supplies. The WM8312 provides a battery charger for the main battery aswell as the backup battery; these can be powered from either the wall adapter or USB supplies. Programmable GPIO pins may be configured as hardware inputs for general use or for selecting different power management configurations. As outputs, the GPIOs can provide indications of the device status, or may be used as control signals for other power management circuits. The WM8312 also provides two LED drivers, which can be controlled manually or configured as status indicators for the OTP memory programmer, operating power state or battery charger. w PP, December 2009, Rev 3.0 3 WM8312 TABLE OF CONTENTS Pre-Production DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 2 TYPICAL APPLICATIONS ..................................................................................... 3 TABLE OF CONTENTS ......................................................................................... 4 1 PIN CONFIGURATION .................................................................................. 9 2 ORDERING INFORMATION .......................................................................... 9 3 PIN DESCRIPTION ...................................................................................... 10 4 THERMAL CHARACTERISTICS ................................................................. 14 5 ABSOLUTE MAXIMUM RATINGS .............................................................. 15 6 RECOMMENDED OPERATING CONDITIONS ........................................... 16 7 ELECTRICAL CHARACTERISTICS ............................................................ 17 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 DC-DC STEP DOWN CONVERTERS ............................................................... 17 DC-DC STEP UP CONVERTER ........................................................................ 18 CURRENT SINKS .............................................................................................. 19 LDO REGULATORS .......................................................................................... 19 RESET THRESHOLDS...................................................................................... 23 REFERENCES .................................................................................................. 23 BATTERY CHARGER........................................................................................ 23 BACKUP BATTERY CHARGER ........................................................................ 24 USB POWER CONTROL .................................................................................. 25 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ...................................... 25 DIGITAL INTERFACES .................................................................................. 25 AUXILIARY ADC ............................................................................................ 25 TOUCH PANEL CONTROLLER ..................................................................... 26 SYSTEM STATUS LED DRIVERS ................................................................. 26 CLOCKING ..................................................................................................... 26 8 9 9.1 9.2 TYPICAL POWER CONSUMPTION ............................................................ 27 TYPICAL PERFORMANCE DATA............................................................... 28 DC-DC CONVERTERS...................................................................................... 28 LDO REGULATORS .......................................................................................... 28 10 11 SIGNAL TIMING REQUIREMENTS............................................................. 29 CONTROL INTERFACE ................................................................................. 29 GENERAL DESCRIPTION ............................................................................. 31 POWER STATES ........................................................................................... 31 POWER STATE CONTROL ........................................................................... 33 POWER STATE INTERRUPTS ...................................................................... 38 POWER STATE GPIO INDICATION .............................................................. 38 ON PIN FUNCTION ........................................................................................ 39 RESET PIN FUNCTION ................................................................................. 40 GENERAL DESCRIPTION ............................................................................. 42 2-WIRE (I2C) CONTROL MODE .................................................................... 42 4-WIRE (SPI) CONTROL MODE .................................................................... 45 REGISTER LOCKING .................................................................................... 45 PP, December 2009, Rev 3.0 4 10.1 11.1 11.2 11.3 11.4 11.5 11.6 11.7 DEVICE DESCRIPTION .............................................................................. 31 12 CONTROL INTERFACE .............................................................................. 42 12.1 12.2 12.3 12.4 w Pre-Production WM8312 12.5 12.6 SOFTWARE RESET AND CHIP ID ................................................................ 46 SOFTWARE SCRATCH REGISTER .............................................................. 46 GENERAL DESCRIPTION ............................................................................. 47 CRYSTAL OSCILLATOR................................................................................ 49 FREQUENCY LOCKED LOOP (FLL) ............................................................. 50 FLL AUTO MODE ................................................................................................................ 53 13 CLOCKING AND OSCILLATOR CONTROL ............................................... 47 13.1 13.2 13.3 13.3.1 14 BOOTSTRAPPING AND OTP MEMORY CONTROL.................................. 54 GENERAL DESCRIPTION ............................................................................. 54 DBE AND OTP MEMORY DEFINITION ......................................................... 54 BOOTSTRAP (START-UP) FUNCTION ......................................................... 55 START-UP FROM OTP MEMORY....................................................................................... 55 START-UP FROM DBE MEMORY (DEVELOPMENT MODE) ............................................. 56 START-UP FROM DORW REGISTER SETTINGS ............................................................. 56 EXTERNAL DBE MEMORY CONNECTION ........................................................................ 56 ENTERING / EXITING THE PROGRAM STATE.................................................................. 58 OTP / DBE READ COMMAND ............................................................................................. 58 OTP WRITE COMMAND ..................................................................................................... 58 OTP VERIFY COMMAND .................................................................................................... 59 OTP FINALISE COMMAND ................................................................................................. 60 OTP CONTROL REGISTER ................................................................................................ 60 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.4 OTP / DBE MEMORY CONTROL ................................................................... 57 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.5 14.6 OTP / DBE INTERRUPTS .............................................................................. 61 DORW MEMORY CONTENTS ....................................................................... 62 DORW DORW DORW DORW DORW PAGE 0.................................................................................................................... 62 PAGE 1.................................................................................................................... 62 PAGE 2.................................................................................................................... 62 PAGE 3.................................................................................................................... 64 PAGE 4.................................................................................................................... 66 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 15 POWER MANAGEMENT ............................................................................. 67 GENERAL DESCRIPTION ............................................................................. 67 DC-DC CONVERTER AND LDO REGULATOR ENABLE .............................. 67 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL ........ 68 OPERATING MODE CONTROL..................................................................... 69 DC-DC BUCK CONVERTERS ............................................................................................. 69 DC-DC BOOST CONVERTERS .......................................................................................... 69 LDO REGULATORS ............................................................................................................ 69 DC-DC BUCK CONVERTERS ............................................................................................. 70 DC-DC BOOST CONVERTERS .......................................................................................... 70 LDO REGULATORS 1-10 .................................................................................................... 70 LDO REGULATOR 11 ......................................................................................................... 70 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.5 OUTPUT VOLTAGE CONTROL..................................................................... 70 15.5.1 15.5.2 15.5.3 15.5.4 15.6 15.7 15.8 15.9 15.10 15.11 15.12 DC-DC BUCK CONVERTER CONTROL ........................................................ 71 DC-DC BOOST CONVERTER CONTROL ..................................................... 72 LDO REGULATOR CONTROL ....................................................................... 72 HARDWARE CONTROL (GPIO) .................................................................... 72 FAULT PROTECTION .................................................................................... 73 MONITORING AND FAULT REPORTING...................................................... 74 POWER MANAGEMENT REGISTER DEFINITIONS ..................................... 74 DC-DC CONVERTER AND LDO REGULATOR ENABLE ............................................... 74 DC-DC (BUCK) CONVERTER CONTROL ...................................................................... 75 DC-DC (BOOST) CONVERTER CONTROL .................................................................... 80 LDO REGULATOR CONTROL ........................................................................................ 80 EXTERNAL POWER ENABLE (EPE) CONTROL............................................................ 88 PP, December 2009, Rev 3.0 5 15.12.1 15.12.2 15.12.3 15.12.4 15.12.5 w WM8312 15.12.6 Pre-Production MONITORING AND FAULT REPORTING ....................................................................... 89 15.13 15.14 15.15 POWER MANAGEMENT INTERRUPTS ........................................................ 90 POWER GOOD INDICATION ........................................................................ 91 DC-DC CONVERTER OPERATION ............................................................... 92 OVERVIEW...................................................................................................................... 92 DC-DC STEP DOWN CONVERTERS ............................................................................. 92 DC-DC STEP UP CONVERTER ...................................................................................... 96 OVERVIEW...................................................................................................................... 97 LDO REGULATORS ........................................................................................................ 97 15.15.1 15.15.2 15.15.3 15.16 LDO REGULATOR OPERATION ................................................................... 97 15.16.1 15.16.2 16 CURRENT SINKS ........................................................................................ 98 GENERAL DESCRIPTION ............................................................................. 98 CURRENT SINK CONTROL .......................................................................... 98 ENABLING THE SINK CURRENT ....................................................................................... 98 PROGRAMMING THE SINK CURRENT.............................................................................. 99 ON/OFF RAMP TIMING ..................................................................................................... 100 16.2.1 16.2.2 16.2.3 16.1 16.2 16.3 16.4 CURRENT SINK INTERRUPTS ................................................................... 101 LED DRIVER CONNECTIONS ..................................................................... 102 GENERAL DESCRIPTION ........................................................................... 103 BATTERY POWERED OPERATION ............................................................ 105 WALL ADAPTOR POWERED OPERATION ................................................ 105 USB POWERED OPERATION ..................................................................... 106 POWER PATH MANAGEMENT INTERRUPTS............................................ 107 BACKUP POWER ........................................................................................ 108 BATTERY CHARGER .................................................................................. 109 GENERAL DESCRIPTION................................................................................................. 109 BATTERY CHARGER ENABLE ......................................................................................... 111 FAST CHARGING .............................................................................................................. 112 CHARGER TIMEOUT AND TERMINATION ...................................................................... 113 BATTERY CHARGE CURRENT MONITORING ................................................................ 115 BATTERY FAULT / OVERVOLTAGE CONDITIONS ......................................................... 116 BATTERY TEMPERATURE MONITORING ....................................................................... 116 BATTERY CHARGER INTERRUPTS ................................................................................ 117 BATTERY CHARGER STATUS ......................................................................................... 119 17 POWER SUPPLY CONTROL .................................................................... 103 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.7.8 17.7.9 18 AUXILIARY ADC ........................................................................................ 120 GENERAL DESCRIPTION ........................................................................... 120 AUXADC CONTROL .................................................................................... 120 AUXADC READBACK .................................................................................. 122 DIGITAL COMPARATORS ........................................................................... 123 AUXADC INTERRUPTS ............................................................................... 126 GENERAL DESCRIPTION ........................................................................... 127 TOUCH PANEL CONFIGURATION ............................................................. 127 TOUCH PANEL CONTROL .......................................................................... 128 TOUCH PANEL READBACK ........................................................................ 130 TOUCH PANEL INTERRUPTS..................................................................... 130 TOUCH PANEL OPERATING PRINCIPLES ................................................ 131 4-WIRE TOUCH PANEL OPERATION .............................................................................. 131 5-WIRE TOUCH PANEL OPERATION .............................................................................. 133 18.1 18.2 18.3 18.4 18.5 19 TOUCH PANEL CONTROLLER ................................................................ 127 19.1 19.2 19.3 19.4 19.5 19.6 19.6.1 19.6.2 20 REAL-TIME CLOCK (RTC)........................................................................ 135 GENERAL DESCRIPTION ........................................................................... 135 RTC CONTROL ............................................................................................ 135 PP, December 2009, Rev 3.0 6 20.1 20.2 w Pre-Production WM8312 20.3 20.4 20.5 RTC INTERRUPTS ...................................................................................... 137 DIGITAL RIGHTS MANAGEMENT ............................................................... 138 BACKUP MODE CLOCKING OPTIONS ....................................................... 138 GENERAL DESCRIPTION ........................................................................... 139 GPIO FUNCTIONS ....................................................................................... 139 CONFIGURING GPIO PINS ......................................................................... 141 GPIO INTERRUPTS ..................................................................................... 145 GENERAL DESCRIPTION ........................................................................... 146 LED DRIVER CONTROL .............................................................................. 146 OTP PROGAM STATUS .................................................................................................... 146 POWER STATE STATUS .................................................................................................. 147 CHARGER STATUS .......................................................................................................... 147 MANUAL MODE................................................................................................................. 148 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ................................. 139 21.1 21.2 21.3 21.4 22 SYSTEM STATUS LED DRIVERS ............................................................ 146 22.2.1 22.2.2 22.2.3 22.2.4 22.1 22.2 22.3 LED DRIVER CONNECTIONS ..................................................................... 149 PRIMARY INTERRUPTS .............................................................................. 151 SECONDARY INTERRUPTS ....................................................................... 153 POWER STATE INTERRUPT............................................................................................ 153 THERMAL INTERRUPTS .................................................................................................. 154 GPIO INTERRUPTS .......................................................................................................... 154 ON PIN INTERRUPTS ....................................................................................................... 155 WATCHDOG INTERRUPTS .............................................................................................. 155 TOUCH PANEL DATA INTERRUPTS ............................................................................... 156 TOUCH PANEL PEN DOWN INTERRUPTS ..................................................................... 156 AUXADC INTERRUPTS .................................................................................................... 156 POWER PATH MANAGEMENT INTERRUPTS ................................................................. 157 CURRENT SINK INTERRUPTS..................................................................................... 157 REAL TIME CLOCK INTERRUPTS ............................................................................... 158 OTP MEMORY INTERRUPTS ....................................................................................... 158 RESERVED ................................................................................................................... 159 BATTERY CHARGER INTERRUPTS ............................................................................ 159 HIGH CURRENT INTERRUPTS .................................................................................... 160 UNDERVOLTAGE INTERRUPTS .................................................................................. 161 23 INTERRUPT CONTROLLER ..................................................................... 150 23.2.1 23.2.2 23.2.3 23.2.4 23.2.5 23.2.6 23.2.7 23.2.8 23.2.9 23.2.10 23.2.11 23.2.12 23.2.13 23.2.14 23.2.15 23.2.16 23.1 23.2 24 RESETS AND SUPPLY VOLTAGE MONITORING ................................... 162 RESETS ....................................................................................................... 162 HARDWARE RESET .................................................................................... 164 SOFTWARE RESET .................................................................................... 164 SUPPLY VOLTAGE MONITORING .............................................................. 166 24.1 24.2 24.3 24.4 25 26 27 28 29 30 WATCHDOG TIMER .................................................................................. 168 TEMPERATURE SENSING ....................................................................... 170 VOLTAGE AND CURRENT REFERENCES.............................................. 171 VOLTAGE REFERENCE (VREF) ................................................................. 171 CURRENT REFERENCE (IREF) .................................................................. 171 27.1 27.2 REGISTER MAP OVERVIEW .................................................................... 172 REGISTER BITS BY ADDRESS................................................................ 179 APPLICATIONS INFORMATION ............................................................... 292 TYPICAL CONNECTIONS ........................................................................... 292 VOLTAGE AND CURRENT REFERENCE COMPONENTS ......................... 293 DC-DC (STEP-DOWN) CONVERTER EXTERNAL COMPONENTS ............ 293 DC-DC (STEP-UP) CONVERTER EXTERNAL COMPONENTS .................. 295 LDO REGULATOR EXTERNAL COMPONENTS ......................................... 297 PP, December 2009, Rev 3.0 7 30.1 30.2 30.3 30.4 30.5 w WM8312 30.6 30.7 Pre-Production BATTERY TEMPERATURE MONITORING COMPONENTS ....................... 298 PCB LAYOUT ............................................................................................... 301 31 32 PACKAGE DIAGRAM ................................................................................ 302 IMPORTANT NOTICE ................................................................................ 303 w PP, December 2009, Rev 3.0 8 Pre-Production WM8312 1 PIN CONFIGURATION 1 A BATTFETEN A_N 2 PVDD1 3 DC3FB 4 DC3VDD 5 DC3LX 6 DC3GND 7 DC2VDD 8 DC2LX 9 DC2GND 10 DC1GND 11 DC1LX 12 DC1VDD 13 DC1FB A B GND GND GND DC3VDD DC3LX DC3GND DC2VDD DC2LX DC2GND DC1GND DC1LX DC1VDD GND B C LDO6VDD LDO6VOUT GND GND DNC DC2FB GND GND GND GND GND GND IRQ_N C D LDO5VDD LDO5VOUT GND PROGVDD SDOUT1 GND SDA1 SCLK1 DBVDD1 CS_N RESET_N GND GPIO2 D E LDO4VDD LDO4VOUT GND GND GPIO1 GPIO3 GPIO7 GPIO8 DBVDD1 LDO13VOUT DC4FB GND GPIO9 E F LDO10VDD LDO10VOUT LDO9VOUT GND GND GND GPIO5 GPIO6 GPIO4 GND GND GND DC4VDD F G LDO8VDD LDO9VDD LDO8VOUT GND AUXADCIN4 GND GND GND GND GPIO12 GPIO11 DC4LX DC4GND G H LDO7VDD LDO7VOUT DNC NTCBIAS NTCMON VREFC GND SDA2 BACKUPVD D GPIO14 GPIO13 GPIO10 TPGND H J LDO3VDD LDO3VOUT CIFMODE WALLVDD SYSVDD SYSVDD USBVMON IREFR AUXADCIN1 GND LED1 TPVDD GPIO16 J K LDO2VDD LDO2VOUT DBGND WALLFETE NA_N SYSVDD SYSVDD USBVDD BATTVMON GND GND LED2 GPIO15 LDO11VOUT K L LDO1VDD LDO1VOUT DBGND CLKOUT USBVDD BATTVDD SYSVDD GND GND XTI ISINKGND ISINK2 REFGND L M GND DNC DNC DBGND USBVDD GND GND GND SCLK2 XTO ISINKGND ISINK1 AUXADCIN2 M N DNC DNC DBVDD2 CLKIN SYSVMON SYSVDD BATTVDD USBVDD PVDD2 LDO12VOUT ON_N XOSCGND AUXADCIN3 N 7x7 BGA - TOP VIEW (WM8312) 2 ORDERING INFORMATION TEMPERATURE RANGE (TA) -40C to +85C -40C to +85C PACKAGE 169-ball (7 x 7mm) (Pb-free) 169-ball (7 x 7mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260C 260C ORDER CODE WM8312GEB/V WM8312GEB/RV Note: Reel quantity = 2200 w PP, December 2009, Rev 3.0 9 WM8312 3 1. 2. Pre-Production PIN DESCRIPTION Pins are sorted by functional groups. The power domain associated with each pin is noted; VPMIC is the domain powered by LDO12 for the `always-on' functions internal to the WM8312. PIN NAME TYPE POWER DOMAIN USBVDD SYSVDD BATTVDD DESCRIPTION Notes: Touch Panel and Auxiliary ADC J7 N5 K8 J9 M13 N13 G5 J12 H13 M10 L10 N12 L4 N4 E5 D13 E6 F9 F7 F8 E7 E8 E13 H12 G11 G10 H11 H10 K12 J13 USBVMON SYSVMON BATTVMON AUXADCIN1 AUXADCIN2 AUXADCIN3 AUXADCIN4 TPVDD TPGND XTO XTI XOSCGND CLKOUT CLKIN GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 Analogue Input Analogue Input Analogue Input Analogue Input/Output Analogue Input Analogue Input Analogue Input Supply Supply Analogue Output Analogue Input Supply Digital Output Digital Input Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O TPVDD DBVDD2 TPVDD USBVDD Supply Voltage Monitor SYSVDD Supply Voltage Monitor BATTVDD Supply Voltage Monitor Auxiliary Analogue Input 1 / Battery Charge Current Monitor Output Auxiliary Analogue Input 2 Auxiliary Analogue Input 3 Auxiliary Analogue Input 4 Touch panel VDD supply Touch panel Power Ground Crystal Drive Output Crystal Drive Input or 32.768kHz CMOS Clock Input Crystal Oscillator Ground CMOS Clock Output CMOS FLL Clock Input GPIO Pin 1 GPIO Pin 2 GPIO Pin 3 GPIO Pin 4 GPIO Pin 5 GPIO Pin 6 GPIO Pin 7 GPIO Pin 8 GPIO Pin 9 GPIO Pin 10 GPIO Pin 11 GPIO Pin 12 GPIO Pin 13 / Touch panel interface GPIO Pin 14 / Touch panel interface GPIO Pin 15 / Touch panel interface GPIO Pin 16 / Touch panel interface ON Request Pin (Internal pull-up) System Reset Input and Open Drain Output. (Internal pull-up) PMIC Interrupt Flag Output. Configurable Open Drain / CMOS mode. (Internal pull-up in Open Drain mode.) SYSVDD Clocking and Real Time Clock VPMIC General Purpose Input / Output DBVDD1 or VPMIC DBVDD1 or SYSVDD DBVDD1 or VPMIC DBVDD1 or SYSVDD Processor Interface and IC Control N11 D11 ON RESET Digital Input Digital I/O VPMIC DBVDD1 C13 IRQ Digital Output DBVDD1 w PP, December 2009, Rev 3.0 10 Pre-Production PIN NAME TYPE POWER DOMAIN DBVDD2 DESCRIPTION WM8312 J3 CIFMODE Digital Input Primary Control Interface Mode Select: 0 = I2C Compatible Control Interface Mode 1 = SPI Compatible Control Interface Mode SPI Compatible Control Interface Mode I2C Compatible Control Interface Mode No Function Control Interface Serial Clock Control Interface Serial Data Input and Open Drain Output. (Output can extend above DBVDD1 domain.) I2C Address Select: 0 = 68h 1 = 6Ch D5 D8 SDOUT1 SCLK1 Digital Output Digital Input Control Interface Serial Data Out Control Interface Serial Clock Control Interface Serial Data In D7 SDA1 Digital I/O DBVDD1 D10 CS Digital Input Control Interface Chip Select M9 SCLK2 Digital I/O VPMIC Control Interface Serial Clock for external DBE EEPROM (Internal pull-down) Control Interface Serial Data to/from external DBE EEPROM (Internal pull-down) Digital Buffer Supply Digital Buffer Supply Digital Buffer Ground High-voltage input for OTP programming. H8 D9, E9 N3 K3, L3, M4 OTP Memory D4 B1, B2, B3, B13, C3, C4, C7, C8, C9, C10, C11, C12, D3, D6, D12, E3, E4, E12, F4, F5, F6, F10, F11, F12, G4, G6, G7, G8, G9, H7, J10, K9, K10, L8, L9, M1, M6, M7, M8 A2 N9 A10, B10 A13 A11, B11 A12, B12 A9, B9 C6 SDA2 DBVDD1 DBVDD2 DBGND PROGVDD Digital I/O Supply Supply Supply Supply DC-DC Converters and LDO Regulators GND1 Supply Ground PVDD1 PVDD2 DC1GND DC1FB DC1LX DC1VDD DC2GND DC2FB Supply Supply Supply Analogue Input Analogue I/O Supply Supply Analogue Input DC2VDD DC1VDD Internal VDD supply; Connect to SYSVDD DC-DC1 Power Ground DC-DC1 Feedback Pin DC-DC1 Inductor Connection DC-DC1 Power Input DC-DC2 Power Ground DC-DC2 Feedback Pin PP, December 2009, Rev 3.0 11 w WM8312 PIN A8, B8 A7, B7 A6, B6 A3 A5, B5 A4, B4 G13 E11 G12 F13 L1 L2 K1 K2 J1 J2 E1 E2 D1 D2 C1 C2 H1 H2 G1 G3 G2 F3 F1 F2 K13 N10 E10 Current Sinks M12 L12 L11, M11 H6 J8 L13 J5, J6, K5, K6, L7, N6 K7, L5, M5, N8 L6, N7 A1 J4 ISINK1 ISINK2 ISINKGND VREFC IREFR REFGND Analogue Output Analogue Output Supply Analogue I/O Analogue I/O Supply SYSVDD LED String Current Sink 1 LED String Current Sink 2 LED String Current Sink Ground NAME DC2LX DC2VDD DC3GND DC3FB DC3LX DC3VDD DC4GND DC4FB DC4LX DC4VDD LDO1VDD LDO1VOUT LDO2VDD LDO2VOUT LDO3VDD LDO3VOUT LDO4VDD LDO4VOUT LDO5VDD LDO5VOUT LDO6VDD LDO6VOUT LDO7VDD LDO7VOUT LDO8VDD LDO8VOUT LDO9VDD LDO9VOUT LDO10VDD LDO10VOUT LDO11VOUT LDO12VOUT LDO13VOUT TYPE Analogue I/O Supply Supply Analogue Input Analogue I/O Supply Supply Analogue Input Analogue I/O Supply Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Supply Analogue Output Analogue Output Analogue I/O Analogue I/O LDO10VDD PVDD2 PVDD2 PVDD2 LDO9VDD LDO8VDD LDO7VDD LDO6VDD LDO5VDD LDO4VDD LDO3VDD LDO2VDD LDO1VDD DC4VDD DC3VDD POWER DOMAIN DESCRIPTION DC-DC2 Inductor Connection DC-DC2 Power Input DC-DC3 Power Ground DC-DC3 Feedback Pin DC-DC3 Inductor Connection DC-DC3 Power Input DC-DC4 Power Ground DC-DC4 Feedback Connection DC-DC4 Inductor Connection DC-DC4 Power Input LDO1 Power Input LDO1 Power Output LDO2 Power Input LDO2 Power Output LDO3 Power Input LDO3 Power Output LDO4 Power Input LDO4 Power Output LDO5 Power Input LDO5 Power Output LDO6 Power Input LDO6 Power Output LDO7 Power Input LDO7 Power Output LDO8 Power Input LDO8 Power Output LDO9 Power Input LDO9 Power Output LDO10 Power Input LDO10 Power Output LDO11 (Alive) Power Output Pre-Production LDO12 (Internal VPMIC) Output; not for general use LDO13 (Internal INTVDD) Output; not for general use Voltage and Current References VPMIC Voltage Reference capacitor connection point Current Reference resistor connection point Reference Ground Power Path Management SYSVDD USBVDD BATTVDD BATTFETENA WALLVDD Supply Supply Supply Digital Output Supply PVDD1 System VDD Supply USB VDD Supply Primary Battery Supply External Battery FET Driver Wall VDD Supply/Sense w PP, December 2009, Rev 3.0 12 Pre-Production PIN NAME TYPE POWER DOMAIN highest VDD supply VPMIC DESCRIPTION WM8312 K4 H4 H5 H9 J11 K11 WALLFETENA NTCBIAS NTCMON BACKUPVDD LED1 LED2 Digital Output Analogue Output Analogue Input Supply Digital Output Digital Output External Wall FET Driver. Power domain is the highest out of WALLVDD, USBVDD or BATTVDD. Battery NTC Temperature Monitor Supply Battery NTC Temperature Monitor Voltage Sense Input Secondary (Backup) Battery Supply Status LED Driver 1. Open Drain Output Status LED Driver 2. Open Drain Output System LED Drivers SYSVDD Do Not Connect C5, H3, M2, M3, N1, N2 DNC Do Not Connect w PP, December 2009, Rev 3.0 13 WM8312 4 THERMAL CHARACTERISTICS Pre-Production Thermal analysis must be performed in the intended application to prevent the WM8312 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction. Three main heat transfer paths exist to surrounding air: Package top to air (radiation). Package bottom to PCB (radiation). Package leads to PCB (conduction). The temperature rise TR is given by TR = PD * JA PD is the power dissipated by the device. JA is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. For WM8312, JA = 45C/W The quoted JA is based on testing to the EIA/JEDEC-51-2 test environment (ie. 1ft3 box, still air, with specific PCB stack-up and tracking rules). Note that this is not guaranteed to reflect all typical end applications. The junction temperature TJ is given by TJ = TA + TR TA, is the ambient temperature. The worst case conditions are when the WM8312 is operating in a high ambient temperature, with low supply voltage, high duty cycle and high output current. Under such conditions, it is possible that the heat dissipated could exceed the maximum junction temperature of the device. Care must be taken to avoid this situation. An example calculation of the junction temperature is given below. PD = 500mW (example figure) JA = 45C/W TR = PD * JA = 22.5C TA = 85C (example figure) TJ = TA +TR = 107.5C The minimum and maximum operating junction temperatures for the WM8312 are quoted in Section 5. The maximum junction temperature is 125C. Therefore, the junction temperature in the above example is within the operating limits of the WM8312. w PP, December 2009, Rev 3.0 14 Pre-Production WM8312 5 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The WM8312 has been classified as MSL3. CONDITION OTP Programming Supply (PROGVDD) BATTVDD, WALLVDD and USBVDD supplies BACKUPVDD Input voltage for LDO regulators Input voltage for DC-DC converters Digital buffer supply (DBVDD1, DBVDD2) Voltage range for digital inputs Operating Temperature Range, TA Junction Temperature, TJ Thermal Impedance Junction to Ambient, JA Storage temperature prior to soldering Storage temperature after soldering Soldering temperature (10 seconds) Note: These ratings assume that all ground pins are at 0V. -65C MIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -40C -40C MAX 7.0V 7.0V 4.5V 7.0V 7.0V 4.5V DBVDD + 0.3V +85C +125C 45C/W 30oC max / 60% RH max +150C +260C w PP, December 2009, Rev 3.0 15 WM8312 6 RECOMMENDED OPERATING CONDITIONS PARAMETER Wall Input power source Battery Input power source USB Input power source Backup Battery power source Digital buffer supply Touch Panel supply (see note 1) OTP Programming Supply (see note2) Ground SYMBOL WALLVDD BATTVDD USBVDD BACKUPVDD DBVDD1, DBVDD2 TPVDD PROGVDD LDO12VOUT GND, DBGND, TPGND, XOSCGND, REFGND 1.71 1.71 6.25 2.5 6.5 3.3 0 MIN 4.3 2.7 4.3 TYP MAX 5.5 5.5 5.5 3.6 3.6 3.6 6.75 Pre-Production UNITS V V V V V V V V V Notes: 1. When the Touch Panel Controller is enabled, then TPVDD must be connected to LDO13VOUT (2.5V). The min/max TPVDD conditions noted above do not apply when the Touch Panel Controller is enabled. (Note that, when the Touch Panel is not enabled, TPVDD is the power domain for GPIO pins 13-16.) The OTP Programming Supply PROGVDD should only be present when programming the OTP. At other times, this pin should be left unconnected. The LDO12VOUT must be overdriven by an external supply when programming the OTP. At other times, the voltage at this pin is driven by the internal circuits of the WM8312. 2. w PP, December 2009, Rev 3.0 16 Pre-Production WM8312 7 7.1 ELECTRICAL CHARACTERISTICS DC-DC STEP DOWN CONVERTERS DC-DC1 and DC-DC2 Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, MODE = FCCM(1), TA = -40C to +85C; typical values are at TA = 25C PARAMETER Input Voltage Programmable Output Voltage VOUT Step Size VOUT Accuracy Output Current SYMBOL VIN VOUT VOUT_STEP VOUT_ACC IOUT VIN = 2.7V to 5.5V, IOUT = 0mA to 1200mA FCCM(1) and CCM/DCM with PS(2) Modes Hysteretic Mode LDO Mode P-channel Current Limit Quiescent Current IP_LIM IQ FSW = 2MHz FSW = 4MHz IOUT = 0mA, FCCM(1) and CCM/DCM with PS(2) Modes (excluding switching losses) IOUT = 0mA, Hysteretic Mode IOUT = 0mA, LDO Mode Shutdown Current P-channel On Resistance N-channel On Resistance Switching Frequency Notes: 1. 2. Forced Continuous Conduction Mode Continuous / Discontinous Conduction with Pulse-Skipping Mode ISD RDSP RDSN FSW DCm_ENA = 0 VIN = VGS = 3.8V, IDCmLX = 100mA VIN = VGS = 3.8V, IDCmLX = -100mA DCm_FREQ = 01 DCm_FREQ = 11 -3 0 0 0 1800 2000 500 70 25 0.01 140 130 2 4 A m m MHz A FSW = 2MHz FSW = 4MHz TEST CONDITIONS MIN 2.7 0.6 0.6 12.5 3 1200 150 10 mA TYP MAX 5.5 1.8 1.4 mV % mA UNIT V V w PP, December 2009, Rev 3.0 17 WM8312 Pre-Production DC-DC3 Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, MODE = FCCM(1), TA = -40C to +85C; typical values are at TA = 25C PARAMETER Input Voltage Programmable Output Voltage VOUT Step Size VOUT Accuracy Output Current SYMBOL VIN VOUT VOUT_STEP VOUT_ACC IOUT VIN = 2.7V to 5.5V, IOUT = 0mA to 1000mA FCCM(1) and CCM/DCM with PS(2) Modes Hysteretic Mode, DC3_STBY_LIM=01 LDO Mode P-channel Current Limit Quiescent Current IP_LIM IQ IOUT = 0mA, FCCM and CCM/DCM with PS Modes (excluding switching losses) IOUT = 0mA, Hysteretic Mode IOUT = 0mA, LDO Mode Shutdown Current P-channel On Resistance N-channel On Resistance Switching Frequency Notes: 1. 2. Forced Continuous Conduction Mode Continuous / Discontinous Conduction with Pulse-Skipping Mode ISD RDSP RDSN FSW DC3_ENA = 0 VIN = VGS = 3.8V, IDC3LX = 100mA VIN = VGS = 3.8V, IDC3LX = -100mA (1) (2) TEST CONDITIONS MIN 2.7 0.85 TYP MAX 5.5 3.4 UNIT V V mV 25 -4 0 0 0 1800 280 90 30 0.01 140 130 2 4 1000 200 10 % mA mA A A m m MHz 7.2 DC-DC STEP UP CONVERTER DC-DC4 Unless otherwise noted: VIN = 3.8V, TA = -40C to +85C; typical values are at TA = 25C PARAMETER Input Voltage Output Voltage Load Current Quiescent Current Shutdown Current N-channel On Resistance Regulated feedback voltage Out of regulation level Overvoltage detection Switching frequency SYMBOL VIN VOUT ILOAD IQ ISD RDSN VISINKn 500 VISINKn VDC4FB FSW 440 500 1 mV mV MHz VOUT = 6.5V to 20V VOUT = 20V to 30V DC4_ENA=1 DC4_ENA=0 TEST CONDITIONS MIN 2.7 6.5 0 0 330 0.1 150 1 TYP MAX 5.5 30 40 25 A A m mV UNIT V V mA w PP, December 2009, Rev 3.0 18 Pre-Production PARAMETER N-channel Current limit SYMBOL IN_LIM TEST CONDITIONS MIN TYP 800 MAX WM8312 UNIT mA 7.3 CURRENT SINKS PARAMETER SYMBOL IISINKn IISINKn IISINKn TEST CONDITIONS 0.3 <= VISINKn <= SYSVDD IISINKn =12mA, VISINKn = 0.5V IISINKn =12mA, VISINKn = 0.5V MIN 2 TBD TBD TYP MAX 28000 UNIT A V Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C Sink Current Current Accuracy Current matching 7.4 LDO REGULATORS LDO1 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input Voltage Programmable Output Voltage Output Current SYMBOL VIN VOUT IOUT Normal mode Low power mode, LDOn_LP_MODE=0 Low power mode, LDOn_LP_MODE=1 VOUT Accuracy Line Regulation Load Regulation Dropout Voltage VOUT_ACC VOUT LINE VOUT LOAD VIN - VOUT ILOAD = 10mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 150mA Note that VIN must be >= 1.5V ILOAD =1mA to 300mA ILOAD =150mA, VOUT > 2.7V ILOAD =150mA, VOUT 1.8V to 2.7V ILOAD =150mA, VOUT < 1.8V Undervoltage level Quiescent Current VOUT IQ VOUT Falling Normal mode, no load Low power mode, LDOn_LP_MODE=0, no load Low power mode, LDOn_LP_MODE=1, no load ILOAD = 1mA to 300mA Power Supply Rejection Ratio On Resistance (Switch mode) PSRR ILOAD = 25mA, <= 1kHz ILOAD = 25mA, 10kHz ILOAD = 25mA, 100kHz RDSON VIN = 1.5V, ILOAD = 100mA VIN = 1.8V, ILOAD = 100mA VIN = 2.5V, ILOAD = 100mA VIN = 3.3V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time ICL tstart_up tshut_down VOUT = 0V No load, Output cap 2.2 F, 90% of VOUT No load, Output cap 2.2 F, 10% of VOUT TEST CONDITIONS MIN 1.5 0.9 0 0 0 -3 0.1 0.015 250 300 500 88 30 10 5 IQ (no load) + 1% of load 50 TBD TBD 1.5 1.2 0.85 0.7 600 10 10 mA s ms dB % A TYP MAX 5.5 3.3 300 50 20 3 % %/V %/mA mV UNIT V V mA w PP, December 2009, Rev 3.0 19 WM8312 LDO2, LDO3 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input Voltage Programmable Output Voltage Output Current SYMBOL VIN VOUT IOUT Normal mode Low power mode, LDOn_LP_MODE=0 Low power mode, LDOn_LP_MODE=1 VOUT Accuracy Line Regulation Load Regulation Dropout Voltage VOUT_ACC VOUT LINE VOUT LOAD VIN - VOUT ILOAD = 10mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA Note that VIN must be >= 1.5V ILOAD =1mA to 200mA ILOAD =100mA, VOUT > 2.7V ILOAD =100mA, VOUT 1.8V to 2.7V ILOAD =100mA, VOUT < 1.8V Undervoltage level Quiescent Current VOUT IQ VOUT Falling Normal mode, no load Low power mode, LDOn_LP_MODE=0, no load Low power mode, LDOn_LP_MODE=1, no load ILOAD = 1mA to 200mA Power Supply Rejection Ratio On Resistance (Switch mode) PSRR ILOAD = 25mA, <= 1kHz ILOAD = 25mA, 10kHz ILOAD = 25mA, 100kHz RDSON VIN = 1.5V, ILOAD = 100mA VIN = 1.8V, ILOAD = 100mA VIN = 2.5V, ILOAD = 100mA VIN = 3.3V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time ICL tstart_up tshut_down VOUT = 0V No load, Output cap 2.2 F, 90% of VOUT No load, Output cap 2.2 F, 10% of VOUT TEST CONDITIONS MIN 1.5 0.9 0 0 0 -3 0.1 0.015 200 250 400 88 30 10 5 IQ (no load) + 1% of load 50 TBD TBD 1.5 1.2 0.85 0.7 400 10 10 TYP MAX 5.5 3.3 200 50 20 3 Pre-Production UNIT V V mA % %/V %/mA mV % A dB mA s ms LDO4, LDO5, LDO6 TJ = -40C to +125 C unless otherwise noted. PARAMETER Input Voltage Programmable Output Voltage Output Current SYMBOL VIN VOUT IOUT Normal mode Low power mode, LDOn_LP_MODE=0 Low power mode, LDOn_LP_MODE=1 VOUT Accuracy Line Regulation Load Regulation Dropout Voltage VOUT_ACC VOUT LINE VOUT LOAD VIN - VOUT ILOAD = 10mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 50mA Note that VIN must be >= 1.5V ILOAD =1mA to 100mA ILOAD =100mA, VOUT > 2.7V ILOAD =100mA, VOUT 1.8V to 2.7V ILOAD =100mA, VOUT < 1.8V Undervoltage level Quiescent Current VOUT IQ VOUT Falling Normal mode, no load Low power mode, LDOn_LP_MODE=0, no load TEST CONDITIONS MIN 1.5 0.9 0 0 0 -3 0.1 0.025 200 250 400 88 30 10 PP, December 2009, Rev 3.0 20 % A TYP MAX 5.5 3.3 100 50 20 3 % % %/mA mV UNIT V V mA w Pre-Production PARAMETER SYMBOL TEST CONDITIONS Low power mode, LDOn_LP_MODE=1, no load ILOAD = 1mA to 100mA Power Supply Rejection Ratio On Resistance (Switch mode) PSRR ILOAD = 25mA, <= 1kHz ILOAD = 25mA, 10kHz ILOAD = 25mA, 100kHz RDSON VIN = 1.5V, ILOAD = 100mA VIN = 1.8V, ILOAD = 100mA VIN = 2.5V, ILOAD = 100mA VIN = 3.3V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time ICL tstart_up tshut_down VOUT = 0V No load, Output cap 2.2 F, 90% of VOUT No load, Output cap 2.2 F, 10% of VOUT MIN TYP 5 IQ (no load) + 1% of load 50 TBD TBD 3.16 2.09 1.35 1.11 230 10 10 MAX WM8312 UNIT dB mA s ms LDO7, LDO8 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input Voltage Programmable Output Voltage Output Current VOUT Accuracy Line Regulation Load Regulation Dropout Voltage SYMBOL VIN VOUT IOUT VOUT_ACC VOUT LINE VOUT LOAD VIN - VOUT Normal mode Low Power mode ILOAD = 10mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA Note that VIN must be >= 1.71V ILOAD =1mA to 200mA ILOAD =100mA, VOUT =1.8V ILOAD =100mA, VOUT =2.5V ILOAD =100mA, VOUT =3.3V Undervoltage level Quiescent Current Power Supply Rejection Ratio Output noise voltage On Resistance (Switch mode) VOUT IQ VOUT Falling Normal mode, no load Low Power mode, no load ILOAD = 1mA to 200mA PSRR ILOAD = 100mA, <= 1kHz ILOAD = 100mA, 10kHz ILOAD = 100mA, 100kHz VOUT f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA RDSON VIN = 1.71V, ILOAD = 100mA VIN = 1.8V, ILOAD = 100mA VIN = 2.5V, ILOAD = 100mA VIN = 3.5V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time ICL tstart_up tshut_down VOUT = 0V No load, Output cap 4.7 F, 90% of VOUT No load, Output cap 4.7 F, 10% of VOUT TEST CONDITIONS MIN 1.71 1.0 0 0 -2 0.025 0.003 95 65 60 92.5 110 70 IQ (no load) + 0.1% of load 85 70 50 30 32 32 550 500 330 250 320 50 10 mA s ms m VRMS dB % A TYP MAX 5.5 3.5 200 50 2 % %/V %/mA mV UNIT V V mA w PP, December 2009, Rev 3.0 21 WM8312 LDO9, LDO10 Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input Voltage Programmable Output Voltage Output Current VOUT Accuracy Line Regulation Load Regulation Dropout Voltage SYMBOL VIN VOUT IOUT VOUT_ACC VOUT LINE VOUT LOAD VIN - VOUT Normal mode Low Power mode ILOAD = 10mA VIN = (VOUT + 0.5) to 5.5V, ILOAD = 75mA Note that VIN must be >= 1.71V ILOAD =1mA to 150mA ILOAD =100mA, VOUT =1.8V ILOAD =100mA, VOUT =2.5V ILOAD =100mA, VOUT =3.3V Undervoltage level Quiescent Current Power Supply Rejection Ratio Output noise voltage On Resistance (Switch mode) VOUT IQ VOUT Falling Normal mode, no load Low Power mode, no load ILOAD = 1mA to 150mA PSRR ILOAD = 100mA, <= 1kHz ILOAD = 100mA, 10kHz ILOAD = 100mA, 100kHz VOUT f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA RDSON VIN = 1.71V, ILOAD = 100mA VIN = 1.8V, ILOAD = 100mA VIN = 2.5V, ILOAD = 100mA VIN = 3.5V, ILOAD = 100mA Current Limit (Switch mode) Start-up time Shutdown time ICL tstart_up tshut_down VOUT = 0V No load, Output cap 4.7 F, 90% of VOUT No load, Output cap 4.7 F, 10% of VOUT TEST CONDITIONS MIN 1.71 1.0 0 0 -2 0.025 0.004 135 100 90 88 110 70 IQ (no load) + 0.1% of load 85 70 50 30 32 32 1000 930 610 430 250 70 10 TYP MAX 5.5 3.5 150 50 2 Pre-Production UNIT V V mA % %/V %/mA mV % A dB VRMS m mA s ms LDO11 Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Programmable Output Voltage Output Current VOUT Accuracy Line Regulation Load Regulation Quiescent Current Start-up time Shutdown time SYMBOL VOUT IOUT VOUT VOUT LINE VOUT LOAD IQ tstart_up tshut_down VIN = 2.7 to 5.5V ; ILOAD = 100A VIN = 2.7 to 5.5V; ILOAD = 1mA ILOAD = 50A to 10mA No load No load, Output cap 0.1 F, 90% of VOUT No load, Output cap 0.1 F, 10% of VOUT TEST CONDITIONS MIN 0.8 0 -3 0.4 0.2 2.5 0.3 0.3 1 1 TYP MAX 1.55 10 3 UNIT V mA % %/V %/mA A ms ms w PP, December 2009, Rev 3.0 22 Pre-Production WM8312 7.5 RESET THRESHOLDS PARAMETER SYMBOL VPOR, DEASSERT Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C TEST CONDITIONS VPMIC rising VPMIC falling MIN TYP 1.18 1.08 MAX UNIT V V Power On Reset Power on Reset threshold VPMIC (LDO12VOUT) voltage at which device transitions between NO POWER and BACKUP states Power on Reset hysteresis Device Reset Control Device Reset threshold VPMIC (LDO12VOUT) voltage at which device transitions between BACKUP and OFF states Device Reset hysteresis Device Shutdown Shutdown threshold SYSVDD voltage at which the device forces an OFF transition SYSOK threshold accuracy SYSVDD voltage at which SYSOK is asserted. SYSLO threshold accuracy SYSVDD voltage at which SYSOK is de-asserted SYSOK hysteresis VSHUTDOWN SYSVDD falling 2.7 V VRES, DEASSERT VPOR, ASSERT VPOR, HYST VPMIC rising VPMIC falling 100 1.94 1.85 mV V V VRES, ASSERT VRES, HYST 92 mV VSYSOK SYSVDD rising, VSYSOK set by SYSOK_THR (2.8V to 3.5V) SYSVDD falling, VSYSLO set by SYSLO_THR (2.8V to 3.5V) TBD TBD % VSYSLO TBD TBD % VSYSOK, HYST 40 mV 7.6 REFERENCES PARAMETER SYMBOL VVREFC VIREFR 100k to REFGND TEST CONDITIONS MIN TYP 0.8 0.5 MAX UNIT V V Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C Voltage Reference Current Reference 7.7 BATTERY CHARGER PARAMETER SYMBOL VSYSVDD TEST CONDITIONS MIN 4.3 TYP MAX 5.5 UNIT V Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C General Supply voltage (Voltage required to commence charging; note that charging can continue at lower supply voltages, eg. under current throttling conditions) Target voltage VBATT_TGT CHG_VSEL = 00 CHG_VSEL = 01 CHG_VSEL = 10 CHG_VSEL = 11 4.0 4.05 4.1 4.15 4.05 4.10 4.15 4.20 CHG_V SEL 100mV 4.1 4.15 4.2 4.25 V Charger re-start threshold (Trickle charging starts when battery voltage is below this threshold) VBATT_RSTRT V w PP, December 2009, Rev 3.0 23 WM8312 PARAMETER Defective battery threshold Defective battery timeout Overvoltage threshold End of Charge Current Maximum trickle charge current Fast charge threshold (Fast charging fast-charge is only possible when battery voltage is above this threshold) Maximum fast charge current Supply voltage regulation level (Current throttling is applied if supply drops to this level) Internal Battery FET `On' Resistance Battery Temperature Monitoring NTCMON voltage for high battery temperature detection VBTEMP_H VNTCMON falling VNTCMON rising NTCMON voltage for low battery temperature detection VBTEMP_L VNTCMON rising VNTCMON falling NTCMON voltage for `no NTC' detection VNO_NTC VNTCMON rising VNTCMON falling 0.344 x VNTCBIAS 0.365 x VNTCBIAS 0.767 x VNTCBIAS 0.743 x VNTCBIAS 0.961 x VNTCBIAS 0.931 x VNTCBIAS SYMBOL VBATT_DEF tBATT_DEF VBATT_OV IEOC ITRKL_LIM VFAST_CHG Set by CHG_ITERM Set by CHG_TRKL_ILIM TEST CONDITIONS MIN TYP 2.85 30 4.5 20 to 90 50 to 200 2.85 MAX Pre-Production UNIT V mins V mA mA V IFAST_LIM VSYS_REG Set by CHG_FAST_ILIM 50 to 1000 mA RCHG_SW VBATTVDD = 3.8V VBATTVDD = 3.3V 90 100 m V V V 7.8 BACKUP BATTERY CHARGER PARAMETER SYMBOL VSYSVDD VBCH VBCH_HYST BKUP_CHG_VLIM = 0 BKUP_CHG_VLIM = 1 BKUP_CHG_MODE = 1 TEST CONDITIONS MIN 2.7 2.5 3.1 BKUP_ CHG_V LIM50mV 5 100 to 400 1.05 VSYSVDD - VBCH 250mV -30 +30 V TYP MAX 5.5 UNIT V V Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C Supply voltage Target voltage Charger re-start threshold End of charge current Charge current Backup battery detect threshold Charge current accuracy IEOC IBCH_LIM VBCH_DET IBCH_LIM BKUP_CHG_MODE = 0 Set by BKUP_CHG_ILIM A A V % w PP, December 2009, Rev 3.0 24 Pre-Production WM8312 7.9 USB POWER CONTROL PARAMETER SYMBOL VUSBVDD RUSB_SW IUSBVDD USB_ILIM = 010 USB_ILIM = 011 or greater USB_ILIM = 010 USB_ILIM = 011 USB_ILIM = 100 USB_ILIM = 101 USB_ILIM = 110 USB_ILIM = 111 TEST CONDITIONS MIN 4.3 230 96 91 454 805 1343 1609 496 10 100 500 900 1500 1800 550 s mA TYP MAX 5.5 UNIT V m Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C Supply voltage USB FET `On' Resistance Current limit Current limit response time 7.10 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) GPIO1 to GPIO16 Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Sink / source current Pull-up resistance to GPn_DOM Pull-down resistance RPU RPD SYMBOL VIH VIL VOH VOL TEST CONDITIONS MIN TYP TBD TBD TBD TBD TBD TBD TBD MAX UNIT V V V V mA k k 7.11 DIGITAL INTERFACES Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level SYMBOL VIH VIL VOH VOL TEST CONDITIONS MIN TYP TBD TBD TBD TBD MAX UNIT V V V V ON, RESET, IRQ, CIFMODE, SDOUT1, SCLK1, SDA1, CS, SCLK2, SDA2 7.12 AUXILIARY ADC Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Input resistance Input voltage range Input capacitance AUXADC Resolution AUXADC Conversion Time AUXADC accuracy SYMBOL RAUXADCINn VAUXADCIN1, 2, 3 VAUXADCIN4 CAUXADCINn TEST CONDITIONS During measurement 0 0 2 12 39 TBD MIN TYP 400 VSYSVDD VTPVDD pF bits s % MAX UNIT V w PP, December 2009, Rev 3.0 25 WM8312 7.13 TOUCH PANEL CONTROLLER Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER Supply voltage Input voltage range Programmable pull-up resistor SYMBOL VSYSVDD VGPIO13, 14, 15, 16 VAUXADCIN4 RPU TCH_RPU = 0000 TCH_RPU = 0111 TCH_RPU = 1111 Pen down detection threshold Pressure measurement current (4-wire mode only) Switch matrix internal impedance ADC Resolution ADC Conversion Time (including default settling time) ADC accuracy TCH_DELAY = 010 VPDD_THR ITCH_PRESS RTCH_SW TCH_ISEL = 0 TCH_ISEL = 1 TEST CONDITIONS TPVDD connected to LDO13VOUT 0 64 8 4 TPVDD/ 2 200 400 12 12 160 TBD MIN TYP 2.5 Pre-Production MAX UNIT V VTPVDD V k V A bits s % 7.14 SYSTEM STATUS LED DRIVERS Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER LED1 and LED2 Sink current TBD mA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 7.15 CLOCKING Unless otherwise noted: TA = -40C to +85C; Typical values are at TA = +25C PARAMETER FLL input reference FLL output frequency SYMBOL 32.768kHz CLKIN CLKOUT TEST CONDITIONS FLL_CLK_SRC=00 FLL_CLK_SRC=01 CLKOUT_SRC=0 32 32 MIN TYP 32.768 25000 25000 MAX UNIT kHz kHz kHz w PP, December 2009, Rev 3.0 26 Pre-Production WM8312 8 TYPICAL POWER CONSUMPTION Data to follow w PP, December 2009, Rev 3.0 27 WM8312 9 9.1 Pre-Production TYPICAL PERFORMANCE DATA DC-DC CONVERTERS Data to follow 9.2 LDO REGULATORS Data to follow w PP, December 2009, Rev 3.0 28 Pre-Production WM8312 10 SIGNAL TIMING REQUIREMENTS 10.1 CONTROL INTERFACE Figure 1 Control Interface Timing - 2-wire (I2C) Control Mode Test Conditions TJ = -40C to +125 C unless otherwise stated. PARAMETER SCLK1 Frequency SCLK1 Low Pulse-Width SCLK1 High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDA1, SCLK1 Rise Time SDA1, SCLK1 Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 SYMBOL MIN 0 1300 600 600 600 100 300 300 TYP MAX 400 UNIT kHz ns ns ns ns ns ns ns ns ns ns w PP, December 2009, Rev 3.0 29 WM8312 Pre-Production Figure 2 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) CS (input) SCLK1 (input) SDOUT1 (output) tDL Figure 3 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions TJ = -40C to +125 C unless otherwise stated. PARAMETER CS falling edge to SCLK1 rising edge SCLK1 falling edge to CS rising edge SCLK1 pulse cycle time SCLK1 pulse width low SCLK1 pulse width high SDA1 to SCLK1 set-up time SDA1 to SCLK1 hold time Pulse width of spikes that will be suppressed SCLK1 falling edge to SDOUT1 transition SYMBOL tCSU tCHO tSCY tSCL tSCH tDSU tDHO tps tDL MIN 40 10 200 80 80 40 10 0 5 40 TYP MAX UNIT ns ns ns ns ns ns ns ns ns The CS pin must be held high for at least 1s after every register write operation in SPI mode. w PP, December 2009, Rev 3.0 30 Pre-Production WM8312 11 DEVICE DESCRIPTION 11.1 GENERAL DESCRIPTION The WM8312 is a multi-purpose Power Management device with a comprehensive range of features. The WM8312 provides 4 DC-DC Converters and 11 LDO Regulators which are all programmable to application-specific requirements. The on-board oscillator and two additional LDOs support the clocking and control functions for the DC Converters and other core functions. The device has flexible power supply options, which enable hot-switching between external supplies (Wall adaptor or USB), or a battery. The WM8312 provides a charger for the main battery and also for an optional backup battery. Other features include 2 Current Sinks (LED drivers), flexible GPIO capability, touch panel controller interface and LED outputs for system status indications. The WM8312 also provides a 32.768kHz crystal oscillator and secure Real Time Clock (SRTC). The Frequency Locked Loop (FLL) enables different clock frequencies to be generated from the 32kHz reference to provide clocking for external circuits. An auxiliary ADC is included, for measurement of internal and external voltages. Under typical operating conditions, the device is powered up and shut down under the control of the ON pin. The device executes a programmable sequence of enabling or disabling the DC-DC Converters, LDOs and other functions when commanded to power up or shut down respectively. An alternate device state (SLEEP power state) is provided, in which selected functions may be separately configured for a low-power or other operating condition. The configuration of the normal operating state may be programmed into an integrated OTP non-volatile memory. If desired, the OTP memory can be programmed during device manufacture in accordance with the user's specification. See Section 14 for details of the OTP and associated bootstrap configuration functions. In the absence of suitable power supplies, the WM8312 automatically reverts to a backup state, under which a minimal functionality is maintained to enable a smooth return to normal operation when the supplies are restored. With a backup battery present, the RTC is updated in the backup state, allowing the main battery to be depleted or changed without loss of RTC function. Without a backup battery, a small capacitor is sufficient to maintain the RTC (unclocked) for up to 5 minutes. 11.2 POWER STATES The WM8312 has 6 main power states, which are described below. Different levels of functionality are associated with each of the power states. Some of the state transitions are made autonomously by the WM8312 (eg. transitions to/from BACKUP are scheduled according to the available power supply conditions). Other transitions are initiated as a result of instructions issued over the Control Interface or as a result of software functions (eg. Watchdog timer) or hardware functions such as the ON pin. The valid transitions and the associated conditions are detailed below. NO POWER - This is the device state when no power is available. All functions are disabled and all register data is lost. OFF - This is the device state when power is available but the device is switched off. The RTC is enabled and the register map contents are maintained. The RST pin is pulled low in this state. LDO11 may optionally be enabled in this state; all other DC-DCs and LDOs are disabled. ON - This is the normal operating state when the device is switched on. All device functions are available in this state. SLEEP - This is a user-configurable operating state which is intended for a low-power operating condition. Selected functions may be enabled, disabled or re-configured according to the user's requirements. A programmable configuration sequence for the DC-DCs and LDOs is executed on transition to/from SLEEP mode. BACKUP - This is the operating state when the available power supplies are below the reset threshold of the device. Typically, this means that USB or Wall supplies are not present and that the main battery is either discharged or removed. The RTC and oscillator and a `software scratch' memory area can be maintained from the backup battery (if available) in this state. All other functions and registers are reset in BACKUP. (Note that, for power saving, an `unclocked' mode, in which the RTC is held constant, may be selected if required.) w PP, December 2009, Rev 3.0 31 WM8312 Pre-Production PROGRAM - This is a special operating state which is used for programming the integrated OTP memory with the device configuration data. The settings stored in the OTP define the device configuration in the ON state, and also the time/sequencing data associated with ON/OFF power state transitions. See Section 14 for details of the OTP features. The valid power state transitions are illustrated in Figure 4. Figure 4 Power States and Transitions State transitions to/from the NO POWER state are controlled automatically by the internal supply (VPMIC) voltage generated by LDO12. The device is in the NO POWER state when this voltage is below the Power-On Reset (POR) threshold. See Section 24 for more details on Power-On Reset. State transitions to/from the BACKUP state are controlled automatically by the internal supply (VPMIC) voltage generated by LDO12. The device is in the BACKUP state when this voltage is below the Device Reset threshold. See Section 24 for more details on Resets. State transitions to/from the PROGRAM state are required to follow specific control sequences. See Section 14 for details of the PROGRAM functions. w PP, December 2009, Rev 3.0 32 Pre-Production WM8312 The remaining transitions between the OFF, ON and SLEEP states may be initiated by a number of different mechanisms - some of them automatic, some of them user-controlled. Transitions between these states are time-controlled sequences of events. These are the OFF, ON, SLEEP and WAKE sequences shown in Figure 4. These transitions are programmable, using data stored in the integrated OTP memory or else data loaded from an external Dynamic Bootstrap EEPROM (DBE) memory. See Section 14 for details. The current power state of the WM8312 can be read from the MAIN_STATE register field. A restricted definition of this field is shown in Table 1. Note that other values of MAIN_STATE are defined for transition states, but it is recommended that only the values quoted below should be used to confirm power state transitions. A power state transition to the BACKUP, SLEEP, ON or OFF state is indicated by the Interrupt bits described in Section 11.4. ADDRESS R16397 (400Dh) System Status BIT 4:0 LABEL MAIN_STATE [4:0] DEFAULT 0_0000 DESCRIPTION Main State Machine condition 0_0000 = OFF 0_1011 = PROGRAM 1_1100 = SLEEP 1_1111 = ACTIVE (ON) Table 1 Power State Readback 11.3 POWER STATE CONTROL The OFF, ON, SLEEP and WAKE sequences are initiated by many different conditions. When such a condition occurs, the WM8312 schedules a series of 5 timeslots, enabling a sequence of enable/disable events to be controlled. The nominal duration of the timeslots is fixed at 2ms, though this may be extended if any selected circuit has not started up within this time, as described later in this section. The OFF, SLEEP and WAKE sequences commence after a programmable delay set by PWRSTATE_DLY. This allows a host processor to request a WM8312 state transition and then complete other tasks before the transition actually occurs. The ON sequence is the transition from OFF to ON power states. Each LDO and each DC-DC Converter (except DC-DC4) may be associated with any one of the available timeslots in the ON sequence. This determines the time, within the sequence, at which that DC-DC Converter or LDO will be enabled following an `ON' event. The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can also be associated with any one of the available timeslots in the ON sequence. The EPE function is a logic output that may be used to control external circuits, including external DC-DC converters. An example `ON' state transition sequence is illustrated in Figure 5. Each of the DC-DC Buck Converters and LDO Regulators can be individually assigned to one of the five timeslots (shown as T1, T2, T3, T4, T5), providing total flexibility in the power sequence. w PP, December 2009, Rev 3.0 33 WM8312 Pre-Production Figure 5 Example Control Sequence for `ON' State Transition The possible `ON' events that may trigger the ON sequence are listed in Table 3. The ON sequence is only permitted when the supply voltage SYSVDD exceeds a programmable threshold SYSOK. See Section 24 for details of SYSVDD voltage monitoring. The OFF sequence is the reverse of the ON sequence. Each DC-DC Converter, LDO Regulator or GPIO output that is associated with a timeslot in the ON sequence is switched off in the reverse sequence following an `OFF' event. If CLKOUT is assigned to a timeslot in the ON sequence, then this is disabled in the reverse (OFF) sequence also. The possible `OFF' events are listed in Table 3. Note that it is possible to modify the OFF sequence by writing to the associated registers in the ON power state if required; this allows the OFF sequence to be independent of the ON sequence. The SLEEP sequence is the transition from ON to SLEEP power states. Each LDO and each DC-DC Converter (except DC-DC4) may be associated with any one of the available timeslots in the SLEEP sequence. This determines the time, within the sequence, at which that DC Converter or LDO will be disabled following a `SLEEP' event. The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can also be associated with any one of the available timeslots in the SLEEP sequence. The possible `SLEEP' events are listed in Table 3. The WAKE sequence is the reverse of the SLEEP sequence. Each DC-DC Converter, LDO Regulator or GPIO output that is associated with a timeslot in the SLEEP sequence is switched on in the reverse sequence following a `WAKE' event. If CLKOUT is assigned to a timeslot in the SLEEP sequence, then this is disabled in the reverse (WAKE) sequence also. The possible `WAKE' events are listed in Table 3. Note that it is possible to modify the WAKE sequence by writing to the associated registers in the SLEEP power state if required; this allows the WAKE sequence to be independent of the SLEEP sequence. Any DC-DC Converter or LDO that is not associated with one of the 5 timeslots in the ON sequence may, instead, be configured to be hardware controlled via a GPIO pin configured as one of the Hardware Enable inputs. See Section 21 for details of the GPIO functions. Any DC-DC Converter or LDO that is not under Hardware control may be enabled or disabled under Software control in the ON state, regardless of whether it is associated with any timeslot in the ON sequence. When a valid OFF event occurs, any DC-DC Converter or LDO which is not allocated a timeslot in the ON sequence is disabled immediately. This includes any DC-DC Converter or LDO which is under GPIO (Hardware Enable) control. The only exception is LDO11 which may, optionally, be configured to be enabled in the OFF state. w PP, December 2009, Rev 3.0 34 Pre-Production WM8312 The WM8312 monitors the DC-DC Converters and LDOs during the ON sequence to ensure that the required circuits have powered up successfully before proceeding to the next timeslot. The nominal timeslot durations are extended if necessary in order to wait for the selected DC-DC Converters or LDOs to power up. If the ON sequence has not completed within 2 seconds of starting the transition, then a Power Sequence Failure has occurred, resulting in the OFF state being forced. The most recent ON or WAKE event can be determined by reading the bits in the "ON Source" register, R400Eh. The most recent OFF event can be determined by reading the bits in the "OFF Source" register, R400Fh. The "ON Source" register is updated when a new ON event occurs. The "OFF Source" register is updated when a new OFF event occurs. Note that some Reset conditions (see Section 24) result in an OFF transition followed by an ON transition; these events are recorded as Reset events in the "ON Source" register. The ON Source and OFF Source register fields are defined in Table 2. ADDRESS R16387 (4003h) Power State BIT 15 LABEL CHIP_ON DEFAULT 0 DESCRIPTION Indicates whether the system is ON or OFF. 0 = OFF 1 = ON (or SLEEP) OFF can be commanded by writing CHIP_ON = 0. Note that writing CHIP_ON = 1 is not a valid `ON' event, and will not trigger an ON transition. Indicates whether the system is in the SLEEP state. 0 = Not in SLEEP 1 = SLEEP WAKE can be commanded by writing CHIP_SLP = 0. SLEEP can be commanded by writing CHIP_SLP = 1. Power State transition delay 00 = No delay 01 = No delay 10 = 1ms 11 = 10ms Most recent ON/WAKE event type 0 = WAKE transition 1 = ON transition Most recent ON/WAKE event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Most recent WAKE event type 0 = Not caused by SYSVDD 1 = Caused by SYSLO threshold. Note that the SYSLO threshold cannot trigger an ON event. Most recent WAKE event type 0 = Not caused by Pen Down 1 = Caused by Touch Panel Pen Down detection. Note that the Pen Down detection cannot trigger an ON event. Most recent WAKE event type 0 = Not caused by Battery Charger 1 = Caused by Battery Charger 14 CHIP_SLP 0 11:10 PWRSTATE_DLY 0 R16398 (400Eh) ON Source 15 ON_TRANS 0 11 ON_GPIO 0 10 ON_SYSLO 0 9 ON_PEN_DOWN 0 8 ON_CHG 0 w PP, December 2009, Rev 3.0 35 WM8312 ADDRESS BIT 7 LABEL ON_WDOG_TO DEFAULT 0 Pre-Production DESCRIPTION Most recent WAKE event type 0 = Not caused by Watchdog timer 1 = Caused by Watchdog timer Most recent WAKE event type 0 = Not caused by software WAKE 1 = Caused by software WAKE command (CHIP_SLP = 0) Most recent ON/WAKE event type 0 = Not caused by RTC Alarm 1 = Caused by RTC Alarm Most recent ON/WAKE event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Most recent ON event type 0 = Not caused by undervoltage 1 = Caused by a Device Reset due to a Converter (LDO or DCDC) undervoltage condition Most recent ON event type 0 = Not caused by Software Reset 1 = Caused by Software Reset Most recent ON event type 0 = Not caused by Hardware Reset 1 = Caused by Hardware Reset Most recent ON event type 0 = Not caused by the Watchdog 1 = Caused by a Device Reset triggered by the Watchdog timer Most recent OFF event type 0 = Not caused by LDO13 Error condition 1 = Caused by LDO13 Error condition Most recent OFF event type 0 = Not caused by Power Sequence Failure 1 = Caused by a Power Sequence Failure Most recent OFF event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Most recent OFF event type 0 = Not caused by SYSVDD 1 = Caused by the SYSLO or SHUTDOWN threshold Most recent OFF event type 0 = Not caused by temperature 1 = Caused by over-temperature Most recent OFF event type 0 = Not caused by software OFF 1 = Caused by software OFF command (CHIP_ON = 0) Most recent OFF event type 0 = Not caused by the ON pin 1 = Caused by the ON pin 6 ON_SW_REQ 0 5 ON_RTC_ALM 0 4 ON_ON_PIN 0 3 RESET_CNV_UV 0 2 RESET_SW 0 1 RESET_HW 0 0 RESET_WDOG 0 R16399 (400Fh) OFF Source 13 OFF_INTLDO_ERR 0 12 OFF_PWR_SEQ 0 11 OFF_GPIO 0 10 OFF_SYSVDD 0 9 OFF_THERR 0 6 OFF_SW_REQ 0 4 OFF_ON_PIN 0 Table 2 Power State Control Registers w PP, December 2009, Rev 3.0 36 Pre-Production WM8312 Table 3 lists all of the events which can trigger an ON, WAKE, OFF or SLEEP transition sequence. It also lists the associated status bits of the `ON Source' and `OFF Source' register bits which are asserted under each condition. TRANSITION SEQUENCE ON (see note 1) EVENT RTC alarm GPIO ON request NOTES An ON request occurs if the RTC Alarm occurs in the OFF power state. See Section 20. Requires a GPIO to be configured as "Power On request" or "Power On/Off request". See Section 21. Requires the ON pin to be configured to generate ON request. See Section 11.6. Writing CHIP_SLP = 0. See Table 2. Occurs when a Charger Interrupt event is triggered. See Section 17.7.8. Requires the Watchdog to be configured to generate WAKE request. See Section 25. A WAKE request occurs if the RTC Alarm occurs in the SLEEP power state. See Section 20. Requires the Touch Panel to be configured to generate WAKE request. See Section 19. Requires a GPIO to be configured as "Sleep/Wake request". See Section 21. Requires the SYSVDD monitor circuit to be configured to generate WAKE request. See Section 24.4. Requires the ON pin to be configured to generate WAKE request. See Section 11.6. Requires the Watchdog to be configured to generate Device Reset. See Section 25. See Section 24. See Section 24. Configurable option for each LDO/DC-DC Converter. See Section 15. Writing CHIP_ON = 0. See Table 2. Requires the ON pin to be configured to generate OFF request. See Section 11.6. See Section 26. Requires the SYSVDD monitor circuit to be configured to generate OFF request. See Section 24.4. SYSVDD has fallen below the SHUTDOWN threshold. See Section 24.4. Requires a GPIO to be configured as "Power On/Off request". See Section 21. DC-DC Converters, LDOs or CLKOUT circuits (including FLL) have failed to start up within the permitted time. Error condition detected in LDO13 Writing CHIP_SLP = 1. See Table 2. Requires a GPIO to be configured as "Sleep request" or "Sleep/Wake request". See Section 21. ON SOURCE / OFF SOURCE ON_TRANS, ON_RTC_ALM ON_TRANS, ON_GPIO ON pin request WAKE Software WAKE Battery Charger event Watchdog timeout RTC alarm ON_TRANS, ON_ON_PIN ON_SW_REQ ON_CHG ON_WDOG_TO ON_RTC_ALM Touch Panel pen down GPIO WAKE request SYSVDD undervoltage ON_PEN_DOWN ON_GPIO ON_SYSLO ON pin request OFF (see note 2) Watchdog timeout Hardware Reset Software Reset Power Management Undervoltage Reset Software OFF request ON pin request Thermal shutdown SYSVDD undervoltage ON_ON_PIN RESET_WDOG (See note 3) RESET_HW (See note 3) RESET_SW (See note 3) RESET_CNV_UV (See note 3) OFF_SW_REQ OFF_ON_PIN OFF_THERR OFF_SYSVDD SYSVDD shutdown GPIO OFF request Power Sequence failure OFF_SYSVDD OFF_GPIO OFF_PWR_SEQ Internal LDO error SLEEP Software SLEEP request GPIO SLEEP request OFF_INTLDO_ERR See note 4 See note 4 Table 3 Power State Transition Events w PP, December 2009, Rev 3.0 37 WM8312 Notes: 1. 2. 3. 4. Pre-Production An ON sequence is only permitted when the supply voltage SYSVDD exceeds a programmable threshold VSYSOK. See Section 24.4 for details of SYSVDD voltage monitoring. Selected OFF events may be masked during Battery Charging using the CHG_OFF_MASK bit. This allows user-initiated OFF events (Software OFF, ON pin request, GPIO OFF request) to be inhibited. See Section 17.7.2. These Reset conditions result in an OFF transition followed by an ON transition. These events are recorded as Reset events in the `ON Source' register. SLEEP events are not recorded in the `OFF Source' register. 11.4 POWER STATE INTERRUPTS Power State transitions are associated with a number of Interrupt event flags. Transitions to BACKUP, SLEEP, ON or OFF states are indicated by the Interrupt bits described in Table 4. Each of these secondary interrupts triggers a primary Power State Interrupt, PS_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 4. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 2 LABEL PS_POR_EINT DESCRIPTION Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a `1' is written. ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 PS_SLEEP_OFF_EINT 0 PS_ON_WAKE_EINT R16410 (401Ah) Interrupt Status 2 Mask 2 IM_PS_POR_EINT 1 IM_PS_SLEEP_OFF_EINT 0 IM_PS_ON_WAKE_EINT Table 4 Power State Interrupts 11.5 POWER STATE GPIO INDICATION The WM8312 can be configured to generate logic signals via GPIO pins to indicate the current Power State. See Section 21 for details of configuring GPIO pins. A GPIO pin configured as "ON state" output will be asserted when the WM8312 is in the ON state. A GPIO pin configured as "SLEEP state" output will be asserted when the WM8312 is in the SLEEP state. w PP, December 2009, Rev 3.0 38 Pre-Production WM8312 The ON pin is intended for connection to the master power switch on the user's application. It can be used to start-up the WM8312 from the SLEEP or OFF states and also to power down the system. This pin operates on the LDO12 (VPMIC) power domain and has an internal pull-up resistor. This pin is asserted by shorting it to GND. A de-bounce circuit is provided on this input pin. The behaviour of the ON pin is programmable. The primary action taken on asserting this pin is determined by the ON_PIN_PRIMACT register field. Note that the ON pin interrupt event is always raised when the ON pin is asserted. If the pin is held asserted for longer than the timeout period set by ON_PIN_TO, then a secondary action is executed. The secondary action is determined by the ON_PIN_SECACT register field. If the pin is held asserted for a further timeout period, then a tertiary action is executed. The tertiary action is not programmable, and is to generate an OFF request. An OFF request initiated by the ON pin may be masked during Battery Charging when the CHG_OFF_MASK bit is set. This allows user-initiated OFF events to be disabled in order to maintain the Battery Charger operation. See Section 17.7.2. The status of the ON pin can be read at any time via the ON_PIN_STS register. Note that the ON pin control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16389 (4005h) ON Pin Control BIT 9:8 LABEL ON_PIN_SECACT DEFAULT 01 DESCRIPTION Secondary action of ON pin (taken after 1 timeout period) 00 = Interrupt 01 = ON request 10 = OFF request 11 = Reserved Protected by user key Primary action of ON pin 00 = Ignore 01 = ON request 10 = OFF request 11 = Reserved Note that an Interrupt is always raised. Protected by user key Current status of ON pin 0 = Asserted (logic 0) 1 = Not asserted (logic 1) ON pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s Protected by user key 11.6 ON PIN FUNCTION 5:4 ON_PIN_PRIMACT 00 3 ON_PIN_STS 0 1:0 ON_PIN_TO 00 Table 5 ON Pin Control Registers The ON pin interrupt event is always raised as part of the primary action when the ON pin is asserted. The ON pin interrupt is a selectable option as the secondary action. The ON pin interrupt event is also raised when the ON pin is de-asserted. The ON pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the mask bit as described in Table 6. w PP, December 2009, Rev 3.0 39 WM8312 ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 12 LABEL ON_PIN_CINT Pre-Production DESCRIPTION ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 12 IM_ON_PIN_CINT Table 6 ON Pin Interrupt 11.7 RESET PIN FUNCTION The RESET pin is an active low input/output which is used to command Hardware Resets in the WM8312 and in other connected devices. The pin is an open-drain type, and can be driven low by external sources or by the WM8312 itself. The WM8312 drives the RESET pin low in the OFF state. The output status of the RESET pin in SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7. The WM8312 clears the RESET pin following the transition to ON. On completion of the state transition, the RESET pin is held low for a further delay time period, extending the RESET low duration. The RESET delay period is set by the RST_DUR register bit. See Figure 6 for further details. The WM8312 detects a Hardware Reset request whenever the RESET pin is driven low by an external source. In this event, the WM8312 resets the internal control registers (excluding the RTC) and initiates a start-up sequence. See Section 24. It is possible to mask the RESET pin input in the SLEEP state by setting the RST_SLP_MSK register bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8312 will take no action if the RESET pin is pulled low. Note that the RESET pin control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16390 (4006h) Reset Control BIT 5 LABEL RST_SLP_MSK DEFAULT 1 DESCRIPTION Masks the RESET pin input in SLEEP mode 0 = External RESET active in SLEEP 1 = External RESET masked in SLEEP Protected by user key Sets the output status of RESET pin in SLEEP 0 = RESET high (not asserted) 1 = RESET low (asserted) Protected by user key Delay period for releasing RESET after ON or WAKE sequence 00 = 1ms 01 = 10ms 10 = 50ms 11 = 100ms Protected by user key 4 RST_SLPENA 1 1:0 RST_DUR 11 Table 7 RESET Pin Control Registers w PP, December 2009, Rev 3.0 40 Pre-Production WM8312 The WM8312 can generate an Auxiliary Reset output via a GPIO pin configured as "Auxiliary Reset" output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8. ADDRESS R16390 (4006h) Reset Control BIT 6 LABEL AUXRST_SLPE NA DEFAULT 1 DESCRIPTION Sets the output status of Auxiliary Reset (GPIO) function in SLEEP 0 = Auxiliary Reset not asserted 1 = Auxiliary Reset asserted Protected by user key Table 8 Auxiliary Reset (GPIO) Control The timing details of the RESET pin relative to an ON state transition are illustrated in Figure 6. ON transition completes Figure 6 RESET Pin Output w PP, December 2009, Rev 3.0 41 RESET is de-asserted ON transition starts `ON' event WM8312 12 CONTROL INTERFACE 12.1 GENERAL DESCRIPTION Pre-Production The WM8312 is controlled by writing to its control registers. Readback is available for all registers, including Chip ID, power management status and GPIO status. The control interface can operate as a 2-wire (I2C) or 4-wire (SPI) control interface. Readback is provided on the bi-directional pin SDA1 in 2-wire (I2C) mode. The WM8312 Control Interface is powered by the DBVDD power domain. The control interface mode is determined by the logic level on the CIFMODE pin as shown in Table 9. CIFMODE Low High INTERFACE FORMAT 2-wire (I2C) mode 4-wire (SPI) mode Table 9 Control Interface Mode Selection 12.2 2-WIRE (I2C) CONTROL MODE In 2-wire (I2C) mode, the WM8312 is a slave device on the control interface; SCLK1 is a clock input, while SDA1 is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8312 transmits logic 1 by tri-stating the SDA1 pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA1 line high so that the logic 1 can be recognised by the master. In order to allow many devices to share a single 2-wire control bus, every device on the bus has a unique 8-bit device ID (this is not the same as the 16-bit address of each register in the WM8312). The device ID is determined by the logic level on the CS pin as shown in Table 10. The LSB of the device ID is the Read/Write bit; this bit is set to logic 1 for "Read" and logic 0 for "Write". CS Low High DEVICE ID 0110 100x = 68h(write) / 69h(read) 0110 110x = 6Ch(write) / 6Dh(read) Table 10 Control Interface Device ID Selection The WM8312 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDA1 while SCLK1 remains high. This indicates that a device ID, register address and data will follow. The WM8312 responds to the start condition and shifts in the next eight bits on SDA1 (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches the device ID of the WM8312, then the WM8312 responds by pulling SDA1 low on the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is `1' when operating in write only mode, the WM8312 returns to the idle condition and waits for a new start condition and valid address. If the device ID matches the device ID of the WM8312, the data transfer continues as described below. The controller indicates the end of data transfer with a low to high transition on SDA1 while SCLK1 remains high. After receiving a complete address and data sequence the WM8312 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDA1 changes while SCLK1 is high), the device returns to the idle condition. The WM8312 supports the following read and write operations: * * * * Single write Single read Multiple write using auto-increment Multiple read using auto-increment The sequence of signals associated with a single register write operation is illustrated in Figure 7. w PP, December 2009, Rev 3.0 42 Pre-Production WM8312 Figure 7 Control Interface 2-wire (I2C) Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 8. Figure 8 Control Interface 2-wire (I2C) Register Read The Control Interface also supports other register operations, as listed above. The interface protocol for these operations is summarised below. The terminology used in the following figures is detailed in Table 11. Note that, for multiple write and multiple read operations, the auto-increment option must be enabled. This feature is enabled by default; it is described in Table 12 below. TERMINOLOGY S Sr A A P R/W [White field] [Grey field] DESCRIPTION Start Condition Repeated start Acknowledge (SDA Low) Not Acknowledge (SDA High) Stop Condition ReadNotWrite 0 = Write 1 = Read Data flow from bus master to WM8312 Data flow from WM8312 to bus master Table 11 Control Interface Terminology Figure 9 Single Register Write to Specified Address w PP, December 2009, Rev 3.0 43 WM8312 Pre-Production Figure 10 Single Register Read from Specified Address Figure 11 Multiple Register Write to Specified Address using Auto-increment Figure 12 Multiple Register Read from Specified Address using Auto-increment Figure 13 Multiple Register Read from Last Address using Auto-increment Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of the data in the WM8312 register map faster than is possible with single register operations. The auto-increment option is enabled when the AUTOINC register bit is set. This bit is defined in Table 12. Auto-increment is enabled by default. ADDRESS R16391 (4007h) Control Interface BIT 2 LABEL AUTOINC DEFAULT 1 DESCRIPTION Enable Auto-Increment function 0 = Disabled 1 = Enabled Table 12 Auto-Increment Control w PP, December 2009, Rev 3.0 44 Pre-Production WM8312 In this mode, the WM8312 registers are accessed using a 4-wire serial control interface. The CS and SCLK1 pins provide the `Chip Select' and `Serial Data Clock' functions respectively. Serial data input is supported on the SDA1 pin; serial data output is supported on the SDOUT1 pin. A control word consists of 32 bits. The first bit is the read/write bit (R/W), which is followed by 15 address bits (A14 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. In Write operations (R/W=0), all SDA1 bits are driven by the controlling device. Each rising edge of SCLK1 clocks in one data bit from the SDA1 pin. A rising edge on CS latches in a complete control word consisting of the last 32 bits. In Read operations, the SDA1 pin is ignored following receipt of the valid register address. The data bits are output by the WM8312 on the SDOUT1 pin. SDOUT1 is undriven (high impedance) when not outputting register data bits. The sequence of signals associated with a register write operation is illustrated in Figure 14. 12.3 4-WIRE (SPI) CONTROL MODE Figure 14 Control Interface 4-wire (SPI) Register Write The sequence of signals associated with a register read operation is illustrated in Figure 15. CS SCLK SDIN SDOUT A14 A13 A12 A2 A1 A0 X B15 X B14 X B13 X B2 X B1 X B0 R/W undriven undriven 15-bit control register address 16-bit control register data Figure 15 Control Interface 4-wire (SPI) Register Read 12.4 REGISTER LOCKING Selected registers are protected by a security key. These registers can only be written to when the appropriate `unlock' code has been written to the Security Key register. The protected registers include those associated with Reset Control, OTP Programming, RTC Trim and Battery Charger operation. Other selected functions also include protected registers; the affected registers are identified in the Register Map definitions throughout the document, and also in Section 29. To unlock the protected registers, a value of 9716h must be written to the Security register (R16392), as defined in Table 13. It is recommended to re-lock the protected registers immediately after writing to them. This helps protect the system against accidental overwriting of register values. To lock the protected registers, a value of 0000h should be written to the Security register. PP, December 2009, Rev 3.0 45 w WM8312 ADDRESS R16392 (4008h) Security Key BIT 15:0 LABEL SECURITY [15:0] DEFAULT 0000h Pre-Production DESCRIPTION Security Key A value of 9716h must be written to this register to access the userkeyed registers. Table 13 Security Key Registers 12.5 SOFTWARE RESET AND CHIP ID A Software Reset can be commanded by writing to Register 0000h. This is a read-only register field and the contents of this register will not be affected by a write operation. For more details of the different reset types, see Section 24. The Chip ID can be read back from Register 0000h. Other ID fields can be read from the registers defined in Table 14. ADDRESS R0 (0000h) Reset/ID BIT 15:0 LABEL CHIP_ID [15:0] DEFAULT 0000h DESCRIPTION Writing to this register causes a Software Reset. The register map contents may be reset, depending on SW_RESET_CFG. Reading from this register will indicate Chip ID. The revision number of the parent die The revision number of the child die (when present) The ID of the parent die R1 (0001h) Revision 15:8 7:0 PARENT_RE V [7:0] CHILD_REV [7:0] PARENT_ID [15:0] 00h 00h 6204h R16384 (4000h) Parent ID 15:0 Table 14 Reading Device Information 12.6 SOFTWARE SCRATCH REGISTER The WM8312 provides one 16-bit register as a "Software Scratch" register. This is available for use by the host processor to store data for any purpose required by the application. The contents of the Software Scratch register are retained in the BACKUP power state. ADDRESS R16393 (4009h) Software Scratch BIT 15:0 LABEL SW_SCRATC H [15:0] DEFAULT 0000h DESCRIPTION Software Scratch Register for use by the host processor. Note that this register's contents are retained in the BACKUP power state. Table 15 Software Scratch Register w PP, December 2009, Rev 3.0 46 Pre-Production WM8312 13 CLOCKING AND OSCILLATOR CONTROL 13.1 GENERAL DESCRIPTION The WM8312 incorporates a 32.768kHz crystal oscillator in order to maintain the Real Time Clock (RTC). An external crystal is normally required. Alternatively, a 32.768kHz signal may be input directly on the XTI pin. The crystal oscillator and RTC are enabled at all times, including the OFF and BACKUP power states. It is possible to disable the crystal oscillator in BACKUP for power-saving RTC `unclocked' mode if desired. The WM8312 clock functions are illustrated in Figure 16. Figure 16 Clocking Configuration The 32.768kHz crystal oscillator is enabled using the XTAL_ENA register. The crystal oscillator is enabled in the OFF, ON and SLEEP states when XTAL_ENA is set. The status of the crystal oscillator in BACKUP is selected using the XTAL_BKUPENA register. Note that the XTAL_ENA field is set via OTP/DBE settings only; it cannot be changed by writing to the control register. Also, if an external 32.768kHz signal is connected as an input to the XTI pin, and the crystal is omitted, it is still required to set XTAL_ENA = 1 for normal operation. The crystal oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state, as described in Section 20.5. The crystal oscillator is maintained in the BACKUP state if both XTAL_ENA and XTAL_BKUPENA are set to 1. A clock output signal CLKOUT is provided, for the purpose of clocking other devices. This output may be driven by the 32.768kHz oscillator or by the output of a Frequency Locked Loop (FLL). The FLL provides a flexible capability to generate a new clock signal either from the 32.768kHz oscillator or from an external input CLKIN. The FLL is tolerant of jitter and may be used to generate a stable clock signal from a less stable input reference. The FLL output can be routed to the CLKOUT pin. The CLKOUT signal can be enabled or disabled directly by writing to the CLKOUT_ENA register in the ON or SLEEP power states. The CLKOUT can also be controlled as part of the power state transitions using the CLKOUT_SLOT and CLKOUT_SLP_SLOT register fields. See Section 11.3 for a description of the state transition timeslots. The CLKOUT pin may be configured as a CMOS output or as an Open-Drain output. At high frequencies, the CMOS output is recommended. The CLKOUT signal is referenced to the DBVDD power domain. If the XTAL_INH bit is set, then an `ON' state transition is inhibited until the CLKOUT output is valid. (Note that CLKOUT may be the crystal oscillator output, or may be the FLL output.) This may be desirable if the CLKOUT signal is used as a clock for another circuit, to ensure that CLKOUT is present before the `ON' state transition occurs. The CLKOUT control fields are described in Table 16. Some of these controls may also be stored in the integrated OTP memory. See Section 14 for details. The 32.768kHz oscillator may also be output on a GPIO pin, as described in Section 21. Note that a GPIO pin configured as 32.768kHz output will continue to output the oscillator clock in the OFF power state; this may be used to provide clocking to the processor in the OFF state. The CLKOUT output is always disabled in the OFF power state. PP, December 2009, Rev 3.0 47 w WM8312 Pre-Production A separate internal RC oscillator generates the required clocks for the integrated DC-DC Converters on the WM8312. Note that a 2MHz `External Power Clock', derived from this oscillator, may be output on a GPIO pin to provide synchronised clocking of external DC-DC Converters if required (see Section 21). The 2MHz External Power Clock is only enabled when either of the External Power Enable signals EPE1 or EPE2 is asserted. The External Power Enable (EPE) signals are controlled as described in Section 15.3. Note that the CLKOUT_ENA control register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16528 (4090h) Clock Control 1 BIT 15 LABEL CLKOUT_EN A DEFAULT 0 DESCRIPTION CLKOUT output enable 0 = Disabled 1 = Enabled Protected by user key CLKOUT pin configuration 0 = CMOS 1 = Open Drain CLKOUT output enable ON slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Do not enable 111 = Do not enable CLKOUT output SLEEP slot select 000 = Controlled by CLKOUT_ENA 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = Controlled by CLKOUT_ENA 111 = Controlled by CLKOUT_ENA CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=1, the `ON' transition is inhibited until the crystal oscillator is valid Crystal Oscillator Enable 0 = Disabled at all times 1 = Enabled in OFF, ON and SLEEP states (Note that the BACKUP behaviour is determined by XTAL_BKUPENA.) Selects the RTC and 32.768kHz oscillator in BACKUP state 0 = RTC unclocked in BACKUP 1 = RTC maintained in BACKUP (Note that XTAL_ENA must also PP, December 2009, Rev 3.0 48 13 CLKOUT_OD 0 10:8 CLKOUT_SLO T 000 6:4 CLKOUT_SLP SLOT 000 0 CLKOUT_SR C XTAL_INH 0 R16529 (4091h) Clock Control 2 15 0 13 XTAL_ENA 0 12 XTAL_BKUPE NA 1 w Pre-Production ADDRESS BIT LABEL DEFAULT WM8312 DESCRIPTION be set if the RTC is to be maintained in BACKUP.) Table 16 Clocking Control 13.2 CRYSTAL OSCILLATOR The crystal oscillator generates a 32.768kHz reference clock, which is used to provide reference clock for the Real Time Clock (RTC) in the WM8312. It may also be used as a reference input to the FLL, for the purpose of generating other clocks. The oscillator requires an external crystal on the XTI and XTO pins, as well as two capacitors, connected as shown in Figure 17. Figure 17 Crystal Oscillator A suitable crystal oscillator should be selected in accordance with the following requirements: PARAMETER Norminal frequency Series resistance Maximum driving level 50 0.5 MIN 32.768 70 MAX UNITS kHz k W Table 17 Selection of Crystal Oscillator Component The load capacitors C1 and C2 should be selected according to the recommended load capacitance, CL of the crystal, which is given by the following equation: Assuming C1 = C2 and CSTRAY = 2.75pF (typical pad i/o capacitance), then: C1 = C2 = 2 x (CL - 2.75pF). For example, if the crystal has a load capacitance CL = 9pF, then C1 = C2 = 12.5pF. If a suitable 32.768kHz clock is already present elsewhere in the system, it is possible for the WM8312 to use that external clock instead. The external clock should be applied to pin XTI, and the XTO pin left floating in this case. w PP, December 2009, Rev 3.0 49 WM8312 13.3 FREQUENCY LOCKED LOOP (FLL) Pre-Production The integrated FLL can be used to generate a clock on the CLKOUT pin from a wide variety of different reference sources and frequencies. The FLL can use either CLKIN or the 32.768kHz oscillator as its reference. A wide range of CLKIN frequencies can be supported; this may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is tolerant of jitter and may be used to generate a stable clock reference from a less stable input signal. The FLL characteristics are summarised in "Electrical Characteristics". To simplify the configuration of the FLL, an `automatic' mode is provided in order to synthesize a number of commonly used reference frequencies using the 32.768kHz crystal oscillator as a reference. The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other register settings have been updated. When changing the input reference frequency FREF, it is recommended that the FLL be reset by setting FLL_ENA to 0. The FLL input reference is configured using the FLL_CLK_SRC register bit. The available sources are the CLKIN pin or the 32.768kHz crystal oscillator. The field FLL_CLK_REF_DIV provides the option to divide the selected input reference by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected. The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set to the recommended value quoted in Table 20. The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field FLL_FRAC. Power consumption in the FLL is reduced in integer mode; however, the performance may also be reduced, with increased noise or jitter on the output. If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie. FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0. For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to produce a non-integer value of N.K. The FLL output frequency is generated according to the following equation: FOUT = (FVCO / FLL_OUTDIV) The FLL operating frequency, FVCO is set according to the following equation: FVCO = (FREF x N.K x FLL_FRATIO) See Table 20 for the coding of the FLL_OUTDIV and FLL_FRATIO fields. FREF is the input frequency, as determined by FLL_CLK_REF_DIV. FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported. Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. w PP, December 2009, Rev 3.0 50 Pre-Production WM8312 In order to follow the above requirements for FVCO, the value of FLL_OUTDIV should be selected according to the desired output FOUT. The divider, FLL_OUTDIV, must be set so that FVCO is in the range 90-100MHz. The available divisions are integers from 4 to 64. Some typical settings of FLL_OUTDIV are noted in Table 18. OUTPUT FREQUENCY FOUT 2.8125 MHz - 3.125 MHz 3.75 MHz - 4.1667 MHz 5.625 MHz - 6.25 MHz 11.25 MHz - 12.5 MHz 18 MHz - 20 MHz 22.5 MHz - 25 MHz Table 18 Selection of FLL_OUTDIV FLL_OUTDIV 011111 (divide by 32) 010111 (divide by 24) 001111 (divide by 16) 000111 (divide by 8) 000100 (divide by 5) 000011 (divide by 4) The value of FLL_FRATIO should be selected as described in Table 19. REFERENCE FREQUENCY FREF 1MHz - 13.5MHz 256kHz - 1MHz 128kHz - 256kHz 64kHz - 128kHz Less than 64kHz Table 19 Selection of FLL_FRATIO FLL_FRATIO 000 (divide by 1) 001 (divide by 2) 010 (divide by 4) 011 (divide by 8) 100 (divide by 16) In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLL_OUTDIV) The value of FLL_N and FLL_K can then be determined as follows: N.K = FVCO / (FLL_FRATIO x FREF) See Table 20 for the coding of the FLL_OUTDIV and FLL_FRATIO fields. Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable. In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field. This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an integer value, as illustrated in the following example: If N.K = 8.192, then K = 0.192. Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex). For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order that N.K is a non-integer value. Care must always be taken to ensure that the FLL operating frequency, FVCO, is within its recommended limits of 90-100 MHz. w PP, December 2009, Rev 3.0 51 WM8312 The register fields that control the FLL are described in Table 20. ADDRESS R16530 (4092h) FLL Control 1 BIT 2 LABEL FLL_FRAC DEFAULT 0 Pre-Production DESCRIPTION Fractional enable 0 = Integer Mode 1 = Fractional Mode Integer mode offers reduced power consumption. Fractional mode offers best FLL performance, provided also that N.K is a noninteger value. FLL Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. FOUT clock divider 000000 = Reserved 000001 = Reserved 000010 = Reserved 000011 = 4 000100 = 5 000101 = 6 ... 111110 = 63 111111 = 64 (FOUT = FVCO / FLL_OUTDIV) Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. 0 FLL_ENA 0 R16531 (4093h) FLL Control 2 13:8 FLL_OUTDIV [5:0] 000000 6:4 FLL_CTRL_R ATE [2:0] 000 2:0 FLL_FRATIO [2:0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for high FREF 011 recommended for low FREF R16532 (4094h) FLL Control 3 R16533 (4095h) FLL Control 4 15:0 14:5 3:0 FLL_K [15:0] FLL_N [9:0] FLL_GAIN [3:0] 0000h 177h 0000 Fractional multiply for FREF (MSB = 0.5) Integer multiply for FREF (LSB = 1) Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 PP, December 2009, Rev 3.0 52 w Pre-Production ADDRESS BIT LABEL DEFAULT WM8312 DESCRIPTION 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1XXX = x 256 Recommended that this register is not changed from default. FLL Clock Reference Divider 00 = 1 01 = 2 10 = 4 11 = 8 CLKIN must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. 1:0 FLL_CLK_SR C [1:0] 00 FLL Clock source 00 = 32.768kHz xtal oscillator 01 = CLKIN 10 = Reserved 11 = Reserved R16534 (4096h) FLL Control 5 4:3 FLL_CLK_RE F_DIV [1:0] 00 Table 20 FLL Control 13.3.1 FLL AUTO MODE To simplify the configuration of the FLL, an `automatic' mode is provided in order to synthesize a number of commonly used reference frequencies using the 32.768kHz crystal oscillator as a reference. FLL Automatic mode is selected by setting the FLL_AUTO register bit as described in Table 21. When FLL_AUTO is set, the FLL is automatically configured to select the 32.768kHz oscillator as the FLL reference, and will generate the output frequency selected by FLL_AUTO_FREQ. FLL Automatic mode should be selected while the FLL is disabled (FLL_ENA = 0). After Automatic mode has been selected, the FLL can be enabled and disabled using FLL_ENA, as described in Table 20. ADDRESS R16529 (4091h) Clock Control 2 BIT 7 LABEL FLL_AUTO DEFAULT 1 DESCRIPTION FLL Automatic Mode Enable 0 = Manual configuration mode 1 = Automatic configuration mode (To enable the FLL output, FLL_ENA must also be set in Automatic mode) FLL Automatic Mode Frequency select 000 = 2.048MHz 001 = 11.2896MHz 010 = 12MHz 011 = 12.288MHz 100 = 19.2MHz 101 = 22.5792MHz 110 = 24MHz 111 = 24.576MHz 2:0 FLL_AUTO_F REQ [2:0] 000 Table 21 FLL Automatic Mode PP, December 2009, Rev 3.0 53 w WM8312 14 BOOTSTRAPPING AND OTP MEMORY CONTROL 14.1 GENERAL DESCRIPTION Pre-Production The WM8312 is a highly configurable device which can be tailored specifically to the requirements of a complex system application. The sequencing and voltage control of the integrated DC-DC Converters and LDOs in power-up, shut-down and SLEEP conditions is crucial to the robust operation of the application. In development, the WM8312 allows designers to modify or experiment with different settings of the control sequences by writing to the applicable registers in the OFF state prior to commanding an `ON' state transition. Configuration settings can also be stored on an external EEPROM and loaded onto the WM8312 as required. For production use, the WM8312 provides an on-chip One-Time Programmable (OTP) memory, in which the essential parameters for starting up the device can be programmed. This allows the WM8312 to start up and shut down the system with no dependency on any other devices for application-specific configuration parameters. 14.2 DBE AND OTP MEMORY DEFINITION An illustration of the WM8312 memory locations is shown in Figure 18. The main Register Map of the WM8312 contains a block of data in a `Window' area which is mirrored in the OTP and/or the DBE Memory. Data from the external DBE Memory can be loaded into the Window area. Data can be transferred from the Window into OTP Memory and also from the OTP Memory into the Window. The Window is called the DBE/OTP Register Window (DORW); the data in this Window is mirrored in other locations within the WM8312 Register Map. WM8312 Register Map Key Unique ID Factory Set Data User Configurable DBE Check Power Management & Configuration Registers Dynamic Bootstrap EEPROM (DBE) Memory 00h 08h 10h 18h 20h 28h DBE Page 4 Data DBE Page 3 Data DBE Page 2 Data DORW Page 0 Data DORW Page 1 Data DORW Page 2 Data DORW Page 3 Data DORW Page 4 Data OTP Memory OTP Page 0 Data OTP Page 1 Data OTP Page 2 Data OTP Page3 Data 00h 08h 10h 18h Note that the recommended external DBE memory is arranged in 8-bit words Figure 18 DBE and OTP Memory Layout w PP, December 2009, Rev 3.0 54 Pre-Production The DORW contains 5 pages of data, as illustrated in Figure 18. WM8312 Page 0 of the DORW contains a 128-bit pseudo-random unique ID. The unique ID is written to the OTP at the time of manufacture. It is copied to the DORW when the WM8312 schedules an `ON' transition. This data cannot be changed. Page 1 of the DORW contains factory-set calibration and configuration data. This data is written to the OTP at the time of manufacture. It is copied to the DORW when the WM8312 schedules an `ON' transition. This data cannot be changed. Page 2 and Page 3 of the DORW contain bootstrap configuration data. This defines the sequence and voltage requirements for powering up the WM8312, and for configuring functions such as the clocks, FLL, GPIO1-6 and LED status indicators. Under default conditions, the bootstrap data is loaded into the DORW when the WM8312 schedules an `ON' transition. The WM8312 automatically determines whether to load the bootstrap data from DBE or from OTP as described in Section 14.3. Page 4 of the DORW contains a register that is used for DBE validity checking. It is copied to the DORW whenever the bootstrap configuration data is loaded from DBE in response to a start-up request in development mode. This register field enables the DBE data to be checked for valid content. The OTP contains 4 pages of data, as illustrated in Figure 18. The contents of the OTP pages correspond to Pages 0, 1, 2 and 3 of the DORW register map addresses. The DBE memory contains 3 pages of data, as illustrated in Figure 18. The contents of the DBE pages correspond to Pages 2, 3 and 4 of the DORW register map addresses. Note that the DBE memory (recommended component) is arranged as 8-bit words in "big-endian" format, and is therefore addressed as 6 pages of 8-bit data, corresponding to 3 pages of 16-bit data. For example, the DBE memory address 00h corresponds to bits 15:8 of the first register map word in DORW Page 2, and DBE address 01h corresponds to bits 7:0 of that same register word in DORW. The DORW can be accessed directly using the Control Interface in the OFF, ON and SLEEP power states. Note that Read/Write access to the DBE or OTP memories is not possible directly; these can only be accessed by copying to/from the DORW. In the PROGRAM state, Page 2 and Page 3 of the DORW can be written to the OTP. 14.3 BOOTSTRAP (START-UP) FUNCTION Under default conditions, the WM8312 bootstrap configuration data is loaded when the WM8312 schedules an `ON' transition. The bootstrap configuration data is loaded into Page 2 and Page 3 of the DORW from either an external DBE or from the integrated OTP. (The factory-set data in Page 0 and Page 1 is always loaded from the integrated OTP memory.) If Development mode is selected, then the bootstrap data is loaded from the Dynamic Bootstrap EEPROM (DBE). If Development mode is not selected, then the bootstrap data is loaded from the OTP memory. 14.3.1 START-UP FROM OTP MEMORY In volume production, development mode is not usually selected. In this case, the bootstrap configuration data is loaded from the internal OTP memory. The WM8312 performs a check for valid OTP data; if the OTP_CUST_ID field is set to zero, then the WM8312 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid OTP contents. The OTP memory contents are defined similarly to Pages 0, 1, 2 and 3 of the DORW memory contents listed in Section 14.6. w PP, December 2009, Rev 3.0 55 WM8312 14.3.2 START-UP FROM DBE MEMORY (DEVELOPMENT MODE) Pre-Production Development mode is selected if a logic high level (referenced to the LDO12 VPMIC voltage) is present on SCLK2. This should be implemented using a pull-up resistor. See Section 14.3.4 for details of the External DBE Memory connection. If development mode is selected, then the WM8312 performs a check for valid DBE data; if the DBE is not connected or contains invalid data, then the WM8312 remains in the OFF power state. The DBE data is deemed valid is the DBE_VALID_DATA field contains the value A596h. The WM8312 also performs a check for valid contents in the OTP_CUST_ID field in development mode; if the OTP_CUST_ID field is set to zero, then the WM8312 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid DBE contents. 14.3.3 START-UP FROM DORW REGISTER SETTINGS Under default settings, the bootstrap configuration data is always loaded when an ON transition is scheduled. For development purposes, this can be disabled by clearing the RECONFIG_AT_ON register bit. (Note that RECONFIG_AT_ON only selects whether Page 2/3/4 data is loaded; Page 0/1 data is always loaded from OTP whenever an ON transition is scheduled.) When RECONFIG_AT_ON = 1, the bootstrap data is reloaded from either the DBE or OTP when an ON transition is scheduled. The logic level on SCLK2 is checked to determine whether the DBE or the OTP memory should be used. If RECONFIG_AT_ON = 0, then the latest contents of the DORW are used to configure the start-up sequence. Note that, when WM8312 start-up is scheduled using this method, the contents of OTP_CUST_ID is still checked for valid contents. In development mode, the DBE_VALID_DATA field is also checked. See Section 14.3.2 for details. Note that the RECONFIG_AT_ON control register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16390 (4006h) Reset Control BIT 15 LABEL RECONFIG_A T_ON DEFAULT 1 DESCRIPTION Selects if the bootstrap configuration data should be reloaded when an ON transition is scheduled 0 = Disabled 1 = Enabled Protected by user key Table 22 Bootstrap Configuration Reload Control 14.3.4 EXTERNAL DBE MEMORY CONNECTION The recommended component for the external DBE is the Microchip 24AA32A, which provides 32 bytes of memory space. The DBE interfaces with the WM8312 via the SCLK2 and SDA2 pins, and initiates an I2C transfer of data from the DBE when required. The necessary electrical connections for this device are illustrated in Figure 19. The WM8312 assumes an EEPROM device ID of 1010 0001 (A1h) for DBE read cycles. The DBE memory contents are defined similarly to Pages 2, 3 and 4 of the DORW memory contents listed in Section 14.6. w PP, December 2009, Rev 3.0 56 Pre-Production A0 A1 A2 VSS VCC WP * SCL SDA WM8312 LDO12VOUT 4k7 4k7 SCLK2 SDA2 Microchip 24AA32A WM8312 * WP is the Write Protect pin; the DBE is WriteProtected when WP is connected to LDO12VOUT Figure 19 DBE Memory Connection Note that the WM8312 does not support programming the external DBE memory. External programming of DBE whilst physically connected to the WM8312 is possible by putting the WM8312 in the OFF state. This is supported on the evaluation board, provided the voltage levels on SCLK2 and SDA2 are less than or equal to the LDO12 VPMIC voltage. Note that the Write-Protect (WP) pin on the DBE must be connected to GND (Vss) in this case. 14.4 OTP / DBE MEMORY CONTROL The OTP and DBE Memory commands are initiated by writing to the OTP Control Register, as defined in Section 14.4.6. The supported commands are described below. READ DBE MEMORY - This command instructs the WM8312 to load data from the external DBE into the WM8312 DORW memory area. Note that this command is performed automatically when the WM8312 starts up in development mode. READ OTP MEMORY - This command instructs the WM8312 to load data from the integrated OTP memory area into the WM8312 DORW memory area. Note that this command is performed automatically when the WM8312 starts up in normal (ie. non-development) mode. WRITE OTP MEMORY - This command instructs the WM8312 to program the integrated OTP, by writing a copy of the DORW memory area (Pages 0, 1, 2 and 3) to the OTP memory. This command should be performed after the required settings have been configured in the DORW memory. The required settings can be configured in the DORW either as a result of a DBE Read command, or else through register writes in the PROGRAM power state. Note that the Write OTP command should only be performed once on each OTP page; after the Write OTP command has been performed, the contents of the affected page(s) cannot be erased or re-programmed. VERIFY OTP MEMORY - This command instructs the WM8312 to compare the contents of the OTP memory with the contents of the DORW memory. The Verify OTP command performs a check that the OTP data is identical to the DORW contents, in order to confirm the success of the Write OTP operation. For increased reliability, the WM8312 can apply a `Margin Read' function when verifying the OTP memory; it is recommended that the Margin Read option is used, as described in Section 14.4.4. FINALISE OTP PAGES - This command instructs the WM8312 to set the OTP_CUST_FINAL bit in the OTP memory. The Finalise OTP command ensures that any subsequent OTP_WRITE commands to Page 2 or Page 3 of the OTP will have no effect and that the OTP contents are maintained securely. The OTP and DBE Memory commands are each described in the following sections. Note that, in some cases, commands may be executed on a single page of memory or may be executed as a Bulk operation on all available memory pages. Completion of each OTP or DBE Memory command is indicated via an Interrupt flag, as described in Section 14.5. The pass/fail outcome of any OTP command is also indicated by the Interrupt bits. Note that read/write access to the WM8312 Register Map is not supported while a DBE/OTP command is in progress. It is recommended that the IRQ pin is configured to indicate any DBE/OTP w PP, December 2009, Rev 3.0 57 WM8312 Pre-Production Interrupt event; the host processor should read the OTP/DBE Interrupt event flags to confirm the OTP/DBE command status following the assertion of the IRQ pin. The programming supply voltage PROGVDD is required for the OTP Write commands and the OTP Finalise command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. 14.4.1 ENTERING / EXITING THE PROGRAM STATE The DBE and OTP commands are only supported when the WM8312 is in the PROGRAM state. The WM8312 can only enter the PROGRAM state as a transition from the OFF state. This is commanded by setting the OTP_PROG register bit. Important note - when the PROGRAM state is selected, the WM8312 will read all pages of the OTP memory into the corresponding pages of the DORW. This is required in order to confirm if the OTP contents have already been finalised (see Section 14.4.5). The previous contents of the DORW registers will be lost when the PROGRAM state is entered. The transition into the PROGRAM state can be confirmed by reading the MAIN_STATE register field as defined in Section 11.2. When the MAIN_STATE register reads back a value of 01011, then the WM8312 is in the PROGRAM state. In the PROGRAM state, the DBE and OTP commands are initiated by further writes to the OTP Control Register (R16394), as described in the following sections. To exit the PROGRAM state and resume normal operations, a Device Reset must be scheduled. 14.4.2 OTP / DBE READ COMMAND The Read command loads either one or all data pages from the DBE or OTP into the corresponding page(s) of the DORW. The Read commands are selected by writing 1 to the OTP_READ bit. To read the OTP, the OTP_MEM bit should be set to 1. To read the DBE, the OTP_MEM bit should be set to 0. The Read Margin Level is selected by setting the OTP_READ_LVL. Note that this register relates to the OTP only; it has no effect on DBE Read commands. The recommended setting for the OTP Read command is `Normal' level. The OTP_READ_LVL field should be set to 00b. To read a single memory page, the applicable page is selected by setting the OTP_PAGE field. To read all memory pages, the OTP_BULK bit should be set to 1. Note that the OTP_PAGE field is defined differently for DBE pages and for OTP pages, as detailed in Section 14.4.6. All other bits in the OTP Control Register should be set to 0 when a Read command is issued. (Note that OTP_PROG should be set to 0 when a Read command is issued.) For typical applications, the Bulk Read commands are recommended. The OTP Control Register contents for the OTP / DBE Bulk Read Commands are detailed in Table 23. READ COMMAND DBE Read All OTP Read All Table 23 OTP / DBE Read Command OTP CONTROL REGISTER VALUE 0120h 2120h 14.4.3 OTP WRITE COMMAND The Write command programs one or all data pages of the OTP with data from the corresponding page(s) of the DORW. The Write commands are selected by writing 1 to the OTP_WRITE bit. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8312 does not support programming the external DBE memory.) w PP, December 2009, Rev 3.0 58 Pre-Production WM8312 To write a single memory page, the applicable page is selected by setting the OTP_PAGE field. To write all memory pages, the OTP_BULK bit should be set to 1. Note that Page 0 and Page 1 will be programmed during manufacture, and cannot be re-written. OTP Write is then only possible to Page 2 and Page 3. Selecting the OTP_BULK bit will select OTP Write to Page 2 and Page 3 only. Note that selecting the OTP_BULK option will cause an OTP Error to be indicated (see Section 14.5). This is because the Bulk Write to Page 0 and Page 1 is not permitted after the factory configuration of the WM8312. It is still possible to Verify the OTP Bulk Write, but the OTP_ERR_EINT flag must be cleared before doing so. The recommended procedure is to Write Page 2 and Page 3 using single page OTP Write commands. All other bits in the OTP Control Register should be set to 0 when a Write command is issued. (Note that OTP_PROG should be set to 0 when a Write command is issued.) The programming supply voltage PROGVDD is required for the OTP Write command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. For typical applications, it is recommended to Write Page 2 and Page 3 in two separate commands. The OTP Control Register contents for these OTP Write Commands are detailed in Table 24. WRITE COMMAND OTP Write Page 2 OTP Write Page 3 Table 24 OTP Write Command OTP CONTROL REGISTER VALUE 2202h 2203h 14.4.4 OTP VERIFY COMMAND The Verify command compares one or all data pages of the OTP with data in the corresponding page(s) of the DORW. The Verify commands are selected by writing 1 to the OTP_VERIFY bit. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8312 does not support verifying the external DBE memory.) The Read Margin Level is selected by setting the OTP_READ_LVL. The recommended setting for the OTP Verify command is Margin 1. The OTP_READ_LVL field should be set to 10b. To verify a single memory page, the applicable page is selected by setting the OTP_PAGE field. To verify all memory pages, the OTP_BULK bit should be set to 1. All other bits in the OTP Control Register should be set to 0 when a Verify command is issued. (Note that OTP_PROG should be set to 0 when a Verify command is issued.) If the OTP Verify operation is unsuccessful (ie. the WM8312 detects a difference between the selected pages of the OTP and DORW memories), then this is indicated by the OTP_ERR_EINT Interrupt flag, as described in Section 14.5. Note that, when Verifying the OTP after it has been Finalised, the CUST_OTP_FINAL bit needs to be set in the DORW using a register write to R30736 prior to the OTP_VERIFY operation. This is because the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DORW; it only sets it in the OTP memory. If the CUST_OTP_FINAL bit is not set in DORW, then the OTP_VERIFY command will result in an OTP error indication. The OTP Control Register contents for all OTP Verify Commands are detailed in Table 25. VERIFY COMMAND OTP Verify Page 0 OTP Verify Page 1 OTP Verify Page 2 OTP Verify Page 3 OTP Verify All Table 25 OTP Verify Command (Margin 1) OTP CONTROL REGISTER VALUE 2480h 2481h 2482h 2483h 24A0h w PP, December 2009, Rev 3.0 59 WM8312 14.4.5 OTP FINALISE COMMAND Pre-Production The Finalise command sets the OTP finalise bit for the user-programmable pages of the OTP memory. The Finalise commands are selected by writing 1 to the OTP_FINAL bit. Note that Page 0 and Page 1 will be programmed and finalised during manufacture; these memory pages cannot be re-written by users. Following the user Finalise command, Page 2 and Page 3 of the OTP memory will be prevented from any further OTP Write commands. Each page of the OTP memory can be programmed only once; the OTP Finalise command ensures that any subsequent Write commands will have no effect and that the OTP contents are maintained securely. The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8312 does not support this function on the external DBE memory.) The Customer Finalise bit (CUST_OTP_FINAL) is in Page 2. This page is selected by setting OTP_PAGE = 10. Note that the Page 2 finalise bit locks the contents of Page 2 and Page 3. All other bits in the OTP Control Register should be set to 0 when a Finalise command is issued. (Note that OTP_PROG should be set to 0 when a Finalise command is issued.) The programming supply voltage PROGVDD is required for the OTP Finalise command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. Note that the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DORW; it only sets it in the OTP memory. Care is required when verifying a Finalised OTP page, to avoid an OTP error indication, as described in Section 14.4.4. The OTP Control Register contents for the OTP Finalise Command is detailed in Table 26. This is the only recommended OTP Finalise Command; no variants of the Finalise Command should be used. FINALISE COMMAND OTP Finalise Page 2 (Note that this command finalises the contents of OTP Page 2 and Page 3.) Table 26 OTP Finalise Command OTP CONTROL REGISTER VALUE 2802h 14.4.6 OTP CONTROL REGISTER The OTP Control register (R16394) is defined in Table 27. Note that some of the OTP Programming registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16394 (400Ah) OTP Control BIT 15 LABEL OTP_PROG DEFAULT 0 DESCRIPTION Selects the PROGRAM device state. 0 = No action 1 = Select PROGRAM mode Note that, after PROGRAM mode has been selected, the chip will remain in PROGRAM mode until a Device Reset. Protected by user key Selects DBE or OTP memory for Program commands. 0 = DBE 1 = OTP Protected by user key Selects the FINALISE command, preventing further OTP programming. 0 = No action 1 = Finalise Command Protected by user key Selects the VERIFY command for the PP, December 2009, Rev 3.0 60 13 OTP_MEM 1 11 OTP_FINAL 0 10 OTP_VERIFY 0 w Pre-Production ADDRESS BIT LABEL DEFAULT WM8312 DESCRIPTION selected OTP memory page(s). 0 = No action 1 = Verify Command Protected by user key Selects WRITE command for the selected OTP memory page(s). 0 = No action 1 = Write Command Protected by user key Selects READ command for the selected memory page(s). 0 = No action 1 = Read Command Protected by user key Selects the Margin Level for READ or VERIFY OTP commands. 00 = Normal 01 = Reserved 10 = Margin 1 11 = Margin 2 Protected by user key Selects the number of memory pages for DBE / OTP commands. 0 = Single Page 1 = All Pages Selects the single memory page for DBE / OTP commands (when OTP_BULK=0). If OTP is selected (OTP_MEM = 1): 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 If DBE is selected (OTP_MEM = 0): 00 = Page 2 01 = Page 3 10 = Page 4 11 = Reserved Table 27 OTP Memory Control 9 OTP_WRITE 0 8 OTP_READ 0 7:6 OTP_READ_L VL [1:0] 00 5 OTP_BULK 0 1:0 OTP_PAGE [1:0] 00 14.5 OTP / DBE INTERRUPTS The OTP and DBE memories are associated with two Interrupt event flags. The OTP_CMD_END_EINT interrupt is set each time an OTP / DBE Command has completed or if OTP Auto-Program has completed. (See Section 14.4 for a definition of the OTP and DBE Commands. See Section 14.6.3 for details of the OTP Auto-Program function.) The OTP_ERR_EINT interrupt is set when an OTP / DBE Error has occurred. The errors detected include DBE Read Failure, OTP Verify Failure and attempted OTP Write to a page that has been `Finalised'. Each of these secondary interrupts triggers a primary OTP Memory Interrupt, OTP_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 76. w PP, December 2009, Rev 3.0 61 WM8312 ADDRESS R16402 (4012h) Interrupt Status 2 BIT 5 LABEL OTP_CMD_END_EINT Pre-Production DESCRIPTION OTP / DBE Command End interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. OTP / DBE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 OTP_ERR_EINT R16410 (401Ah) Interrupt Status 2 Mask 5 IM_OTP_CMD_END_EINT 4 IM_OTP_ERR_EINT Table 28 OTP Memory Interrupts 14.6 DORW MEMORY CONTENTS The DORW is the DBE/OTP Register Window, as described in Section 14.2. Under normal operating conditions, this memory area is initialised with data from the integrated OTP or an external DBE memory. The DORW memory addresses range from R30720 (7800h) to R30759 (7827h). The complete register map definition is described in Section 28. The register fields in the DORW allow the start-up configuration of the DC-DC Converters, the LDO Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DORW also provides control of the Battery Charger, Clocking, USB Current Limit and the Start-Up (SYSOK) voltage threshold. Most of the DORW contents are duplicates of control registers that exist in the main register area below the DORW addresses. In theses cases, reading or writing to either address will have the same effect. Some register fields are defined only in the DORW area; a detailed description of these fields is provided in the following sub-sections. 14.6.1 DORW PAGE 0 Page 0 of the DORW occupies register addresses R30720 (7800h) to R30727 (7807h). This contains factory-preset data which is loaded from OTP when an `ON' state transition is scheduled. Page 0 of the DORW contains a 128-bit unique ID. Note that these fields are Read-Only in the OTP and cannot be changed. 14.6.2 DORW PAGE 1 Page 1 of the DORW occupies register addresses R30728 (7808h) to R30735 (780Fh). This contains factory-preset data which is loaded from OTP when an `ON' state transition is scheduled. Page 1 of the DORW contains trim parameters that ensure the accuracy of the voltage references and the power management RC oscillator. Note that these fields are Read-Only in the OTP and cannot be changed. 14.6.3 DORW PAGE 2 Page 2 of the DORW occupies register addresses R30736 (7810h) to R30743 (7817h). This contains user-programmable data. w PP, December 2009, Rev 3.0 62 Pre-Production WM8312 This page of data is normally loaded from OTP when `ON' state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the first page of DBE memory (00h to 0Fh) when `ON' state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from DBE using the DBE Read command. Note that DBE Address 00h corresponds to bits 15:8 at the start address of DORW Page 2; DBE Address 01h corresponds to bits 7:0 at the same DORW address. If the WM8312 configuration data is loaded from external DBE in response to an `ON' state transition request, and the OTP_AUTO_PROG register bit is set, then the WM8312 will program the OTP with the contents Page 2 and Page 3 of the DORW data, after the DBE data has been loaded and confirmed as valid. The WM8312 will also perform a Margin 1 Verify as part of the auto-program function. The programming supply voltage PROGVDD is required for the OTP_AUTO_PROG command. It is also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the required supply voltages. Using the auto-program function described above, the OTP will be finalised if the OTP_CUST_FINAL bit is set in the DBE data. Completion of the auto-program is indicated using the OTP interrupts, as described in Section 14.5. The auto-program completion is also indicated on the Status LED outputs, as described in Section 22. The OTP_CUST_ID field is used to hold a Customer Identifier for the OTP data contents. Whenever an `ON' state transition is requested, then the OTP_CUST_ID field is checked to confirm valid OTP data. If the OTP_CUST_ID field is set to zero, then the WM8312 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid OTP contents. The OTP_CUST_FINAL bit is used to control whether the user-programmable OTP data (Page 2 and Page 3) is finalised. If OTP_CUST_FINAL is set in the OTP and also set in the DORW, then the WM8312 prevents any further Writes to the OTP. If the DORW has been loaded from the OTP, then the OTP_CUST_FINAL bit indicates whether any further Write operations are possible. If the DORW has been loaded from the DBE, and the OTP auto-progamming option is selected (see above), then the value of the OTP_CUST_FINAL bit will be copied from the DBE memory to the OTP memory. The above registers are defined in Table 29. ADDRESS R30736 (7810h) Customer OTP ID BIT 15 LABEL OTP_AUTO_ PROG DEFAULT 0 DESCRIPTION If this bit is set when bootstrap data is loaded from DBE (in development mode), then the DBE contents will be programmed in the OTP. This field is checked when an `ON' transition is requested. A non-zero value is used to confirm valid data. If OTP_CUST_FINAL is set in the OTP and also set in the DORW, then no further Writes are possible to the OTP. 14:1 OTP_CUST_ ID [13:0] OTP_CUST_ FINAL 0000h 0 0 Table 29 OTP Registers - DORW Page 2 The remaining contents of DORW Page 2 include the registers listed in Table 30, which are defined in other sections of this datasheet. w PP, December 2009, Rev 3.0 63 WM8312 REGISTER DC1_ON_SLOT [2:0] DC1_FREQ [1:0] DC1_PHASE DC1_ON_VSEL [6:2] DC1_CAP [1:0] DC2_ON_SLOT [2:0] DC2_FREQ [1:0] DC2_PHASE DC2_ON_VSEL [6:2] DC2_CAP [1:0] DC3_ON_SLOT [2:0] DC3_PHASE DC3_ON_VSEL [6:2] DC3_CAP [1:0] LDO1_ON_SLOT [2:0] LDO1_ON_VSEL [4:0] LDO2_ON_SLOT [2:0] LDO2_ON_VSEL [4:0] LDO3_ON_SLOT [2:0] LDO3_ON_VSEL [4:0] LDO4_ON_SLOT [2:0] LDO4_ON_VSEL [4:0] LDO5_ON_SLOT [2:0] LDO5_ON_VSEL [4:0] LDO6_ON_SLOT [2:0] LDO6_ON_VSEL [4:0] LDO7_ON_SLOT [2:0] LDO7_ON_VSEL [4:0] LDO8_ON_SLOT [2:0] LDO8_ON_VSEL [4:0] Table 30 DORW Page 2 LDO Regulator 8 LDO Regulator 7 LDO Regulator 6 LDO Regulator 5 LDO Regulator 4 LDO Regulator 3 LDO Regulator 2 LDO Regulator 1 DC-DC Converter 3 DC-DC Converter 2 FUNCTION DC-DC Converter 1 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.2 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 Pre-Production REFERENCE 14.6.4 DORW PAGE 3 Page 3 of the DORW occupies register addresses R30744 (7818h) to R30751 (781Fh). This contains user-programmable data. This page of data is normally loaded from OTP when `ON' state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the second page of DBE memory (10h to 1Fh) when `ON' state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from DBE using the DBE Read command. Note that DBE Address 10h corresponds to bits 15:8 at the start address of DORW Page 3; DBE Address 11h corresponds to bits 7:0 at the same DORW address. The contents of DORW Page 3 include the registers listed in Table 31. w PP, December 2009, Rev 3.0 64 Pre-Production REGISTER LDO9_ON_SLOT [2:0] LDO9_ON_VSEL [4:0] LDO10_ON_SLOT [2:0] LDO10_ON_VSEL [4:0] LDO11_ON_SLOT [2:0] LDO11_ON_VSEL [3:0] EPE1_ON_SLOT [2:0] EPE2_ON_SLOT [2:0] GP1_DIR GP1_PULL [1:0] GP1_INT_MODE GP1_PWR_DOM GP1_POL GP1_OD GP1_ENA GP1_FN [3:0] GP2_DIR GP2_PULL [1:0] GP2_INT_MODE GP2_PWR_DOM GP2_POL GP2_OD GP2_ENA GP2_FN [3:0] GP3_DIR GP3_PULL [1:0] GP3_INT_MODE GP3_PWR_DOM GP3_POL GP3_OD GP3_ENA GP3_FN [3:0] GP4_DIR GP4_PULL [1:0] GP4_INT_MODE GP4_PWR_DOM GP4_POL GP4_OD GP4_ENA GP4_FN [3:0] GP5_DIR GP5_PULL [1:0] GP5_INT_MODE GP5_PWR_DOM GP5_POL GP5_OD GP5_ENA GP5_FN [3:0] GP6_DIR GP6_PULL [1:0] GP6_INT_MODE GP6_PWR_DOM GP6_POL GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 External Power Converter Enable GPIO1 LDO Regulator 11 LDO Regulator 10 FUNCTION LDO Regulator 9 WM8312 REFERENCE See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.4 See Section 15.12.5 See Section 15.12.5 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 See Section 21.3 PP, December 2009, Rev 3.0 65 w WM8312 REGISTER GP6_OD GP6_ENA GP6_FN [3:0] CLKOUT_SLOT [2:0] CLKOUT_SRC XTAL_ENA XTAL_INH FLL_AUTO_FREQ [2:0] USB_ILIM [2:0] USB100MA_STARTUP [1:0] CHG_ENA WDOG_ENA LED1_SRC [1:0] LED2_SRC [1:0] SYSOK_THR [2:0] Table 31 DORW Page 3 Battery Charger Enable Watchdog Timer System Status LED Drivers Supply Voltage Monitoring USB Configuration Clocking FUNCTION See Section 21.3 See Section 21.3 See Section 21.3 See Section 13.1 See Section 13.1 See Section 13.1 See Section 13.1 See Section 13.3 See Section 17.4 See Section 17.4 See Section 17.7 See Section 25 See Section 22.2 See Section 22.2 See Section 24.4 Pre-Production REFERENCE 14.6.5 DORW PAGE 4 Page 4 of the DORW occupies register addresses R30752 (7820h) to R30759 (7827h). This page of data is loaded from the third page of DBE memory (20h to 2Fh) when `ON' state transition is scheduled in Development Mode. This page of data can also be loaded from DBE using the DBE Read command. Note that DBE Address 20h corresponds to bits 15:8 at the start address of DORW Page 4; DBE Address 21h corresponds to bits 7:0 at the same DORW address. The DBE_VALID_DATA register is used to hold a validation field for the DBE data contents. If the WM8312 configuration data is loaded from the external DBE in response to an `ON' state transition request in Development Mode, then the DBE_VALID_DATA field is checked to confirm valid DBE data. The DBE data is deemed valid if the DBE_VALID_DATA field contains the value A596h. If the DBE is not connected or contains invalid data, then the WM8312 remains in the OFF power state until a Device Reset. The DBE_VALID_DATA register is defined in Table 32. ADDRESS R30759 (7827h) DBE CHECK DATA BIT 15:0 LABEL DBE_VALID _DATA [15:0] DEFAULT 0000h DESCRIPTION This field is checked in development mode when an `ON' transition is requested. A value of A596h is required to confirm valid data. Table 32 DBE Registers - DORW Page 5 w PP, December 2009, Rev 3.0 66 Pre-Production WM8312 15 POWER MANAGEMENT 15.1 GENERAL DESCRIPTION The WM8312 provides 4 DC-DC Converters and 11 LDO Regulators. The DC-DC Converters comprise 3 step-down (Buck) converters and 1 step-up (Boost) converter. The Regulators comprise general purpose LDOs (LDO1 - LDO6) and low-noise analogue LDOs (LDO7 - LDO10). The analogue LDOs offer superior PSRR, noise and load-transient performance. LDO11 is a low power LDO intended for powering "always on" circuits connected to the WM8312; this LDO can be configured to remain enabled in the OFF state. These power management components are designed to support application processors and associated peripherals. DC-DC1 and DC-DC2 are intended to provide power to the processor voltage domains; DC-DC3 is suitable for powering memory circuits or for use as a pre-regulator for the LDOs. The output voltage of each of the buck converters and regulators is programmable in software through control registers. The WM8312 can execute programmable sequences of enabling and disabling the DC-DC Buck Converters and LDO Regulators as part of the transitions between the ON, OFF and SLEEP power states. The WM8312 power management circuits can also interface with configurable hardware control functions supported via GPIO pins. These include GPIO inputs for selecting alternate voltages or operating modes, and GPIO outputs for controlling external power management circuits. The configuration of the power management circuits, together with some of the GPIO pins and other functions, may be stored in the integrated OTP memory. This avoids any dependence on a host processor to configure the WM8312 at start-up. See Section 14 for details of the OTP memory. 15.2 DC-DC CONVERTER AND LDO REGULATOR ENABLE The integrated DC-DC Converters and LDO Regulators can each be enabled in the ON or SLEEP power states by setting the DCm_ENA or LDOn_ENA bits as defined in Section 15.12.1. Note that setting the DCm_ENA or LDOn_ENA bits in the OFF state will not enable the DC-DC Converters or LDO Regulators. These bits should not be written to when the WM8312 is in the OFF state; writing to these bits in the OFF state may cause a malfunction. In many applications, there will be no need to write to the DCm_ENA or LDOn_ENA bits, as these bits are controlled by the WM8312 when a power state transition is scheduled. Dynamic, run-time control of the DC-DC Converters or LDOs is also possible by writing to these registers. Note that the DC-DC4 Boost Converter cannot be configured as part of the power state transitions; this Converter must always be enabled by writing to the DC4_ENA bit. The DC-DC Converters and LDO Regulators can be assigned to a Hardware Enable (GPIO) input for external enable/disable control. In this case, the Converter or Regulator is not affected by the associated DCm_ENA or LDOn_ENA bits. See Section 15.3 for further details. The WM8312 can also control other circuits, including external DC-DC Converters or LDO Regulators using the External Power Enable (EPE) outputs. The External Power Enable outputs are alternate functions supported via GPIO - see Section 21. The External Power Enable outputs can be controlled in the same way as the internal DC-DC Converters and LDO Regulators. The associated control bits are EPE1_ENA and EPE2_ENA, as defined in Section 15.12.1. LDO Regulator 11 is a Low Power LDO Regulator, which is configured differently to the other LDOs. It is a low-power LDO intended for "Always-On" functions external to the WM8312 and can be enabled when the WM8312 is in the OFF power state. When LDO11_FRCENA is set, then LDO11 is enabled at all times in the OFF, ON and SLEEP states. Note that LDO11 is always disabled in the BACKUP and NO POWER states. See Section 15.12.4 for the definition of LDO11_FRCENA. The current commanded state of each of the DC-DC Converters, LDO Regulators and EPE outputs is indicated in the DCm_STS, LDOn_STS and EPEn_STS register bits. If a fault condition causes any Converter or Regulator to be disabled, then the associated _ENA and _STS fields are reset to 0. w PP, December 2009, Rev 3.0 67 WM8312 15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL Pre-Production The DC-DC Converters 1-3 and LDO Regulators 1-11 may be programmed to switch on in a selected timeslot within the ON sequence using the DCm_ON_SLOT or LDOn_ON_SLOT fields. These register fields are defined in Section 15.12.2 and Section 15.12.4. Alternatively, these fields can be used to assign a converter / regulator to one of the Hardware Enable Inputs. (The Hardware Enable Inputs are alternate functions supported via GPIO - see Section 21.) Converters / regulators which are assigned to one of the Hardware Enable Inputs are enabled or disabled according to the logic level of the respective GPIO input in the ON or SLEEP power states. The Hardware Enable Inputs are effective from the end of the ON sequence until the start of the OFF sequence. Note that the GPIO Hardware Enable function is not the same as the GPIO Hardware Control function. Any converters / regulators which are assigned to timeslots within the ON sequence will be disabled in the reverse sequence when an OFF sequence is scheduled. Any converters / regulators which are not assigned to timeslots, or are assigned to Hardware Enable Inputs, will be disabled immediately at the start of the OFF sequence. Each of the converters / regulators may also be programmed to be disabled in a selected timeslot within the SLEEP sequence using the DCm_SLP_SLOT or LDOn_SLP_SLOT fields. In the case of converters / regulators which are not disabled by the SLEEP sequence, these fields determine in which timeslot each converter or regulator enters its SLEEP configuration. Any converters / regulators which are disabled as part of the SLEEP sequence will be enabled in the reverse sequence when a WAKE transition is scheduled. By default, the OFF sequence is the reverse of the ON sequence. Similarly, the WAKE sequence is the reverse of the SLEEP sequence. If a different behaviour is required, this can be achieved by writing to the _ON_SLOT or _SLP_SLOT registers between transitions in order to re-define the sequences. Any converters / regulators which are assigned to Hardware Enable Inputs will remain under control of the Hardware Enable Inputs in the SLEEP power state. In this case, the DCm_SLP_SLOT or LDOn_SLP_SLOT fields determine in which timeslot the converter / regulator enters its SLEEP configuration. The WM8312 will control the DCm_ENA or LDOn_ENA bit (see Section 15.2) for any converter / regulator that is enabled or disabled during the power state transitions. In the case of a converter / regulator assigned to a Hardware Enable (GPIO) input, the DCm_ENA or LDOn_ENA bit is not controlled and the converter / regulator is not affected by this bit. The DC-DC converters include a soft-start feature that limits in-rush current at start-up. However, in order to further reduce supply in-rush current, it is recommended that the individual converters are programmed to start up in different time slots within the start-up sequence, as described in Section 11.3. Similarly, it is recommended that the individual LDO regulators are programmed to start up in different time slots within the start-up sequence, as described in Section 11.3. Note that the DC-DC4 Boost Converter cannot be configured as part of the power state transitions; this Converter must always be enabled by writing to the DC4_ENA bit. The External Power Enable (EPE) outputs, EPE1 and EPE2, may also be assigned to timeslots in the ON / SLEEP sequences or assigned to Hardware Enable inputs using the EPEn_ON_SLOT and EPEn_SLP_SLOT fields described in 15.12.5. w PP, December 2009, Rev 3.0 68 Pre-Production WM8312 15.4.1 DC-DC BUCK CONVERTERS 15.4 OPERATING MODE CONTROL The DC-DC (Buck) Converters DC-DC1, DC-DC2 and DC-DC3 can be configured to operate in four different operating modes. The operating modes are summarised in Table 33. For more detailed information on the DC-DC Step-Down Converter operating modes, see Section 15.15.2. DC-DC CONVERTER OPERATING MODE Forced Continuous Conduction Mode (FCCM) Continuous / Discontinuous Conduction with Pulse-Skipping Mode (CCM/DCM with PS) Hysteretic Mode DESCRIPTION High performance mode for all static and transient load conditions. High efficiency mode for all static and transient load conditions. Performance may be less than FCCM mode for heavy load transients. High efficiency mode for light static and light transient loads only. Maximum load current is restricted; output voltage ripple is increased. Power saving mode for light loads only. High efficiency for ultra light loads. Low current soft-start control. LDO Mode Table 33 DC-DC (Buck) Converters Operating Modes The operating mode of the DC-DC Converters in the ON power state is selected using the DCm_ON_MODE register fields. The operating mode of the DC-DC Converters in the SLEEP power state is selected using the DCm_SLP_MODE register fields. When changing the operating mode of the DC-DC Converters in preparation for an increased load, a set-up time of 100s should be allowed for the operating mode to be established before applying the new load. Note that the operating mode of the DC-DC Converters may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.9 for details of Hardware Control. 15.4.2 DC-DC BOOST CONVERTERS The DC-DC4 Boost Converter is enabled by setting the DC4_ENA bit as described in Section 15.2. Note that this Converter cannot be enabled automatically under timeslot control in the ON transition. However, the Converter can either be disabled or unchanged in the SLEEP transition, as determined by DC4_SLPENA. The Boost Converter is intended to be used as a power supply for either of the Current Sinks, ISINK1 or ISINK2 (see Section 16). The Boost Converter must be configured for the applicable Current Sink using the DC4_FBSRC bit. When the DC-DC4 Boost Converter is enabled, its output voltage is regulated in such a way that the selected ISINK voltage (at ISINK1 or ISINK2) is 0.5V. Output voltages of up to 30V can be generated in order to support the current that has been selected for the ISINK. The required voltage range must be set using the DC4_RANGE field in order to ensure stable operation. If the Boost Converter is used to provide a supply for both ISINKs simultaneously, then the DC4_RANGE and DC4_FBSRC bits should be set according to whichever of the ISINKs requires the higher supply voltage. 15.4.3 LDO REGULATORS The LDO Regulators LDO1 - LDO10 can be configured to operate in Normal operating mode or in Low Power mode. The operating mode of the LDO Regulators in the ON power state is selected using the LDOn_ON_MODE register fields. The operating mode of the LDO Regulators in the SLEEP power state is selected using the LDOn_SLP_MODE register fields. w PP, December 2009, Rev 3.0 69 WM8312 Pre-Production For the standard LDOs, LDO1 - LDO6, two different Low Power modes are provided, offering limited load current capability and reduced quiescent current. When Low Power mode is selected in the ON or SLEEP power states, then the LDOn_LP_MODE register bits determine which Low Power mode is selected. Note that the operating mode and output voltage of the LDO Regulators may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.9 for details of Hardware Control. 15.5 OUTPUT VOLTAGE CONTROL 15.5.1 DC-DC BUCK CONVERTERS The output voltage of the DC-DC Converters 1-3 in the ON power state is selected using the DCm_ON_VSEL register fields. The output voltage of these converters in the SLEEP power state is selected using the DCm_SLP_VSEL register fields. DC-DC Converters 1 and 2 support two different switching frequencies, as described in Section 15.6. Note that the supported output voltage range for these converters is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The DC-DC Converters are dynamically programmable - the output voltage may be adjusted in software at any time. These converters are Buck (step-down) converters; their output voltage can therefore be lower than the input voltage, but cannot be higher. Note that the output voltage of DC-DC Converters 1 and 2 may also be controlled using the Dynamic Voltage Scaling features described in Section 15.6. Software control (using register writes) and hardware control (using the Hardware DVS Control inputs supported via GPIO) is supported. Note that the output voltage of the DC-DC Converters may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.9 for details of Hardware Control. When changing the output voltage of DC-DC Converters 1 and 2, the GPIO output "DC-DCm DVS Done" can be used to confirm the DVS Control has completed; see Section 15.6 for details. 15.5.2 DC-DC BOOST CONVERTERS The output voltage of the DC-DC4 Boost Converter is set as described in Section 15.4.3. The voltage is not commanded directly, but is regulated automatically by the WM8312 in order to support the current that has been commanded for the selected Current Sink (ISINK). 15.5.3 LDO REGULATORS 1-10 The output voltage of the LDO Regulators 1-10 in the ON power state is selected using the LDOn_ON_VSEL register fields. The output voltage of the LDO Regulators in the SLEEP power state is selected using the LDOn_SLP_VSEL register fields. The LDO Regulators are dynamically programmable - the output voltage may be adjusted in software at any time. Note that the output voltage of the LDO Regulators may also be controlled by the Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.9 for details of Hardware Control. 15.5.4 LDO REGULATOR 11 The output voltage of LDO11 can be set in two ways - it can be commanded directly, or it can be commanded to follow the voltage selection of DC-DC Converter 1. When LDO11_VSEL_SRC = 0, then the output voltage of LDO11 is set by LDO11_ON_VSEL (in the ON state) or by LDO11_SLP_VSEL (in the SLEEP state) in the same way as the other LDOs. w PP, December 2009, Rev 3.0 70 Pre-Production WM8312 When LDO11_VSEL_SRC = 1, the output voltage of LDO11 follows the voltage selection of DC-DC Converter 1. This enables both domains to be changed at the same time, eg. the processor core and processor `alive' domains. The LDO11 output voltage follows DC1_ON_VSEL or DC1_SLP_VSEL regardless of whether DC-DC1 is enabled or disabled. Note that, when LDO11_VSEL_SRC = 1, the LDO11 regulator adopts the nearest achievable output voltage, which may not be identical to the DC-DC1 voltage, due to the more limited range and resolution of LDO11 - the output voltage of LDO11 is in the range 0.8V to 1.55V in 50mV steps; the output voltage of DC-DC1 is in the range 0.6V to 1.8V in 12.5mV steps. 15.6 DC-DC BUCK CONVERTER CONTROL Soft-Start control is provided for each of the DC-DC Converters, using the DCm_SOFT_START register fields. When a DC-DC Converter is switched on, the soft-start circuit will apply current limiting in order to control the in-rush current. For DC-DC1 and DC-DC2, the current limit is increased through up to 8 stages to the full load condition. The DCm_SOFT_START registers select the duration of these stages. (Note that, under light loads, the full start-up may be achieved in fewer than 8 stages.) A similar function is provided for DC-DC3, but only 4 intermediate stages are implemented for this converter. When DC-DC3 is operating in Hysteretic Mode, the maximum DC output current can be set using the DC3_STNBY_LIM register. See Section 15.4.1 for details of the DC-DC3 operating modes. To ensure stable operation, the register fields DCm_CAP must be set for each of the DC-DC Converters according to the output capacitance. (Note that these fields are set via OTP/DBE settings only; they cannot be changed by writing to the control register.) The choice of output capacitor is described in Section 30.3. When a DC-DC Converter is disabled, the output pin can be configured to be floating or to be actively discharged. This is selected using DCm_FLT. DC-DC Converters 1 and 2 also support selectable switching frequency. This can either be 2MHz or 4MHz, according to the DCm_FREQ register field. (Note that these fields are set via OTP/DBE settings only; they cannot be changed by writing to the control register.) The switching frequency of DC-DC3 is fixed at 2MHz. Note that the supported output voltage range for DC-DC Converters 1 and 2 is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The switching phase of each DC-DC converter can be set using the DCm_PHASE bits. Where two converters are operating at the same switching frequency, the supply current ripple can be minimised by selecting a different switching phase for each converter. The Dynamic Voltage Scaling (DVS) feature on DC-DC1 and DC-DC2 enables hardware or software selection of an alternate output voltage, DCm_DVS_VSEL. This may be useful if a short-term variation in output voltage is required. The DVS voltage (set by DCm_DVS_VSEL) may be selected by setting DCm_DVS_SRC = 01. Alternatively, the DVS voltage may be selected under control of one of the Hardware DVS Control inputs supported via the GPIO pins. See Section 21 for details of configuring the GPIO pins as Hardware DVS Control inputs. Whenever the DVS voltage is selected by any method, the DVS selection takes precedence over the ON, SLEEP or Hardware Control (HWC) configuration. See Section 15.9 for details of Hardware Control options. The output voltage ramp rate is selectable for DC-DC Converters 1 and 2. The DCm_RATE field selects the rate of change of output voltage, whether this is in response to an operating mode transition, or any hardware or software command. Note that the DCm_RATE field is accurate in Forced Continuous Conduction Mode (FCCM); in other modes, the actual slew rate may be longer in the case of a decreasing output voltage selection, especially under light load conditions. w PP, December 2009, Rev 3.0 71 WM8312 Pre-Production The WM8312 can indicate the status of the Dynamic Voltage Scaling via a GPIO pin configured as a "DC-DC1 DVS Done" or "DC-DC2 DVS Done" output (see Section 21). When a GPIO pin is configured to indicate the DVS status, this signal is temporarily de-asserted during a DVS transition on the associated DC-DC Converter, and is subsequently asserted to indicate the transition has completed. Note that the GPIO DVS outputs indicate the progress of all output voltage slews; they are not limited to transitions associated with DCm_DVS_SRC; the GPIO DVS output also indicates the status of a slew caused by a write to the DCm_ON_VSEL register, or a slew to the DCm_SLP_VSEL voltage. Note also that the GPIO DVS outputs are indicators of the DVS control mechanism only; they do not confirm the output voltage accuracy. The output voltage can be checked using the voltage status bits if required (see Section 15.2). 15.7 DC-DC BOOST CONVERTER CONTROL The DC-DC4 Boost Converter is designed as a power source for the Current Sinks described in Section 16. The associated control registers for DC-DC4 are described in Section 15.4.2. The Boost Converter uses one or other of the Current Sinks to provide voltage feedback in order to control the converter output voltage. The selected Current Sink is determined by the DC4_FBSRC register bit. If the Boost Converter is used to provide a supply for both ISINKs simultaneously, then the DC4_RANGE and DC4_FBSRC bits should be set according to whichever of the ISINKs requires the higher supply voltage. It is important to follow the recommended control sequences for switching on/off the Boost Converter and Current Sinks. These sequences are described in Section 16. The maximum current that can be supported by the Boost Converter varies with the output voltage, as noted in the Electrical Characteristics (see Section 7.2). The Current Sinks are suited to controlling LED backlight circuits. At low output voltages (eg. 5V), the DC-DC4 boost converter is capable of supporting currents which exceed the maximum current rating of the Current Sinks. Please contact Wolfson Applications support if further guidance is required on configuring DC-DC4 for higher current than is supported by the Current Sinks. 15.8 LDO REGULATOR CONTROL The LDO Regulators 1-10 can be configured to act as Current Limited Switches by setting the LDOn_SWI field. When this bit is selected, there is no voltage regulation and the operating mode and output voltage controls of the corresponding LDO are ignored. In Switch mode, the switch is enabled (closed) and disabled (opened) by enabling or disabling the LDO. Note that Switch mode cannot be selected via the OTP memory settings, and must be configured after the WM8312 has entered the ON state. When the LDO Regulator is disabled (and Switch mode is not selected), the output pin can be configured to be floating or to be actively discharged. This is selected using LDOn_FLT. 15.9 HARDWARE CONTROL (GPIO) The DC-DC Converters, LDO Regulators and EPE outputs may be controlled by the Hardware Control inputs supported via the GPIO pins. The DCm_HWC_SRC, LDOn_HWC_SRC or EPEn_HWC_SRC fields determine which of these Hardware Control inputs is effective. See Section 21 for details of configuring the GPIO pins as Hardware Control inputs. Note that the GPIO Hardware Control function is not the same as the GPIO Hardware Enable function. Hardware Control is only possible when the applicable DCm_ENA, LDOn_ENA or EPEn_ENA control bit is set (see Section 15.2), or if a Hardware Enable has been assigned to the relevant function and is asserted. The action taken in response to the selected Hardware Control inputs is configurable for each DC-DC Converter, LDO Regulator or EPE output. The available options are described below. w PP, December 2009, Rev 3.0 72 Pre-Production WM8312 When a Hardware Control input is assigned to DC-DC Buck Converters 1-3, and is asserted, the operating mode and output voltage of the relevant DC-DC Converters is determined by the DCm_HWC_VSEL and DCm_HWC_MODE fields; this takes precedence over the normal ON or SLEEP settings. Note that the Hardware Control input can be used to disable a DC-DC Buck Converter if required, by setting DCm_HWC_MODE = 01. When a Hardware Control input is assigned to the DC-DC4 Boost Converter, and is asserted, the Converter is controlled as determined by the DC4_HWC_MODE field; this takes precedence over the normal ON or SLEEP settings. The available options are to disable the Converter, or to remain under control of DC4_ENA. When a Hardware Control input is assigned to LDO Regulators 1-10, and is asserted, the operating mode and output voltage of the relevant LDO Regulators is determined by the LDOn_HWC_VSEL and LDOn_HWC_MODE fields; this takes precedence over the normal ON or SLEEP settings. Note that, for the standard LDOs (LDO1 - LDO6), when Low Power Mode is selected (LDOn_HWC_MODE = 00 or 10), then the Low Power mode type is determined by the LDOn_LP_MODE register bits. When a Hardware Control input is assigned to the External Power Enable (EPE) outputs, and is asserted, the relevant EPE outputs are controlled as determined by the EPEn_HWC_ENA field; this takes precedence over the normal ON or SLEEP settings. The available options are to de-assert the EPE, or for the EPE to remain under control of EPEn_ENA. 15.10 FAULT PROTECTION Each of the DC-DC Buck Converters 1-3 is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the output voltage falls below the required level by more than the applicable undervoltage margin, as specified in Section 7.1. The DC-DC4 Boost Converter is monitored for voltage accuracy and fault conditions. The voltage at ISINK1 or ISINK2 is monitored as an indicator of an overcurrent condition. Each LDO Regulator is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the output voltage falls below the required level by more than the undervoltage margin, as specified in Section 7.4. The DCm_ERR_ACT and LDOn_ERR_ACT fields configure the fault response to an Undervoltage condition. An Interrupt is always triggered under this condition (see Section 15.13); additional action can also be selected independently for each converter / regulator. The options are to ignore the fault, shut down the converter, or to shut down the system. To prevent false alarms during short current surges, faults are only signalled if the fault condition persists. If a fault condition is detected, and the selected response is to shut down the converter or regulator, then the associated _ENA and _STS fields are reset to 0, as described in Section 15.2. If a fault condition is detected, and the selected response is to shut down the system, then a Device Reset is triggered, as described in Section 24.1, forcing a transition to the OFF state. The WM8312 will automatically return to the ON state after performing the Device Reset. Note that, if the fault condition persists, then a maximum of 7 attempts will be made to initiate the start-up sequence. Note that the DC-DC4 Boost Converter will not be automatically enabled following a Device Reset; this must be re-enabled using the DC4_ENA bit if required. Note that DC-DC1 and DC-DC2 overvoltage and high current conditions can be detected and reported as described in Section 15.11. The DCm_ERR_ACT fields have no relation to these conditions. w PP, December 2009, Rev 3.0 73 WM8312 Pre-Production The DC-DC3 Buck Converter has a selectable overvoltage protection feature, controlled by DC3_OVP. This affects the converter response when DC3 is enabled or when its output voltage is increased. When the overvoltage protection is enabled, there is less overshoot in the output voltage, but some oscillation may occur as the voltage settles. This function should only be enabled if steep load transients are present on the output of DC-DC3 and if voltage overshoot is critical. 15.11 MONITORING AND FAULT REPORTING Each of the DC-DC Converters (1 to 4) and LDOs (1 to 10) is monitored for voltage accuracy and fault conditions. An undervoltage condition is detected if the voltage falls below the required level by more than a pre-determined tolerance. If an undervoltage condition occurs, then this is indicated using the corresponding status bit(s) defined in Section 15.12.6. An undervoltage condition also triggers an Undervoltage Interrupt (see Section 15.13). Additional actions to shut down the converter or perform a Device Reset may also be selected. The Internal LDO (LDO13) is also monitored for voltage accuracy and fault conditions. An undervoltage condition in LDO13 is indicated using the INTLDO_UV_STS bit. This undervoltage condition also causes an OFF transition to be scheduled, as described in Section 11.3. DC-DC Converters 1 and 2 are monitored for overvoltage conditions. An overvoltage condition is set if the voltage is more than 100mV above the required level. If an overvoltage condition occurs, then this is indicated using the corresponding status bit(s). Note that there is no Interrupt or other selectable response to an overvoltage condition. The current draw on DC-DC Converters 1 and 2 can be monitored against user-programmable thresholds in order to detect a high current condition. This feature is enabled using DCm_HC_IND_ENA and the current threshold is set using DCm_HC_THR. Note that the high current threshold is not the same as the maximum current capability of the DC-DC Converters, but is set according to the application requirements. If a high current condition occurs, then this is indicated using the corresponding status bit(s). A high current condition also triggers a High Current Interrupt (see Section 15.13). 15.12 POWER MANAGEMENT REGISTER DEFINITIONS 15.12.1 DC-DC CONVERTER AND LDO REGULATOR ENABLE The Enable and Status register bits for the DC-DC Converters and LDO Regulators are defined in Table 34. ADDRESS R16464 (4050h) DCDC Enable BIT 3:0 LABEL DCm_ENA DEFAULT 0 DESCRIPTION DC-DCm Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DCm_STS) LDOn Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDOn_STS) DC-DCm Status 0 = Disabled 1 = Enabled LDOn Status 0 = Disabled 1 = Enabled R16465 (4051h) LDO Enable 10:0 LDOn_ENA 0 R16466 (4052h) DCDC Status R16467 (4053h) LDO Status 3:0 DCm_STS 0 10:0 LDOn_STS 0 Notes: 1. n is a number between 1 and 11 that identifies the individual LDO Regulator. 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter. Table 34 DC Converter and LDO Regulator Control w PP, December 2009, Rev 3.0 74 Pre-Production WM8312 The Enable and Status register bits for the External Power Enable (EPE) Controls are defined in Table 35. ADDRESS R16464 (4050h) DCDC Enable BIT 7 LABEL EPE2_ENA DEFAULT 0 DESCRIPTION EPE2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE2_STS) EPE1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE1_STS) EPE2 Status 0 = Disabled 1 = Enabled EPE1 Status 0 = Disabled 1 = Enabled 6 EPE1_ENA 0 R16466 (4052h) DCDC Status 7 EPE2_STS 0 6 EPE1_STS 0 Table 35 External Power Enable (EPE) Control 15.12.2 DC-DC (BUCK) CONVERTER CONTROL The register controls for configuring the DC-DC (Buck) Converters 1-3 are defined in Table 36. Note that the DCm_ON_SLOT fields and the 5 MSBs of DCm_ON_VSEL may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS R16470 (4056h) DC1 Control 1 BIT 15:14 LABEL DC1_RATE [1:0] DEFAULT 10 DESCRIPTION DC-DC1 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz 10 = Reserved 11 = 4.0MHz DC-DC1 Output float 0 = DC-DC1 output discharged when disabled 1 = DC-DC1 output floating when disabled DC-DC1 Soft-Start Control (Current limiting is stepped through 8 intermediate steps.) 00 = 31.25us steps (250us max total) 01 = 62.5us steps (500us max total) 10 = 125us steps (1000us max total) 11 = 250us steps (2000us max total) 12 DC1_PHASE 0 9:8 DC1_FREQ [1:0] 00 7 DC1_FLT 0 5:4 DC1_SOFT_ START [1:0] 00 w PP, December 2009, Rev 3.0 75 WM8312 ADDRESS BIT 1:0 LABEL DC1_CAP DEFAULT 00 Pre-Production DESCRIPTION DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved DC-DC1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC1 Hardware Control Voltage select 0 = Set by DC1_ON_VSEL 1 = Set by DC1_SLP_VSEL DC-DC1 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode DC-DC1 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA DC-DC1 High Current detect enable 0 = Disabled 1 = Enabled DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 DC-DC1 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode PP, December 2009, Rev 3.0 76 R16471 (4057h) DC1 Control 2 15:14 DC1_ERR_A CT [1:0] 00 12:11 DC1_HWC_ SRC [1:0] 00 10 DC1_HWC_ VSEL 0 9:8 DC1_HWC_ MODE [1:0] 11 6:4 DC1_HC_TH R [2:0] 000 0 DC1_HC_IN D_ENA DC1_ON_SL OT [2:0] 0 R16472 (4058h) DC1 ON Config 15:13 000 9:8 DC1_ON_M ODE [1:0] 00 w Pre-Production ADDRESS BIT 6:2 1:0 LABEL DC1_ON_VS EL [6:2] DC1_ON_VS EL [1:0] DEFAULT 00000 00 WM8312 DESCRIPTION DC-DC1 ON Voltage select DC1_ON_VSEL[6:0] selects the DCDC1 output voltage from 0.6V to 1.8V in 12.5mV steps. DC1_ON_VSEL[6:2] also exist in DBE/OTP memory, controlling the voltage in 50mV steps. DC1_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). R16473 (4059h) DC1 SLEEP Control 15:13 DC1_SLP_S LOT [2:0] 000 DC-DC1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. DC-DC1 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC1 SLEEP Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 9:8 DC1_SLP_M ODE [1:0] 00 6:0 DC1_SLP_V SEL [6:0] 000_0000 w PP, December 2009, Rev 3.0 77 WM8312 ADDRESS R16474 (405Ah) DC1 DVS Control BIT 12:11 LABEL DC1_DVS_S RC [1:0] DEFAULT 00 Pre-Production DESCRIPTION DC-DC1 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 DC-DC1 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). R16475 (405Bh) DC2 Control 1 15:14 12 9:8 7 5:4 1:0 R16476 (405Ch) DC2 Control 2 15:14 12:11 10 9:8 6:4 0 R16477 (405Dh) DC2 ON Config 15:13 9:8 6:2 1:0 R16478 (405Eh) DC2 SLEEP Control 15:13 9:8 6:0 R16479 (405Fh) DC2 DVS Control 12:11 6:0 DC2_RATE [1:0] DC2_PHASE DC2_FREQ [1:0] DC2_FLT DC2_SOFT_ START [1:0] DC2_CAP DC2_ERR_A CT [1:0] DC2_HWC_ SRC [1:0] DC2_HWC_ VSEL DC2_HWC_ MODE [1:0] DC2_HC_TH R [2:0] DC2_HC_IN D_ENA DC2_ON_SL OT [2:0] DC2_ON_M ODE [1:0] DC2_ON_VS EL [6:2] DC2_ON_VS EL [1:0] DC2_SLP_S LOT [2:0] DC2_SLP_M ODE [1:0] DC2_SLP_V SEL [6:0] DC2_DVS_S RC [1:0] DC2_DVS_V SEL [6:0] 10 0 00 0 00 00 00 00 0 11 000 0 000 00 00000 00 000 00 000_0000 00 000_0000 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 6:0 DC1_DVS_V SEL [6:0] 000_0000 w PP, December 2009, Rev 3.0 78 Pre-Production ADDRESS R16480 (4060h) DC3 Control 1 BIT 12 7 5:4 LABEL DC3_PHASE DC3_FLT DC3_SOFT_ START [1:0] DEFAULT 0 0 01 WM8312 DESCRIPTION Same as DC-DC1 Same as DC-DC1 DC-DC3 Soft-Start Control (Current limiting is stepped through 4 intermediate steps.) 00 = Immediate start-up 01 = 4 x 400us (1600us total) 10 = 4 x 4ms (16ms total) 11 = 4 x 40ms (160ms total) DC-DC3 Current Limit Sets the maximum DC output current in Hysteretic Mode 00 = 100mA 01 = 200mA 10 = 400mA 11 = 800mA Protected by user key. DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 Same as DC-DC1 DC-DC3 Overvoltage Protection 0 = Disabled 1 = Enabled Same as DC-DC1 Same as DC-DC1 DC-DC3 ON Voltage select DC3_ON_VSEL[6:0] selects the DCDC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL[6:2] also exist in DBE/OTP memory, controlling the voltage in 100mV steps. DC3_ON_VSEL[6:0] is coded as follows: 00h = 0.85V 01h = 0.875V ... 65h = 3.375V 66h to 7Fh = 3.4V R16483 (4063h) DC3 SLEEP Control 15:13 9:8 DC3_SLP_S LOT [2:0] DC3_SLP_M ODE [1:0] 000 00 Same as DC-DC1 Same as DC-DC1 3:2 DC3_STNBY _LIM [1:0] 01 1:0 DC3_CAP 00 R16481 (4061h) DC3 Control 2 15:14 12:11 10 9:8 7 DC3_ERR_A CT [1:0] DC3_HWC_ SRC [1:0] DC3_HWC_ VSEL DC3_HWC_ MODE [1:0] DC3_OVP 00 00 0 11 0 R16482 (4062h) DC3 ON Config 15:13 9:8 6:2 1:0 DC3_ON_SL OT [2:0] DC3_ON_M ODE [1:0] DC3_ON_VS EL [6:2] DC3_ON_VS EL [1:0] 000 00 00000 00 w PP, December 2009, Rev 3.0 79 WM8312 ADDRESS BIT 6:0 LABEL DC3_SLP_V SEL [6:0] DEFAULT 000_0000 Pre-Production DESCRIPTION DC-DC3 SLEEP Voltage select 0.85V to 3.4V in 25mV steps 00h = 0.85V 01h = 0.875V ... 65h = 3.375V 66h to 7Fh = 3.4V Table 36 DC-DC (Buck) Converter Control 15.12.3 DC-DC (BOOST) CONVERTER CONTROL The register controls for configuring the DC-DC4 (Boost) Converter are defined in Table 37. Note that the DC4_RANGE control register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16484 (4064h) DC4 Control BIT 15:14 LABEL DC4_ERR_A CT [1:0] DEFAULT 00 DESCRIPTION DC-DC4 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC4 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC4 Hardware Control Operating Mode 0 = DC-DC4 is disabled when Hardware Control Source is asserted 1 = DC-DC4 is controlled by DC4_ENA Selects the voltage range for DC-DC4 00 = 20V < VOUT <= 30V 01 = 10V < VOUT <= 20V 10 = 5V < VOUT <= 10V 11 = VOUT <=5V Protected by user key DC-DC4 Voltage Feedback source 0 = ISINK1 1 = ISINK2 DC-DC4 SLEEP Enable 0 = Disabled 1 = Controlled by DC4_ENA 12:11 DC4_HWC_ SRC[1:0] 00 8 DC4_HWC_ MODE 0 3:2 DC4_RANG E[1:0] 01 0 DC4_FBSRC 0 R16485 (4065h) DC4 SLEEP Control 8 DC4_SLPEN A 0 Table 37 DC-DC (Boost) Converter Control 15.12.4 LDO REGULATOR CONTROL The register controls for configuring the LDO Regulators 1-6 are defined in Table 38. Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. w PP, December 2009, Rev 3.0 80 Pre-Production ADDRESS R16488 (4068h) LDO1 Control BIT 15:14 LABEL LDO1_ERR_ ACT [1:0] DEFAULT 00 WM8312 DESCRIPTION LDO1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO1 Hardware Control Voltage select 0 = Set by LDO1_ON_VSEL 1 = Set by LDO1_SLP_VSEL LDO1 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO1_ON_MODE LDO1 Output float 0 = LDO1 output discharged when disabled 1 = LDO1 output floating when disabled LDO1 Switch Mode 0 = LDO mode 1 = Switch mode LDO1 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. LDO1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO1 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V PP, December 2009, Rev 3.0 81 12:11 LDO1_HWC _SRC [1:0] 00 10 LDO1_HWC _VSEL LDO1_HWC _MODE 0 9:8 10 7 LDO1_FLT 0 6 LDO1_SWI 0 0 LDO1_LP_M ODE 0 R16489 (4069h) LDO1 ON Control 15:13 LDO1_ON_S LOT [2:0] 000 8 LDO1_ON_ MODE LDO1_ON_V SEL [4:0] 0 4:0 00000 w WM8312 ADDRESS R16490 (406Ah) LDO1 SLEEP Control BIT 15:13 LABEL LDO1_SLP_ SLOT [2:0] DEFAULT 000 Pre-Production DESCRIPTION LDO1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO1 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO1 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 8 LDO1_SLP_ MODE LDO1_SLP_ VSEL [4:0] 0 4:0 00000 R16491 (406Bh) LDO2 Control 15:14 12:11 10 9:8 7 6 0 LDO2_ERR_ ACT [1:0] LDO2_HWC _SRC [1:0] LDO2_HWC _VSEL LDO2_HWC _MODE LDO2_FLT LDO2_SWI LDO2_LP_M ODE LDO2_ON_S LOT [2:0] LDO2_ON_ MODE LDO2_ON_V SEL [4:0] LDO2_SLP_ SLOT [2:0] LDO2_SLP_ MODE LDO2_SLP_ VSEL [4:0] LDO3_ERR_ ACT [1:0] 00 00 0 10 0 0 0 000 0 00000 000 0 00000 00 R16492 (406Ch) LDO2 ON Control 15:13 8 4:0 R16493 (406Dh) LDO2 SLEEP Control 15:13 8 4:0 R16494 (406Eh) 15:14 w PP, December 2009, Rev 3.0 82 Pre-Production ADDRESS LDO3 Control BIT 12:11 10 9:8 7 6 0 R16495 (406Fh) LDO3 ON Control 15:13 8 4:0 R16496 (4070h) LDO3 SLEEP Control 15:13 8 4:0 R16497 (4071h) LDO4 Control 15:14 12:11 10 9:8 7 6 0 R16498 (4072h) LDO4 ON Control 15:13 8 4:0 R16499 (4073h) LDO4 SLEEP Control 15:13 8 4:0 R16500 (4074h) LDO5 Control 15:14 12:11 10 9:8 7 6 0 LABEL LDO3_HWC _SRC [1:0] LDO3_HWC _VSEL LDO3_HWC _MODE LDO3_FLT LDO3_SWI LDO3_LP_M ODE LDO3_ON_S LOT [2:0] LDO3_ON_ MODE LDO3_ON_V SEL [4:0] LDO3_SLP_ SLOT [2:0] LDO3_SLP_ MODE LDO3_SLP_ VSEL [4:0] LDO4_ERR_ ACT [1:0] LDO4_HWC _SRC [1:0] LDO4_HWC _VSEL LDO4_HWC _MODE LDO4_FLT LDO4_SWI LDO4_LP_M ODE LDO4_ON_S LOT [2:0] LDO4_ON_ MODE LDO4_ON_V SEL [4:0] LDO4_SLP_ SLOT [2:0] LDO4_SLP_ MODE LDO4_SLP_ VSEL [4:0] LDO5_ERR_ ACT [1:0] LDO5_HWC _SRC [1:0] LDO5_HWC _VSEL LDO5_HWC _MODE LDO5_FLT LDO5_SWI LDO5_LP_M ODE DEFAULT 00 0 10 0 0 0 000 0 00000 000 0 00000 00 00 0 10 0 0 0 000 0 00000 000 0 00000 00 00 0 10 0 0 0 WM8312 DESCRIPTION Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 w PP, December 2009, Rev 3.0 83 WM8312 ADDRESS R16501 (4075h) LDO5 ON Control BIT 15:13 8 4:0 R16502 (4076h) LDO5 SLEEP Control 15:13 8 4:0 R16503 (4077h) LDO6 Control 15:14 12:11 10 9:8 7 6 0 R16504 (4078h) LDO6 ON Control 15:13 8 4:0 R16505 (4079h) LDO6 SLEEP Control 15:13 8 4:0 LABEL LDO5_ON_S LOT [2:0] LDO5_ON_ MODE LDO5_ON_V SEL [4:0] LDO5_SLP_ SLOT [2:0] LDO5_SLP_ MODE LDO5_SLP_ VSEL [4:0] LDO6_ERR_ ACT [1:0] LDO6_HWC _SRC [1:0] LDO6_HWC _VSEL LDO6_HWC _MODE LDO6_FLT LDO6_SWI LDO6_LP_M ODE LDO6_ON_S LOT [2:0] LDO6_ON_ MODE LDO6_ON_V SEL [4:0] LDO6_SLP_ SLOT [2:0] LDO6_SLP_ MODE LDO6_SLP_ VSEL [4:0] DEFAULT 000 0 00000 000 0 00000 00 00 0 10 0 0 0 000 0 00000 000 0 00000 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Same as LDO1 Pre-Production DESCRIPTION Table 38 LDO Regulators 1-6 Control The register controls for configuring the LDO Regulators 7-10 are defined in Table 39. Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS R16506 (407Ah) LDO7 Control BIT 15:14 LABEL LDO7_ERR_ ACT [1:0] DEFAULT 00 DESCRIPTION LDO7 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO7 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 12:11 LDO7_HWC _SRC [1:0] 00 w PP, December 2009, Rev 3.0 84 Pre-Production ADDRESS BIT 10 LABEL LDO7_HWC _VSEL LDO7_HWC _MODE DEFAULT 0 WM8312 DESCRIPTION LDO7 Hardware Control Voltage select 0 = Set by LDO7_ON_VSEL 1 = Set by LDO7_SLP_VSEL LDO7 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO7_ON_MODE LDO7 Output float 0 = LDO7 output discharged when disabled 1 = LDO7 output floating when disabled LDO7 Switch Mode 0 = LDO mode 1 = Switch mode LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO7 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V LDO7 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO7 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. PP, December 2009, Rev 3.0 85 9:8 00 7 LDO7_FLT 0 6 LDO7_SWI 0 R16507 (407Bh) LDO7 ON Control 15:13 LDO7_ON_S LOT [2:0] 000 8 LDO7_ON_ MODE LDO7_ON_V SEL [4:0] 0 4:0 00000 R16508 (407Ch) LDO7 SLEEP Control 15:13 LDO7_SLP_ SLOT [2:0] 000 w WM8312 ADDRESS BIT 8 LABEL LDO7_SLP_ MODE LDO7_SLP_ VSEL [4:0] DEFAULT 0 Pre-Production DESCRIPTION LDO7 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO7 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 PP, December 2009, Rev 3.0 86 4:0 00000 R16509 (407Dh) LDO8 Control 15:14 12:11 10 9:8 7 6 LDO8_ERR_ ACT [1:0] LDO8_HWC _SRC [1:0] LDO8_HWC _VSEL LDO8_HWC _MODE LDO8_FLT LDO8_SWI LDO8_ON_S LOT [2:0] LDO8_ON_ MODE LDO8_ON_V SEL [4:0] LDO8_SLP_ SLOT [2:0] LDO8_SLP_ MODE LDO8_SLP_ VSEL [4:0] LDO9_ERR_ ACT [1:0] LDO9_HWC _SRC [1:0] LDO9_HWC _VSEL LDO9_HWC _MODE LDO9_FLT LDO9_SWI LDO9_ON_S LOT [2:0] LDO9_ON_ MODE LDO9_ON_V SEL [4:0] LDO9_SLP_ SLOT [2:0] LDO9_SLP_ MODE 00 00 0 00 0 0 000 0 00000 000 0 00000 00 00 0 00 0 0 000 0 00000 000 0 R16510 (407Eh) LDO8 ON Control 15:13 8 4:0 R16511 (407Fh) LDO8 SLEEP Control 15:13 8 4:0 R16512 (4080h) LDO9 Control 15:14 12:11 10 9:8 7 6 R16513 (4081h) LDO9 ON Control 15:13 8 4:0 R16514 (4082h) LDO9 SLEEP Control 15:13 8 w Pre-Production ADDRESS BIT 4:0 R16515 (4083h) LDO10 Control 15:14 12:11 10 9:8 7 6 R16516 (4084h) LDO10 ON Control 15:13 8 4:0 R16517 (4085h) LDO10 SLEEP Control 15:13 8 4:0 LABEL LDO9_SLP_ VSEL [4:0] LDO10_ERR _ACT [1:0] LDO10_HW C_SRC [1:0] LDO10_HW C_VSEL LDO10_HW C_MODE LDO10_FLT LDO10_SWI LDO10_ON_ SLOT [2:0] LDO10_ON_ MODE LDO10_ON_ VSEL [4:0] LDO10_SLP _SLOT [2:0] LDO10_SLP _MODE LDO10_SLP _VSEL [4:0] DEFAULT 00000 00 00 0 00 0 0 000 0 00000 000 0 00000 WM8312 DESCRIPTION Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Same as LDO7 Table 39 LDO Regulators 7-10 Control The register controls for configuring the LDO Regulator 11 are defined in Table 40. Note that the LDO11_ON_SLOT and LDO11_ON_VSEL fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS R16519 (4087h) LDO11 ON Control BIT 15:13 LABEL LDO11_ON_ SLOT [2:0] DEFAULT 000 DESCRIPTION LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO11 Force Enable (forces LDO11 to be enabled at all times in the OFF, ON and SLEEP states) 0 = Disabled 1 = Enabled LDO11 Voltage Select source 0 = Normal (LDO11 settings) 1 = Same as DC-DC Converter 1 LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V ... Eh = 1.50V Fh = 1.55V PP, December 2009, Rev 3.0 87 12 LDO11_FRC ENA 0 7 LDO11_VSE L_SRC LDO11_ON_ VSEL [3:0] 0 3:0 w WM8312 ADDRESS R16520 (4088h) LDO11 SLEEP Control BIT 15:13 LABEL LDO11_SLP _SLOT [2:0] DEFAULT 000 Pre-Production DESCRIPTION LDO11 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO11 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO11 SLEEP Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V ... Eh = 1.50V Fh = 1.55V 3:0 LDO11_SLP _VSEL [3:0] Table 40 LDO Regulator 11 Control 15.12.5 EXTERNAL POWER ENABLE (EPE) CONTROL The register controls for configuring the External Power Enable (EPE) outputs are defined in Table 41. Note that the EPE1_ON_SLOT and EPE2_ON_SLOT fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS R16486 (4066h) EPE1 Control BIT 15:13 LABEL EPE1_ON_S LOT [2:0] DEFAULT 000 DESCRIPTION EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 EPE1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 EPE1 Hardware Control Enable 0 = EPE1 is controlled by EPE1_ENA (Hardware Control input(s) are ignored) 1 = EPE1 is controlled by HWC inputs (Hardware Control input(s) force EPE1 to be de-asserted) 12:11 EPE1_HWC _SRC [1:0] 00 8 EPE1_HWC ENA 0 w PP, December 2009, Rev 3.0 88 Pre-Production ADDRESS BIT 7:5 LABEL EPE1_SLP_ SLOT [2:0] DEFAULT 000 WM8312 DESCRIPTION EPE1 SLEEP Slot select 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Same as EPE1 Same as EPE1 Same as EPE1 Same as EPE1 R16487 (4067h) EPE2 Control 15:13 12:11 8 7:5 EPE2_ON_S LOT [2:0] EPE2_HWC _SRC [1:0] EPE2_HWC ENA EPE2_SLP_ SLOT [2:0] 000 00 0 000 Table 41 External Power Enable (EPE) Control 15.12.6 MONITORING AND FAULT REPORTING The overvoltage, undervoltage and high current status registers are defined in Table 42. ADDRESS R16468 (4054h) DCDC UV Status BIT 13 LABEL DC2_OV_ST S DC1_OV_ST S DC2_HC_ST S DC1_HC_ST S DCm_UV_S TS INTLDO_UV _STS DEFAULT 0 DESCRIPTION DC-DC2 Overvoltage Status 0 = Normal 1 = Overvoltage DC-DC1 Overvoltage Status 0 = Normal 1 = Overvoltage DC-DC2 High Current Status 0 = Normal 1 = High Current DC-DC1 High Current Status 0 = Normal 1 = High Current DC-DCm Undervoltage Status 0 = Normal 1 = Undervoltage LDO13 (Internal LDO) Undervoltage Status 0 = Normal 1 = Undervoltage LDOn Undervoltage Status 0 = Normal 1 = Undervoltage 12 0 9 0 8 0 3:0 0 R16469 (4055h) LDO UV Status 15 0 9:0 LDOn_UV_S TS 0 Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4). Table 42 DC Converter and LDO Regulator Status w PP, December 2009, Rev 3.0 89 WM8312 15.13 POWER MANAGEMENT INTERRUPTS Pre-Production Undervoltage monitoring is provided on all DC-DC Converters and LDO Regulators, as described in Section 15.11. The associated interrupt flags indicate an undervoltage condition in each individual DC-DC Converter or LDO Regulator. Each of these secondary interrupts triggers a primary Undervoltage Interrupt, UV_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 43. Current monitoring is provided on DC-DC1 and DC-DC2, as described in Section 15.11. The interrupt flags HC_DC1_EINT and HC_DC2_EINT indicate a high current condition in DC-DC1 and DC-DC2 respectively. Each of these secondary interrupts triggers a primary High Current Interrupt, HC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 43. The high current thresholds are programmable; these are set by DC1_HC_THR and DC2_HC_THR for DC-DC1 and DC-DC2 respectively. See Section 15.12.2 for details of these register fields. Note that these functions are for current monitoring; they do not equate to the DC-DC Converter maximum current limit. ADDRESS R16403 (4013h) Interrupt Status 3 R16404 (4014h) Interrupt Status 4 BIT 9:0 LABEL UV_LDOn_EINT DESCRIPTION LDOn Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC2 High current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC1 High current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DCm Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 9 HC_DC2_EINT 8 HC_DC1_EINT 3:0 UV_DCm_EINT R16411 (401Bh) Interrupt Status 3 Mask R16412 (401Ch) Interrupt Status 4 Mask 9:0 IM_UV_LDOn_EINT 9 IM_HC_DC2_EINT 8 IM_HC_DC1_EINT 3:0 IM_UV_DCm_EINT Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4). Table 43 Power Management Interrupts w PP, December 2009, Rev 3.0 90 Pre-Production WM8312 The WM8312 can indicate the status of the DC-DC Converters and LDO Regulators via a GPIO pin configured as a "PWR_GOOD" output (see Section 21). Each DC-DC Converter and LDO Regulator to be monitored in this way must be individually enabled as an input to the PWR_GOOD function using the register bits defined in Table 44. When a GPIO pin is configured as a "PWR_GOOD" output, this signal is asserted when all selected DC-DC Converters and LDO Regulators are operating correctly. If any of the enabled DC-DC Converters or LDO Regulators is undervoltage, then the PWR_GOOD will be de-asserted. In this event, the host processor should read the Undervoltage Interrupt fields to determine which DC-DC Converter or LDO Regulator is affected. Note that an Undervoltage condition may lead to a Converter being switched off automatically. In this case, the disabled Converter will not indicate the fault condition via PWR_GOOD. Accordingly, the PWR_GOOD signal may not be a reliable output in cases where the WM8312 is configured to shut down any Converters automatically under Undervoltage conditions. It is recommended that the host processor should read the Undervoltage Interrupts in response to PWR_GOOD being de-asserted. The host processor can then initiate the most appropriate response. ADDRESS R16526 (408Eh) Power Good Source 1 BIT 3 LABEL DC4_OK DEFAULT 0 DESCRIPTION DC-DC4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO10 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO9 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO8 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO7 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO6 status selected selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO5 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled PP, December 2009, Rev 3.0 91 15.14 POWER GOOD INDICATION 2 DC3_OK 1 1 DC2_OK 1 0 DC1_OK 1 R16527 (408Fh) Power Good Source 2 9 LDO10_OK 1 8 LDO9_OK 1 7 LDO8_OK 1 6 LDO7_OK 1 5 LDO6_OK 1 4 LDO5_OK 1 w WM8312 ADDRESS BIT 3 LABEL LDO4_OK DEFAULT 1 Pre-Production DESCRIPTION LDO4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled 2 LDO3_OK 1 1 LDO2_OK 1 0 LDO1_OK 1 Table 44 PWR_GOOD (GPIO) Configuration 15.15 DC-DC CONVERTER OPERATION 15.15.1 OVERVIEW The WM8312 provides four DC-DC switching converters. Three of these are Buck (Step-down) converters; the fourth of these is a Boost (Step-up) converter. The principal characteristics of each DC-DC converter are shown below. DC-DC1 / DC-DC2 Converter Type Input Voltage Range Output Voltage Range Load Current Rating Switching Frequency Step-down 2.5V to 5.5V 0.6V to 1.8V Up to 1200mA 2MHz or 4MHz DC-DC3 Step-down 2.7V to 5.5V 0.85V to 3.4V Up to 1000mA 2MHz DC-DC4 Step-up 2.7V to 5.5V 5V to 30V Up to 25mA @ 30V Up to 40mA @ 20V 1MHz Table 45 DC-DC Converter Overview 15.15.2 DC-DC STEP DOWN CONVERTERS DC-DC Converters 1, 2 and 3 are synchronous Buck converters which deliver high performance and high efficiency across a wide variety of operating conditions. The high switching frequency, together with the current mode architecture, delivers exceptional transient performance suitable for supplying processor power domains and similar applications requiring high stability through fast-changing load (or line) conditions. The current mode architecture enables extended bandwidth of the control loop, allowing the DC-DC converter to adapt for changes in input or output conditions more rapidly than can be achieved using other feedback mechanisms. This improves the converter's performance under transient load conditions. The flexible design of the DC-DC Converters allows a selection of different operating configurations, which can be chosen according to the performance, efficiency, space or external component cost requirements. w PP, December 2009, Rev 3.0 92 Pre-Production WM8312 The DC-DC Converter design achieves high performance with a small inductor component. This is highly advantageous in size-critical designs for portable applications. In the case of DC-DC1 and DCDC2, the switching frequency is selectable (2MHz or 4MHz). The higher frequency supports best transient performance and the smallest external inductor, whilst the lower rate supports best power efficiency. It should be noted that the supported output voltage range is restricted in the 4MHz mode; for output voltages greater than 1.4V, the 2MHz mode must be used. The DC-DC Converters are compatible with a range of external output capacitors. A larger capacitor (eg. 47F) will deliver best transient performance, whilst a smaller capacitor (eg. 4.7F) may be preferred for size or cost reasons. Four different operating modes can be selected, allowing the user to configure the converter performance and efficiency according to different demands. This includes power-saving modes for light load conditions and a high performance mode for best transient load performance. A low power LDO Regulator mode is also provided. The DC-DC Converters maintain output voltage regulation when switching between operating modes. Forced Continuous Conduction Mode (FCCM) This mode delivers the best load transient performance across the entire operating load range of the converter. It also provides the best EMI characteristics due to the fixed, regular switching pattern. For normal DC-DC buck converter operation, there is an inductor charging phase followed by a discharging phase. Under light load conditions, the inductor current may be positive or negative during this cycle. (Note that the load current corresponds to the average inductor current.) The negative portion of the cycle corresponds to inefficient operation, as the output capacitor is discharged unnecessarily by the converter circuit. Accordingly, this mode is not optimally efficient for light load conditions. This mode offers excellent performance under transient load conditions. It exceeds the performance of the other operating modes in the event of a decreasing current demand or a decreasing voltage selection. This is because FCCM mode can actively pull down the output voltage to the required level, whilst other modes rely on the load to pull the converter voltage down under these conditions. Another important benefit of this mode is that the switching pattern is fixed, regardless of load conditions. This provides best compatibility with noise-sensitive circuits where the noise frequency spectrum must be well-defined. Although this mode is not optimally efficient for light loads, it delivers the best possible transient load performance and fixed frequency switching. This mode should be selected when best performance is required, delivering minimum output voltage ripple across all static or transient load conditions. Continuous / Discontinuous Conduction with Pulse-Skipping Mode (CCM/DCM with PS) This is an automatic mode that selects different control modes according to the load conditions. The converter supports the full range of load conditions in this mode, and automatically selects powersaving mechanisms when the load conditions are suitable. Under light load conditions, the efficiency in this mode is superior to the FCCM mode. The transient load performance may be slightly worse than FCCM mode. The converter operates in Continuous Conduction Mode (CCM) for heavy load conditions, and Discontinuous Conduction Mode (DCM) under lighter loads. Discontinuous conduction is when the inductor current falls to zero during the discharge phase, and the converter disables the synchronous rectifier transistor in order that the inductor current remains at zero until the next charge phase. Negative inductor current is blocked in this mode, eliminating the associated losses, and improving efficiency. The transient response in this mode varies according to the operating conditions; it differs from FCCM in the case of a decreasing current demand or a decreasing voltage, as the converter uses the load to pull the output voltage down to the required level. A light load will result in a slow response time. w PP, December 2009, Rev 3.0 93 WM8312 Pre-Production A minimum inductor charge time is applied in DCM mode; this leads to a minimum average inductor current when operating as described above. Under very light load conditions, pulse skipping is used to reduce the average inductor current to the level required by the load. In pulse-skipping mode, the charge phase of selected cycles is not scheduled, and the load is supported by the output capacitor over more than one cycle of the switching frequency. As well as supporting very light load current conditions, this mechanism offers power savings, as the switching losses associated with the skipped pulses are eliminated. A disadvantage of this is that the transient response is degraded even further with respect to DCM. When the pulse-skipping behaviour is invoked, an increased output voltage ripple may be observed under some load conditions. This mode is suitable for a wide range of operating conditions. It supports the full range of load currents, and offers efficiency savings under light load conditions. Hysteretic Mode Hysteretic mode is a power-saving mode. It does not support the full load capability of the DC-DC converter, but offers efficiency improvements over the FCCM and DCM modes. The control circuit in Hysteretic mode operates very differently to Pulse-Skipping mode. In PulseSkipping mode, selected switching cycles are dropped in order to reduce the output current to match a light load condition, whilst maintaining good output voltage ripple as far as possible. In Hysteretic mode, the converter uses switched operation on an adaptive intermittent basis to deliver the required average current to the load. In the switched operation portion of the Hysteretic mode, the converter drives the output voltage up; this is followed by a power-saving period in which the control circuit is largely disabled whilst the load pulls the output voltage down again over a period of many switching cycles. The duration of the fixed frequency bursts and the time between bursts is adapted automatically by the output voltage monitoring circuit. In this mode, the power dissipation is reduced to a very low level by disabling parts of the control circuitry for the duration of selected switching cycles. This improves the overall efficiency, but also leads to output voltage ripple and limited performance. This mode produces a larger output voltage ripple than the Pulse-Skipping mode. In order to limit the degradation of the DC-DC converter performance in Hysteretic mode, the control circuit is designed for a restricted range of load conditions only. Note that the irregular switching pattern also results in degraded EMI behaviour. Hysteretic mode and Pulse Skipping mode are both Pulse Frequency Modulation (PFM)-type modes, where the switching pulse frequency is adjusted dynamically according to the load requirements. A consequence of this frequency modulation is that the circuit's EMI characteristics are less predictable. In Hysteretic mode in particular, the EMI effects arising from the DC-DC switching are present across a wider frequency band than is the case in CCM and DCM. It is more difficult to effectively suppress the wide band interference, and this factor may result in Hysteretic mode being unsuitable for some operating conditions. Hysteretic mode is suitable for light load conditions only, and only suitable for operating modes that are not sensitive to wide band RF/EMI effects. The output voltage ripple (and frequency) is load dependent, and is generally worse than DCM mode. Provided that the EMI and voltage ripple can be tolerated, this mode offers an efficiency advantage over the DCM / Pulse-Skipping mode. LDO Mode In this mode, there is no FET switching at all, and the converter operates as a Low Drop-Out Regulator (LDO). In this mode, the FET switching losses are eliminated, as is the power consumption of the DC-DC control circuit. Under suitable operating conditions, this provides the most efficient option for light loads, without any of the EMI or voltage ripple limitations of Hysteretic mode. As with any LDO, the output voltage is constant, and there is no internal source of voltage ripple. Unlike the switching modes, the power efficiency of the LDO mode is highly dependent on the input and output voltages; the LDO is most efficient when the voltage drop between input and output is small. The power dissipated as heat loss by an LDO increases rapidly as the input - output voltage difference increases. w PP, December 2009, Rev 3.0 94 Pre-Production WM8312 LDO mode is suitable for light loads, and provides a ripple-free output. The LDO mode features a very low start-up current; this mode can be used to avoid the higher in-rush current that occurs in the switching converter modes. The efficiency is dependent on the input - output voltage configuration; the LDO mode can be highly efficient, but may also be unacceptably inefficient. If an improvement in power efficiency is required, then Hysteretic mode may be the preferred choice or, for better EMI and voltage ripple, DCM with Pulse-Skipping may be the optimum selection. Operating Mode Summary MODE Forced Continuous Conduction Mode (FCCM) DESCRIPTION Buck converter operation where inductor current is continuous at all times. APPLICATION High performance for all static and transient load conditions. Fixed frequency switching offers best compatibility with sensitive circuits. High efficiency for all static and transient load conditions. Performance may be less than FCCM mode for heavy load transients. High efficiency for light static and light transient loads only. Maximum load current is restricted; output voltage ripple is increased. Power saving mode for light loads only. High efficiency for ultra light loads. Low current soft-start control. Continuous / Discontinuous Conduction with Pulse-Skipping Mode (CCM/DCM with PS) Hysteretic Mode Buck converter operation where inductor current may be discontinuous under reduced loads; pulse-skipping also enabled under lighter loads. The converter uses a hysteretic control scheme with pulsed switching operation. The control circuitry is disabled intermittently for power saving. No FET switching at all; linear regulator operation. LDO Mode Table 46 Step-Down DC-DC Converter Operating Modes Summary Typical Connections The typical connections to DC-DC Converter 1 are illustrated in Figure 20. The equivalent circuit applies to DC-DC Converters 2 and 3 also. The input voltage connection to DC-DC Converters 1, 2 and 3 is provided on DC1VDD, DC2VDD and DC3VDD respectively; these are typically connected to the SYSVDD voltage node. Note that the internal supply pins PVDD1 and PVDD2 should also be connected to SYSVDD. Figure 20 Step-Down DC-DC Converter Connections The recommended output capacitor COUT varies according to the required transient response. Note that the DCm_CAP register field must be set according to the output capacitance on each DC-DC Converter in order to achieve best performance. w PP, December 2009, Rev 3.0 95 WM8312 Pre-Production In the case of DC-DC1 and DC-DC2, the recommended inductor component varies according to the switching frequency. See Section 30.3 for details of specific recommended external components. 15.15.3 DC-DC STEP UP CONVERTER DC-DC Converter 4 is a step-up DC-DC Converter designed to deliver high power efficiency across full load conditions. It is designed to provide a voltage which is determined by the selected current of either Current Sink 1 or Current Sink 2 through an external load - typically a string of LEDs. DC-DC Converter 4 is designed with fixed frequency current mode architecture. The clock frequency is set by an internal RC oscillator, which provides a 1MHz clock. The typical connections to DC-DC Converter 4 are illustrated in Figure 21. The DC4_FBSRC register field can select either ISINK1 or ISINK2 as input to the feedback circuit. The input voltage connection, DC4VDD, is typically connected to the SYSVDD voltage node. Note that the internal supply pins PVDD1 and PVDD2 should also be connected to SYSVDD. 2.7V - 5.5V L VO CIN DC4VDD DC4LX COUT WM8312 DC-DC4 DC4_FBSRC = 0 (ISINK1) DC4_FBSRC = 1 (ISINK2) DC4GND ISINKn R1 DC4FB R2 Figure 21 Step-Up DC-DC Converter Connections Note that the recommended output capacitor COUT varies according to the required output voltage. The DC4_RANGE register field must be set according to the required output voltage. See Section 30.4 for details of specific recommended external components. w PP, December 2009, Rev 3.0 96 Pre-Production WM8312 15.16.1 OVERVIEW The WM8312 provides 11 LDO Regulators. Four of these are low-noise analogue LDOs. One of the LDO Regulators (LDO11) can be configured to be enabled even when the WM8312 is in the OFF state. The principal characteristics of the LDO Regulators are shown below. LDO1 LDO2, 3 General Purpose 1.5V to 5.5V 0.9V to 3.3V Up to 200mA 1 LDO4, 5, 6 General Purpose 1.5V to 5.5V 0.9V to 3.3V Up to 100mA 2 LDO7, 8 Analogue 2.3V to 5.5V 1.0V to 3.5V Up to 200mA 1 LDO9, 10 Analogue 2.3V to 5.5V 1.0V to 3.5V Up to 150mA 2 LDO11 General Purpose 1.8V to 5.5V 0.8V to 1.55V Up to 10mA n/a 15.16 LDO REGULATOR OPERATION Converter Type Input Voltage Range Output Voltage Range Load Current Rating Pass device impedance @ 2.5V General Purpose 1.5V to 5.5V 0.9V to 3.3V Up to 300mA 1 Table 47 LDO Regulator Overview 15.16.2 LDO REGULATORS The LDO Regulators are configurable circuits which generate accurate, low-noise supply voltages for various system components. The LDO Regulators are dynamically programmable and can be reconfigured at any time. Two low power modes are provided for the general purpose LDOs 1-6; a single low power mode is provided for the analogue LDOs 7-10; this enables the overall device power consumption to be minimised at all times. The LDOs 1-10 can also operate as current-limited switches, with no voltage regulation; this is useful for `Hot Swap' outputs, i.e. supply rails for external devices that are plugged in when the system is already powered up - the current-limiting function prevents the in-rush current into the external device from disturbing other system power supplies. The input voltage to these LDOs is provided on pin LDO1VDD through to LDO10VDD respectively. These input voltages may be provided from the SYSVDD voltage node. LDO11 is a configurable LDO intended for `always-on' functions external to the WM8312. The WM8312 contains a further two non-configurable LDOs which support internal functions only. The connections to LDO Regulator 1 are illustrated in Figure 22. The equivalent circuit applies to LDO2 through to LDO10. The input voltage connection to LDO Regulators 1 to 10 is provided on pins LDOnVDD, where n identifies the individual LDO Regulator; these pins are typically connected to the SYSVDD node. Note that the internal supply pins PVDD1 and PVDD2 should also be connected to SYSVDD. Figure 22 LDO Regulator Connections An input and output capacitor are recommended for each LDO Regulator, as illustrated above. See Section 30.5 for details of specific recommended external components. w PP, December 2009, Rev 3.0 97 WM8312 16 CURRENT SINKS 16.1 GENERAL DESCRIPTION Pre-Production The WM8312 provides two Current Sinks, ISINK1 and ISINK2. These are programmable constantcurrent sinks designed to drive strings of serially connected LEDs, including white LEDs used in display backlight applications. The WM8312 Boost Converter, DC-DC4, is designed as a power source for LED strings. Driving LEDs in this way is particularly power efficient because no series resistor is required. The Boost Converter can generate voltages higher than the Battery, Wall or USB supply, producing the necessary combined forward voltages of long LED strings. See Section 15.15.3 for details of DCDC4 operation. 16.2 CURRENT SINK CONTROL The configuration of the Current Sinks is described in the following sections. 16.2.1 ENABLING THE SINK CURRENT In the ON power state, the Current Sinks ISINK1 and ISINK2 can be enabled in software using the CS1_ENA and CS2_ENA register fields as defined in Table 48. When the Current Sinks are enabled, the drive current is controlled by the CS1_DRIVE and CS2_DRIVE bits. Note that the Current Sinks permit current flow only when the applicable CSn_ENA and CSn_DRIVE bits are both set. The WM8312 Boost Converter, DC-DC4, is the recommended power source for the Current Sinks. The recommended switch-on sequence is as follows: * * Enable Current Sink and Current Drive (CSn_ENA = 1; CSn_DRIVE = 1) Enable Boost Converter (DC4_ENA = 1) The status of the Current Sinks in the SLEEP power state are controlled by CS1_SLPENA and CS2_SLPENA, as described in Table 48. The Current Sinks may either be disabled in SLEEP or remain under control of the applicable CSn_ENA register bit. If a Current Sink is disabled in SLEEP, then the applicable CSn_DRIVE bit is automatically reset to 0 as part of the SLEEP transition sequence. Note that the CSn_DRIVE bit will remain reset at 0 following a WAKE transition; the Current Sink can only be re-enabled by writing to the applicable CSn_DRIVE register bit. If both Current Sinks are disabled in SLEEP, then DC4 can also be disabled in SLEEP, by setting DC4_SLPENA = 0, as described in Section 15.4.2. If DC4 is not disabled, then it is important that CSn_ENA also remains set in the SLEEP power state. The recommended switch-off sequence for DC-DC4 and the Current Sinks is as follows: * * * Disable Current Drive (CSn_DRIVE = 0) Disable Boost Converter (DC4_ENA = 0) Disable Current Sink (CSn_ENA = 0) Note that this switch-off sequence is important in order to avoid forward-biasing on-chip ESD protection diodes. w PP, December 2009, Rev 3.0 98 Pre-Production WM8312 When the Current Sinks output drive is enabled or disabled using CS1_DRIVE or CS2_DRIVE, the current ramps up or down at a programmable rate. The ramp durations are programmed using the register bits defined in Section 16.2.3. If the current ramp is not required when switching off DC-DC4 and the Current Sinks, then the following switch-off sequence may be used: * * Disable Boost Converter (DC4_ENA = 0) Disable Current Sink and Current Drive (CSn_ENA = 0; CSn_DRIVE = 0) When the Current Sinks are enabled, the status of each is indicated using the CSn_STS bits. If the Current Sinks are unable to sink the demanded current (eg. if the power source is too low or if the load is open circuit), then the respective CSn_STS bit will be set to 1. When the Current Sink circuit is correctly regulated, then the respective CSn_STS bits are set to 0. ADDRESS R16462 (404Eh) Current Sink 1 BIT 15 LABEL CS1_ENA DEFAULT 0 DESCRIPTION Current Sink 1 Enable (ISINK1 pin) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Current Sink 1 output drive enable 0 = Disabled 1 = Enabled Current Sink 1 status 0 = Normal 1 = Sink current cannot be regulated Current Sink 1 SLEEP Enable 0 = Disabled 1 = Controlled by CS1_ENA Current Sink 2 Enable (ISINK2 pin) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Current Sink 2 output drive enable 0 = Disabled 1 = Enabled Current Sink 2 status 0 = Normal 1 = Sink current cannot be regulated Current Sink 2 SLEEP Enable 0 = Disabled 1 = Controlled by CS2_ENA 14 CS1_DRIVE 0 13 CS1_STS 0 12 CS1_SLPENA 0 R16463 (404Fh) Current Sink 2 15 CS2_ENA 0 14 CS2_DRIVE 0 13 CS2_STS 0 12 CS2_SLPENA 0 Table 48 Enabling ISINK1 and ISINK2 16.2.2 PROGRAMMING THE SINK CURRENT The sink currents for ISINK1 and ISINK2 can be independently programmed by writing to the CS1_ISEL and CS2_ISEL register bits. The current steps are logarithmic to match the logarithmic light sensitivity characteristic of the human eye. The step size is 1.51dB (i.e. the current doubles every four steps). Note that the maximum programmable sink current is 27.6mA. The maximum current that can be supported by the DC-DC4 Boost Converter varies with the output voltage; the maximum ISINK current that can be supported by the Boost Converter will depend upon the forward voltage required by the current sink load(s). w PP, December 2009, Rev 3.0 99 WM8312 ADDRESS R16462 (404Eh) Current Sink 1 BIT 5:0 LABEL CS1_ISEL DEFAULT 00 0000 Pre-Production DESCRIPTION ISINK1 current. Current = 2.0A x 2^(CS1_ISEL/4), where CS1_ISEL is an unsigned binary number. Alternatively, CS1_ISEL = 13.29 x LOG(current/2.0A) 00_0000 = 2.0A 11_0111 = 27.6mA Values greater than 11_0111 will result in the maximum current of approx 27.6mA. R16463 (404Fh) Current Sink 2 5:0 CS2_ISEL 00 0000 ISINK2 current. Current = 2.0A x 2^(CS2_ISEL/4), where CS2_ISEL is an unsigned binary number. Alternatively, CS2_ISEL = 13.29 x LOG(current/2.0A) 00_0000 = 2.0A 11_0111 = 27.6mA Values greater than 11_0111 will result in the maximum current of approx 27.6mA. Table 49 Controlling the Sink Current for ISINK1 and ISINK2 16.2.3 ON/OFF RAMP TIMING When the Current Sinks output drive is enabled or disabled using CS1_DRIVE or CS2_DRIVE, the current ramps up or down at a programmable rate. This can be used in order to switch the LEDs on or off gradually. The ramp durations are programmed using the register bits defined in Table 50. ADDRESS R16462 (404Eh) Current Sink 1 BIT 11:10 LABEL CS1_OFF_RA MP DEFAULT 01 DESCRIPTION ISINK1 Switch-Off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. ISINK1 Switch-On ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. PP, December 2009, Rev 3.0 100 9:8 CS1_ON_RAM P 01 w Pre-Production ADDRESS R16463 (404Fh) Current Sink 2 BIT 11:10 LABEL CS2_OFF_RA MP DEFAULT 01 WM8312 DESCRIPTION ISINK2 Switch-Off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. ISINK2 Switch-On ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. 9:8 CS2_ON_RAM P 01 Table 50 Configuring On/Off Ramp Timing for ISINK1 and ISINK2 16.3 CURRENT SINK INTERRUPTS The Current Sinks are associated with two Interrupt event flags, which indicate if the Current Sinks are unable to sink the demanded current (eg. if the power source is too low or if the load is open circuit). Each of these secondary interrupts triggers a primary Current Sink Interrupt, CS_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 51. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 7 LABEL CS2_EINT DESCRIPTION Current Sink 2 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Current Sink 1 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 6 CS1_EINT R16410 (401Ah) Interrupt Status 2 Mask 7 IM_CS2_EINT 6 IM_CS1_EINT Table 51 Current Sink Interrupts w PP, December 2009, Rev 3.0 101 WM8312 16.4 LED DRIVER CONNECTIONS Pre-Production The recommended connections for LEDs on ISINK1 and ISINK2 are illustrated in Figure 23. VDD WM8312 ISINK1 ISINKGND Figure 23 LED Connections to ISINK1 and ISINK2 The ground connection associated with these two Current Sinks is the ISINKGND pin. The DC-DC4 Boost Converter can be used to provide the VDD supply for ISINK1 or ISINK2. It is also possible to drive ISINK1 and ISINK2 simultaneously from the DC-DC4 Boost Converter. See Section 15.4.2 for details of configuring DC-DC4 correctly according to whether it is supplying ISINK1 or ISINK2. w PP, December 2009, Rev 3.0 102 Pre-Production WM8312 17 POWER SUPPLY CONTROL 17.1 GENERAL DESCRIPTION The WM8312 can take its power supply from a Wall adaptor, a USB interface or from a single-cell lithium battery. The WM8312 autonomously chooses the most appropriate power source available, and supports hot-swapping between sources (ie. the system can remain in operation while different sources are connected and disconnected). Comparators within the WM8312 identify which power supplies are available and select the power source in the following order of preference: * * * Wall adaptor (WALLVDD) USB power rail (USBVDD) Battery (BATTVDD) Note that the Wall supply is normally the first choice of supply, provided that it is within the operating limits quoted in Section 6. The WM8312 can operate with any combination of these power supplies, or with just a single supply. When WALLVDD or USBVDD is selected as the power source, this may be used to charge the Battery, using the integrated battery charger circuit. The recommended connections between the WM8312 and the WALL, USB and Battery supplies are illustrated in Figure 24. Note that the external FET components may be omitted in some applications, as described later in this section. Figure 24 WM8312 Power Supply Connections SYSVDD is primarily an output from the WM8312; this output is the preferred supply, where the WM8312 has arbitrated between the Wall, Battery and USB connections. This output is suitable for supplying power to the other blocks of the WM8312, including the DC-DC Converters and LDO Regulators. SYSVDD is also an input under some conditions, such as battery charging from the Wall supply. The voltage at the SYSVDD load connection point is sensed using the SYSVMON pin. All loads connected to the WM8312 should be connected to the SYSVDD pin. The inputs to the DCDC Converters and LDOs are typically connected to the SYSVDD pin. The inputs to the LDOs may, alternatively, be connected to the outputs of the DC-DCs if desired. w PP, December 2009, Rev 3.0 103 WM8312 Pre-Production Note that connecting the BATTVDD pin directly to a load is not recommended; this may lead to incorrect behaviour of the battery charger. The Wall Adaptor supply connects to SYSVDD via a FET switch as illustrated in Figure 24. The FET switch is necessary in order to provide isolation between the Wall supply and the Battery/USB supplies. The Wall Adapter voltage is sensed directly on the WALLVDD pin; this allows the WM8312 to determine the preferred supply, including when the Wall FET is switched off. The gate connection to the Wall FET is driven by the WALLFETENA pin. The drive strength of this pin can be selected using the WALL_FET_ENA_DRV_STR register bit as described in Section 17.3. Note that, when the Wall Adapter is the preferred power supply, the Battery will be used if necessary to supplement the current provided at SYSVDD. If the Wall Adapter power source is not used, then the associated FET may be omitted, as illustrated in Figure 24. The main battery connects directly to the BATTVDD pin. The voltage at the battery is sensed using the BATTVMON pin. It is highly recommended that an external FET is connected between BATTVDD and SYSVDD as illustrated in Figure 24. Under battery-powered operation, this FET controls the current flow from the battery to SYSVDD. By using this external path, the power losses under heavy load conditions are reduced, and power efficiency is increased. When this FET is not present, all the system current flows internally from BATTVDD to SYSVDD, which can lead to unnecessary thermal losses. The external Battery FET should always be used for average loads in excess of 1A. The gate connection to the Battery FET is driven by the BATTFETENA pin. The functionality of this pin is enabled by setting the BATT_FET_ENA register bit, as described in Section 17.2. If the average load drawn from the Battery is less than 1A, then the associated FET may be omitted, as illustrated in Figure 24. Note that the external FET is open during battery charging. The USB interface connects directly to the USBVDD pin. The WM8312 can use this pin as an input to power the device and/or to charge a battery connected to the BATTVDD pin. The voltage at the USB supply is sensed using the USBVMON pin. Note that, when USB is the preferred power supply, the Battery will be used if necessary to supplement the current drawn from the USBVDD pin. A backup battery may be connected to the BACKUPVDD pin. When no other supply is available, the backup battery provides power to maintain the RTC memory whilst in the BACKUP power state. At other times, the backup battery charger maintains the charge on this pin. See Section 17.6 for more details of Backup Power. The status of the Wall and USB power supplies is indicated in the System Status register, as described in Table 52. When PWR_WALL or PWR_USB is set, this indicates that the corresponding power source is available for powering the WM8312. If the status of either these power supplies changes, indicating a connection, disconnection, or a voltage that is outside the required limits, the Power Path Source interrupt, PPM_PWR_SRC_EINT, is set (see Section 17.5). Note that this interrupt does not indicate the availability of the battery power source. The PWR_SRC_BATT bit indicates when the battery is supplying current to the WM8312. This includes when the battery is supplementing the Wall or USB power supply sources. w PP, December 2009, Rev 3.0 104 Pre-Production ADDRESS R16397 (400Dh) System Status BIT 10 LABEL PWR_SRC_BATT DEFAULT 0 WM8312 DESCRIPTION Battery Power Source status 0 = Battery is not supplying current 1 = Battery is supplying current Wall Adaptor status 0 = Wall Adaptor voltage not present 1 = Wall Adaptor voltage is present USB status 0 = USB voltage not present 1 = USB voltage is present 9 PWR_WALL 0 8 PWR_USB 0 Table 52 Power Source Status Registers 17.2 BATTERY POWERED OPERATION The WM8312 selects Battery power via BATTVDD when the battery voltage is higher than the WALLVDD and USBVDD supply voltages. In practical usage, this means the Battery is used when the Wall and USB supplies are both disconnected. The battery will be used to supplement the USB or Wall Adaptor supplies when required. If the WALLVDD or USBVDD supply becomes available during battery operation, then the selected power source is adjusted accordingly. When an external FET is provided between BATTVDD and SYSVDD, as described in Section 17.1, the BATTFETENA pin functionality must be enabled by setting BATT_FET_ENA as described in Table 53. ADDRESS R16390 (4006h) Reset Control BIT 12 LABEL BATT_FET_ENA DEFAULT 0 DESCRIPTION Enables the FET gate functionality on the BATTFETENA pin. (Note this pin is Active Low.) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Table 53 Configuring the Battery Power Operation 17.3 WALL ADAPTOR POWERED OPERATION The WM8312 selects Wall Adaptor power whenever this supply is within the normal operating limits of 4.3V to 5.5V and WALLVDD is higher than BATTVDD. The Wall adaptor power source is also selected below 4.3V if USBVDD is less than 4.3V and WALLVDD is higher than BATTVDD. Note that USBVDD supply is not used when WALLVDD is within its normal operating limits, even if the USBVDD supply is higher than the WALLVDD supply. When the WALLVDD supply is selected and a Battery is connected, then battery charging is possible in the ON or SLEEP power states; see Section 17.7. The drive strength of the Wall FET gate connection, WALLFETENA, can be selected using the WALL_FET_ENA_DRV_STR register bit as described in Table 54. ADDRESS R16390 (4006h) Reset Control BIT 13 LABEL WALL_FET_ENA_D RV_STR DEFAULT 0 DESCRIPTION Sets the drive strength of the WALLFETENA pin. (Note this pin is Active Low.) 0 = Weak drive (500kOhm) 1 = Strong drive (50kOhm) Table 54 Configuring the Wall Adaptor Power Operation w PP, December 2009, Rev 3.0 105 WM8312 17.4 USB POWERED OPERATION Pre-Production The WM8312 selects USB power via the USBVDD pin when this supply is within the normal USB operating limits of 4.3V to 5.5V, and WALLVDD is less than 4.3V and USBVDD is the highest supply source available. USB power is also selected below 4.3V if WALLVDD is less than 3.4V and USBVDD is the highest supply available. The maximum current drawn from the USB supply is determined by the USB_ILIM register field. Currents ranging from 0mA to 1800mA may be selected. See also Section 7 for the limits of the USB Current switch. If the system current demand is greater than the limit set by USB_ILIM, then this is indicated via the USB_CURR_STS bit and by setting the PPM_USB_CURR_EINT interrupt (see Section 17.5). The USB power source will be supplemented by battery power, when available, in order to maintain the USB current within the applicable limit. If there is no battery connected, or there is insufficient capacity to support the system demands, then the supply rails may drop as the WM8312 attempts to meet the USB current limit. If a suitable WALLVDD supply becomes available during USB operation, then this will be selected as the preferred power source. When the USBVDD supply is selected and a Battery is connected, then battery charging is possible in the ON or SLEEP power states, provided that sufficient current capacity is available. See Section 17.7 for details of the Battery Charger. The user-configurable OTP memory contains the USB_ILIM register field. This allows users to program their chosen USB current limit on start-up. (Note that the current limit can still be updated during normal operation.) If the WM8312 is powered up with USBVDD as the selected power source, and the applicable USB current limit is 100mA, then the start-up behaviour is determined by the USB100MA_STARTUP field, as defined in Table 55. When starting up in 100mA USB mode, a normal or soft-start process can be selected. The soft-start option controls the DC-DC converters and LDO Regulators in order to reduce the start-up current demand. In 100mA USB soft-start operation, the DC-DC Converters are initially enabled in LDO mode in order that the in-rush current does not exceed the USB limit. The LDO Regulators are also current-limited during the soft start-up. Care is required when using the 100mA soft-start; if the LDOs or DC-DCs present an excessive load, then the WM8312 may be unable to power up; it must be ensured that the connected load is compatible with the 100mA current limit. In particular, it is important that the loads on the DC-DC Converters do not exceed the capacity of their LDO operating modes. (See Section 7.1 for the maximum current in LDO mode.) It is also possible to delay the USB start-up if the battery voltage is less than a selectable threshold; in these cases, the WM8312 enables the battery trickle charge mode (provided that CHG_ENA = 1), and delays the start-up request until the battery voltage threshold has been met. ADDRESS R16387 (4003h) Power State BIT 5:4 LABEL USB100MA_START UP [1:0 DEFAULT 00 DESCRIPTION Sets the device behaviour when starting up under USB power, when USB_ILIM = 010 (100mA) 00 = Normal 01 = Soft-Start 10 = Only start if BATTVDD > 3.1V 11 = Only start if BATTVDD > 3.4V In the 1X modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. The start-up request is delayed until the battery voltage threshold has been met. Note that trickle charge is only possible when CHG_ENA=1. w PP, December 2009, Rev 3.0 106 Pre-Production ADDRESS BIT 3 LABEL USB_CURR_STS DEFAULT 0 WM8312 DESCRIPTION Indicates if the USB current limit has been reached 0 = Normal 1 = USB current limit Sets the USB current limit 000 = 0mA (USB switch is open) 001 = 2.5mA 010 = 100mA 011 = 500mA 100 = 900mA 101 = 1500mA 110 = 1800mA 111 = 550mA 2:0 USB_ILIM 010 Table 55 Configuring the USB Power Operation 17.5 POWER PATH MANAGEMENT INTERRUPTS The Power Path Management circuit is associated with three Interrupt event flags. The PPM_SYSLO_EINT interrupt bit is set when the internal signal SYSLO is asserted. This indicates a SYSVDD undervoltage condition, described in Section 24.4. The PPM_PWR_SRC_EINT interrupt bit is set whenever the status of the Wall or USB supplies changes, indicating a connection, disconnection, or a voltage. See Section 17.1. The PPM_USB_CURR_EINT interrupt bit is set whenever the permitted USB current limit has been reached. See Section 17.4. Each of these secondary interrupts triggers a primary Power Path Management Interrupt, PPM_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 56. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 15 LABEL PPM_SYSLO_EINT DESCRIPTION Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path Source interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path USB Current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 14 PPM_PWR_SRC_EINT 13 PPM_USB_CURR_EINT R16409 (4019h) Interrupt Status 1 Mask 15 IM_PPM_SYSLO_EINT 14 IM_PPM_PWR_SRC_EINT 13 IM_PPM_USB_CURR_EIN T Table 56 Power Path Management Interrupts w PP, December 2009, Rev 3.0 107 WM8312 17.6 BACKUP POWER Pre-Production As an option, a backup power source can be provided for the WM8312. This can either be a rechargeable battery (coin cell or super/gold-capacitor) on the BACKUPVDD pin or else a standard capacitor on the LDO12VOUT pin. The purpose of the backup is to power the always-on functions such as the crystal oscillator, RTC and ALARM control registers. The backup power also maintains a `software scratch' memory area in the register map - see Section 12.6. Maintaining these functions at all times provides system continuity even when the main battery is removed and no other power supply is available. Backup Battery detection is enabled using BKUP_BATT_DET_ENA. The presence of a Backup Battery connected to BACKUPVDD is indicated in the BKUP_BATT_STS field. (Note that, in the case of a discharged battery or capacitor, the BKUP_BATT_STS may indicate that no battery is present.) If a backup battery is connected to the WM8312, then the backup battery charger should be configured in accordance with the system requirements and the operating voltage of the backup battery (or super/gold-capacitor). The backup battery charger is configured using the register bits described in Table 57. The backup battery charger is enabled using the BKUP_CHG_ENA bit. The target voltage and the maximum charge current are determined by the BKUP_CHG_ILIM and BKUP_CHG_VLIM fields. The backup battery charger operation is configurable using the BKUP_CHG_MODE field. Under default conditions, a constant current mode is used until the target voltage is reached, after which a constant voltage mode is selected. By setting BKUP_CHG_MODE = 1, only the constant current mode is used, and charging stops when the target voltage has been reached. See Section 17.7 for details of constant current and constant voltage battery charging. The BKUP_CHG_STS field indicates whether the circuit is actively charging the backup battery. This field may be used in conjunction with the BKUP_BATT_STS field in order to confirm if a backup battery is present and whether charging is successful. If desired, it is possible to connect a capacitor to the WM8312 as a backup power source, connected via a 1k resistor to the LDO12VOUT pin. In this case, however, it is particularly important to minimise the device power consumption in the BACKUP state. A 22F capacitor will maintain the device settings for up to 5 minutes in `unclocked' mode, where power consumption is minimised by stopping the RTC in the BACKUP state. The RTC is unclocked in the BACKUP state if the XTAL_BKUPENA register field is set to 0, as described in Section 20.5. It is recommended to use a rechargeable battery as the backup power source, as this can provide power to the WM8312 in BACKUP mode for many months whilst also maintaining the RTC and the `software scratch' register. Note that the Backup Battery Charger control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16459 (404Bh) Backup Charger Control BIT 15 LABEL BKUP_CHG_ENA DEFAULT 0 DESCRIPTION Backup Charger Enable 0 = Disable 1 = Enable Note - this bit is reset to 0 when the OFF power state is entered. Protected by user key w PP, December 2009, Rev 3.0 108 Pre-Production 14 BKUP_CHG_STS 0 Backup Charger status 0 = Not charging 1 = Charging WM8312 12 BKUP_CHG_MODE 0 Backup Charger mode 0 = Constant current and Constant voltage modes enabled 1 = Constant current mode only Protected by user key Backup Battery detection enable 0 = Disable 1 = Enable Note - this bit is reset to 0 when the OFF power state is entered. Backup Battery detection status 0 = Backup battery not present 1 = Backup battery is present Backup Charger voltage limit 0 = 2.5V 1 = 3.1V Protected by user key Backup Charger current limit 00 = 100uA 01 = 200uA 10 = 300uA 11 = 400uA Protected by user key 11 BKUP_BATT_DET_ ENA 0 10 BKUP_BATT_STS 0 4 BKUP_CHG_VLIM 0 1:0 BKUP_CHG_ILIM 00 Table 57 Backup Battery Charger Control 17.7 BATTERY CHARGER 17.7.1 GENERAL DESCRIPTION The WM8312 incorporates a battery charger which is designed for charging single-cell lithium batteries. The battery charger can operate from either the Wall or USB power sources. The battery charger implements constant-current (CC) and constant-voltage (CV) charge methods, and can run automatically without any intervention required by the host processor. The battery charger voltage and current are programmable. Trickle charging and fast charging modes are supported. In both modes, the SYSVDD voltage is monitored to ensure the power supply capacity or USB current limit is not exceeded. If the SYSVDD voltage drops to 3.9V, (eg. if the USB current limit has been reached), then the battery charge current is automatically reduced to try and prevent further voltage drop at SYSVDD. Under high operating load conditions, the battery may be required to supplement the USB or Wall Adaptor power sources. Note that this capability is supported even when battery charging is enabled; in this case, the battery provides power to the system when required, and the charger resumes when sufficient current capacity is available. Typical connections for the WM8312 battery charger are illustrated in Figure 25. w PP, December 2009, Rev 3.0 109 WM8312 Pre-Production Figure 25 Typical Connections for WM8312 Battery Charger The main battery terminal is connected to BATTVDD. The WM8312 also incorporates a battery temperature monitoring circuit, which monitors the NTC thermistor that is typically incorporated within a rechargeable battery pack. The NTCMON pin allows the charger to detect a hot or cold battery condition that may be outside the battery's usable operating conditions. Battery removal is also detected using the NTCMON pin. The bias resistor connected between NTCBIAS and NTCMON should be a 1% tolerance resistor with a nominal value equal to the value of the battery's NTC thermistor at 25C. The temperature monitoring circuit can be disabled by shorting NTCMON to LDO12VOUT. This is only recommended if there is no NTC thermistor incorporated in the battery pack or if battery temperature monitoring is provided by other methods. Note that the short between NTCMON and LDO12VOUT is only sensed during start-up; the temperature monitoring circuit cannot be enabled / disabled dynamically in the ON or SLEEP power states. See Section 17.7.7 for more details of the battery temperature monitoring function. A typical battery charge cycle is illustrated in Figure 26. This shows both the trickle charge and fast charge processes. The trickle charge mode is a constant current mode. The small charge current in this mode is suitable for pre-conditioning a deeply discharged battery, or when only limited power is available for battery charging. When the charger is enabled and the conditions for fast charging are not met, then trickle charging is selected. (Note that fast charging is not permitted if the battery voltage is below the defective battery threshold voltage.) Trickle charging is disabled when the charger enters the fast charging stage, or when the charge current drops to a programmable `End of Charge' threshold level at the end of the constant voltage charge phase. The fast charge mode is also a constant current mode, but higher charge currents are possible in this mode. In the fast charge phase, the WM8312 drives a programmable constant current into the battery through the BATTVDD pin. During this phase, the battery voltage rises until the battery reaches the target voltage. When the battery reaches the target voltage (through trickle charge and/or fast charge), the charger enters the constant voltage charge phase, in which the WM8312 regulates BATTVDD to the target voltage. During this phase of the charge process, the charge current decreases over time as the battery approaches its fully charged state. Battery charging is terminated when the current falls to a programmable `End of Charge' threshold level at the end of the constant voltage charge phase. w PP, December 2009, Rev 3.0 110 Pre-Production WM8312 Note that, at any time during trickle charging or fast charging, the battery may be required to supplement the USB or Wall Adaptor power source. In this case, the battery voltage may drop while it is providing power to the system. The charger resumes operation automatically as soon as sufficient current capacity is available from the main power source. After the battery has been fully charged and the charge process has terminated, battery charging will automatically re-start if the battery voltage falls below the charger re-start threshold. Figure 26 A Typical Charge Cycle 17.7.2 BATTERY CHARGER ENABLE The battery charger may be enabled when the WM8312 is in the ON or SLEEP power states. Note that battery charging is only possible when the selected power source is within normal operating limits. The battery charger is enabled when the CHG_ENA register bit is set to 1. When enabled, it checks if the conditions for charging are fulfilled and it controls the charging processes accordingly. The status of the battery charger can be read from the CHG_ACTIVE register bit. The target voltage for the battery is set by the CHG_VSEL field, as defined in Table 58. It is important that this field is correctly set according to the type of battery that is connected. Incorrect setting of this register may lead to a safety hazard condition. The trickle charge current is selected using the CHG_TRKL_ILIM field. This is the maximum trickle charge current - the actual charge current will be reduced if the battery is fully charged, or if the system supply, SYSVDD, drops as described in Section 17.7.1. When the battery reaches the target voltage, the charger enters the constant voltage charge phase, in which the WM8312 regulates BATTVDD to the target voltage. When the charger is in the constant voltage charge phase, then the CHG_TOPOFF bit will be set to indicate that the charge is approaching completion. The WM8312 incorporates thermal sensors to detect excessive temperatures within the device and to provide self-protection (see Section 26). By default, the battery charger will be disabled if the Thermal Warning condition occurs, and will be re-enabled after the condition has cleared. This response can be disabled by setting CHG_CHIP_TEMP_MON = 0, allowing the battery charge to continue. The Thermal Warning threshold is the lower of the two device temperature thresholds; the Thermal Shutdown threshold is the higher threshold. Note that the Thermal Shutdown condition cannot be ignored; this event causes a System Reset and a termination of battery charging. If the WM8312 is commanded to the OFF state for any reason, then battery charging will be terminated. The CHG_OFF_MASK bit can be used to prevent certain OFF transitions whilst the battery charger is active. Setting the CHG_OFF_MASK bit causes a `Software OFF request', `ON pin request' or GPIO OFF request to be ignored whilst the charger is active. See Section 11.3 for a full list of OFF transition events. The register control fields for trickle charging are described in Table 58. See Section 17.7.4 for details of battery charge termination. w PP, December 2009, Rev 3.0 111 WM8312 Pre-Production Note that the Battery Charger control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16456 (4048h) Charger Control 1 BIT 15 LABEL CHG_ENA DEFAULT 0 DESCRIPTION Battery Charger Enable 0 = Disable 1 = Enable Protected by user key Battery Charger Thermal warning select 0 = Thermal Warning is ignored 1 = Thermal Warning pauses Battery Charger Protected by user key Battery Charger OFF mask select 0 = OFF requests not masked 1 = OFF requests masked during Charging Protected by user key Battery Trickle Charge current limit 00 = 50mA 01 = 100mA 10 = 150mA 11 = 200mA Protected by user key Battery Charger target voltage 00 = 4.05V 01 = 4.10V 10 = 4.15V 11 = 4.20V Note that incorrect setting of this register may lead to a safety hazard condition. Protected by user key Battery Charger constant-voltage charge mode status 0 = Constant-voltage mode not active 1 = Constant-voltage mode is active Battery Charger status 0 = Not charging 1 = Charging 0 CHG_CHIP_TEMP_ MON 1 R16457 (4049h) Charger Control 2 14 CHG_OFF_MASK 0 7:6 CHG_TRKL_ILIM [1:0] 00 5:4 CHG_VSEL [1:0] 00 R16458 (404Ah) Charger Status 9 CHG_TOPOFF 0 8 CHG_ACTIVE 0 Table 58 Battery Charger Control The Battery Charger is associated with a number of Interrupt flags. Whenever the Battery Charger state changes, the CHG_MODE_EINT interrupt is set (see Section 17.7.8). This interrupt is set whenever charging starts, charging stops, fast charge is selected, fast charge is de-selected, an overtemperature condition occurs, or if the charger detects a battery failure. The CHG_START_EINT interrupt is also set whenever Battery Charging commences, including after pause due to USB limit or over-temperature condition. 17.7.3 FAST CHARGING Fast charging provides a faster way to charge the battery than is possible with trickle charge. See Section 17.7.1 for a description of fast charging. Fast charging mode is only possible under certain conditions. It is only possible when the selected power source is Wall or when the USB current limit is set to 500mA or more. It is also required that w PP, December 2009, Rev 3.0 112 Pre-Production WM8312 the battery voltage is above the fast charge voltage threshold; this ensures that fast charging is not applied to a heavily discharged battery. Fast charging is enabled by setting the CHG_FAST register bit, provided that the conditions for fast charging are satisfied. The fast charge current limit is selected using the CHG_FAST_ILIM field. The battery charge current is automatically controlled, up to a maximum set by CHG_FAST_ILIM. The current is automatically limited when required if the battery is fully charged, or if the system supply, SYSVDD, drops as described in Section 17.7.1. When the battery reaches the target voltage, the charger enters the constant voltage charge phase, in which the WM8312 regulates BATTVDD to the target voltage. When the charger is in the constant voltage charge phase, then the CHG_TOPOFF bit will be set (see Section 17.7.2) to indicate that the charge is approaching completion. The register control fields for fast charging are described in Table 59. Note that the Battery Charger control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16456 (4048h) Charger Control 1 R16457 (4049h) Charger Control 2 BIT 15 LABEL CHG_FAST DEFAULT 0 DESCRIPTION Battery Fast Charge Enable 0 = Disable 1 = Enable Protected by user key Battery Fast Charge current limit 0000 = 0mA 0001 = 50mA 0010 = 100mA 0011 = 150mA 0100 = 200mA 0101 = 250mA 0110 = 300mA 0111 = 350mA 1000 = 400mA 1001 = 450mA 1010 = 500mA 1011 = 600mA 1100 = 700mA 1101 = 800mA 1110 = 900mA 1111 = 1000mA Protected by user key 3:0 CHG_FAST_ILIM [3:0] 0010 Table 59 Fast Charge Control 17.7.4 CHARGER TIMEOUT AND TERMINATION Fast charging and trickle charging is terminated under any of the following conditions: * * * * * Charge current falls below the `End of Charge' threshold Charger timeout Battery fault or overvoltage condition (see Section 17.7.6) Chip overtemperature condition (see Section 17.7.2) Transition to the OFF power state The End of Charge current threshold can be set using the CHG_ITERM register field, as defined in Table 60. Charging is terminated when the charge current is below the CHG_ITERM threshold, provided also that the battery voltage has reached the target voltage CHG_VSEL at the end of the constant voltage charge phase. w PP, December 2009, Rev 3.0 113 WM8312 Pre-Production If the battery charge current is reduced or paused due to a drop in SYSVDD voltage (as described in Section 17.7.1), then the End of Charge current threshold does not cause battery charging to be terminated, as the charge current is not indicative of the battery charge status in this case. The battery charger has a programmable safety timer to control the battery charge duration. The timer is started when either fast charging or trickle charging commences, including charging that is triggered as a result of the battery voltage dropping to the charger re-start threshold. The timer is restarted if the charging mode is changed (eg. between fast charge and trickle charge modes). The timeout period may be set by writing to the CHG_TIME register field; this allows charge times of up to 510mins (8.5 hours) to be selected. When the timeout period completes, the battery charge cycle is terminated. In this event, the charger will not re-start until the charger has been disabled (CHG_ENA = 0) and then re-enabled (CHG_ENA = 1). Note that the charger re-start threshold is ignored in this case, and the charger will not re-start automatically. The elapsed battery charge time can be read from the CHG_TIME_ELAPSED register field. This field is reset whenever the charger timer is started (ie. by starting charging, stopping charging, or changing charging modes). If charging is paused due to a battery temperature or chip temperature condition, then the charge timer is paused until charging resumes. Battery charging is terminated if removal of the battery is detected via the NTC monitor connections (see Section 17.7.2). The register control fields for battery charger termination are described in Table 60. Note that the Battery Charger control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16456 (4048h) Charger Control 1 BIT 12:10 LABEL CHG_ITERM [2:0] DEFAULT 000 DESCRIPTION Battery End of Charge current threshold 000 = 20mA 001 = 30mA 010 = 40mA 011 = 50mA 100 = 60mA 101 = 70mA 110 = 80mA 111 = 90mA Protected by user key Battery charger timeout 0000 = 60min 0001 = 90min 0010 = 120min 0011 = 150min 0100 = 180min 0101 = 210min 0110 = 240min 0111 = 270min 1000 = 300min 1001 = 330min 1010 = 360min 1011 = 390min 1100 = 420min 1101 = 450min 1110 = 480min 1111 = 510min Protected by user key R16457 (4049h) Charger Control 2 11:8 CHG_TIME [3:0] 0110 w PP, December 2009, Rev 3.0 114 Pre-Production ADDRESS R16458 (404Ah) Charger Status BIT 7:0 LABEL CHG_TIME_EL APSED [7:0] DEFAULT 00h WM8312 DESCRIPTION Battery charger elapsed time 00h = 0min 01h = 2min 02h = 4min 03h = 6min ... FFh = 510min Table 60 Battery Charger Termination The Battery Charger is associated with a number of Interrupt flags, as described in Section 17.7.8. If battery charging is terminated due to the End of Charge current threshold being reached, then the CHG_END_EINT interrupt is set. If battery charging is terminated due to the charge timeout, then the charger will set the CHG_TO_EINT interrupt. 17.7.5 BATTERY CHARGE CURRENT MONITORING The battery charge current can be monitored externally or internally. When the CHG_IMON_ENA bit is set, then the WM8312 sources an output current at AUXADCIN1 which is proportional to the battery charger current. When a resistor is connected between AUXADCIN1 and GND, then the charge monitor current is converted to a voltage which can be measured by the Auxiliary ADC. The recommended value of the resistor is 10k. Larger resistors may also be used in order to improve the measurement resolution, but the voltage at AUXADCIN1 must not exceed 2.5V. Note that the CHG_IMON_ENA register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16456 (4048h) Charger Control 1 BIT 2 LABEL CHG_IMON_E NA DEFAULT 0 DESCRIPTION Enable battery charge current monitor at AUXADCIN1. 0 = Disabled 1 = Enabled (Note - a resistor is required between AUXADCIN1 and GND in order to measure the charge current using the AUXADC. The recommended resistor value is 10k.) Protected by user key Table 61 Battery Charge Current Monitoring The AUXADCIN1 monitor output current is equal to the battery charge current divided by 12500. The battery charge current can be determined by measuring the voltage at the AUXADCIN1 pin, as described in the following equations. Monitor Current IM = Charge Current IC 12500 VAUXADCIN1 x 12500 10000 (assuming 10k resistor, R) = VAUXADCIN1 R Charge Current IC = For example, a measurement of 0.72V at AUXADCIN1 would indicate that the battery charge current is 900mA. w PP, December 2009, Rev 3.0 115 WM8312 Pre-Production Note that the integrated Auxiliary ADC can be used to perform this measurement if required. In this case, the digitised AUXADC measurement (AUX_DATA) represents the battery charge current in accordance with the following equation. See Section 18 for further details of the Auxiliary ADC. 17.7.6 BATTERY FAULT / OVERVOLTAGE CONDITIONS The battery is monitored to detect an overvoltage or failure condition. These features are incorporated to prevent malfunction of the battery charger or of the WM8312 system. The BATT_OV_STS bit indicates if an overvoltage condition has been detected. The overvoltage threshold is defined in Section 7.7. If a battery overvoltage condition is detected, then charging is terminated and the CHG_OV_EINT interrupt flag is set (see Section 17.7.8). The battery charger also detects if the battery is faulty. This is detected if the battery voltage does not reach the fast charge threshold voltage within the defective battery timeout period (see Section 7.7), or within a quarter of the charging time CHG_TIME (whichever is the longer time). The battery failure condition is cleared if the battery voltage rises above the defective battery threshold, or if any of the WM8312 power sources (including the battery) is removed and reconnected. When the failure condition is cleared, the charger then reverts back to its initial state, and may re-start if the conditions for charging are fulfilled. If the battery failure condition is detected in fast charge mode, then the charger reverts to trickle charging mode. If the fault persists, then trickle charging stops as described above. If battery failure condition is detected, then charging is terminated and the CHG_BATT_FAIL_EINT interrupt is set (see Section 17.7.8). The battery overvoltage bit is defined in Table 62. ADDRESS R16458 (404Ah) Charger Status BIT 15 LABEL BATT_OV_ST S DEFAULT 0 DESCRIPTION Battery Overvoltage status 0 = Normal 1 = Battery Overvoltage Table 62 Battery Overvoltage Status 17.7.7 BATTERY TEMPERATURE MONITORING As described in Section 17.7.1, the WM8312 is designed to monitor battery temperature using a standard NTC thermistor component which is typically incorporated within the battery pack. This allows the battery charger to detect a hot or cold battery condition that may be outside the battery's usable operating conditions. (Note that the temperature monitoring circuit also detects if the NTC circuit is not connected, in order to mask any erroneous fault indications.) The BATT_HOT_STS and BATT_COLD_STS register bits indicate if a hot battery or cold battery temperature condition has been detected. If a battery temperature fault condition is detected, then charging is paused temporarily and the CHG_BATT_HOT_EINT or CHG_BATT_COLD_EINT interrupt is set (see Section 17.7.8). Under typical circuit configurations, the hot and cold temperature conditions are designed to be +40C and 0C respectively. These temperatures can be adjusted by the use of different resistor components, as described in the applications information in Section 30.6. Battery removal is also detected using the NTC circuit. This is used to terminate battery charging if a battery is removed during charging. w PP, December 2009, Rev 3.0 116 Pre-Production WM8312 The temperature monitoring circuit can be disabled by shorting NTCMON to LDO12VOUT. This is only recommended if there is no NTC thermistor incorporated in the battery pack or if battery temperature monitoring is provided by other methods. Note that the short between NTCMON and LDO12VOUT is only sensed during start-up; the temperature monitoring circuit cannot be enabled / disabled dynamically in the ON or SLEEP power states. The battery temperature status bits are described in Table 63. ADDRESS R16458 (404Ah) Charger Status BIT 11 LABEL BATT_HOT_ST S BATT_COLD_ STS DEFAULT 0 DESCRIPTION Battery Hot status 0 = Normal 1 = Battery Hot Battery Cold status 0 = Normal 1 = Battery Cold 10 0 Table 63 Battery Temperature Status Battery temperature monitoring is configured as illustrated in Figure 27. The principle of operation is that a temperature change in the battery pack causes a change in resistance of the NTC thermistor, which results in a voltage change at the NTCMON pin. Figure 27 Battery Temperature Monitoring For information on how to set the hot and cold temperature limits, see the Applications Information in Section 30.6. 17.7.8 BATTERY CHARGER INTERRUPTS The Battery Charger is associated with a number of Interrupt event flags, described in Table 64. Each of these secondary interrupts triggers a primary Battery Charger Interrupt, CHG_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 64. If any Battery Charger interrupt event occurs while in the SLEEP power state, then a WAKE transition request is generated. Note that this behaviour is not affected by any of the interrupt mask bits. See Section 11.3 for a description of the WM8312 power state transitions. w PP, December 2009, Rev 3.0 117 WM8312 ADDRESS R16402 (4012h) Interrupt Status 2 BIT 15 LABEL CHG_BATT_HOT_EINT Pre-Production DESCRIPTION Battery Hot interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Cold interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Overvoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge End interrupt (End of Charge Current threshold reached) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Timeout interrupt (Charger Timer has expired) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Mode interrupt (Charger Mode has changed) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Start interrupt (Charging has started) (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. PP, December 2009, Rev 3.0 118 14 CHG_BATT_COLD_EINT 13 CHG_BATT_FAIL_EINT 12 CHG_OV_EINT 11 CHG_END_EINT 10 CHG_TO_EINT 9 CHG_MODE_EINT 8 CHG_START_EINT R16410 (401Ah) Interrupt Status 2 Mask 15 IM_CHG_BATT_HOT_EINT 14 IM_CHG_BATT_COLD_EIN T 13 IM_CHG_BATT_FAIL_EINT 12 IM_CHG_OV_EINT 11 IM_CHG_END_EINT 10 IM_CHG_TO_EINT 9 IM_CHG_MODE_EINT w Pre-Production ADDRESS BIT 8 LABEL IM_CHG_START_EINT DESCRIPTION Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) WM8312 Table 64 Battery Charger Interrupts 17.7.9 BATTERY CHARGER STATUS The status of the Battery Charger can be read from various registers and interrupts noted in the above sections. The Battery Charger status can also be read from the CHG_STATE register field, as defined in Table 65. Note that the LED Status outputs can also be configured to indicate the Battery Charger status - see Section 22. ADDRESS R16458 (404Ah) Charger Status BIT 14:12 LABEL CHG_STATE [2:0] DEFAULT 000 DESCRIPTION Battery Charger state 000 = Off 001 = Trickle Charge 010 = Fast Charge 011 = Trickle Charge overtemperature 100 = Fast Charge overtemperature 101 = Defective 110 = Reserved 111 = Reserved Table 65 Battery Charger State w PP, December 2009, Rev 3.0 119 WM8312 18 AUXILIARY ADC 18.1 GENERAL DESCRIPTION Pre-Production The WM8312 incorporates a 12-bit Auxiliary ADC (AUXADC). This can be used to perform a number of system measurements (including supply voltages and battery temperature) and can also be used to measure analogue voltages from external sources and sensors. External inputs to the AUXADC should be connected to the pins AUXADCIN1, AUXADCIN2, AUXADCIN3 and AUXADCIN4. The maximum voltage that can be measured is determined by the power domain associated with each (see Section 3). In the case of AUXADCIN 1-3, the maximum voltage is SYSVDD; in the case of AUXADCIN4, the maximum voltage is TPVDD. Note that SYSVDD varies according to the voltage of the preferred power source (WALLVDD, USBVDD or BATTVDD). The AUXADC can also measure the voltage on WALLVDD, USBVDD and BATTVDD. Internal resistor dividers enable voltages higher than SYSVDD to be measured by the AUXADC - voltages up to 6V can be measured on these pins. 18.2 AUXADC CONTROL The AUXADC is enabled by setting the AUX_ENA register bit. By default, the AUXADC is not enabled in the SLEEP state, but this can be selected using the AUX_SLPENA field. The AUXADC measurements can be initiated manually or automatically. For automatic operation, the AUX_RATE register is set according to the required conversion rate, and conversions are enabled by setting the AUX_CVT_ENA bit. For manual operation, the AUX_RATE register is set to 00h, and each manual conversion is initiated by setting the AUX_CVT_ENA bit. In manual mode, the AUX_CVT_ENA bit is reset by the WM8312 at the end of each conversion. Note that the AUXADC measurements are interleaved with the Touch Panel measurements, when both are enabled. If a Touch Panel measurement set is already in progress at the time when an AUXADC measurement is due, then the AUXADC measurement will be delayed until after the Touch Panel measurement set has completed. This applies equally to Manual and to Automatic AUXADC modes. The AUXADC has 11 available input sources. Each of these inputs is enabled by setting the respective bit in the AuxADC Source Register (R16431). For each AUXADC measurement event (in Manual or Automatic modes), the WM8312 selects the next enabled input source. Any number of inputs may be selected simultaneously; the AUXADC will measure each one in turn. Note that only a single AUXADC measurement is made on any Manual or Automatic trigger. For example, if the AUX1, BATT and USB voltages are enabled for AUXADC measurement, then AUX1 would be measured in the first instance, and BATT then USB would be measured on the next manual or automatic AUXADC triggers. In this case, a total of three manual or automatic AUXADC triggers would be required to measure all of the selected inputs. w PP, December 2009, Rev 3.0 120 Pre-Production WM8312 The control fields associated with initiating AUXADC measurements are defined in Table 66. ADDRESS R16430 (402Eh) AuxADC Control BIT 15 LABEL AUX_ENA DEFAULT 0 DESCRIPTION AUXADC Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. AUXADC Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (AUX_RATE = 0), setting this bit will initiate a conversion; the bit is reset at the end of the conversion. AUXADC SLEEP Enable 0 = Disabled 1 = Controlled by AUX_ENA AUXADC Conversion Rate 0 = Manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s ... 31 = 62 samples/s 32 = Reserved 33 = 16 samples/s 34 = 32 samples/s 35 = 48 samples/s ... 63 = 496 samples/s AUXADC BACKUP input select 0 = Disable BACKUPVDD measurement 1 = Enable BACKUPVDD measurement AUXADC WALL input select 0 = Disable WALLVDD measurement 1 = Enable WALLVDD measurement AUXADC BATT input select 0 = Disable BATTVDD measurement 1 = Enable BATTVDD measurement AUXADC USB input select 0 = Disable USBVDD measurement 1 = Enable USBVDD measurement AUXADC SYSVDD input select 0 = Disable SYSVDD measurement 1 = Enable SYSVDD measurement AUXADC Battery Temp input select 0 = Disable Battery Temp measurement 1 = Enable Battery Temp measurement AUXADC Chip Temp input select 0 = Disable Chip Temp measurement 1 = Enable Chip Temp measurement PP, December 2009, Rev 3.0 121 14 AUX_CVT_ENA 0 12 AUX_SLPENA 0 5:0 AUX_RATE [5:0] 00_0000 R16431 (402Fh) AuxADC Source 10 AUX_BKUP_BAT T_SEL 0 9 AUX_WALL_SEL 0 8 AUX_BATT_SEL 0 7 AUX_USB_SEL 0 6 AUX_SYSVDD_S EL AUX_BATT_TEM P_SEL 0 5 0 4 AUX_CHIP_TEM P_SEL 0 w WM8312 ADDRESS BIT 3 LABEL AUX_AUX4_SEL DEFAULT 0 Pre-Production DESCRIPTION AUXADCIN4 input select 0 = Disable AUXADCIN4 measurement 1 = Enable AUXADCIN4 measurement AUXADCIN3 input select 0 = Disable AUXADCIN3 measurement 1 = Enable AUXADCIN3 measurement AUXADCIN2 input select 0 = Disable AUXADCIN2 measurement 1 = Enable AUXADCIN2 measurement AUXADCIN1 input select 0 = Disable AUXADCIN1 measurement 1 = Enable AUXADCIN1 measurement 2 AUX_AUX3_SEL 0 1 AUX_AUX2_SEL 0 0 AUX_AUX1_SEL 0 Table 66 AUXADC Control 18.3 AUXADC READBACK Measured data from the AUXADC is read via the AuxADC Data Register (R16429), which contains two fields. The AUXADC Data Source is indicated in the AUX_DATA_SRC field; the associated measurement data is contained in the AUX_DATA field. Reading from the AuxADC Data Register returns a 12-bit code which represents the most recent AUXADC measurement on the associated channel. It should be noted that every time an AUXADC measurement is written to the AuxADC Data Register, the previous data is overwritten - the host processor should ensure that data is read from this register before it is overwritten. The AUXADC interrupts can be used to indicate when new data is available - see Section 18.5. The 12-bit AUX_DATA field can be equated to the actual voltage (or temperature) according to the following equations, where AUX_DATA is regarded as an unsigned integer: Battery Temperature measurement varies according to the selected NTC thermistor component. In a typical application, it is anticipated that the AUXADC Interrupts would be used to control the AUXADC readback - the host processor should read the AUXADC Data Register in response to the AUXADC Interrupt event. See Section 18.5 for details of AUXADC Interrupts. In Automatic AUXADC mode, the processor should complete this action before the next measurement occurs, in order to avoid losing any AUXADC samples. In Manual conversion mode, the interrupt signal provides confirmation that the commanded measurement has been completed. The control fields associated with initiating AUXADC readback are defined in Table 67. w PP, December 2009, Rev 3.0 122 Pre-Production ADDRESS R16429 (402Dh) AuxADC Data BIT 15:12 LABEL AUX_DATA_SRC [3:0] DEFAULT 000 WM8312 DESCRIPTION AUXADC Data Source 0 = Reserved 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage 8 = USB voltage 9 = BATT voltage 10 = WALL voltage 11 = Backup Battery voltage 12 = Reserved 13 = Reserved 14 = Reserved 15 = Reserved AUXADC Measurement Data Voltage (mV) = AUX_DATA x 1.465 ChipTemp (C) = (512.18 AUX_DATA) / 1.0983 BattTemp (C) = (value is dependent on NTC thermistor) 11:0 AUX_DATA [11:0] 000h Table 67 AUXADC Readback 18.4 DIGITAL COMPARATORS The WM8312 has four digital comparators which may be used to compare AUXADC measurement data against programmable threshold values. Each comparator has a status bit, and also an associated interrupt flag (described in Section 18.5), which indicates that the associated data is beyond the threshold value. The digital comparators are enabled using the DCMPn_ENA register bits as described in Table 66. After an AUXADC conversion, the measured value is compared with the threshold level of any associated comparator(s). Note that this comparison is only performed following a conversion. The source data for each comparator is selected using the DCMPn_SRC register bits; this selects one of eight possible AUXADC channels for each comparator. If required, the same AUXADC channel may be selected for more than one comparator; this would allow more than one threshold to be monitored on the same AUXADC channel. Note that the coding of the 000b value of the DCMPn_SRC fields differs between the four comparators. The DCMPn_GT register bits select whether the status bit and associated interrupt flag will be asserted when the measured value is above the threshold or when the measured value is below the threshold. The output of the most recent threshold comparison is indicated in the DCOMPn_STS fields. The threshold DCMPn_THR is a 12-bit code for each comparator. This field follows the same voltage or temperature coding as the associated AUXADC channel source (see Section 18.3). w PP, December 2009, Rev 3.0 123 WM8312 ADDRESS R16432 (4030h) Comparator Control BIT 11 LABEL DCOMP4_STS DEFAULT 0 Pre-Production DESCRIPTION Digital Comparator 4 status 0 = Comparator 4 threshold not detected 1 = Comparator 4 threshold detected (Trigger is controlled by DCMP4_GT) Digital Comparator 3 status 0 = Comparator 3 threshold not detected 1 = Comparator 3 threshold detected (Trigger is controlled by DCMP3_GT) Digital Comparator 2 status 0 = Comparator 2 threshold not detected 1 = Comparator 2 threshold detected (Trigger is controlled by DCMP2_GT) Digital Comparator 1 status 0 = Comparator 1 threshold not detected 1 = Comparator 1 threshold detected (Trigger is controlled by DCMP1_GT) Digital Comparator 4 Enable 0 = Disabled 1 = Enabled Digital Comparator 3 Enable 0 = Disabled 1 = Enabled Digital Comparator 2 Enable 0 = Disabled 1 = Enabled Digital Comparator 1 Enable 0 = Disabled 1 = Enabled Digital Comparator 1 source select 0 = USB voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold Digital Comparator 1 threshold (12-bit unsigned binary number; PP, December 2009, Rev 3.0 124 10 DCOMP3_STS 0 9 DCOMP2_STS 0 8 DCOMP1_STS 0 3 DCMP4_ENA 0 2 DCMP3_ENA 0 1 DCMP2_ENA 0 0 DCMP1_ENA 0 R16433 (4031h) Comparator 1 15:13 DCMP1_SRC [2:0] 000 12 DCMP1_GT 0 11:0 DCMP1_THR 000h w Pre-Production ADDRESS BIT LABEL DEFAULT WM8312 DESCRIPTION coding is the same as AUX_DATA) Digital Comparator 2 source select 0 = WALL voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold Digital Comparator 2 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) Digital Comparator 3 source select 0 = BATT voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold Digital Comparator 3 threshold (12-bit unsigned binary number; coding is the same as AUX_DATA) Digital Comparator 4 source select 0 = Backup Battery voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold Digital Comparator 4 threshold (12-bit unsigned binary number; PP, December 2009, Rev 3.0 125 R16434 (4032h) Comparator 2 15:13 DCMP2_SRC [2:0] 000 12 DCMP2_GT 0 11:0 DCMP2_THR 000h R16435 (4033h) Comparator 3 15:13 DCMP3_SRC [2:0] 000 12 DCMP3_GT 0 11:0 DCMP3_THR 000h R16436 (4034h) Comparator 4 15:13 DCMP4_SRC [2:0] 000 12 DCMP4_GT 0 11:0 DCMP4_THR 000h w WM8312 ADDRESS BIT LABEL DEFAULT Pre-Production DESCRIPTION coding is the same as AUX_DATA) Table 68 AUXADC Digital Comparator Control 18.5 AUXADC INTERRUPTS The AUXADC is associated with a number of Interrupt event flags to indicate when new AUXADC data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed. Each of these secondary interrupts triggers a primary AUXADC Interrupt, AUXADC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 69. Note that AUXADC_DATA_EINT is not cleared by reading the measured AUXADC data, it can only be cleared by writing `1' to the AUXADC_DATA_EINT register. The AUXADC interrupts can be programmed using bits in Table 69. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 8 LABEL AUXADC_DATA_EINT DESCRIPTION AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. AUXADC Digital Comparator n interrupt (Trigger is controlled by DCMPn_GT) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7:4 AUXADC_DCOMPn_EINT R16409 (4019h) Interrupt Status 1 Mask 8 IM_AUXADC_DATA_EINT 7:4 IM_AUXADC_DCOMPn_EI NT Note: n is a number between 1 and 4 that identifies the individual Comparator. Table 69 AUXADC Interrupts w PP, December 2009, Rev 3.0 126 Pre-Production WM8312 19 TOUCH PANEL CONTROLLER 19.1 GENERAL DESCRIPTION The WM8312 incorporates a Touch Panel controller interface, supporting standard resistive 4-wire and 5-wire panel types. The controller supports X, Y co-ordinate measurement and Pen Down detection. The 4-wire configuration also supports Touch Pressure (Z-axis) measurement. The Touch Panel interfaces via GPIO pins 13-16. (In 5-wire mode, the AUXADCIN4 pin is also used.) The controller provides high resolution digitiser measurements, using the same 12-bit AUXADC as described in Section 18. Touch Panel conversion requests are interleaved with AUXADC measurement requests. The Touch Panel can be enabled or disabled in the SLEEP state; Pen Down detection can be used to issue a WAKE request, including when the Touch Panel is disabled. Touch Panel Interrupts can be generated on completion of a set of measurements, or on Pen Down detection. Read access to the Touch Panel measurement data is controlled in order to ensure the host always reads a complete set of data, and does not read mixed data that relates to separate measurement events. An overview of Touch Panel operating principles is provided in Section 19.6. 19.2 TOUCH PANEL CONFIGURATION The Touch Panel interface uses GPIO pins 13-16. When the Touch Panel is enabled, the GPIO functionality on these pins must be disabled by tri-stating the GPIO using GPn_TRI (see Section 21.3). When the Touch Panel is enabled, then TPVDD should be connected to the LDO13VOUT (INTVDD) power domain. It is important that TPVDD is not connected to a higher voltage than this. Note that, due to the ratiometric measurement method, the accuracy of the supply voltage does not affect the measurement accuracy. The 5-wire Touch Panel interface also uses the AUXADCIN4 pin; in this case, the AUXADCIN4 input is not available to the AUXADC function. The Touch Panel pin configuration differs between 4-wire and 5-wire modes as follows: PIN NAME GPIO13 GPIO14 GPIO15 GPIO16 AUXADCIN4 Table 70 Touch Panel Pin Configuration 4-WIRE FUNCTION Right contact Top contact Left contact Bottom contact n/a 5-WIRE FUNCTION Bottom Right contact Top Right contact Top Left contact Bottom Left contact Wiper Contact The Touch Panel 4-wire or 5-wire mode is selected using the TCH_5WIRE bit. Pressure measurement (4-wire mode only) uses a constant current source to measure the resistance between the top and bottom sheets of the touch panel. The current is selectable using TCH_ISEL, to suit different types of touch panel. Pen Down detection sensitivity can be controlled using TCH_RPU. Decreasing the resistance makes the touch panel less sensitive; increasing the resistance makes the touch panel more sensitive. The Touch Panel configuration register bits are defined in Table 71. w PP, December 2009, Rev 3.0 127 WM8312 ADDRESS R16425 (4029h) Touch Control 2 BIT 12 LABEL TCH_5WIRE DEFAULT 0 Pre-Production DESCRIPTION Touch Panel control mode 0 = 4-wire 1 = 5-wire Pressure measurement current select 0 = 200uA 1 = 400uA Note - this applies to 4-wire mode only Pen-Down sensitivity (pull-up resistor) 0000 = 64k (most sensitive) 0001 = 64k / 2 0010 = 64k / 3 0011 = 64k / 4 .... 1111 = 64k / 16 (least sensitive) 8 TCH_ISEL 0 3:0 TCH_RPU [3:0] 0111 Table 71 Touch Panel Configuration 19.3 TOUCH PANEL CONTROL The Touch Panel is enabled by setting the TCH_ENA register bit. By default, the Touch Panel is not enabled in the SLEEP state, but this can be selected using the TCH_SLPENA field. The Touch Panel can be configured to issue a WAKE request when the `Pen Down' is detected by setting the TCH_PD_WK bit. This function is only supported when TCH_ENA = 1. Note that the WAKE request may be generated regardless of the TCH_SLPENA setting. The Touch Panel measurements can be initiated manually or automatically. For automatic operation, the TCH_RATE register is set according to the required conversion rate, and measurements are enabled by setting the TCH_CVT_ENA bit. For manual operation, the TCH_RATE register is set to 00h, and a set of measurements is initiated by setting the TCH_CVT_ENA bit. In manual mode, the TCH_CVT_ENA bit is reset by the WM8312 at the end of set of measurements. Note that the Touch Panel measurements are interleaved with the AUXADC measurements, when both are enabled. If an AUXADC measurement set is already in progress at the time when an Touch Panel measurement is due, then the Touch Panel measurement will be delayed until after the AXUADC measurement set has completed. This applies equally to Manual and to Automatic Touch Panel modes. The Touch Panel `Pen Down' detection can be used to control measurements in automatic mode. When TCH_PDONLY is set, then automatic conversions will only be scheduled when `Pen Down' is detected. In this mode, automatic conversions are suspended after a measurement has been made for which `Pen Down' is not detected. Automatic measurements are resumed when `Pen Down' is detected. Note that manual conversion commands are not affected by TCH_PDONLY. For each Touch Panel measurement event (in Manual or Automatic modes), the WM8312 performs a set of measurements encompassing all enabled input sources; the X-axis, Y-axis and Z-axis measurements are enabled using the TCH_X_ENA, TCH_Y_ENA and TCH_Z_ENA register bits respectively. To allow settling time between consecutive measurements, a programmable delay is applied between the X, Y and Z-axis measurements; this is set using the TCH_DELAY field. The control fields associated with initiating Touch Panel measurements are defined in Table 72. w PP, December 2009, Rev 3.0 128 Pre-Production ADDRESS R16424 (4028h) Touch Control 1 BIT 15 LABEL TCH_ENA DEFAULT 0 WM8312 DESCRIPTION Touch Panel Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Touch Panel Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (TCH_RATE = 0), setting this bit will initiate a set of conversion; the bit is reset at the end of the conversion. Touch Panel SLEEP Enable 0 = Disabled 1 = Controlled by TCH_ENA Enables Z-axis touch panel measurements. (Z-axis is the pressure axis - 4-wire only.) 0 = Disabled 1 = Enabled Enables Y-axis touch panel measurements 0 = Disabled 1 = Enabled Enables X-axis touch panel measurements 0 = Disabled 1 = Enabled Settling time between X, Y and Z measurements. (Nominal timing only; typically +/-20% of quoted values.) 000 = 30us 001 = 60us 010 = 120us 011 = 240us 100 = 480us 101 = 960us 110 = 1920us 111 = 3840us Touch-panel Conversion Rate 0 = Manual 1 = 16 packets/s 2 = 32 packets/s 3 = 48 packets/s ... 31 = 496 packets/s WAKE transition select for Pen Down event 0 = Disabled 1 = Enabled Select Automatic conversions only when Pen Down is detected. (No effect on Manual conversion.) PP, December 2009, Rev 3.0 129 14 TCH_CVT_ENA 0 12 TCH_SLPENA 0 10 TCH_Z_ENA 0 9 TCH_Y_ENA 0 8 TCH_X_ENA 0 7:5 TCH_DELAY [2:0] 010 4:0 TCH_RATE [4:0] 0_0000 R16425 (4029h) Touch Control 2 13 TCH_PD_WK 0 11 TCH_PDONLY 0 w WM8312 ADDRESS BIT LABEL DEFAULT 0 = Normal 1 = Pen-Down only Table 72 Touch Panel Control Pre-Production DESCRIPTION 19.4 TOUCH PANEL READBACK Measured data from the Touch Panel controller is read via the Touch Data registers. The X-axis, Yaxis and Z-axis (pressure) measurements are provided in the TCH_X, TCH_Y and TCH_Z registers respectively. The TCH_PD1, TCH_PD2 and TCH_PD3 bits indicate whether the Pen Down status was asserted when the measurement set was made. To read a set of Touch Panel measurements, the host processor must access each of the applicable Touch Data registers. (Note that Z-axis measurement is applicable to 4-wire mode only.) When the host processor starts to read these registers, the WM8312 will inhibit any new touch panel measurements until the host processor has read all of the applicable registers. This ensures that the data read by the host processor all relates to the same set of measurements. The touch panel inhibit (preventing new touch panel measurements) commences when any of the Touch Data registers is read. The touch panel inhibit ceases when all selected Touch Data registers have been read, or if a read/write operation is made to any other register. If all 3 touch panel channels are selected (using TCH_X_ENA, TCH_Y_ENA and TCH_Z_ENA as described in Section 19.3), then all 3 Touch Data registers must be read before further measurements are permitted. If fewer channels are selected, then only those selected channels need to be read before touch panel measurements are enabled again. ADDRESS R16426 (402Ah) Touch Data X BIT 15 LABEL TCH_PD1 DEFAULT 0 DESCRIPTION Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected Touch panel X-axis data Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected Touch panel Y-axis data Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected Touch panel Z-axis data 11:0 R16427 (402Bh) Touch Data Y 15 TCH_X [11:0] TCH_PD2 000h 0 11:0 R16428 (402Ch) Touch Data Z 15 TCH_Y [11:0] TCH_PD3 000h 0 11:0 TCH_Z [11:0] 000h Table 73 Touch Panel Readback 19.5 TOUCH PANEL INTERRUPTS Touch panel events are associated with two Interrupt event flags. The TCHDATA_EINT interrupt bit is set when new Touch Panel data is available. This secondary interrupt triggers a primary Interrupt, TCHDATA_INT (see Section 23). This can be masked by setting the IM_TCHDATA_EINT mask bit as described in Table 74. The TCHPD_EINT interrupt bit is set when a Touch Panel `Pen Down' event is detected. This secondary interrupt triggers a primary Interrupt, TCHPD_INT (see Section 23). This can be masked by setting the IM_TCHPD_EINT mask bit as described in Table 74. w PP, December 2009, Rev 3.0 130 Pre-Production ADDRESS R16401 (4011h) Interrupt Status 1 BIT 10 LABEL TCHDATA_EINT WM8312 DESCRIPTION Touch panel Data interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Touch panel Pen Down interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 9 TCHPD_EINT R16409 (4019h) Interrupt Status 1 Mask 10 IM_TCHDATA_EINT 9 IM_TCHPD_EINT Table 74 Touch Panel Interrupts 19.6 TOUCH PANEL OPERATING PRINCIPLES A typical resistive Touch Panel comprises two conductive sheets, connected via a switch matrix to the Touch Panel supply voltage. When the Touch Panel is touched (usually with a pen-style pointer), an electrical contact is made between the two sheets. The switch matrix is used to determine the position of the pen contact by establishing a potential divider on one of the conductive sheets in either the X-axis or Y-axis, and measuring the voltage on the other sheet. Separate configuration is required for each axis measurement; these are configured one after the other to determine the X and Y co-ordinate positions. Note that, due to the ratiometric measurement method, the accuracy of the supply voltage does not affect the measurement accuracy in either axis. Pen Down detection and Z-axis (pressure) measurements are achieved in a similar fashion, by configuring the switch matrix and taking the appropriate voltage measurement via an ADC. Note that Z-axis measurement is only supported in 4-wire configuration. The standard operating principles of 4-wire and 5-wire Touch Panels are each described in the following pages. 19.6.1 4-WIRE TOUCH PANEL OPERATION In 4-wire operation, the Touch Panel interface connects to the Left / Right sides of one sheet and to the Top / Bottom sides of the other sheet. The illustrations show the top sheet for X-axis and the bottom sheet for Y-axis, but the reverse is also possible. X-axis measurement is performed by applying a potential difference between the Left and Right sides of the touch panel. When contact is made between the two sheets, the voltage present on the Top or Bottom connections is a measure of the X-axis position of the contact. The configuration is illustrated in Figure 28. w PP, December 2009, Rev 3.0 131 WM8312 Y+ (GPIO14) Pre-Production WM8312 X+ (GPIO13) TPVDD Y- (GPIO16) X- (GPIO15) AUX ADC X position TPGND Figure 28 X-axis Measurement on 4-wire Touch Panel Y-axis measurement is performed by applying a potential difference between the Top and Bottom sides of the touch panel. When contact is made between the two sheets, the voltage present on the Left or Right connections is a measure of the Y-axis position of the contact. The configuration is illustrated in Figure 29. WM8312 TPVDD Y+ (GPIO14) X+ (GPIO13) AUX ADC Y- (GPIO16) X (GPIO15) - Y position TPGND Figure 29 Y-axis Measurement on 4-wire Touch Panel `Pen Down' detection uses a zero-power comparator with an internal, programmable pull-up resistor. When the touch panel is not being touched, no current flows between the touch panel sheets, and the comparator output is low. When the touch panel is touched, current flows through the panel and through the pull-up resistor, and the comparator output goes high. The sensitivity of the circuit can be adjusted using different values of pull-up resistor; a large pull-up resistance leads to the most sensitive response. The configuration is illustrated in Figure 30. WM8312 AVDD Y+ (GPIO14) X+ (GPIO13) RPU PEN_DOWN zero power comparator Y- (GPIO16) X (GPIO15) - TPGND Figure 30 Pen-Down Detection on 4-wire Touch Panel w PP, December 2009, Rev 3.0 132 Pre-Production WM8312 Touch pressure can only be determined indirectly, using the results of two separate measurements. A constant current is applied through the plates, and the voltage on each plate is measured. The difference between the two voltages is proportional to the resistance between the plates, which is a measure of the pressure being applied to the panel. The configuration is illustrated in Figure 31. In this example, a constant current flows from the Top + + (Y ) connection to the Left (X ) connection. The Right (X ) and Bottom (Y ) points are measured in turn, and the difference, VX - VY is equal to IP x RC, where IP is the current applied and RC is the resistance between the plates. The smaller the measured resistance, the greater the pressure being applied. WM8312 TPVDD Y+ (GPIO14) X+ (GPIO13) AUX ADC Y (GPIO16) X- (GPIO15) - Pressure TPGND Figure 31 Z-axis (Pressure) Measurement on 4-wire Touch Panel 19.6.2 5-WIRE TOUCH PANEL OPERATION In 5-wire operation, the Touch Panel interface connects to the four separate corners of one sheet and to a single point on the other sheet. The illustrations show the top sheet for wiper contact and the bottom sheet for corner contacts, but the reverse is also possible. The principles of operation are the same for 5-wire and 4-wire modes, but different configuration of the switching matrix within the Touch Panel controller is required in order to implement the equivalent functionality. X-axis measurement is performed by applying a potential difference between the Left and Right sides of the touch panel. This requires the two Left corners to be connected to one potential and the two Right corners connected to another. When contact is made between the two sheets, the voltage present on the Wiper connection is a measure of the X-axis position of the contact. The configuration is illustrated in Figure 32. Figure 32 X-axis Measurement on 5-wire Touch Panel Y-axis measurement is performed by applying a potential difference between the Top and Bottom sides of the touch panel. This requires the two Top corners to be connected to one potential and the two Bottom corners connected to another. When contact is made between the two sheets, the voltage present on the Wiper connection is a measure of the Y-axis position of the contact. The configuration is illustrated in Figure 33. w PP, December 2009, Rev 3.0 133 WM8312 Pre-Production Figure 33 Y-axis Measurement on 5-wire Touch Panel `Pen Down' detection uses a zero-power comparator with an internal, programmable pull-up resistor. When the touch panel is not being touched, no current flows between the touch panel sheets, and the comparator output is low. When the touch panel is touched, current flows through the panel and through the pull-up resistor, and the comparator output goes high. The sensitivity of the circuit can be adjusted using different values of pull-up resistor; a large pull-up resistance leads to the most sensitive response. The configuration is illustrated in Figure 34. Figure 34 Pen-Down Detection on 5-wire Touch Panel Note that Z-axis (pressure) measurement is not supported on the 5-wire Touch Panel. w PP, December 2009, Rev 3.0 134 Pre-Production WM8312 20 REAL-TIME CLOCK (RTC) 20.1 GENERAL DESCRIPTION The WM8312 provides a Real Time Clock (RTC) in the form of a 32-bit counter. The RTC uses the 32.768kHz crystal oscillator as its clock source and increments the register value once per second. (Note that a direct CMOS input may be used in place of the crystal oscillator; both options are described in Section 13.) To compensate for errors in the clock frequency, the RTC includes a frequency trim capability. The RTC is enabled at all times, including when the WM8312 is in the BACKUP state. When required, the RTC can be maintained via a backup battery in the absence of any other power supply. In the absence of a backup battery, the RTC contents can be held (unclocked) for a limited period of up to 5 minutes via a 22F capacitor. The RTC incorporates an Alarm function. The Alarm time is held in a 32-bit register. When the RTC counter matches the Alarm time, a selectable response will be actioned. For digital rights management purposes, the RTC includes security features designed to detect unauthorised modifications to the RTC counter. 20.2 RTC CONTROL The 32-bit RTC counter value, RTC_TIME is held in two 16-bit registers, R16417 (4021h) and R16418 (4022h). The value of RTC_TIME is incremented by the WM8312 once per second. On initial power-up (from the NO POWER state), these registers will be initialised to default values. Once either of these registers has been written to, the RTC_VALID bit is set to indicate that the RTC_TIME registers contain valid data. When RTC registers are updated, the RTC_SYNC_BUSY bit indicates that the RTC is busy. The RTC registers should not be written to when RTC_SYNC_BUSY = 1. The RTC_WR_CNT field is provided as a security feature for the RTC. After initialisation, this field is updated on every write to R16417 (4021h) or to R16418 (4022h). This enables the host processor to detect unauthorised modifications to the RTC counter value. See Section 20.4 for more details. For additional security, the WM8312 does not allow the RTC to be updated more than 8 times in a one-hour period. Additional write attempts will be ignored. The RTC Alarm time is held in registers R16419 (4023h) and R16420 (4024h). The Alarm function is enabled when RTC_ALM_ENA is set. When the Alarm is enabled, and the RTC counter matches the Alarm time, the RTC Alarm Interrupt is triggered, as described in Section 20.3. If the RTC Alarm occurs in the SLEEP power state, then a WAKE transition request is generated. If the RTC Alarm occurs in the OFF power state, then an ON transition request is generated. See Section 11.3 for details. When updating the RTC Alarm time, it is recommended to disable the Alarm first, by setting RTC_ALM_ENA = 0. The RTC Alarm registers should not be written to when RTC_SYNC_BUSY = 1. The RTC has a frequency trim feature to allow compensation for known and constant errors in the crystal oscillator frequency up to 8Hz. The RTC_TRIM field is a 10-bit fixed point 2's complement number. MSB scaling = -8Hz. To compensate for errors in the clock frequency, this register should be set to the error (in Hz) with respect to the ideal (32768Hz) of the input crystal frequency. For example, if the actual crystal frequency = 32769.00Hz, then the frequency error = +1Hz. The value of RTC_TRIM in this case is 0001_000000. For example, if the actual crystal frequency = 32763.78Hz, then the frequency error = -4.218750Hz. The value of RTC_TRIM in this case is 1011_110010. Note that the RTC_TRIM control register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. w PP, December 2009, Rev 3.0 135 WM8312 ADDRESS R16416 (4020h) RTC Write Counter R16417 (4021h) RTC Time 1 R16418 (4022h) RTC Time 2 R16419 (4023h) RTC Alarm 1 R16420 (4024h) RTC Alarm 2 R16421 (4025h) RTC Control BIT 15:0 LABEL RTC_WR_CNT DEFAULT 0000h Pre-Production DESCRIPTION RTC Write Counter. This random number is updated on every write to the RTC_TIME registers. RTC Seconds counter (MSW) RTC_TIME increments by 1 every second. This is the 16 MSBs. RTC Seconds counter (LSW) RTC_TIME increments by 1 every second. This is the 16 LSBs. RTC Alarm time (MSW) 16 MSBs of RTC_ALM RTC Alarm time (LSW) 16 LSBs of RTC_ALM RTC Valid status 0 = RTC_TIME has not been set since Power On Reset 1 = RTC_TIME has been written to since Power On Reset RTC Busy status 0 = Normal 1 = Busy The RTC registers should not be written to when RTC_SYNC_BUSY = 1. RTC Alarm Enable 0 = Disabled 1 = Enabled RTC frequency trim. Value is a 10bit fixed point <4,6> 2's complement number. MSB Scaling = -8Hz. The register indicates the error (in Hz) with respect to the ideal 32768Hz) of the input crystal frequency. Protected by user key 15:0 RTC_TIME [31:16] RTC_TIME [15:0] 0000h 15:0 0000h 15:0 RTC_ALM [31:16] 0000h 15:0 RTC_ALM [15:0] 0000h 15 RTC_VALID 0 14 RTC_SYNC_BUS Y 0 10 RTC_ALM_ENA 0 R16422 (4026h) RTC Trim 9:0 RTC_TRIM 000h Table 75 Real Time Clock (RTC) Control w PP, December 2009, Rev 3.0 136 Pre-Production WM8312 The Real Time Clock (RTC) is associated with two Interrupt event flags. The RTC_PER_EINT interrupt is set each time a periodic timeout occurs. The periodic timeout is configured using the RTC_PINT_FREQ field described in Table 77. The RTC_ALM_EINT interrupt is set when the RTC Alarm is triggered. The RTC Alarm time is configured as described in Section 20.2. Each of these secondary interrupts triggers a primary Real Time Clock Interrupt, RTC_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 76. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 3 LABEL RTC_PER_EINT DESCRIPTION RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 20.3 RTC INTERRUPTS 2 RTC_ALM_EINT R16409 (4019h) Interrupt Status 1 Mask 3 IM_RTC_PER_EINT 2 IM_RTC_ALM_EINT Table 76 Real Time Clock (RTC) Interrupts The frequency of the RTC periodic interrupts is set by the RTC_PINT_FREQ field, as described in Table 77. ADDRESS R16421 (4025h) RTC Control BIT 6:4 LABEL RTC_PINT_FRE Q [2:0] DEFAULT 000 DESCRIPTION RTC Periodic Interrupt timeout period 000 = Disabled 001 = 1s 010 = 2s 011 = 4s 100 = 8s 101 = 16s 110 = 32s 111 = 64s Table 77 Real Time Clock (RTC) Periodic Interrupt Control w PP, December 2009, Rev 3.0 137 WM8312 20.4 DIGITAL RIGHTS MANAGEMENT Pre-Production The Real Time Clock (RTC) maintains a continuous record of the time; this is maintained at all times, including when the WM8312 is powered down and the RTC function is maintained by the backup battery. It is highly desirable to be able to write to the RTC counter in order to configure it for logical translation into hours/minutes and to support calendar functions. However, for digital rights management purposes, it is important that malicious modification of the RTC is either prevented or detected. The security measure implemented on the WM8312 is the RTC Write Counter. This register is initialised to 0000h during Power On Reset, and is updated automatically whenever a Write operation is scheduled on either of the RTC_TIME registers. Note that, when the RTC Write Counter is updated, the new value is generated at random; it is not a sequential counter. It is assumed that legitimate updates to the RTC_TIME are only those initiated by the Application Processor (AP). When the AP makes an update to the RTC_TIME, the AP can also read the new value of the RTC Write Counter, and should store the value in non-volatile memory. If the AP detects a change in value of the RTC Write Counter, and this was not caused by the AP itself writing to the RTC_TIME, this means that an unauthorised write to the RTC_TIME registers has occurred. In order to make it difficult for an unauthorised RTC_TIME update to be masked by simply writing to the RTC Write Counter, the RTC_WR_CNT field is generated at random by the WM8312 whenever the RTC_TIME field is updated. For additional security, the WM8312 does not allow the RTC to be updated more than 8 times in a one-hour period. Additional write attempts will be ignored. The RTC Control registers are described in Table 75. 20.5 BACKUP MODE CLOCKING OPTIONS The BACKUP state is entered when the available power supplies are below the reset threshold of the device. Typically, this means that USB or Wall supplies are not present and that the main battery is either discharged or removed. Most of the device functions and registers are reset in this state. The RTC and oscillator and a `software scratch' memory area can be maintained from a backup power source in the BACKUP state. This can either be a rechargeable battery (coin cell or super/gold-capacitor) on the BACKUPVDD pin or else a standard capacitor on the LDO12VOUT pin. The RTC and oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state. A 22F capacitor connected to LDO12VOUT can maintain the RTC value, unclocked, for up to 5 minutes in BACKUP if the oscillator is disabled. The XTAL_BKUPENA register bit is defined in Section 13.1. For more details on backup power, see Section 17.6. w PP, December 2009, Rev 3.0 138 Pre-Production WM8312 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) 21.1 GENERAL DESCRIPTION The WM8312 has 16 general-purpose input/output (GPIO) pins, GPIO1 - GPIO16. These can be configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can be tri-stated and can also be used to trigger Interrupts. The function of each GPIO pin is selected individually. Different voltage power domains are selectable on a pin by pin basis for GPIOs 1-12. Input de-bounce is automatically implemented on selected GPIO functions. 21.2 GPIO FUNCTIONS The list of GPIO functions supported by the WM8312 is contained in Table 78 (for input functions) and Table 79 (for output functions). The input functions are selected when the respective GPn_DIR register bit is 1. The output functions are selected when the respective GPn_DIR register bit is 0. The selected function for each GPIO pin is selected by writing to the respective GPn_FN register bits. All functions are available on all GPIO pins. The polarity of each input or output GPIO function can be selected using the applicable GPn_POL register bit. The available power domains for each pin are specific to different GPIOs. The de-bounce time for the GPIO input functions is determined by the GPn_FN field. Some of the input functions allow a choice of de-bounce times, as detailed in Table 78. The register controls for configuring the GPIO pins are defined in Section 21.3. GPn_FN 0h 1h 2h ON/OFF Request GPIO INPUT FUNCTION GPIO DESCRIPTION GPIO input. Logic level is read from the GPn_LVL register bits. See Section 21.3. Control input for requesting an ON/OFF state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge requests the OFF state. Control input for requesting a SLEEP/WAKE state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge requests the WAKE transition to the ON state. Control input for requesting a SLEEP state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the SLEEP state and a falling edge has no effect. Control input for requesting an ON state transition. See Section 11.3. Under default polarity (GPn_POL=1), a rising edge requests the ON state and a falling edge has no effect. Control input for resetting the Watchdog Timer. See Section 25. Control input for selecting the DVS output voltage in one or more DC Converters. See Section 15.6. Control input for selecting the DVS output voltage in one or more DC Converters. See Section 15.6. DE-BOUNCE TIME 32s to 64s 4ms to 8ms 32ms 64ms 3h 4h SLEEP/WAKE Request 32s to 64s 32ms to 64ms 5h SLEEP Request 32s to 64s 6h ON Request 32s to 64s 7h 8h Watchdog Reset Hardware DVS control 1 Hardware DVS control 2 32s to 64s None 9h None w PP, December 2009, Rev 3.0 139 WM8312 GPn_FN Ah GPIO INPUT FUNCTION Hardware Enable 1 Hardware Enable 2 Hardware Control input 1 DESCRIPTION Control input for enabling one or more DC Converters and LDO Regulators. See Section 15. Control input for enabling one or more DC Converters and LDO Regulators. See Section 15. Control input for selecting the operating mode and/or output voltage of one or more DC Converters and LDO Regulators. See Section 15. Control input for selecting the operating mode and/or output voltage of one or more DC Converters and LDO Regulators. See Section 15. Control input for selecting the operating mode and/or output voltage of one or more DC Converters and LDO Regulators. See Section 15. Control input for selecting the operating mode and/or output voltage of one or more DC Converters and LDO Regulators. See Section 15. Pre-Production DE-BOUNCE TIME 32s to 64s Bh 32s to 64s Ch 32s to 64s Dh Hardware Control input 2 32s to 64s Eh Hardware Control input 1 32ms to 64ms Fh Hardware Control input 2 32ms to 64ms Table 78 List of GPIO Input Functions Further details of the GPIO input de-bounce time are noted in Section 21.3. GPn_FN 0h 1h 2h 3h 4h GPIO OUTPUT FUNCTION GPIO Oscillator clock ON state SLEEP state Power State Change DESCRIPTION GPIO output. Logic level is set by writing to the GPn_LVL register bits. See Section 21.3. 32.768kHz clock output. See Section 13. Logic output indicating that the WM8312 is in the ON state. See Section 11.5. Logic output indicating that the WM8312 is in the SLEEP state. See Section 11.5. Logic output asserted whenever a Power On Reset, or an ON, OFF, SLEEP or WAKE transition has completed. Under default polarity (GPn_POL=1), the logic level is the same as the PS_INT interrupt status flag. Note that, if any of the associated Secondary interrupts is masked, then the respective event will not affect the Power State Change GPIO output. See Section 11.2 and Section 11.4. Logic output indicating that a PenDown event has occurred. See Section 19. Logic output indicating that a touch panel AUXADC conversion has completed. See Section 19. Logic output indicating that DC-DC1 Buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. Logic output indicating that DC-DC1 Buck converter DVS slew has been completed. This signal is temporarily de-asserted during voltage transitions (including non-DVS transitions). See Section 15.6. PP, December 2009, Rev 3.0 140 6h Touch Panel PenDown detected Touch Panel Conversion Complete DC-DC1 DVS Done 7h 8h 9h DC-DC2 DVS Done w Pre-Production GPn_FN Ah GPIO OUTPUT FUNCTION External Power Enable 1 External Power Enable 2 System Supply Good (SYSVDD Good) Converter Power Good (PWR_GOOD) External Power Clock Auxiliary Reset DESCRIPTION WM8312 Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. Logic output assigned to one of the timeslots in the ON/OFF and SLEEP/WAKE sequences. This can be used for sequenced control of external circuits. See Section 15.3. Logic output from SYSVDD monitoring circuit. This function represents the internal SYSOK signal. See Section 24.4. Status output indicating that all selected DC Converters and LDO Regulators are operating correctly. Only asserted in ON and SLEEP modes. See Section 15.14. 2MHz clock output suitable for clocking external DC-DC Converters. This clock signal is synchronized with the WM8312 DC Converters clocking signal. See Section 13. Logic output indicating a Reset condition. This signal is asserted in the OFF state. The status in SLEEP mode is configurable. See Section 11.7. Note that the default polarity for this function (GPn_POL=1) is "Active High". Setting GPn_POL=0 will select "Active Low" function. Bh Ch Dh Eh Fh Table 79 List of GPIO Output Functions 21.3 CONFIGURING GPIO PINS The GPIO pins are configured using the Resister fields defined in Table 80. The function of each GPIO is selected using the GPn_FN register field. The pin direction field GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of the available GPIO functions. The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective both on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted `Active High' polarity applies. The opposite logic can be selected by setting GPn_POL = 0. The voltage power domain of GPIOs 1-12 is determined by the GPn_PWR_DOM register. Note that the available options vary between different GPIO pins, as described in Table 82. A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits. Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both resistors are available for use when the associated GPIO is an input. When the GPIO pin is configured as an Open Drain output, the internal pull-up resistor may be required if no external pullup resistors are present. The GPIO pins may be enabled or tri-stated using the GPn_ENA register field. When GPn_ENA = 0, the respective pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is disconnected from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when a GPIO pin is tri-stated. GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether the interrupt occurs on a single active edge only, or else on both rising and falling edges. When single edge is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when GPn_POL = 0). w PP, December 2009, Rev 3.0 141 WM8312 ADDRESS R16440 (4038h) to R16455 (4047h) BIT 15 LABEL GPn_DIR DEFAULT 1 GPIOn pin direction 0 = Output 1 = Input Pre-Production DESCRIPTION 14:13 GPn_PULL [1:0] 01 GPIOn Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIOn Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GPn_POL=1) or falling edge triggered (if GPn_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIOn Power Domain See Table 82. GPIOn Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIOn Output pin configuration 0 = CMOS 1 = Open Drain GPIOn Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIOn Pin Function See Table 83. 12 GPn_INT_M ODE 0 11 10 GPn_PWR_ DOM GPn_POL 0 1 9 GPn_OD 0 7 GPn_ENA 0 3:0 GPn_FN [3:0] 0000 Note: n is a number between 1 and 16 that identifies the individual GPIO. Table 80 GPIO Pin Configuration When the GPIO output function is selected (GPn_FN = 0h, GPn_DIR = 0), the state of a GPIO output is controlled by writing to the corresponding GPn_LVL register bit, as defined in Table 81. The logic level of a GPIO input is determined by reading the corresponding GPn_LVL register bit. If GPn_POL is set, then the read value of the GPn_LVL field for a GPIO input is the inverse of the external signal. Note that, when the GPIO input level changes, the logic level of GPn_LVL will only be updated after the maximum de-bounce period, as listed in Table 78. An input pulse that is shorter than the minimum de-bounce period will be filtered by the de-bounce function and will be ignored. If a GPIO is configured as a CMOS output (ie. GPn_OD = 0), then the read value of the GPn_LVL field will indicate the logic level of that output. If GPn_POL is set, then the read value of the GPn_LVL field for a GPIO output is the inverse of the level on the external pad. If a GPIO is configured as an Open Drain output, then the read value of GPn_LVL is only valid when the internal pull-up resistor is enabled on the pin (ie. when GPn_PULL = 10). The read value is also affected by the GPn_POL bit, as described above for the CMOS case. w PP, December 2009, Rev 3.0 142 Pre-Production WM8312 If a GPIO is tri-stated (GPn_ENA = 0), then the read value of the corresponding GPn_LVL field is invalid. ADDRESS R16396 (400Ch) GPIO Level BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LABEL GP16_LVL GP15_LVL GP14_LVL GP13_LVL GP12_LVL GP11_LVL GP10_LVL GP9_LVL GP8_LVL GP7_LVL GP6_LVL GP5_LVL GP4_LVL GP3_LVL GP2_LVL GP1_LVL DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION GPIOn level. When GPn_FN = 0h and GPn_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GPn_POL is 0, the register contains the opposite logic level to the external pin. Table 81 GPIO Level Register The power domain for each GPIO is controlled using the GPn_PWR_DOM registers as described in Table 82. The power domain for GPIO13 - GPIO16 is fixed; these pins are referenced to TPVDD. ADDRESS R16440 (4038h) GPIO1 Control R16441 (4039h) GPIO2 Control R16442 (403Ah) GPIO3 Control R16443 (403Bh) GPIO4 Control R16444 (403Ch) GPIO5 Control R16445 (403Dh) GPIO6 Control R16446 (403Eh) GPIO7 Control R16447 (403Fh) GPIO8 Control R16448 (4040h) GPIO9 Control R16449 (4041h) GPIO10 BIT 11 LABEL GP1_PWR_DO M GP2_PWR_DO M GP3_PWR_DO M GP4_PWR_DO M GP5_PWR_DO M GP6_PWR_DO M GP7_PWR_DO M GP8_PWR_DO M GP9_PWR_DO M GP10_PWR_D OM DEFAULT 0 DESCRIPTION GPIO1 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO2 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO3 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO4 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO5 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO6 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO7 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO8 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO9 Power Domain select 0 = DBVDD 1 = VPMIC (LDO12) GPIO10 Power Domain select 0 = DBVDD PP, December 2009, Rev 3.0 143 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 w WM8312 ADDRESS Control R16450 (4042h) GPIO11 Control R16451 (4043h) GPIO12 Control BIT 11 LABEL GP11_PWR_D OM DEFAULT 0 1 = SYSVDD Pre-Production DESCRIPTION GPIO11 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO12 Power Domain select 0 = DBVDD 1 = SYSVDD 11 GP12_PWR_D OM 0 Table 82 GPIO Power Domain Registers The function of each GPIO is controlled using the GPn_FN registers defined in Table 83. Note that the selected function also depends on the associated GPn_DIR field described in Table 80. See also Section 21.2 for additional details of each GPIO function, including the applicable debounce times for GPIO input functions. The Touch Panel controller must be disabled if using GPIO13 to GPIO16 as GPIO functions. Note that, when the Touch Panel controller is enabled, GPIO13 to GPIO16 must be tri-stated using the GPn_ENA register bits (see Table 80). ADDRESS R16440 (4038h) GPIO1 Control R16441 (4039h) GPIO2 Control R16442 (403Ah) GPIO3 Control R16443 (403Bh) GPIO4 Control R16444 (403Ch) GPIO5 Control R16445 (403Dh) GPIO6 Control R16446 (403Eh) GPIO7 Control R16447 (403Fh) GPIO8 Control R16448 (4040h) GPIO9 Control R16449 (4041h) GPIO10 Control R16450 (4042h) GPIO11 Control R16451 BIT 3:0 LABEL GP1_FN [3:0] DEFAULT 0000 DESCRIPTION Input functions: 0h = GPIO input (long de-bounce) 1h = GPIO input 2h = Power On/Off request 3h = Sleep/Wake request 4h = Sleep/Wake request (long debounce) 5h = Sleep request 6h = Power On request 7h = Watchdog Reset input 8h = DVS1 input 9h = DVS2 input Ah = HW Enable1 input Bh = HW Enable2 input Ch = HW Control1 input Dh = HW Control2 input Eh = HW Control1 input (long debounce) Fh = HW Control2 input (long debounce) Output functions: 0h = GPIO output 1h = 32.768kHz oscillator output 2h = ON state 3h = SLEEP state 4h = Power State Change 5h = Reserved 6h = Touch Panel Pen Down 7h = Touch Panel Conversion complete 8h = DC1 DVS Done 9h = DC2 DVS Done Ah = External Power Enable1 3:0 GP2_FN [3:0] 0000 3:0 GP3_FN [3:0] 0000 3:0 GP4_FN [3:0] 0000 3:0 GP5_FN [3:0] 0000 3:0 GP6_FN [3:0] 0000 3:0 GP7_FN [3:0] 0000 3:0 GP8_FN [3:0] 0000 3:0 GP9_FN [3:0] 0000 3:0 GP10_FN [3:0] 0000 3:0 GP11_FN [3:0] 0000 3:0 GP12_FN [3:0] 0000 PP, December 2009, Rev 3.0 144 w Pre-Production ADDRESS (4043h) GPIO12 Control R16452 (4044h) GPIO13 Control R16453 (4045h) GPIO14 Control R16454 (4046h) GPIO15 Control R16455 (4047h) GPIO16 Control BIT LABEL DEFAULT WM8312 DESCRIPTION Bh = External Power Enable2 Ch = System Supply Good (SYSOK) Dh = Converter Power Good (PWR_GOOD) Eh = External Power Clock (2MHz) Fh = Auxiliary Reset 3:0 GP13_FN [3:0] 0000 3:0 GP14_FN [3:0] 0000 3:0 GP15_FN [3:0] 0000 3:0 GP16_FN [4:0] 0000 Table 83 GPIO Function Select Registers Note that GPIO input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. The associated state transition(s) are scheduled only when a rising or falling edge is detected on the respective GPIO pin. At other times, it is possible that other state transition events may cause a state transition regardless of the state of the GPIO input. See Section 11.3 for details of all the state transition events. 21.4 GPIO INTERRUPTS Each GPIO pin has an associated interrupt flag, GPn_EINT, in Register R16405 (4015h). Each of these secondary interrupts triggers a primary GPIO Interrupt, GP_INT (see Section 23). This can be masked by setting the mask bit(s) as described in Table 84. See Section 28 and Section 29 for a definition of the register bit positions applicable to each GPIO. ADDRESS R16405 (4015h) Interrupt Status 5 R16413 (401Dh) Interrupt Status 5 Mask BIT 15:0 LABEL GPn_EINT DESCRIPTION GPIO interrupt. (Trigger is controlled by GPn_INT_MODE) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 15:0 IM_GPn_EINT Note: n is a number between 1 and 16 that identifies the individual GPIO. Table 84 GPIO Interrupts w PP, December 2009, Rev 3.0 145 WM8312 22 SYSTEM STATUS LED DRIVERS 22.1 GENERAL DESCRIPTION Pre-Production The WM8312 provides two System Status LED Drivers. These are digital outputs intended for driving LEDs directly. The LED outputs can be assigned to indicate OTP Program status, Power State status or Battery Charger status. They can also be commanded directly via register control, in order to provide any other required functionality. 22.2 LED DRIVER CONTROL LED Drivers are configurable in the ON and SLEEP power states only. The functionality of the LED Drivers is controlled by the LEDn_SRC register bits, as described in Table 85. ADDRESS R16460 (404Ch) Status LED1 BIT 15:14 LABEL LED1_SRC [1:0] DEFAULT 11 DESCRIPTION LED1 Source (Selects the LED1 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program LED2 Source (Selects the LED2 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED2 also indicates an OTP Auto Progam Error condition R16461 (404Dh) Status LED2 15:14 LED2_SRC [1:0] 11 Table 85 Status LED Control 22.2.1 OTP PROGAM STATUS The LED drivers indicate the status of the OTP Auto Program function, where the contents of the external DBE memory are automatically programmed into the OTP. See Section 14.6.3 for further details of the OTP Auto Program function. When the OTP Auto Program function is executed, the System Status LED drivers follow the functionality defined in Table 86. LED DRIVER LED1 LED2 DESCRIPTION OTP Auto Program Complete OTP Auto Progam Error DRIVE MODE Constant Constant LED `ON' TIME n/a n/a ON:OFF DUTY CYCLE n/a n/a Table 86 Status LED outputs - OTP Program Status The OTP Program Status LED outputs will continue until a Device Reset. Note that the OTP Program Status is always indicated via the LED outputs, regardless of the LEDn_SRC register fields. w PP, December 2009, Rev 3.0 146 Pre-Production WM8312 22.2.2 POWER STATE STATUS Setting LEDn_SRC = 01 configures the associated LED to indicate Power State status. Under this selection, four different conditions may be indicated, as defined in Table 87. LED DRIVER DESCRIPTION Power Sequence Failure SYSVDD Low LED1 or LED2 ON state SLEEP state DRIVE MODE Pulsed sequence (4 pulses) Continuous pulsed Constant Continuous pulsed LED `ON' TIME 1s 250ms n/a 250ms ON:OFF DUTY CYCLE 1:1 1:3 n/a 1:7 Table 87 Status LED outputs - Power State Status If more than one of the conditions listed occurs simultaneously, then the LED output pattern is controlled by the condition in the highest position within the list above. For example, if the SYSVDD Low condition occurs while in the ON or SLEEP states, then the LED output follows the pattern defined for the SYSVDD Low condition. The SYSVDD Low indication is asserted if SYSVDD is less than the user-selectable threshold SYSLO_THR, as described in Section 24.4. Note that, in the case of Power Sequence Failure, the transition to OFF occurs after the 4 LED pulses have been emitted. 22.2.3 CHARGER STATUS Setting LEDn_SRC = 10 configures the associated LED to indicate Battery Charger status. Under this selection, two different conditions may be indicated, as defined in Table 88. LED DRIVER DESCRIPTION Charger Complete LED1 or LED2 Charger On DRIVE MODE Constant Continuous pulsed LED `ON' TIME n/a 1s ON:OFF DUTY CYCLE n/a 1:2 Table 88 Status LED outputs - Charger Status w PP, December 2009, Rev 3.0 147 WM8312 22.2.4 MANUAL MODE Pre-Production Setting LEDn_SRC = 11 configures the associated LED to operate in Manual Mode, which is configured using additional register fields. In Manual Mode, the LED output can be commanded as Off, On (Constant), Continuous Pulsed or Pulsed Sequence. The selected operation is determined by the LEDn_MODE registers as described in Table 89. In Continuous Pulsed mode and Pulsed Sequence mode, the `On' time and the Duty Cycle can be configured using the LEDn_DUR and LEDn_DUTY_CYC registers respectively. In Pulsed Sequence mode, the number of pulses in the sequence can be selected using the LEDn_SEQ_LEN register. On completion of the commanded number of pulses, the LED remains off until LEDn_MODE or LEDn_SRC is changed to another value. ADDRESS R16460 (404Ch) Status LED1 BIT 9:8 LABEL LED1_MODE [1:0] DEFAULT 00 DESCRIPTION LED1 Mode (Controls LED1 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence LED1 Pulse Sequence Length (when LED1_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses LED1 On time (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms LED1 Duty Cycle (On:Off ratio) (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) LED2 Mode (Controls LED2 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence LED2 Pulse Sequence Length (when LED2_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses LED2 On time PP, December 2009, Rev 3.0 148 5:4 LED1_SEQ_LE N [1:0] 10 3:2 LED1_DUR [1:0] 01 1:0 LED1_DUTY_C YC [1:0] 10 R16461 (404Dh) Status LED2 9:8 LED2_MODE [1:0] 00 5:4 LED2_SEQ_LE N [1:0] 10 3:2 LED2_DUR 01 w Pre-Production ADDRESS BIT LABEL [1:0] DEFAULT WM8312 DESCRIPTION (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 10 LED2 Duty Cycle (On:Off ratio) (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) 1:0 LED2_DUTY_C YC [1:0] Table 89 Status LED Manual Mode Control 22.3 LED DRIVER CONNECTIONS The recommended connection for Status LEDs is illustrated in Figure 35. The LED outputs are referenced to the SYSVDD power domain. A series resistor may be required, depending on the LED characteristics and the SYSVDD voltage. SYSVDD WM8312 LED1 GND Figure 35 LED Connections to LED1 and LED2 w PP, December 2009, Rev 3.0 149 WM8312 23 INTERRUPT CONTROLLER Pre-Production The WM8312 has a comprehensive Interrupt logic capability. The dedicated IRQ pin can be used to alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be individually enabled or masked. Following an interrupt event, the host processor should read the interrupt registers in order to determine what caused the interrupt, and take appropriate action if required. The WM8312 interrupt controller has two levels: Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register bit. Note that reading the register does not clear the secondary interrupt. Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts associated with one particular circuit block). Each of the secondary interrupts can be individually masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register R16400 (4010h) is read-only. The status of the IRQ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually masked or enabled as an input to the IRQ pin output. The IRQ pin output can either be CMOS driven or Open Drain configuration, as determined by the IRQ_OD register bit. When the IRQ pin is Open Drain, it is pulled low when asserted and is open circuit when not asserted. An external pull-up resistor may be required in the Open Drain mode. The IRQ pin output can be masked by setting the IM_IRQ register bit. When the IRQ pin is masked, it is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event. Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of whether the primary interrupt bit is enabled or masked as an input to the IRQ pin output. Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg. the Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any interrupt mask bits. The IRQ pin output is configured using the register bits desribed in Table 90. ADDRESS R16407 (4017h) IRQ Config BIT 1 IRQ_OD LABEL DESCRIPTION IRQ pin configuration 0 = CMOS 1 = Open Drain IRQ pin output mask 0 = Normal 1 = IRQ output is masked 0 IM_IRQ Table 90 IRQ Pin Configuration w PP, December 2009, Rev 3.0 150 Pre-Production The interrupt logic is illustrated in Figure 36. WM8312 Figure 36 Interrupt Logic Following the assertion of the IRQ pin to indicate an Interrupt event, the host processor can determine which primary interrupt caused the event by reading the primary interrupt register R16400 (4010h). This register is defined in Section 23.1. After reading the primary interrupt register, the host processor must read the corresponding secondary interrupt register(s) in order to determine which specific event caused the IRQ pin to be asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit. 23.1 PRIMARY INTERRUPTS The primary interrupts are defined in Table 91. These bits are Read Only. They are set when any of the associated unmasked secondary interrupts is set. They can only be reset when all of the associated secondary resets are cleared or masked. Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is masked and does not cause the IRQ pin to be asserted. The primary interrupt bits in R16408 (4018h) are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default. ADDRESS R16400 (4010h) System Interrupts BIT 15 PS_INT LABEL DESCRIPTION Power State primary interrupt 0 = No interrupt 1 = Interrupt is asserted Thermal primary interrupt 0 = No interrupt 1 = Interrupt is asserted GPIO primary interrupt 0 = No interrupt 1 = Interrupt is asserted ON Pin primary interrupt 0 = No interrupt 1 = Interrupt is asserted Watchdog primary interrupt 0 = No interrupt 1 = Interrupt is asserted Touch Panel Data primary interrupt 0 = No interrupt 1 = Interrupt is asserted Touch Panel Pen Down primary interrupt 0 = No interrupt PP, December 2009, Rev 3.0 151 14 TEMP_INT 13 GP_INT 12 ON_PIN_INT 11 WDOG_INT 10 TCHDATA_INT 9 TCHPD_INT w WM8312 ADDRESS BIT 8 LABEL AUXADC_INT 1 = Interrupt is asserted Pre-Production DESCRIPTION AUXADC primary interrupt 0 = No interrupt 1 = Interrupt is asserted Power Path Management primary interrupt 0 = No interrupt 1 = Interrupt is asserted Current Sink primary interrupt 0 = No interrupt 1 = Interrupt is asserted Real Time Clock primary interrupt 0 = No interrupt 1 = Interrupt is asserted OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted Battery Charger primary interrupt 0 = No interrupt 1 = Interrupt is asserted High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) PP, December 2009, Rev 3.0 152 7 PPM_INT 6 CS_INT 5 RTC_INT 4 OTP_INT 2 CHG_INT 1 HC_INT 0 UV_INT R16408 (4018h) System Interrupts Mask 15 IM_PS_INT 14 IM_TEMP_INT 13 IM_GP_INT 12 IM_ON_PIN_INT 11 IM_WDOG_INT 10 IM_TCHDATA_INT 9 IM_TCHPD_INT w Pre-Production ADDRESS BIT 8 LABEL IM_AUXADC_INT WM8312 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 7 IM_PPM_INT 6 IM_CS_INT 5 IM_RTC_INT 4 IM_OTP_INT 2 IM_CHG_INT 1 IM_HC_INT 0 IM_UV_INT Table 91 Primary Interrupt Status and Mask Bits 23.2 SECONDARY INTERRUPTS The following sections define the secondary interrupt status and control bits associated with each of the primary interrupt bits defined in Table 91. 23.2.1 POWER STATE INTERRUPT The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The secondary interrupt bits are defined in Table 92. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. w PP, December 2009, Rev 3.0 153 WM8312 ADDRESS R16402 (4012h) Interrupt Status 2 BIT 2 LABEL PS_POR_EINT Pre-Production DESCRIPTION Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a `1' is written. ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 PS_SLEEP_OFF_EINT 0 PS_ON_WAKE_EINT R16410 (401Ah) Interrupt Status 2 Mask 2 IM_PS_POR_EINT 1 IM_PS_SLEEP_OFF_EINT 0 IM_PS_ON_WAKE_EINT Table 92 Power State Interrupts 23.2.2 THERMAL INTERRUPTS The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26. The secondary interrupt bit is defined in Table 93. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 R16410 (4019h) Interrupt Status 1 Mask BIT 1 LABEL TEMP_THW_CINT DESCRIPTION Thermal Warning interrupt (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_TEMP_THW_CINT Table 93 Thermal Interrupts 23.2.3 GPIO INTERRUPTS The primary GP_INT interrupt comprises sixteen secondary interrupts as described in Section 21.4. The secondary interrupt bits are defined in Table 94. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405 (4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. w PP, December 2009, Rev 3.0 154 Pre-Production ADDRESS R16405 (4015h) Interrupt Status 5 R16413 (401Dh) Interrupt Status 5 Mask BIT 15:0 LABEL GPn_EINT DESCRIPTION WM8312 GPIO interrupt. (Trigger is controlled by GPn_INT_MODE) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 15:0 IM_GPn_EINT Note: n is a number between 1 and 16 that identifies the individual GPIO. Table 94 GPIO Interrupts 23.2.4 ON PIN INTERRUPTS The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in Section 11.6. The secondary interrupt bit is defined in Table 95. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 12 LABEL ON_PIN_CINT DESCRIPTION ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 12 IM_ON_PIN_CINT Table 95 ON Pin Interrupt 23.2.5 WATCHDOG INTERRUPTS The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25. The secondary interrupt bits are defined in Table 96. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 11 LABEL WDOG_TO_EINT DESCRIPTION Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 11 IM_WDOG_TO_EINT Table 96 Watchdog Timer Interrupts w PP, December 2009, Rev 3.0 155 WM8312 23.2.6 TOUCH PANEL DATA INTERRUPTS Pre-Production The primary TCHDATA_INT interrupt comprises a single secondary interrupt as described in Section 19.5. The secondary interrupt bits are defined in Table 97. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a TCHDATA_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 10 LABEL TCHDATA_EINT DESCRIPTION Touch panel Data interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 10 IM_TCHDATA_EINT Table 97 Touch Panel Data Interrupts 23.2.7 TOUCH PANEL PEN DOWN INTERRUPTS The primary TCHPD_INT interrupt comprises a single secondary interrupt as described in Section 19.5. The secondary interrupt bits are defined in Table 98. The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event is masked and does not trigger a TCHPD_INT interrupt. The secondary interrupt bit in R16401 (4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 9 LABEL TCHPD_EINT DESCRIPTION Touch panel Pen Down interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 9 IM_TCHPD_EINT Table 98 Touch Panel Pen Down Interrupts 23.2.8 AUXADC INTERRUPTS The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5. The secondary interrupt bits are defined in Table 99. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 8 LABEL AUXADC_DATA_EINT DESCRIPTION AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. AUXADC Digital Comparator n interrupt (Trigger is controlled by DCMPn_GT) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. PP, December 2009, Rev 3.0 156 7:4 AUXADC_DCOMPn_EINT R16409 (4019h) 8 IM_AUXADC_DATA_EINT w Pre-Production ADDRESS Interrupt Status 1 Mask 7:4 IM_AUXADC_DCOMPn_EI NT BIT LABEL WM8312 DESCRIPTION 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Note: n is a number between 1 and 4 that identifies the individual Comparator. Table 99 AUXADC Interrupts 23.2.9 POWER PATH MANAGEMENT INTERRUPTS The primary PPM_INT interrupt comprises three secondary interrupts as described in Section 17.5. The secondary interrupt bits are defined in Table 100. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bits in R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 15 LABEL PPM_SYSLO_EINT DESCRIPTION Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path Source interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path USB Current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 14 PPM_PWR_SRC_EINT 13 PPM_USB_CURR_EINT R16409 (4019h) Interrupt Status 1 Mask 15 IM_PPM_SYSLO_EINT 14 IM_PPM_PWR_SRC_EINT 13 IM_PPM_USB_CURR_EIN T Table 100 Power Path Management Interrupts 23.2.10 CURRENT SINK INTERRUPTS The primary CS_INT interrupt comprises two secondary interrupts as described in Section 16.3. The secondary interrupt bits are defined in Table 101. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a CS_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. w PP, December 2009, Rev 3.0 157 WM8312 ADDRESS R16402 (4012h) Interrupt Status 2 BIT 7 LABEL CS2_EINT Pre-Production DESCRIPTION Current Sink 2 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Current Sink 1 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 6 CS1_EINT R16410 (401Ah) Interrupt Status 2 Mask 7 IM_CS2_EINT 6 IM_CS1_EINT Table 101 Current Sink Interrupts 23.2.11 REAL TIME CLOCK INTERRUPTS The primary RTC_INT interrupt comprises two secondary interrupts as described in Section 20.3. The secondary interrupt bits are defined in Table 102. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16401 (4011h) Interrupt Status 1 BIT 3 LABEL RTC_PER_EINT DESCRIPTION RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 2 RTC_ALM_EINT R16409 (4019h) Interrupt Status 1 Mask 3 IM_RTC_PER_EINT 2 IM_RTC_ALM_EINT Table 102 Real Time Clock (RTC) Interrupts 23.2.12 OTP MEMORY INTERRUPTS The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The secondary interrupt bits are defined in Table 103. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. w PP, December 2009, Rev 3.0 158 Pre-Production ADDRESS R16402 (4012h) Interrupt Status 2 BIT 5 LABEL OTP_CMD_END_EINT DESCRIPTION WM8312 OTP / DBE Command End interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. OTP /DBE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 4 OTP_ERR_EINT R16410 (401Ah) Interrupt Status 2 Mask 5 IM_OTP_CMD_END_EINT 4 IM_OTP_ERR_EINT Table 103 OTP Memory Interrupts 23.2.13 RESERVED 23.2.14 BATTERY CHARGER INTERRUPTS The primary CHG_INT interrupt comprises six secondary interrupts as described in Section 17.7.8. The secondary interrupt bits are defined in Table 104. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a CHG_INT interrupt. The secondary interrupt bits in R16402 (4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16402 (4012h) Interrupt Status 2 BIT 15 LABEL CHG_BATT_HOT_EINT DESCRIPTION Battery Hot interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Cold interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Overvoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge End interrupt (End of Charge Current threshold reached) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Timeout interrupt (Charger Timer has expired) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Mode interrupt (Charger Mode has changed) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Start interrupt (Charging has started) (Rising Edge triggered) PP, December 2009, Rev 3.0 159 14 CHG_BATT_COLD_EINT 13 CHG_BATT_FAIL_EINT 12 CHG_OV_EINT 11 CHG_END_EINT 10 CHG_TO_EINT 9 CHG_MODE_EINT 8 CHG_START_EINT w WM8312 ADDRESS R16410 (401Ah) Interrupt Status 2 Mask BIT 15 LABEL IM_CHG_BATT_HOT_EINT Pre-Production DESCRIPTION Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 14 IM_CHG_BATT_COLD_EIN T 13 IM_CHG_BATT_FAIL_EINT 12 IM_CHG_OV_EINT 11 IM_CHG_END_EINT 10 IM_CHG_TO_EINT 9 IM_CHG_MODE_EINT 8 IM_CHG_START_EINT Table 104 Battery Charger Interrupts 23.2.15 HIGH CURRENT INTERRUPTS The primary HC_INT interrupt comprises two secondary interrupts as described in Section 15.13. The secondary interrupt bits are defined in Table 105. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a HC_INT interrupt. The secondary interrupt bits in R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. w PP, December 2009, Rev 3.0 160 Pre-Production ADDRESS R16404 (4014h) Interrupt Status 4 BIT 9 LABEL HC_DC2_EINT WM8312 DESCRIPTION DC-DC2 High Current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC1 High Current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 8 HC_DC1_EINT R16412 (401Ch) Interrupt Status 4 Mask 9 IM_HC_DC2_EINT 8 IM_HC_DC1_EINT Table 105 Overcurrent Interrupts 23.2.16 UNDERVOLTAGE INTERRUPTS The primary UV_INT interrupt comprises fourteen secondary interrupts as described in Section 15.13). The secondary interrupt bits are defined in Table 106. Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403 (4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked by default. ADDRESS R16403 (4013h) Interrupt Status 3 R16404 (4014h) Interrupt Status 4 R16411 (401Bh) Interrupt Status 3 Mask R16412 (401Ch) Interrupt Status 4 Mask BIT 9:0 LABEL UV_LDOn_EINT DESCRIPTION LDOn Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DCm Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 3:0 UV_DCm_EINT 9:0 IM_UV_LDOn_EINT 3:0 IM_UV_DCm_EINT Notes: 1. n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1-LDO10). 2. m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC1-DC4). Table 106 Undervoltage Interrupts w PP, December 2009, Rev 3.0 161 WM8312 24 RESETS AND SUPPLY VOLTAGE MONITORING 24.1 RESETS Pre-Production The WM8312 provides hardware and software monitoring functions as inputs to a Reset management system. These functions enable the device to take appropriate action when power supplies are critically low or if a hardware or software fault condition is detected. There are different levels of Resets, providing different response mechanisms according to the condition that caused the Reset event. Where applicable, the WM8312 will automatically return to the ON state and resume normal operation as quickly as possible following a Reset. A System Reset occurs in the event of a Power Sequence Failure, Device overtemperature, SYSVDD undervoltage, Software `OFF' request or VPMIC (LDO12) undervoltage condition. Under these conditions, the WM8312 asserts the RESET pin and transitions to the OFF state. The contents of the Register map are not reset under these conditions. If the System Reset was caused by a Converter Undervoltage condition, then the WM8312 will automatically return to the ON state after performing the System Reset. A Device Reset occurs in the event of a Watchdog Timeout, Hardware Reset request or Converter (LDO or DC-DC) Undervoltage condition. Under these conditions, the WM8312 asserts the RESET pin and transitions to the OFF state. In the case of VPMIC undervoltage, the WM8312 enters the BACKUP state. The contents of the Register map are cleared to default values, except for the RTC and software scratch registers, which are maintained. If the Device Reset was caused by a Watchdog timeout or Hardware Reset request, then the WM8312 will automatically return to the ON state after performing the Device Reset. A Software Reset occurs when any value is written to Register 0000h, as described in Section 12.5. In this event, the WM8312 asserts the RESET pin and transitions to the OFF state. The Register map contents may or may not be affected, depending on the value of the SW_RESET_CFG field. See Section 24.3 for further details of Software Reset configuration. The WM8312 will automatically return to the ON state after performing the Software Reset. A Power-On Reset occurs when the supply voltage is less than the Power-On Reset threshold, as described in Section 24.4. In this event, the WM8312 is forced into the NO POWER state, as described in Section 11.2. All the contents of the Register map are lost in the NO POWER state. w PP, December 2009, Rev 3.0 162 Pre-Production A summary of the WM8312 Resets is contained in Table 107. RESET TYPE System Reset RESET CONDITION Power Sequence Failure DESCRIPTION DC Converters, LDOs or CLKOUT circuits (including FLL) have failed to start up within the permitted time. See Section 11.3. An overtemperature condition has been detected. See Section 26. SYSVDD is less than the userselectable threshold SYSLO_THR and SYSLO_ERR_ACT is configured to select OFF in this condition. See Section 24.4. SYSVDD is less than the SHUTDOWN voltage. See Section 24.4. OFF has been commanded by writing CHIP_ON = 0. See Section 11.3 The WM8312 supply voltage is less than the System Reset threshold. See Section 24.4. Watchdog timer has expired and the selected response is to generate a Device Reset. See Section 25. The RESET pin has been pulled low by an external source. See Section 24.2. An undervoltage condition has been detected and the selected response is "Shut down system (Device Reset)" See Section 15. Software Reset has been commanded by writing to Register 0000h. See Section 12.5. Assert RESET pin. Shutdown and restart the WM8312. See Section 24.3 for configurable options regarding the Register Map contents. The WM8312 is in the NO POWER state. All register contents are lost. Assert RESET pin. Shutdown and restart the WM8312. Reset Register map (Note the RTC and software scratch registers are not reset.) RESPONSE Assert RESET pin. Select OFF state. If the Reset Condition is VPMIC (LDO12) undervoltage, then the WM8312 enters the BACKUP state. WM8312 AUTOMATIC RECOVERY No Device overtemperature SYSVDD undervoltage (1) No No SYSVDD undervoltage (2) Software OFF request No No VPMIC (LDO12) undervoltage Device Reset Watchdog timeout No Yes Hardware Reset Yes Converter (LDO or DCDC) Undervoltage Yes Software Reset Software Reset Yes Power On Reset Power On Reset The WM8312 supply voltage is less than the Power-On Reset (POR) threshold. See Section 24.4. No Table 107 Resets Summary In the cases where Automatic Recovery is supported (as noted in Table 107), the WM8312 will restart the WM8312 following the Reset, and return the device to the ON state. The particular Reset condition which caused the return to the ON state will be indicated in the "ON Source" register - see Section 11.3. Note that, if a Watchdog timeout or Converter undervoltage fault persists, causing recurring Device Resets, then a maximum of 7 attempts will be made to initiate the start-up sequence. After 7 attempts, the WM8312 will remain in the OFF state until the next valid ON state transition event occurs. The WM8312 asserts the RESET low as soon as the device begins the shutdown sequence. RESET is held low for the duration of the shutdown sequence and is held low in the OFF state. In the cases where Automatic Recovery is supported, RESET is automatically cleared (high) after successful completion of the startup sequence. The duration of the RESET low period after the w PP, December 2009, Rev 3.0 163 WM8312 Pre-Production startup sequence has completed is governed by the RST_DUR register field described in Section 11.7. 24.2 HARDWARE RESET A Hardware Reset is triggered when an external source pulls the RESET pin low. Under this condition, the WM8312 transitions to the OFF state. The contents of the Register map are cleared to default values, except for the RTC and software scratch registers, which are maintained. The WM8312 will then automatically schedule an ON state transition to resume normal operation. If the external source continues to pull the RESET pin low, then the WM8312 cannot fully complete the ON state transition following the Hardware Reset. In this case, the WM8312 will mask the external reset for up to 32 seconds. If the RESET pin is released (ie. it returns to logic `1') during this time, then the ON state transition is completed and the Hardware Reset input is valid again from this point. If the RESET pin is not released, then the WM8312 will force an OFF condition on expiry of the 32 seconds timeout. Recovery from this forced OFF condition cannot occur until the external reset condition is de-asserted, followed by a valid ON event. If an ON event occurs before the external reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a return to the OFF state. It is possible to mask the RESET pin input in the SLEEP state by setting the RST_SLP_MSK register bit as described in Section 11.7. 24.3 SOFTWARE RESET A Software Reset is triggered by writing to Register 0000h, as described in Section 12.5. In this event, the WM8312 asserts the RESET pin and transitions to the OFF state. If the Reset occurred in the ON state, then the WM8312 will automatically return to the ON state following the Reset. The SWRST_DLY register field determines whether a time delay is applied between the Software Reset command and the resultant shutdown and start-up sequences. When the SWRST_DLY bit is set, the programmable time delay PWRSTATE_DLY is applied before commencing the shutdown sequence. The timing of the Software Reset is illustrated in Figure 37. See Section 11.3 for a definition of the PWRSTATE_DLY register. The SW_RESET_CFG register field determines if the Register Map is reset under a Software Reset condition. Note that the SW_RESET_CFG control register is locked by the WM8312 User Key. This register can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16387 (4003h) Power State BIT 9 LABEL SWRST_DLY DEFAULT 0 DESCRIPTION Software Reset Delay 0 = No delay 1 = Software Reset is delayed by PWRSTATE_DLY following the Software Reset command Software Reset Configuration. Selects whether the register map is reset to default values when Software Reset occurs. 0 = All registers except RTC and Software Scratch registers are reset by Software Reset 1 = Register Map is not affected by Software Reset Protected by user key R16390 (4006h) Reset Control 10 SW_RESET_C FG 1 Table 108 Software Reset Configuration w PP, December 2009, Rev 3.0 164 Pre-Production The timing details of the Software Reset are illustrated in Figure 37. WM8312 Power State ON Software Reset (shutdown / start-up) ON RESET pin Time Time delay set by SWRST_DLY and PWRSTATE_DELAY 0ms, 1ms or 10ms OFF transition then ON transition Nominal duration = 10 x 2ms RESET delay set by RST_DUR 1ms, 10ms, 50ms or 100ms Figure 37 Software Reset Timing w PP, December 2009, Rev 3.0 165 WM8312 24.4 SUPPLY VOLTAGE MONITORING Pre-Production The WM8312 includes a number of mechanisms to prevent the system from starting up, or to force it to shut down, when the power sources are critically low. The power supply configuration for the WM8312 is described in Section 17. The chip automatically chooses the most suitable supply, selecting between a Wall adapter supply, USB or Battery. The preferred source is routed to the SYSVDD pin, to which the other power management circuits would typically be connected. The SYSVDD voltage is monitored internally, as described below. The internal regulator LDO12 is powered from an internal domain equivalent to SYSVDD and generates an internal supply (VPMIC) to support various "always-on" functions. In the absence of the Wall, USB or Battery supplies, LDO12 can be powered from a backup battery. (Note that SYSVDD is not maintained by the backup battery.) The VPMIC monitoring function controls the Power-On Reset circuit, which sets the threshold below which the WM8312 cannot operate. The operation of the VPMIC monitoring circuit is illustrated in Figure 38. The internal signal PORRST is governed by the VPOR thresholds. These determine when the WM8312 is kept in the NO POWER state. The internal signal PMICRST is governed by the VRES thresholds. These determine when the WM8312 is kept in the BACKUP state. The VPMIC monitoring thresholds illustrated in Figure 38 are fixed. The voltage levels are defined in the Electrical Characteristics - see Section 7.5. VVPMIC VRES, DE-ASSERT VRES, ASSERT VPOR, DE-ASSERT VPOR, ASSERT time PORRST time PMICRST Operating State time Figure 38 VPMIC Monitoring The operation of the SYSVDD monitoring circuit is illustrated in Figure 39. The VSHUTDOWN threshold is the voltage below which the WM8312 forces an OFF transition. This threshold voltage is fixed and is defined in the Electrical Characteristics - see Section 7.5. The VSYSOK threshold is the level at which the internal signal SYSOK is asserted. Any ON request will be inhibited if SYSOK is not set. The VSYSOK threshold can be set using the SYSOK_THR register field in accordance with the minimum voltage requirements of the application. The VSYSLO threshold is the level at which the internal signal SYSLO is asserted. This indicates a SYSVDD undervoltage condition, at which a selectable response can be initiated. The VSYSLO threshold can be set using the SYSLO_THR register field. The action taken under this undervoltage condition is selected using the SYSLO_ERR_ACT register field, as defined in Table 109. An Interrupt event is associated with the SYSLO condition - see Section 17.5. w PP, December 2009, Rev 3.0 166 Pre-Production WM8312 The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when SYSVDD is below the SYSLO threshold. The WM8312 can also indicate the status of the SYSOK signal via a GPIO pin configured as a "SYSVDD Good" output (see Section 21). A GPIO pin configured as "SYSVDD Good" output will be asserted when the SYSVDD is above the SYSOK threshold. Figure 39 SYSVDD Monitoring ADDRESS R16385 (4001h) SYSVDD Control BIT 15:14 LABEL SYSLO_ERR_ ACT DEFAULT 00 DESCRIPTION SYSLO Error Action Selects the action taken when SYSLO is asserted 00 = Interrupt 01 = WAKE transition 10 = Reserved 11 = OFF transition SYSLO Status 0 = Normal 1 = SYSVDD is below SYSLO threshold SYSLO threshold (falling SYSVDD) This is the falling SYSVDD voltage at which SYSLO will be asserted 000 = 2.8V 001 = 2.9V ... 111 = 3.5V SYSOK threshold (rising SYSVDD) This is the rising SYSVDD voltage at which SYSLO will be de-asserted 000 = 2.8V 001 = 2.9V ... 111 = 3.5V 11 SYSLO_STS 0 6:4 SYSLO_THR [2:0] 010 2:0 SYSOK_THR [2:0] 101 Table 109 SYSVDD Monitoring Control w PP, December 2009, Rev 3.0 167 WM8312 25 WATCHDOG TIMER Pre-Production The WM8312 includes a Watchdog Timer designed to detect a possible software fault condition where the host processor has locked up. The Watchdog Timer is a free-running counter driven by the internal RC oscillator. The Watchdog Timer is enabled by default; it can be enabled or disabled by writing to the WDOG_ENA register bit. The Watchdog behaviour in SLEEP is configurable; it can either be set to continue as normal or to be disabled. The Watchdog behaviour in SLEEP is determined by the WDOG_SLPENA bit. The watchdog timer duration is set using WDOG_TO. The watchdog timer can be halted for debug purposes using the WDOG_DEBUG bit. The Watchdog reset source is selectable between Software and Hardware triggers. (Note that the de-selected reset source has no effect.) If the Watchdog is not reset within a programmable timeout period, this is interpreted by the WM8312 as a fault condition. The Watchdog Timer then either triggers a Device Reset, or issues a WAKE request or raises an Interrupt. The action taken is determined by the WDOG_PRIMACT register field. If the Watchdog is not reset within a further timeout period of the Watchdog counter, a secondary action is triggered. The secondary action taken at this point is determined by the WDOG_SECACT register field. The Watchdog reset source is selected using the WDOG_RST_SRC register bit. When Software WDOG reset source is selected, the Watchdog is reset by writing a `1' to the WDOG_RESET field. When Hardware WDOG reset source is selected, the Watchdog is reset by toggling a GPIO pin that has been configured as a Watchdog Reset Input (see Section 21). If a Device Reset is triggered by the watchdog timeout, the WM8312 asserts the RESET pin, resets the internal control registers (excluding the RTC) and initiates a start-up sequence. Note that, if the watchdog timeout fault persists, then a maximum of 7 attempts will be made to initiate the start-up sequence. See Section 24. Note that the Watchdog control registers are locked by the WM8312 User Key. These registers can only be changed by writing the appropriate code to the Security register, as described in Section 12.4. ADDRESS R16388 (4004h) Watchdog BIT 15 LABEL WDOG_ENA DEFAULT 1 DESCRIPTION Watchdog Timer Enable 0 = Disabled 1 = Enabled (enables the watchdog; does not reset it) Protected by user key Watchdog Pause 0 = Disabled 1 = Enabled (halts the Watchdog timer for system debugging) Protected by user key Watchdog Reset Source 0 = Hardware only 1 = Software only Protected by user key Watchdog SLEEP Enable 0 = Disabled 1 = Controlled by WDOG_ENA Protected by user key Watchdog Software Reset 0 = Normal 1 = Watchdog Reset (resets the watchdog, if WDOG_RST_SRC = 1) Protected by user key Secondary action of Watchdog timeout PP, December 2009, Rev 3.0 168 14 WDOG_DEBU G 0 13 WDOG_RST_ SRC 1 12 WDOG_SLPE NA 0 11 WDOG_RESE T 0 9:8 WDOG_SECA 10 w Pre-Production ADDRESS BIT CT LABEL DEFAULT DESCRIPTION (taken after 2 timeout periods) 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by user key WM8312 5:4 WDOG_PRIMA CT 01 Primary action of Watchdog timeout 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by user key Watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s 110 = 16.384s 111 = 32.768s Protected by user key 2:0 WDOG_TO [2:0] 111 Table 110 Controlling the Watchdog Timer The Watchdog timeout interrupt event is indicated by the WDOG_TO_EINT register field. This secondary interrupt triggers a primary Watchdog Interrupt, WDOG_INT (see Section 23). This can be masked by setting the mask bit as described in Table 111. ADDRESS R16401 (4011h) Interrupt Status 1 R16409 (4019h) Interrupt Status 1 Mask BIT 11 LABEL WDOG_TO_EINT DESCRIPTION Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 11 IM_WDOG_TO_EINT Table 111 Watchdog Timer Interrupts w PP, December 2009, Rev 3.0 169 WM8312 26 TEMPERATURE SENSING Pre-Production The WM8312 provides temperature monitoring as status information and also for self-protection of the device. Temperature monitoring is always enabled in the ON and SLEEP states. The thermal warning temperature can be set using the THW_TEMP register field. The thermal warning hysteresis ensures that the THW_TEMP is not reset until the device temperature has dropped below the threshold by a suitable margin. The extent of the hysteresis can be selected using the THW_HYST register field. The Thermal Warning condition can be read using the THW_STS register bit. An overtemperature condition causes the thermal warning interrupt (TEMP_THW_CINT) to be set. The thermal warning interrupt is also set when the overtemperature condition clears, ie. when the device has returned to its normal operating limits. The thermal shutdown temperature is set at a fixed level. If a thermal shutdown condition is detected whilst in the ON or SLEEP states, then a System Reset is triggered, as described in Section 24.1, forcing a transition to the OFF state. The temperature sensing circuit is configured and monitored using the register fields described in Table 112. ADDRESS R16386 (4002h) BIT 3 LABEL THW_HYST DEFAULT 1 DESCRIPTION Thermal Warning hysteresis 0 = 8 degrees C 1 = 16 degrees C Thermal Warning temperature 00 = 90 degrees C 01 = 100 degress C 10 = 110 degrees C 11 = 120 degrees C Thermal Warning status 0 = Normal 1 = Overtemperature Warning (warning temperature is set by THW_TEMP) 1:0 THW_TEMP [1:0] 10 R16397 (400Dh) 15 THW_STS 0 Table 112 Temperature Sensing Control The thermal warning interrupt event is indicated by the TEMP_THW_CINT register field. This secondary interrupt triggers a primary Thermal Interrupt, TEMP_INT (see Section 23). This can be masked by setting the mask bit as described in Table 113. ADDRESS R16401 (4011h) Interrupt Status 1 R16410 (4019h) Interrupt Status 1 Mask BIT 1 LABEL TEMP_THW_CINT DESCRIPTION Thermal Warning interrupt (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 IM_TEMP_THW_CINT Table 113 Thermal Interrupts w PP, December 2009, Rev 3.0 170 Pre-Production WM8312 27 VOLTAGE AND CURRENT REFERENCES 27.1 VOLTAGE REFERENCE (VREF) The main voltage reference generated by the WM8312 is bonded to the VREFC pin. The accuracy of this reference is optimised by factory-set trim registers. The voltage reference (VREF) requires an external decoupling capacitor; a 100nF X5R capacitor is recommended, as noted in Section 30.2. Omitting this capacitor will result in increased noise on the voltage reference; this will particularly affect the analogue LDOs. The VREFC capacitor should be grounded to the REFGND pin. The voltage reference circuit includes a low-power mode, which enables power consumption to be minimised where appropriate. The low-power reference mode may lead to increased noise on the voltage reference; this mode should only be selected when minimum power consumption is more important than voltage stability. Note that the Low Power Reference mode is not supported when the Touch Panel or Auxiliary ADC functions are enabled. The Low Power Reference mode is enabled when REF_LP register is set. The Low Power Reference mode should only be enabled when the Touch Panel and Auxiliary ADC are both disabled. Enabling the Low Power Reference mode will lead to a malfunction of the Touch Panel or Auxiliary ADC functions. ADDRESS R16387 (4003h) BIT 12 LABEL REF_LP DEFAULT 0 DESCRIPTION Low Power Voltage Reference Control 0 = Normal 1 = Low Power Reference Mode select Note that Low Power Reference Mode is only supported when the Touch Panel and Auxiliary ADC are both disabled. Table 114 Low Power Voltage Reference Control 27.2 CURRENT REFERENCE (IREF) The Power Management circuits of the WM8312 use an integrated current reference. This current reference (IREF) requires the connection of an external resistor to the IREFR pin; a 100k (1%) resistor is recommended, as noted in Section 30.2. The WM8312 will malfunction if this resistor is omitted. The IREFR resistor should be grounded to the REFGND pin. w PP, December 2009, Rev 3.0 171 Block ID CHIP_ID[15:0] 0000_0000_0000_0000 CHILD_REV[7:0] 0000_0000_0000_0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0110_0010_0000_0100 SYSLO_THR[2:0] 0 0 THW_HYST 0 0 0 0 0 AUXRST_SL RST_SLP_M RST_SLPEN PENA SK A 0 0 0 0 0 ON_PIN_PRIMACT[1:0] ON_PIN_ST S 0 0 AUTOINC WDOG_PRIMACT[1:0] 0 USB100MA_STARTUP[1:0 USB_CURR_ ] STS 0 SYSOK_THR[2:0] THW_TEMP[1:0] USB_ILIM[2:0] WDOG_TO[2:0] ON_PIN_TO[1:0] RST_DUR[1:0] 0 0 0000_0000_0010_0101 0000_0000_0000_1010 UU00_1000_0000_0010 1010_P010_0001_0111 0000_0010_0001_0010 1000_0100_0111_0011 0000_0000_0000_0100 0000_0000_0000_0000 0000_0000_0000_0000 OTP_BULK 0 GP6_LVL 0 0 0 0 GP5_LVL 0 0 GP4_LVL 0 0 GP3_LVL OTP_PAGE[1:0] 0 GP2_LVL MAIN_STATE[4:0] 0 GP1_LVL U010_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 PPM_INT OFF_SW_R EQ CS_INT 0 RTC_INT OFF_ON_PI N OTP_INT 0 0 0 CHG_INT 0 HC_INT 0 UV_INT 0000_0000_0000_0000 PPPP_PPPP_PPPP_PPPP PPPP_PPPP_PPPP_PPP0 PPPP_PPPP_PPPP_0PPP 0000_00PP_PPPP_PPPP HC_DC2_EI HC_DC1_EI NT NT 0 GP11_EINT 0 0 0 GP10_EINT 0 0 GP9_EINT 0 0 0 GP8_EINT 0 0 0 GP7_EINT 0 0 0 GP6_EINT 0 0 0 GP5_EINT 0 0 UV_DC4_EI UV_DC3_EI UV_DC2_EI UV_DC1_EI NT NT NT NT GP4_EINT 0 0 GP3_EINT 0 0 GP2_EINT 0 IRQ_OD GP1_EINT 0 IM_IRQ 0000_00PP_0000_PPPP PPPP_PPPP_PPPP_PPPP 0000_0000_0000_0000 0000_0000_0000_0010 0 0 0000_0000_0000_0000 0 0 0000_0000_0000_0000 0 0 0 0 0 0 PARENT_ID[15:0] SYSLO_ERR_ACT[1:0] 0 0 0 0 0 SW_RESET_C FG 0 0 SECURITY[15:0] SW_SCRATCH[15:0] OTP_PROG 0 GP16_LVL THW_STS ON_TRANS 0 PS_INT TEMP_INT GP_INT ON_PIN_INT WDOG_INT 0 OFF_INTLD OFF_PWR_ O_ERR SEQ OFF_GPIO OFF_SYSVDD 0 OFF_THER R 0 0 0 ON_GPIO ON_SYSLO ON_PEN_D OWN ON_CHG 0 0 0 0 PWR_SRC_B PWR_WALL PWR_USB ATT 0 GP15_LVL GP14_LVL GP13_LVL GP12_LVL GP11_LVL GP10_LVL GP9_LVL GP8_LVL GP7_LVL 0 0 0 0 0 0 0 0 0 0 OTP_MEM 0 OTP_FINAL OTP_VERIFY OTP_WRITE OTP_READ OTP_READ_LVL[1:0] 0 0 0 0 0 ON_PIN_SECACT[1:0] 0 WDOG_SECACT[1:0] 0 REF_LP PWRSTATE_DLY[1:0] 0 0 SWRST_DL Y 0 0 0 0 0 0 0 SYSLO_STS 0 0 0 0 0 CHIP_ON WDOG_ENA 0 RECONFIG_ AT_ON 0 0 0 0 0 0 0 WALL_FET_ BATT_FET_ ENA_DRV_S ENA TR 0 0 0 0 WDOG_DEB WDOG_RST WDOG_SLP WDOG_RES UG _SRC ENA ET CHIP_SLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARENT_REV[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dec Addr Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 0 0000 Reset ID 1 0001 Revision WM8312 2 0002 Reserved 3 0003 Reserved 000 4 0004 Reserved w ON_WDOG_ ON_SW_RE ON_RTC_AL RESET_CNV RESET_WD ON_ON_PIN RESET_SW RESET_HW TO Q M _UV OG AUXADC_IN TCHDATA_IN TCHPD_INT T T AUXADC_D AUXADC_D AUXADC_D AUXADC_D PPM_SYSLO PPM_PWR_ PPM_USB_ ON_PIN_EIN WDOG_TO_ TCHDATA_EI TCHPD_EIN AUXADC_D RTC_PER_E RTC_ALM_ TEMP_THW 0 COMP4_EIN COMP3_EIN COMP2_EIN COMP1_EIN _EINT SRC_EINT CURR_EINT T EINT NT T ATA_EINT INT EINT _EINT T T T T CHG_BATT_ CHG_BATT_ CHG_BATT_ CHG_OV_EI CHG_END_ CHG_TO_EIN CHG_MODE CHG_STAR OTP_CMD_ OTP_ERR_E PS_POR_EI PS_SLEEP_ PS_ON_WA CS2_EINT CS1_EINT 0 HOT_EINT COLD_EINT FAIL_EINT NT EINT T _EINT T_EINT END_EINT INT NT OFF_EINT KE_EINT 0 0 GP16_EINT 0 0 0 0 0 0 0 0 0 GP15_EINT GP14_EINT GP13_EINT GP12_EINT 0 0 0 0 0 0 0 0 0 UV_LDO10_ UV_LDO9_E UV_LDO8_E UV_LDO7_E UV_LDO6_E UV_LDO5_E UV_LDO4_EI UV_LDO3_ UV_LDO2_E UV_LDO1_E EINT INT INT INT INT INT NT EINT INT INT 5 0005 Reserved 6 0006 Reserved 7 0007 Reserved 16384 4000 Parent ID 16385 4001 SYSVDD Control 16386 4002 Thermal Monitoring 16387 4003 Power State 28 REGISTER MAP OVERVIEW 800 16388 4004 Watchdog 16389 4005 ON Pin Control 16390 4006 Reset Control 16391 4007 Control Interface 16392 4008 Security Key 16393 4009 Software Scratch 16394 400A OTP Control 16395 400B Security Key 2 801 16396 400C GPIO Level 16397 400D System Status 16398 400E ON Source 16399 400F OFF Source 16400 4010 System Interrupts 16401 4011 Interrupt Status 1 16402 4012 Interrupt Status 2 16403 4013 Interrupt Status 3 802 16404 4014 Interrupt Status 4 16405 4015 Interrupt Status 5 16406 4016 Reserved 16407 4017 IRQ Config PP, December 2009, Rev 3.0 Pre-Production 172 Dec Addr CHIP_ID[15:0] 0000_0000_0000_0000 CHILD_REV[7:0] 0000_0000_0000_0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0110_0010_0000_0100 SYSLO_THR[2:0] 0 0 THW_HYST 0 0 0 0 0 AUXRST_SL RST_SLP_M RST_SLPEN PENA SK A 0 0 0 ON_PIN_PRIMACT[1:0] WDOG_PRIMACT[1:0] 0 ON_PIN_ST S 0 0 0 0 AUTOINC USB100MA_STARTUP[1:0 USB_CURR_ ] STS 0 SYSOK_THR[2:0] THW_TEMP[1:0] USB_ILIM[2:0] WDOG_TO[2:0] ON_PIN_TO[1:0] RST_DUR[1:0] 0 0 0000_0000_0010_0101 0000_0000_0000_1010 UU00_1000_0000_0010 1010_P010_0001_0111 0000_0010_0001_0010 1000_0100_0111_0011 0000_0000_0000_0100 0000_0000_0000_0000 0000_0000_0000_0000 OTP_BULK 0 GP7_LVL 0 0 0 GP6_LVL 0 0 0 GP5_LVL 0 0 GP4_LVL 0 0 GP3_LVL OTP_PAGE[1:0] 0 GP2_LVL MAIN_STATE[4:0] ON_WDOG_ ON_SW_RE ON_RTC_AL RESET_CNV RESET_WD ON_ON_PIN RESET_SW RESET_HW TO Q M _UV OG ON_CHG 0 0 PPM_INT OFF_SW_R EQ CS_INT 0 RTC_INT OFF_ON_PI N OTP_INT 0 0 0 CHG_INT 0 HC_INT 0 UV_INT 0 GP1_LVL U010_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 PPPP_PPPP_PPPP_PPPP PPPP_PPPP_PPPP_PPP0 PPPP_PPPP_PPPP_0PPP 0 0 GP11_EINT 0 0 0 0 0 UV_LDO10_ UV_LDO9_E UV_LDO8_E UV_LDO7_E UV_LDO6_E UV_LDO5_E UV_LDO4_EI UV_LDO3_ UV_LDO2_E UV_LDO1_E EINT INT INT INT INT INT NT EINT INT INT HC_DC2_EI HC_DC1_EI NT NT 0 GP10_EINT 0 0 GP9_EINT 0 0 0 GP8_EINT 0 0 0 GP7_EINT 0 0 0 GP6_EINT 0 0 0 GP5_EINT 0 0 UV_DC4_EI UV_DC3_EI UV_DC2_EI UV_DC1_EI NT NT NT NT GP4_EINT 0 0 GP3_EINT 0 0 GP2_EINT 0 IRQ_OD GP1_EINT 0 IM_IRQ 0000_00PP_PPPP_PPPP 0000_00PP_0000_PPPP PPPP_PPPP_PPPP_PPPP 0000_0000_0000_0000 0000_0000_0000_0010 0 0 0 0 0 0 PARENT_ID[15:0] SYSLO_ERR_ACT[1:0] 0 0 0 0 0 SW_RESET_C FG 0 0 SECURITY[15:0] SW_SCRATCH[15:0] OTP_PROG 0 GP16_LVL THW_STS ON_TRANS 0 PS_INT TEMP_INT GP_INT ON_PIN_INT WDOG_INT 0 OFF_INTLD OFF_PWR_ O_ERR SEQ OFF_THER OFF_GPIO OFF_SYSVDD R 0 0 0 ON_GPIO ON_SYSLO ON_PEN_D OWN 0 0 0 0 PWR_SRC_B PWR_WALL PWR_USB ATT GP15_LVL GP14_LVL GP13_LVL GP12_LVL GP11_LVL GP10_LVL GP9_LVL GP8_LVL 0 0 0 0 0 0 0 0 0 OTP_MEM 0 OTP_FINAL OTP_VERIFY OTP_WRITE OTP_READ OTP_READ_LVL[1:0] 0 0 0 0 0 ON_PIN_SECACT[1:0] 0 WDOG_SECACT[1:0] 0 REF_LP PWRSTATE_DLY[1:0] 0 0 SWRST_DL Y 0 0 0 0 0 0 0 SYSLO_STS 0 0 0 0 0 CHIP_ON WDOG_ENA 0 RECONFIG_ AT_ON 0 0 0 0 0 0 0 WALL_FET_ BATT_FET_ ENA_DRV_S ENA TR 0 0 0 0 WDOG_DEB WDOG_RST WDOG_SLP WDOG_RES UG _SRC ENA ET CHIP_SLP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARENT_REV[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 0 0000 Reset ID 1 0001 Revision Pre-Production 2 0002 Reserved 3 0003 Reserved 4 0004 Reserved w TCHDATA_IN AUXADC_IN TCHPD_INT T T AUXADC_D AUXADC_D AUXADC_D AUXADC_D PPM_SYSLO PPM_PWR_ PPM_USB_ ON_PIN_EIN WDOG_TO_ TCHDATA_EI TCHPD_EIN AUXADC_D RTC_PER_E RTC_ALM_ TEMP_THW 0 COMP4_EIN COMP3_EIN COMP2_EIN COMP1_EIN _EINT SRC_EINT CURR_EINT T EINT NT T ATA_EINT INT EINT _EINT T T T T CHG_BATT_ CHG_BATT_ CHG_BATT_ CHG_OV_EI CHG_END_ CHG_TO_EIN CHG_MODE CHG_STAR OTP_CMD_ OTP_ERR_E PS_POR_EI PS_SLEEP_ PS_ON_WA CS2_EINT CS1_EINT 0 HOT_EINT COLD_EINT FAIL_EINT NT EINT T _EINT T_EINT END_EINT INT NT OFF_EINT KE_EINT 0 0 GP16_EINT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP15_EINT GP14_EINT GP13_EINT GP12_EINT 5 0005 Reserved 6 0006 Reserved 7 0007 Reserved 16384 4000 Parent ID 16385 4001 SYSVDD Control 16386 4002 Thermal Monitoring 16387 4003 Power State 16388 4004 Watchdog 16389 4005 ON Pin Control 16390 4006 Reset Control 16391 4007 Control Interface 16392 4008 Security Key 16393 4009 Software Scratch 16394 400A OTP Control 16395 400B Security Key 2 16396 400C GPIO Level 16397 400D System Status 16398 400E ON Source 16399 400F OFF Source 16400 4010 System Interrupts 16401 4011 Interrupt Status 1 16402 4012 Interrupt Status 2 16403 4013 Interrupt Status 3 16404 4014 Interrupt Status 4 16405 4015 Interrupt Status 5 16406 4016 Reserved 16407 4017 IRQ Config PP, December 2009, Rev 3.0 WM8312 173 Dec Addr GP1_DIR GP2_DIR GP3_DIR GP4_DIR GP5_DIR GP6_DIR GP7_DIR GP8_DIR GP9_DIR GP10_DIR GP11_DIR GP12_DIR GP13_DIR GP14_DIR GP15_DIR GP16_DIR CHG_ENA 0 BATT_OV_S TS CHG_STATE[2:0] 0 0 0 0 0 0 0 0 0 DC2_OV_ST DC1_OV_ST S S 0 0 0 0 DC1_PHASE 0 0 0 DC1_HWC_SRC[1:0] 0 0 0 0 0 LDO11_STS 0 0 0 DC1_HWC_VS EL 0 0 0 0 0 0 CS2_SLPEN A CS2_OFF_RAMP[1:0] CS1_SLPEN A CS1_OFF_RAMP[1:0] 0 0 0 LED2_MODE[1:0] CS1_ON_RAMP[1:0] CS2_ON_RAMP[1:0] 0 0 0 0 LED1_MODE[1:0] 0 0 0 0 EPE2_ENA LDO8_ENA 0 0 LDO10_STS LDO9_STS DC2_HC_ST DC1_HC_ST S S EPE2_STS LDO8_STS 0 BKUP_CHG BKUP_BATT BKUP_BATT_ _MODE _DET_ENA STS 0 0 0 BKUP_CHG_ BKUP_CHG ENA _STS LED1_SRC[1:0] LED2_SRC[1:0] CS1_ENA CS2_ENA 0 0 0 0 0 INTLDO_UV_ STS 0 DC1_RATE[1:0] DC1_ERR_ACT[1:0] 0 0 0 0 0 CS2_DRIVE CS1_DRIVE BATT_HOT_ BATT_COLD_ CHG_TOPO CHG_ACTIV STS STS FF E 0 0 0 0 0 EPE1_ENA LDO7_ENA EPE1_STS LDO7_STS 0 0 LDO6_ENA 0 LDO6_STS 0 0 LDO5_ENA 0 LDO5_STS 0 0 CHG_OFF_ MSK 0 0 CHG_TIME[3:0] CHG_TRKL_ILIM[1:0] CHG_FRC 0 CHG_ITERM[2:0] 0 0 0 0 CHG_FAST GP16_PULL[1:0] 0 GP16_POL GP16_OD 0 GP16_TRI 0 0 GP16_INT_ MODE GP15_PULL[1:0] 0 GP15_POL GP15_OD 0 GP15_TRI 0 0 GP15_INT_ MODE 0 0 0 CHG_VSEL[1:0] CHG_TIME_ELAPSED[7:0] BKUP_CHG _VLIM LED1_SEQ_LEN[1:0] LED2_SEQ_LEN[1:0] 0 0 LED1_DUR[1:0] LED2_DUR[1:0] CS1_ISEL[5:0] CS2_ISEL[5:0] DC4_ENA DC3_ENA DC2_ENA LDO4_ENA LDO3_ENA LDO2_ENA DC4_STS LDO4_STS DC3_STS LDO3_STS DC2_STS LDO2_STS DC1_ENA LDO1_ENA DC1_STS LDO1_STS DC4_UV_ST DC3_UV_S DC2_UV_ST DC1_UV_ST S S TS S LDO10_UV_ LDO9_UV_S LDO8_UV_S LDO7_UV_S LDO6_UV_S LDO5_UV_S LDO4_UV_S LDO3_UV_ LDO2_UV_S LDO1_UV_S STS TS TS TS TS TS TS STS TS TS DC1_FREQ[1:0] DC1_HWC_MODE[1:0] DC1_FLT 0 0 DC1_SOFT_START[1:0] DC1_HC_THR[2:0] 0 0 0 0 DC1_CAP[1:0] 0 DC1_HC_IN D_ENA BKUP_CHG_ILIM[1:0] LED1_DUTY_CYC[1:0] LED2_DUTY_CYC[1:0] 0 GP14_PULL[1:0] 0 GP14_POL GP14_OD 0 GP14_TRI 0 0 0 GP14_INT_ MODE GP13_PULL[1:0] 0 GP13_POL GP13_OD 0 GP13_TRI 0 0 0 GP13_INT_ MODE GP12_PULL[1:0] GP12_POL GP12_OD 0 GP12_TRI 0 0 0 GP12_INT_ GP12_PWR MODE _DOM GP11_PULL[1:0] GP11_POL GP11_OD 0 GP11_TRI 0 0 0 GP11_INT_ GP11_PWR MODE _DOM GP10_PULL[1:0] GP10_POL GP10_OD 0 GP10_TRI 0 0 0 GP10_INT_ GP10_PWR MODE _DOM GP10_FN[3:0] GP11_FN[3:0] GP12_FN[3:0] GP13_FN[3:0] GP14_FN[3:0] GP15_FN[3:0] GP16_FN[3:0] 0 CHG_IMON_ CHG_CHIP_ ENA TEMP_MON CHG_FAST_ILIM[3:0] GP9_PULL[1:0] GP9_POL GP9_OD 0 GP9_TRI 0 0 0 GP9_FN[3:0] GP9_INT_M GP9_PWR_ ODE DOM GP8_PULL[1:0] GP8_POL GP8_OD 0 GP8_TRI 0 0 0 GP8_INT_M GP8_PWR_ ODE DOM GP8_FN[3:0] GP7_PULL[1:0] GP7_POL GP7_OD 0 GP7_TRI 0 0 0 GP7_FN[3:0] GP7_INT_M GP7_PWR_ ODE DOM GP6_PULL[1:0] GP6_POL GP6_OD 0 GP6_TRI 0 0 0 GP6_FN[3:0] GP6_INT_M GP6_PWR_ ODE DOM GP5_PULL[1:0] GP5_POL GP5_OD 0 GP5_TRI 0 0 0 GP5_FN[3:0] GP5_INT_M GP5_PWR_ ODE DOM GP4_PULL[1:0] GP4_POL GP4_OD 0 GP4_TRI 0 0 0 GP4_FN[3:0] GP4_INT_M GP4_PWR_ ODE DOM GP3_PULL[1:0] GP3_POL GP3_OD 0 GP3_TRI 0 0 0 GP3_FN[3:0] GP3_INT_M GP3_PWR_ ODE DOM 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 1010_0100_1000_0000 0000_0000_0000_0001 0000_0110_0000_0010 0000_0000_0000_0000 0000_0000_0000_0000 1100_0000_0010_0110 1100_0000_0010_0110 0U00_0101_0000_0000 0U00_0101_0000_0000 0000_0000_UU00_UUUU 0000_0UUU_UUUU_UUUU 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 1000_0000_0000_0000 0000_0011_0000_0000 GP2_PULL[1:0] GP2_POL GP2_OD 0 GP2_TRI 0 0 0 GP2_FN[3:0] 1010_0100_1000_0000 GP2_INT_M GP2_PWR_ ODE DOM GP1_PULL[1:0] GP1_POL GP1_OD 0 GP1_TRI 0 0 0 GP1_FN[3:0] 1010_0100_1000_0000 GP1_INT_M GP1_PWR_ ODE DOM Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 16440 4038 GPIO1 Control WM8312 16441 4039 GPIO2 Control 16442 403A GPIO3 Control 16443 403B GPIO4 Control 16444 403C GPIO5 Control w LDO11_ENA LDO10_ENA LDO9_ENA 16445 403D GPIO6 Control 16446 403E GPIO7 Control 16447 403F GPIO8 Control 16448 4040 GPIO9 Control 16449 4041 GPIO10 Control 16450 4042 GPIO11 Control 16451 4043 GPIO12 Control 16452 4044 GPIO13 Control 16453 4045 GPIO14 Control 16454 4046 GPIO15 Control 16455 4047 GPIO16 Control 16456 4048 Charger Control 1 16457 4049 Charger Control 2 16458 404A Charger Status 16459 404B Backup Charger Control 16460 404C Status LED 1 16461 404D Status LED 2 16462 404E Current Sink 1 16463 404F Current Sink 2 16464 4050 DCDC Enable 16465 4051 LDO Enable 16466 4052 DCDC Status 16467 4053 LDO Status 16468 4054 DCDC UV Status 16469 4055 LDO UV Status 16470 4056 DC1 Control 1 PP, December 2009, Rev 3.0 Pre-Production 16471 4057 DC1 Control 2 174 Dec Addr DC1_ON_SLOT[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPE1_HWC_SRC[1:0] 0 0 LDO1_HWC_V LDO1_HWC_MODE[1:0] SEL LDO1_FLT 0 0 LDO2_FLT 0 0 LDO3_FLT LDO3_ON_ MODE 0 0 LDO3_SLP_ MODE 0 0 LDO4_FLT 0 0 0 LDO4_ON_ MODE 0 LDO4_SLP_ MODE 0 LDO5_HWC_V LDO5_HWC_MODE[1:0] SEL 0 0 0 0 LDO6_HWC_SRC[1:0] 0 0 0 0 LDO5_ON_ MODE 0 LDO5_SLP_ MODE LDO6_HWC_V LDO6_HWC_MODE[1:0] SEL 0 0 LDO5_FLT 0 0 LDO6_FLT 0 LDO2_SWI 0 0 LDO3_SWI 0 0 LDO4_SWI 0 0 LDO5_SWI 0 0 LDO6_SWI 0 LDO1_SWI 0 0 LDO2_HWC_V LDO2_HWC_MODE[1:0] SEL 0 0 0 LDO2_SLP_ MODE 0 LDO2_ON_ MODE 0 LDO1_SLP_ MODE 0 LDO1_ON_ MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPE2_HWC ENA EPE2_SLP_SLOT[2:0] 0 EPE2_HWC_SRC[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO4_HWC_SRC[1:0] 0 0 0 0 LDO3_HWC_SRC[1:0] 0 0 LDO2_HWC_SRC[1:0] 0 0 LDO1_HWC_SRC[1:0] EPE1_HWC ENA EPE1_SLP_SLOT[2:0] 0 0 0 0 0 0 0 DC4_SLPEN A 0 0 0 0 DC4_HWC_SRC[1:0] 0 0 0 0 0 0 DC4_HWC_ MODE 0 0 0 0 0 0 DC3_SLP_MODE[1:0] 0 DC3_SLP_VSEL[6:0] DC4_RANGE[1:0] 0 0 0 0 LDO1_ON_VSEL[4:0] LDO1_SLP_VSEL[4:0] 0 LDO2_ON_VSEL[4:0] LDO2_SLP_VSEL[4:0] 0 LDO3_ON_VSEL[4:0] LDO3_SLP_VSEL[4:0] 0 LDO4_ON_VSEL[4:0] LDO4_SLP_VSEL[4:0] 0 LDO5_ON_VSEL[4:0] LDO5_SLP_VSEL[4:0] 0 0 LDO6_LP_M ODE 0 LDO5_LP_M ODE 0 LDO4_LP_M ODE 0 LDO3_LP_M ODE 0 LDO2_LP_M ODE 0 0 0 0 0 DC4_FBSR C 0 0 0 LDO1_LP_M ODE 0 0 DC3_ON_MODE[1:0] 0 DC3_ON_VSEL[6:2] DC3_HWC_SRC[1:0] DC3_HWC_MODE[1:0] DC3_OVP 0 0 0 0 0 DC3_HWC_VS EL 0 DC3_PHASE 0 0 0 0 DC3_FLT 0 DC3_SOFT_START[1:0] 0 DC2_DVS_SRC[1:0] 0 0 0 0 DC2_DVS_VSEL[6:0] 0 0 DC2_SLP_MODE[1:0] 0 DC2_SLP_VSEL[6:0] 0 0 DC2_ON_MODE[1:0] 0 DC2_ON_VSEL[6:2] DC2_ON_VSEL[1:0] DC2_HWC_SRC[1:0] DC2_HWC_MODE[1:0] 0 0 0 0 DC2_HWC_VS EL DC2_HC_THR[2:0] DC2_HC_IN D_ENA DC2_PHASE 0 0 DC2_FREQ[1:0] DC2_FLT 0 0 0 DC2_SOFT_START[1:0] DC2_CAP[1:0] DC1_DVS_SRC[1:0] 0 0 0 0 DC1_DVS_VSEL[6:0] 0000_0000_0000_0000 1001_0000_0000_0000 0000_0011_0000_0000 0000_0001_0000_0000 0000_0011_0000_0000 0000_0000_0000_0000 0 0 DC1_SLP_MODE[1:0] 0 0000_0011_0000_0000 DC1_SLP_VSEL[6:0] 0 0 0 DC1_ON_VSEL[1:0] 0000_0001_0000_0000 DC1_SLP_SLOT[2:0] 0 DC2_RATE[1:0] DC2_ERR_ACT[1:0] DC2_ON_SLOT[2:0] DC2_SLP_SLOT[2:0] 0 0 DC3_ERR_ACT[1:0] DC3_ON_SLOT[2:0] DC3_SLP_SLOT[2:0] DC4_ERR_ACT[1:0] 0 EPE1_ON_SLOT[2:0] EPE2_ON_SLOT[2:0] LDO1_ERR_ACT[1:0] LDO1_ON_SLOT[2:0] LDO1_SLP_SLOT[2:0] LDO2_ERR_ACT[1:0] LDO2_ON_SLOT[2:0] LDO2_SLP_SLOT[2:0] LDO3_ERR_ACT[1:0] LDO3_ON_SLOT[2:0] LDO3_SLP_SLOT[2:0] LDO4_ERR_ACT[1:0] LDO4_ON_SLOT[2:0] LDO4_SLP_SLOT[2:0] LDO5_ERR_ACT[1:0] LDO5_ON_SLOT[2:0] LDO5_SLP_SLOT[2:0] LDO6_ERR_ACT[1:0] 0 0 0 0 DC1_ON_MODE[1:0] DC1_ON_VSEL[6:2] Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 16472 4058 DC1 ON Config 16473 4059 DC1 SLEEP Control Pre-Production 16474 405A DC1 DVS Control 16475 405B DC2 Control 1 16476 405C DC2 Control 2 w 0 DC3_CAP[1:0] 0 DC3_ON_VSEL[1:0] 0000_0000_0001_0000 0000_0011_0000_0000 0000_0001_0000_0000 0000_0011_0000_0000 0000_0001_0000_0100 0000_0000_0000_0000 0000_0001_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 LDO3_HWC_V LDO3_HWC_MODE[1:0] SEL LDO4_HWC_V LDO4_HWC_MODE[1:0] SEL LDO5_HWC_SRC[1:0] 16477 405D DC2 ON Config 16478 405E DC2 SLEEP Control 16479 405F DC2 DVS Control 16480 4060 DC3 Control 1 16481 4061 DC3 Control 2 16482 4062 DC3 ON Config 16483 4063 DC3 SLEEP Control 16484 4064 DC4 Control 16485 4065 DC4 SLEEP Control 16486 4066 EPE1 Control 16487 4067 EPE2 Control 16488 4068 LDO1 Control 16489 4069 LDO1 ON Control 16490 406A LDO1 SLEEP Control 16491 406B LDO2 Control 16492 406C LDO2 ON Control 16493 406D LDO2 SLEEP Control 16494 406E LDO3 Control 16495 406F LDO3 ON Control 16496 4070 LDO3 SLEEP Control 16497 4071 LDO4 Control 16498 4072 LDO4 ON Control 16499 4073 LDO4 SLEEP Control 16500 4074 LDO5 Control 16501 4075 LDO5 ON Control 16502 4076 LDO5 SLEEP Control PP, December 2009, Rev 3.0 WM8312 16503 4077 LDO6 Control 175 Dec Addr LDO6_ON_SLOT[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO11_OFF ENA 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL_OUTDIV[5:0] FLL_K[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 FLL_N[9:0] 0 0 0 0 0 0 0 0 0 0 0 FLL_CLK_REF_DIV[1:0] 0 0 0 0 FLL_GAIN[3:0] FLL_CLK_SRC[1:0] 0 0 0 0 LDO10_OK 0 0 0 LDO9_OK 0 0 0 0 0 0 0 0 0 LDO8_OK 0 0 0 0 0 FLL_AUTO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO7_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO6_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUT_O D 0 XTAL_BKUP ENA 0 0 0 0 0 0 0 0 0 0 LDO11_VSE L_SRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDO5_OK CLKOUT_SLPSLOT[2:0] 0 0 FLL_CTRL_RATE[2:0] 0 0 0 0 0 0 0 DC4_OK LDO4_OK 0 0 0 0 0 0 0 LDO10_SLP _MODE 0 0 0 0 0 0 0 LDO10_ON_ MODE 0 0 0 LDO10_HWC_SRC[1:0] 0 0 0 LDO10_HWC_ LDO10_HWC_MODE[1:0] LDO10_FLT LDO10_SWI VSEL 0 LDO10_ON_VSEL[4:0] LDO10_SLP_VSEL[4:0] 0 0 LDO11_ON_VSEL[3:0] LDO11_SLP_VSEL[3:0] 0 0 0 0 0 DC3_OK LDO3_OK 0 0 0 0 0 0 DC2_OK LDO2_OK 0 0 0 0 0 0 DC1_OK LDO1_OK CLKOUT_S RC FLL_AUTO_FREQ[2:0] FLL_FRAC 0 FLL_FRATIO[2:0] FLL_ENA 0 0 0 0 LDO9_SLP_ MODE 0 0 0 0 0 0 LDO9_ON_ MODE 0 0 0 LDO9_ON_VSEL[4:0] LDO9_SLP_VSEL[4:0] 0 0 LDO9_HWC_SRC[1:0] LDO9_FLT LDO9_SWI 0 0 0 0 0 LDO9_HWC_V LDO9_HWC_MODE[1:0] SEL 0 0 0 LDO8_SLP_ MODE 0 0 0 LDO8_SLP_VSEL[4:0] 0 0 0 0 LDO8_ON_ MODE 0 0 0 LDO8_ON_VSEL[4:0] LDO8_HWC_SRC[1:0] LDO8_FLT LDO8_SWI 0 0 0 0 0 0 LDO8_HWC_V LDO8_HWC_MODE[1:0] SEL 0 0 0 LDO7_SLP_ MODE 0 0 0 LDO7_SLP_VSEL[4:0] 0 0 0 LDO7_ON_ MODE 0 0 0 LDO7_ON_VSEL[4:0] LDO7_HWC_SRC[1:0] LDO7_FLT LDO7_SWI 0 0 0 0 0 0 LDO7_HWC_V LDO7_HWC_MODE[1:0] SEL 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0010_0000_0000 0000_0000_0000_0000 0000_0001_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0111 0000_0011_1111_1111 U000_0000_0000_0000 0001_0000_1000_0000 0 0 0 LDO6_SLP_ MODE 0 0 0 LDO6_SLP_VSEL[4:0] 0000_0001_0000_0000 0 0 0 0 0 0 0000_0000_0000_0000 LDO6_SLP_SLOT[2:0] LDO7_ERR_ACT[1:0] LDO7_ON_SLOT[2:0] LDO7_SLP_SLOT[2:0] LDO8_ERR_ACT[1:0] LDO8_ON_SLOT[2:0] LDO8_SLP_SLOT[2:0] LDO9_ERR_ACT[1:0] LDO9_ON_SLOT[2:0] LDO9_SLP_SLOT[2:0] LDO10_ERR_ACT[1:0] LDO10_ON_SLOT[2:0] LDO10_SLP_SLOT[2:0] 0 LDO11_ON_SLOT[2:0] LDO11_SLP_SLOT[2:0] 0 0 0 0 0 0 0 CLKOUT_EN A 0 0 0 0 XTAL_INH 0 0 0 0 0 0 0 0 0 0 LDO6_ON_ MODE LDO6_ON_VSEL[4:0] Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 16504 4078 LDO6 ON Control WM8312 16505 4079 LDO6 SLEEP Control 16506 407A LDO7 Control 16507 407B LDO7 ON Control 16508 407C LDO7 SLEEP Control w CLKOUT_SLOT[2:0] 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0010_1110_1110_0000 0000_0000_0000_0000 0000_0000_0000_0000 16509 407D LDO8 Control 16510 407E LDO8 ON Control 16511 407F LDO8 SLEEP Control 16512 4080 LDO9 Control 16513 4081 LDO9 ON Control 16514 4082 LDO9 SLEEP Control 16515 4083 LDO10 Control 16516 4084 LDO10 ON Control 16517 4085 LDO10 SLEEP Control 16518 4086 Reserved 16519 4087 LDO11 ON Control 16520 4088 LDO11 SLEEP Control 16521 4089 Reserved 16522 408A Reserved 16523 408B Reserved 16524 408C Reserved 16525 408D Reserved 16526 408E Power Good Source 1 16527 408F Power Good Source 2 16528 4090 Clock Control 1 16529 4091 Clock Control 2 16530 4092 FLL Control 1 16531 4093 FLL Control 2 16532 4094 FLL Control 3 16533 4095 FLL Control 4 16534 4096 FLL Control 5 PP, December 2009, Rev 3.0 Pre-Production 16535 4097 Reserved 176 Dec Addr UNIQUE_ID[127:112] 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 OTP_FACT_ FINAL DC1_TRIM[5:0] 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 BG_TRIM[3:0] CHILD_I2C_ADDR[6:0] 0 0 0 0 0 0 0 0 0 0 CHARGE_TRIM[5:0] 0 0 0 0 0 0 0 0 OTP_CUST _FINAL DC1_ON_VSEL[6:2] DC2_ON_VSEL[6:2] DC3_ON_VSEL[6:2] LDO1_ON_SLOT[2:0] LDO3_ON_SLOT[2:0] LDO5_ON_SLOT[2:0] LDO7_ON_SLOT[2:0] LDO9_ON_SLOT[2:0] EPE2_ON_SLOT[2:0] GP1_OD GP2_POL GP3_POL GP4_POL GP5_POL GP6_INT_M GP6_PWR_ ODE DOM GP6_POL GP2_OD GP3_OD GP4_OD GP5_OD GP6_OD GP1_TRI GP2_TRI GP3_TRI GP4_TRI GP5_TRI GP6_TRI GP1_FN[3:0] GP1_POL GP2_FN[3:0] GP3_FN[3:0] GP4_FN[3:0] GP5_FN[3:0] GP6_FN[3:0] LDO1_ON_VSEL[4:0] LDO3_ON_VSEL[4:0] LDO5_ON_VSEL[4:0] LDO7_ON_VSEL[4:0] LDO9_ON_VSEL[4:0] EPE1_ON_SLOT[2:0] CLKOUT_SR C 0 USB100MA_STARTUP[1:0 ] XTAL_INH CLKOUT_SLOT[2:0] FLL_AUTO_FREQ[2:0] LED1_SRC[1:0] USB_ILIM[2:0] SYSOK_THR[2:0] CHG_ENA 0 0 LED2_SRC[1:0] 0 0 DC1_CAP[1:0] DC2_CAP[1:0] DC3_CAP[1:0] LPBG_TRIM[2:0] CH_AW 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_1000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 1010_0101_0000_0000 1010_0101_0000_0000 1010_0101_0000_0000 1010_0101_0000_1111 1010_0101_0000_0100 1010_0101_0000_1010 UNIQUE_ID[111:96] UNIQUE_ID[95:80] UNIQUE_ID[79:64] UNIQUE_ID[63:48] UNIQUE_ID[47:32] UNIQUE_ID[31:16] UNIQUE_ID[15:0] OTP_FACT_ID[14:0] DC3_TRIM[3:0] CHIP_ID[15:0] 0 0 0 0 0 OTP_AUTO_ PROG OTP_CUST_ID[13:0] 0 0 0 LDO2_ON_VSEL[4:0] LDO4_ON_VSEL[4:0] LDO6_ON_VSEL[4:0] LDO8_ON_VSEL[4:0] LDO10_ON_VSEL[4:0] 0 GP1_INT_M GP1_PWR_ ODE DOM GP2_INT_M GP2_PWR_ ODE DOM GP3_INT_M GP3_PWR_ ODE DOM GP4_INT_M GP4_PWR_ ODE DOM GP5_INT_M GP5_PWR_ ODE DOM LDO11_ON_VSEL[3:0] 0 0 0 0 DC3_PHASE 0 0 DC2_FREQ[1:0] DC2_PHASE 0 0 DC1_FREQ[1:0] DC1_PHASE DC1_ON_SLOT[2:0] DC2_ON_SLOT[2:0] DC3_ON_SLOT[2:0] LDO2_ON_SLOT[2:0] LDO4_ON_SLOT[2:0] LDO6_ON_SLOT[2:0] LDO8_ON_SLOT[2:0] LDO10_ON_SLOT[2:0] LDO11_ON_SLOT[2:0] GP1_DIR GP2_DIR GP3_DIR GP4_DIR GP5_DIR GP6_DIR GP6_PULL[1:0] GP5_PULL[1:0] GP4_PULL[1:0] GP3_PULL[1:0] GP2_PULL[1:0] GP1_PULL[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC_TRIM[3:0] DC2_TRIM[5:0] Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 30720 7800 Unique ID 1 30721 7801 Unique ID 2 Pre-Production 30722 7802 Unique ID 3 30723 7803 Unique ID 4 30724 7804 Unique ID 5 w WM8312 30725 7805 Unique ID 6 30726 7806 Unique ID 7 30727 7807 Unique ID 8 30728 7808 Factory OTP ID 30729 7809 Factory OTP 1 30730 780A Factory OTP 2 30731 780B Factory OTP 3 30732 780C Factory OTP 4 30733 780D Factory OTP 5 30734 780E Reserved 30735 780F Reserved 30736 7810 Customer OTP ID 30737 7811 DC1 OTP Control 30738 7812 DC2 OTP Control 30739 7813 DC3 OTP Control 30740 7814 LDO1/2 OTP Control 30741 7815 LDO3/4 OTP Control 30742 7816 LDO5/6 OTP Control 30743 7817 LDO7/8 OTP Control 30744 7818 LDO9/10 OTP Control 30745 7819 LDO11/EPE Control 30746 781A GPIO1 OTP Control 30747 781B GPIO2 OTP Control 30748 781C GPIO3 OTP Control 30749 781D GPIO4 OTP Control 30750 781E GPIO5 OTP Control PP, December 2009, Rev 3.0 30751 781F GPIO6 OTP Control 177 Dec Addr 0 0 0 0 0 0 0 DBE_VALID_DATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 0000_0000_0L0H_H0LL 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0000_0000_0000_0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 Hex Addr Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bin Default 30752 7820 Reserved WM8312 30753 7821 Reserved 30754 7822 Reserved 30755 7823 Reserved 30756 7824 Reserved w Pre-Production 30757 7825 Reserved 30758 7826 Reserved 30759 7827 DBE CHECK DATA PP, December 2009, Rev 3.0 178 Pre-Production WM8312 29 REGISTER BITS BY ADDRESS REGISTER ADDRESS R0 (00h) Reset ID BIT 15:0 LABEL CHIP_ID[15:0] DEFAULT DESCRIPTION REFER TO 0000_0000 Writing to this register causes a Software Reset. The _0000_000 register map contents may be reset, depending on SW_RESET_CFG. 0 Reading from this register will indicate Chip ID. Register 00h Reset ID REGISTER ADDRESS R1 (01h) Revision BIT 15:8 7:0 LABEL DEFAULT DESCRIPTION REFER TO PARENT_REV[ 0000_0000 The revision number of the parent die 7:0] CHILD_REV[7: 0000_0000 The revision number of the child die (when present) 0] Register 01h Revision REGISTER ADDRESS R16384 (4000h) Parent ID BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO PARENT_ID[15 0110_0010 The ID of the parent die :0] _0000_010 0 Register 4000h Parent ID REGISTER ADDRESS R16385 (4001h) SYSVDD Control BIT 15:14 LABEL SYSLO_ERR_ ACT[1:0] DEFAULT 00 DESCRIPTION SYSLO Error Action Selects the action taken when SYSLO is asserted 00 = Interrupt 01 = WAKE transition 10 = Reserved 11 = OFF transition SYSLO Status 0 = Normal 1 = SYSVDD is below SYSLO threshold SYSLO threshold (falling SYSVDD) This is the falling SYSVDD voltage at which SYSLO will be asserted 000 = 2.8V 001 = 2.9V ... 111 = 3.5V SYSOK threshold (rising SYSVDD) This is the rising SYSVDD voltage at which SYSLO will be de-asserted 000 = 2.8V 001 = 2.9V ... 111 = 3.5V REFER TO 11 SYSLO_STS 0 6:4 SYSLO_THR[2 :0] 010 2:0 SYSOK_THR[2 :0] 101 Register 4001h SYSVDD Control w PP, December 2009, Rev 3.0 179 WM8312 REGISTER ADDRESS R16386 (4002h) Thermal Monitoring BIT 3 LABEL THW_HYST DEFAULT 1 DESCRIPTION Thermal Warning hysteresis 0 = 8 degrees C 1 = 16 degrees C Thermal Warning temperature 00 = 90 degrees C 01 = 100 degress C 10 = 110 degrees C 11 = 120 degrees C Pre-Production REFER TO 1:0 THW_TEMP[1: 0] 10 Register 4002h Thermal Monitoring REGISTER ADDRESS R16387 (4003h) Power State BIT 15 LABEL CHIP_ON DEFAULT 0 DESCRIPTION Indicates whether the system is ON or OFF. 0 = OFF 1 = ON (or SLEEP) OFF can be commanded by writing CHIP_ON = 0. Note that writing CHIP_ON = 1 is not a valid `ON' event, and will not trigger an ON transition. Indicates whether the system is in the SLEEP state. 0 = Not in SLEEP 1 = SLEEP WAKE can be commanded by writing CHIP_SLP = 0. SLEEP can be commanded by writing CHIP_SLP = 1. Low Power Voltage Reference Control 0 = Normal 1 = Low Power Reference Mode select Note that Low Power Reference Mode is only supported when the Touch Panel and Auxiliary ADC are both disabled. Power State transition delay 00 = No delay 01 = No delay 10 = 1ms 11 = 10ms Software Reset Delay 0 = No delay 1 = Software Reset is delayed by PWRSTATE_DLY following the Software Reset command Sets the device behaviour when starting up under USB power, when USB_ILIM = 010 (100mA) 00 = Normal 01 = Soft-Start 10 = Only start if BATTVDD > 3.1V 11 = Only start if BATTVDD > 3.4V In the 1X modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. The start-up request is delayed until the battery voltage threshold has been met. Note that trickle charge is only possible when CHG_ENA=1. Indicates if the USB current limit has been reached 0 = Normal 1 = USB current limit Sets the USB current limit REFER TO 14 CHIP_SLP 0 12 REF_LP 0 11:10 PWRSTATE_D LY[1:0] 10 9 SWRST_DLY 0 5:4 USB100MA_S TARTUP[1:0] 00 3 USB_CURR_S TS USB_ILIM[2:0] 0 2:0 010 w PP, December 2009, Rev 3.0 180 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 000 = 0mA (USB switch is open) 001 = 2.5mA 010 = 100mA 011 = 500mA 100 = 900mA 101 = 1500mA 110 = 1800mA 111 = 1800mA Register 4003h Power State WM8312 REFER TO REGISTER ADDRESS R16388 (4004h) Watchdog BIT 15 LABEL WDOG_ENA DEFAULT 1 DESCRIPTION Watchdog Timer Enable 0 = Disabled 1 = Enabled (enables the watchdog; does not reset it) Protected by security key. Watchdog Pause 0 = Disabled 1 = Enabled (halts the Watchdog timer for system debugging) Protected by security key. Watchdog Reset Source 0 = Hardware only 1 = Software only Protected by security key. Watchdog SLEEP Enable 0 = Disabled 1 = Controlled by WDOG_ENA Protected by security key. Watchdog Software Reset 0 = Normal 1 = Watchdog Reset (resets the watchdog, if WDOG_RST_SRC = 1) Secondary action of Watchdog timeout (taken after 2 timeout periods) 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by security key. Primary action of Watchdog timeout 00 = No action 01 = Interrupt 10 = Device Reset 11 = WAKE transition Protected by security key. Watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s REFER TO 14 WDOG_DEBU G 0 13 WDOG_RST_ SRC 1 12 WDOG_SLPE NA 0 11 WDOG_RESE T 0 9:8 WDOG_SECA CT[1:0] 10 5:4 WDOG_PRIMA CT[1:0] 01 2:0 WDOG_TO[2:0 ] 111 w PP, December 2009, Rev 3.0 181 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 110 = 16.384s 111 = 32.768s Protected by security key. Register 4004h Watchdog Pre-Production REFER TO REGISTER ADDRESS R16389 (4005h) ON Pin Control BIT 9:8 LABEL ON_PIN_SECA CT[1:0] DEFAULT 01 DESCRIPTION Secondary action of ON pin (taken after 1 timeout period) 00 = Interrupt 01 = ON request 10 = OFF request 11 = Reserved Protected by security key. Primary action of ON pin 00 = Ignore 01 = ON request 10 = OFF request 11 = Reserved Note that an Interrupt is always raised. Protected by security key. Current status of ON pin 0 = Asserted (logic 0) 1 = Not asserted (logic 1) ON pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s Protected by security key. REFER TO 5:4 ON_PIN_PRIM ACT[1:0] 00 3 ON_PIN_STS 0 1:0 ON_PIN_TO[1: 0] 00 Register 4005h ON Pin Control REGISTER ADDRESS R16390 (4006h) Reset Control BIT 15 LABEL RECONFIG_A T_ON DEFAULT 1 DESCRIPTION Selects if the bootstrap configuration data should be reloaded when an ON transition is scheduled 0 = Disabled 1 = Enabled Protected by security key. Sets the drive strength of the WALLFETENA pin. (Note this pin is Active Low.) 0 = Weak drive (500kOhm) 1 = Strong drive (50kOhm) Enables the FET gate functionality on the BATTFETENA pin. (Note this pin is Active Low.) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Software Reset Configuration. Selects whether the register map is reset to default values when Software Reset occurs. REFER TO 13 WALL_FET_E NA_DRV_STR 0 12 BATT_FET_EN A 0 10 SW_RESET_C FG 1 w PP, December 2009, Rev 3.0 182 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 = All registers except RTC and Software Scratch registers are reset by Software Reset 1 = Register Map is not affected by Software Reset Protected by security key. 6 AUXRST_SLP ENA 1 Sets the output status of Auxiliary Reset (GPIO) function in SLEEP 0 = Auxiliary Reset not asserted 1 = Auxiliary Reset asserted Protected by security key. Masks the RESET pin input in SLEEP mode 0 = External RESET active in SLEEP 1 = External RESET masked in SLEEP Protected by security key. Sets the output status of RESET pin in SLEEP 0 = RESET high (not asserted) 1 = RESET low (asserted) Protected by security key. Delay period for releasing RESET after ON or WAKE sequence 00 = 1ms 01 = 10ms 10 = 50ms 11 = 100ms Protected by security key. WM8312 REFER TO 5 RST_SLP_MS K 1 4 RST_SLPENA 1 1:0 RST_DUR[1:0] 11 Register 4006h Reset Control REGISTER ADDRESS R16391 (4007h) Control Interface BIT 2 LABEL AUTOINC DEFAULT 1 DESCRIPTION Enable Auto-Increment function 0 = Disabled 1 = Enabled REFER TO Register 4007h Control Interface REGISTER ADDRESS R16392 (4008h) Security Key BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO SECURITY[15: 0000_0000 Security Key 0] _0000_000 A value of 9716h must be written to this register to 0 access the user-keyed registers. Register 4008h Security Key REGISTER ADDRESS R16393 (4009h) Software Scratch BIT 15:0 LABEL SW_SCRATC H[15:0] DEFAULT DESCRIPTION REFER TO 0000_0000 Software Scratch Register for use by the host _0000_000 processor. 0 Note that this register's contents are retained in the BACKUP power state. Register 4009h Software Scratch w PP, December 2009, Rev 3.0 183 WM8312 REGISTER ADDRESS R16394 (400Ah) OTP Control BIT 15 LABEL OTP_PROG DEFAULT 0 DESCRIPTION Selects the PROGRAM device state. 0 = No action 1 = Select PROGRAM mode Note that, after PROGRAM mode has been selected, the chip will remain in PROGRAM mode until a Device Reset. Protected by security key. Selects DBE or OTP memory for Program commands. 0 = DBE 1 = OTP Protected by security key. Selects the FINALISE command, preventing further OTP programming. 0 = No action 1 = Finalise Command Protected by security key. Selects the VERIFY command for the selected OTP memory page(s). 0 = No action 1 = Verify Command Protected by security key. Selects WRITE command for the selected OTP memory page(s). 0 = No action 1 = Write Command Protected by security key. Selects READ command for the selected memory page(s). 0 = No action 1 = Read Command Protected by security key. Selects the Margin Level for READ or VERIFY OTP commands. 00 = Normal 01 = Reserved 10 = Margin 1 11 = Margin 2 Protected by security key. Selects the number of memory pages for DBE / OTP commands. 0 = Single Page 1 = All Pages Selects the single memory page for DBE / OTP commands (when OTP_BULK=0). If OTP is selected (OTP_MEM = 1): 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 If DBE is selected (OTP_MEM = 0): 00 = Page 2 01 = Page 3 10 = Page 4 11 = Reserved Register 400Ah OTP Control Pre-Production REFER TO 13 OTP_MEM 1 11 OTP_FINAL 0 10 OTP_VERIFY 0 9 OTP_WRITE 0 8 OTP_READ 0 7:6 OTP_READ_L VL[1:0] 00 5 OTP_BULK 0 1:0 OTP_PAGE[1: 0] 00 w PP, December 2009, Rev 3.0 184 Pre-Production WM8312 BIT 15 LABEL GP16_LVL DEFAULT 0 DESCRIPTION GPIO16 level. When GP16_FN = 0h and GP16_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP16_POL is 0, the register contains the opposite logic level to the external pin. When GP15_FN = 0h and GP15_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP15_POL is 0, the register contains the opposite logic level to the external pin. When GP14_FN = 0h and GP14_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP14_POL is 0, the register contains the opposite logic level to the external pin. When GP13_FN = 0h and GP13_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP13_POL is 0, the register contains the opposite logic level to the external pin. When GP12_FN = 0h and GP12_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP12_POL is 0, the register contains the opposite logic level to the external pin. When GP11_FN = 0h and GP11_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP11_POL is 0, the register contains the opposite logic level to the external pin. When GP10_FN = 0h and GP10_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP10_POL is 0, the register contains the opposite logic level to the external pin. When GP9_FN = 0h and GP9_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP9_POL is 0, the register contains the opposite logic level to the external pin. When GP8_FN = 0h and GP8_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP8_POL is 0, the register contains the opposite logic level to the external pin. When GP7_FN = 0h and GP7_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP7_POL is 0, the register contains the opposite logic level to the external pin. When GP6_FN = 0h and GP6_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP6_POL is 0, the register contains the opposite logic level to the external pin. PP, December 2009, Rev 3.0 185 REFER TO REGISTER ADDRESS R16396 (400Ch) GPIO Level 14 GP15_LVL 0 13 GP14_LVL 0 12 GP13_LVL 0 11 GP12_LVL 0 10 GP11_LVL 0 9 GP10_LVL 0 8 GP9_LVL 0 7 GP8_LVL 0 6 GP7_LVL 0 5 GP6_LVL 0 w WM8312 REGISTER ADDRESS BIT 4 LABEL GP5_LVL DEFAULT 0 DESCRIPTION When GP5_FN = 0h and GP5_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP5_POL is 0, the register contains the opposite logic level to the external pin. When GP4_FN = 0h and GP4_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP4_POL is 0, the register contains the opposite logic level to the external pin. When GP3_FN = 0h and GP3_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP3_POL is 0, the register contains the opposite logic level to the external pin. When GP2_FN = 0h and GP2_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP2_POL is 0, the register contains the opposite logic level to the external pin. When GP1_FN = 0h and GP1_DIR = 0, write to this bit to set a GPIO output. Read from this bit to read GPIO input level. When GP1_POL is 0, the register contains the opposite logic level to the external pin. Pre-Production REFER TO 3 GP4_LVL 0 2 GP3_LVL 0 1 GP2_LVL 0 0 GP1_LVL 0 Register 400Ch GPIO Level REGISTER ADDRESS R16397 (400Dh) System Status BIT 15 LABEL THW_STS DEFAULT 0 DESCRIPTION Thermal Warning status 0 = Normal 1 = Overtemperature Warning (warning temperature is set by THW_TEMP) Battery Power Source status 0 = Battery is not supplying current 1 = Battery is supplying current Wall Adaptor status 0 = Wall Adaptor voltage not present 1 = Wall Adaptor voltage is present USB status 0 = USB voltage not present 1 = USB voltage is present Main State Machine condition 0_0000 = OFF 0_0001 = ON_CHK 0_0010 = OTP_DN 0_0011 = READ_OTP 0_0100 = READ_DBE 0_0101 = DBE_DN 0_0110 = BGDELAY 0_0111 = HYST 0_1000 = S_PRG_RD_OTP 0_1001 = S_PRG_OTP_DN 0_1010 = PWRDN1 REFER TO 10 PWR_SRC_BA TT PWR_WALL 0 9 0 8 PWR_USB 0 4:0 MAIN_STATE[ 4:0] 0_0000 w PP, December 2009, Rev 3.0 186 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0_1011 = PROGRAM 0_1100 = PROG_DN 0_1101 = PROG_OTP 0_1110 = VFY_OTP 0_1111 = VFY_DN 1_0000 = SD_RD_OTP 1_0001 = UNUSED 1_0010 = DBE_FAIL 1_0011 = SHUTDOWN 1_0100 = STARTFAIL 1_0101 = STARTUP 1_0110 = PREACTIVE 1_0111 = XTAL_CHK 1_1000 = PWRDN2 1_1001 = SHUT_DLY 1_1010 = RESET 1_1011 = RESET_DLY 1_1100 = SLEEP 1_1101 = SLEEP_DLY 1_1110 = CHK_RST 1_1111 = ACTIVE (ON) Register 400Dh System Status WM8312 REFER TO REGISTER ADDRESS R16398 (400Eh) ON Source BIT 15 LABEL ON_TRANS DEFAULT 0 DESCRIPTION Most recent ON/WAKE event type 0 = WAKE transition 1 = ON transition Reset by state machine. Most recent ON/WAKE event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Reset by state machine. Most recent WAKE event type 0 = Not caused by SYSVDD 1 = Caused by SYSLO threshold. Note that the SYSLO threshold cannot trigger an ON event. Reset by state machine. Most recent WAKE event type 0 = Not caused by Pen Down 1 = Caused by Touch Panel Pen Down detection. Note that the Pen Down detection cannot trigger an ON event. Reset by state machine. Most recent WAKE event type 0 = Not caused by Battery Charger 1 = Caused by Battery Charger TBC if this could cause ON due to Charger plugged in? Reset by state machine. Most recent WAKE event type 0 = Not caused by Watchdog timer 1 = Caused by Watchdog timer Reset by state machine. REFER TO 11 ON_GPIO 0 10 ON_SYSLO 0 9 ON_PEN_DO WN 0 8 ON_CHG 0 7 ON_WDOG_T O 0 w PP, December 2009, Rev 3.0 187 WM8312 REGISTER ADDRESS BIT 6 LABEL ON_SW_REQ DEFAULT 0 DESCRIPTION Most recent WAKE event type 0 = Not caused by software WAKE 1 = Caused by software WAKE command (CHIP_SLP = 0) Reset by state machine. Most recent ON/WAKE event type 0 = Not caused by RTC Alarm 1 = Caused by RTC Alarm Reset by state machine. Most recent ON/WAKE event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Reset by state machine. Most recent ON event type 0 = Not caused by undervoltage 1 = Caused by a Device Reset due to a Converter (LDO or DC-DC) undervoltage condition Reset by state machine. Most recent ON event type 0 = Not caused by Software Reset 1 = Caused by Software Reset Reset by state machine. Most recent ON event type 0 = Not caused by Hardware Reset 1 = Caused by Hardware Reset Reset by state machine. Most recent ON event type 0 = Not caused by the Watchdog 1 = Caused by a Device Reset triggered by the Watchdog timer Reset by state machine. Pre-Production REFER TO 5 ON_RTC_ALM 0 4 ON_ON_PIN 0 3 RESET_CNV_ UV 0 2 RESET_SW 0 1 RESET_HW 0 0 RESET_WDO G 0 Register 400Eh ON Source REGISTER ADDRESS R16399 (400Fh) OFF Source BIT 13 LABEL OFF_INTLDO_ ERR DEFAULT 0 DESCRIPTION Most recent OFF event type 0 = Not caused by LDO13 Error condition 1 = Caused by LDO13 Error condition Reset by state machine. Most recent OFF event type 0 = Not caused by Power Sequence Failure 1 = Caused by a Power Sequence Failure Reset by state machine. Most recent OFF event type 0 = Not caused by GPIO input 1 = Caused by GPIO input Reset by state machine. Most recent OFF event type 0 = Not caused by SYSVDD 1 = Caused by the SYSLO or SHUTDOWN threshold Reset by state machine. Most recent OFF event type REFER TO 12 OFF_PWR_SE Q 0 11 OFF_GPIO 0 10 OFF_SYSVDD 0 9 OFF_THERR 0 w PP, December 2009, Rev 3.0 188 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 = Not caused by temperature 1 = Caused by over-temperature Reset by state machine. 6 OFF_SW_REQ 0 Most recent OFF event type 0 = Not caused by software OFF 1 = Caused by software OFF command (CHIP_ON = 0) Reset by state machine. Most recent OFF event type 0 = Not caused by the ON pin 1 = Caused by the ON pin Reset by state machine. WM8312 REFER TO 4 OFF_ON_PIN 0 Register 400Fh OFF Source REGISTER ADDRESS R16400 (4010h) System Interrupts BIT 15 LABEL PS_INT DEFAULT 0 DESCRIPTION Power State primary interrupt 0 = No interrupt 1 = Interrupt is asserted Thermal primary interrupt 0 = No interrupt 1 = Interrupt is asserted GPIO primary interrupt 0 = No interrupt 1 = Interrupt is asserted ON Pin primary interrupt 0 = No interrupt 1 = Interrupt is asserted Watchdog primary interrupt 0 = No interrupt 1 = Interrupt is asserted Touch Panel Data primary interrupt 0 = No interrupt 1 = Interrupt is asserted Touch Panel Pen Down primary interrupt 0 = No interrupt 1 = Interrupt is asserted AUXADC primary interrupt 0 = No interrupt 1 = Interrupt is asserted Power Path Management primary interrupt 0 = No interrupt 1 = Interrupt is asserted Current Sink primary interrupt 0 = No interrupt 1 = Interrupt is asserted Real Time Clock primary interrupt 0 = No interrupt 1 = Interrupt is asserted OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted Battery Charger primary interrupt REFER TO 14 TEMP_INT 0 13 GP_INT 0 12 ON_PIN_INT 0 11 WDOG_INT 0 10 TCHDATA_INT 0 9 TCHPD_INT 0 8 AUXADC_INT 0 7 PPM_INT 0 6 CS_INT 0 5 RTC_INT 0 4 OTP_INT 0 2 CHG_INT 0 w PP, December 2009, Rev 3.0 189 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 = No interrupt 1 = Interrupt is asserted 1 HC_INT 0 High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted Pre-Production REFER TO 0 UV_INT 0 Register 4010h System Interrupts REGISTER ADDRESS R16401 (4011h) Interrupt Status 1 BIT 15 LABEL PPM_SYSLO_ EINT PPM_PWR_S RC_EINT PPM_USB_CU RR_EINT ON_PIN_CINT DEFAULT 0 DESCRIPTION Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path Source interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power Path USB Current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a `1' is written. Touch panel Data interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Touch panel Pen Down interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. AUXADC Digital Comparator 4 interrupt (Trigger is controlled by DCMP4_GT) Note: Cleared when a `1' is written. AUXADC Digital Comparator 3 interrupt (Trigger is controlled by DCMP3_GT) Note: Cleared when a `1' is written. AUXADC Digital Comparator 2 interrupt (Trigger is controlled by DCMP2_GT) Note: Cleared when a `1' is written. AUXADC Digital Comparator 1 interrupt (Trigger is controlled by DCMP1_GT) Note: Cleared when a `1' is written. RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. REFER TO 14 0 13 0 12 0 11 WDOG_TO_EI NT TCHDATA_EIN T TCHPD_EINT 0 10 0 9 0 8 AUXADC_DAT A_EINT AUXADC_DCO MP4_EINT AUXADC_DCO MP3_EINT AUXADC_DCO MP2_EINT AUXADC_DCO MP1_EINT RTC_PER_EIN T 0 7 0 6 0 5 0 4 0 3 0 w PP, December 2009, Rev 3.0 190 Pre-Production REGISTER ADDRESS BIT 2 LABEL RTC_ALM_EIN T TEMP_THW_C INT DEFAULT 0 DESCRIPTION RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Thermal Warning interrupt (Rising and Falling Edge triggered) Note: Cleared when a `1' is written. WM8312 REFER TO 1 0 Register 4011h Interrupt Status 1 REGISTER ADDRESS R16402 (4012h) Interrupt Status 2 BIT 15 LABEL CHG_BATT_H OT_EINT CHG_BATT_C OLD_EINT CHG_BATT_F AIL_EINT CHG_OV_EIN T CHG_END_EI NT DEFAULT 0 DESCRIPTION Battery Hot interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Cold interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Overvoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge End interrupt (End of Charge Current threshold reached) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Timeout interrupt (Charger Timer has expired) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Mode interrupt (Charger Mode has changed) (Rising Edge triggered) Note: Cleared when a `1' is written. Battery Charge Start interrupt (Charging has started) (Rising Edge triggered) Note: Cleared when a `1' is written. Current Sink 2 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Current Sink 1 interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. OTP / DBE Command End interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. OTP / DBE Command Fail interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. Power On Reset interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. REFER TO 14 0 13 0 12 0 11 0 10 CHG_TO_EINT 0 9 CHG_MODE_E INT 0 8 CHG_START_ EINT CS2_EINT 0 7 0 6 CS1_EINT 0 5 OTP_CMD_EN D_EINT OTP_ERR_EIN T PS_POR_EINT 0 4 0 2 0 w PP, December 2009, Rev 3.0 191 WM8312 REGISTER ADDRESS BIT 1 LABEL PS_SLEEP_O FF_EINT DEFAULT 0 DESCRIPTION SLEEP or OFF interrupt (Power state transition to SLEEP or OFF states) (Rising Edge triggered) Note: Cleared when a `1' is written. ON or WAKE interrupt (Power state transition to ON state) (Rising Edge triggered) Note: Cleared when a `1' is written. Pre-Production REFER TO 0 PS_ON_WAKE _EINT 0 Register 4012h Interrupt Status 2 REGISTER ADDRESS R16403 (4013h) Interrupt Status 3 BIT 9 LABEL UV_LDO10_EI NT UV_LDO9_EIN T UV_LDO8_EIN T UV_LDO7_EIN T UV_LDO6_EIN T UV_LDO5_EIN T UV_LDO4_EIN T UV_LDO3_EIN T UV_LDO2_EIN T UV_LDO1_EIN T DEFAULT 0 DESCRIPTION LDO10 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO9 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO8 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO7 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO6 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO5 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO4 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO3 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO2 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. LDO1 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. REFER TO 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Register 4013h Interrupt Status 3 w PP, December 2009, Rev 3.0 192 Pre-Production REGISTER ADDRESS R16404 (4014h) Interrupt Status 4 BIT 9 LABEL HC_DC2_EINT DEFAULT 0 DESCRIPTION DC-DC2 High current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC1 High current interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC4 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC3 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC2 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. DC-DC1 Undervoltage interrupt (Rising Edge triggered) Note: Cleared when a `1' is written. WM8312 REFER TO 8 HC_DC1_EINT 0 3 UV_DC4_EINT 0 2 UV_DC3_EINT 0 1 UV_DC2_EINT 0 0 UV_DC1_EINT 0 Register 4014h Interrupt Status 4 REGISTER ADDRESS R16405 (4015h) Interrupt Status 5 BIT 15 LABEL GP16_EINT DEFAULT 0 DESCRIPTION GPIO16 interrupt. (Trigger is controlled by GP16_INT_MODE) Note: Cleared when a `1' is written. GPIO15 interrupt. (Trigger is controlled by GP15_INT_MODE) Note: Cleared when a `1' is written. GPIO14 interrupt. (Trigger is controlled by GP14_INT_MODE) Note: Cleared when a `1' is written. GPIO13 interrupt. (Trigger is controlled by GP13_INT_MODE) Note: Cleared when a `1' is written. GPIO12 interrupt. (Trigger is controlled by GP12_INT_MODE) Note: Cleared when a `1' is written. GPIO11 interrupt. (Trigger is controlled by GP11_INT_MODE) Note: Cleared when a `1' is written. GPIO10 interrupt. (Trigger is controlled by GP10_INT_MODE) Note: Cleared when a `1' is written. GPIO9 interrupt. (Trigger is controlled by GP9_INT_MODE) Note: Cleared when a `1' is written. GPIO8 interrupt. (Trigger is controlled by GP8_INT_MODE) Note: Cleared when a `1' is written. GPIO7 interrupt. (Trigger is controlled by GP7_INT_MODE) Note: Cleared when a `1' is written. REFER TO 14 GP15_EINT 0 13 GP14_EINT 0 12 GP13_EINT 0 11 GP12_EINT 0 10 GP11_EINT 0 9 GP10_EINT 0 8 GP9_EINT 0 7 GP8_EINT 0 6 GP7_EINT 0 w PP, December 2009, Rev 3.0 193 WM8312 REGISTER ADDRESS BIT 5 LABEL GP6_EINT DEFAULT 0 DESCRIPTION GPIO6 interrupt. (Trigger is controlled by GP6_INT_MODE) Note: Cleared when a `1' is written. GPIO5 interrupt. (Trigger is controlled by GP5_INT_MODE) Note: Cleared when a `1' is written. GPIO4 interrupt. (Trigger is controlled by GP4_INT_MODE) Note: Cleared when a `1' is written. GPIO3 interrupt. (Trigger is controlled by GP3_INT_MODE) Note: Cleared when a `1' is written. GPIO2 interrupt. (Trigger is controlled by GP2_INT_MODE) Note: Cleared when a `1' is written. GPIO1 interrupt. (Trigger is controlled by GP1_INT_MODE) Note: Cleared when a `1' is written. Pre-Production REFER TO 4 GP5_EINT 0 3 GP4_EINT 0 2 GP3_EINT 0 1 GP2_EINT 0 0 GP1_EINT 0 Register 4015h Interrupt Status 5 REGISTER ADDRESS R16407 (4017h) IRQ Config BIT 1 LABEL IRQ_OD DEFAULT 1 DESCRIPTION IRQ pin configuration 0 = CMOS 1 = Open Drain IRQ pin output mask 0 = Normal 1 = IRQ output is masked REFER TO 0 IM_IRQ 0 Register 4017h IRQ Config REGISTER ADDRESS R16408 (4018h) System Interrupts Mask BIT 15 LABEL IM_PS_INT DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. REFER TO 14 IM_TEMP_INT 1 13 IM_GP_INT 1 12 IM_ON_PIN_IN T 1 11 IM_WDOG_IN T 1 w PP, December 2009, Rev 3.0 194 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Default value is 1 (masked) 10 IM_TCHDATA_ INT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) WM8312 REFER TO 9 IM_TCHPD_IN T 1 8 IM_AUXADC_I NT 1 7 IM_PPM_INT 1 6 IM_CS_INT 1 5 IM_RTC_INT 1 4 IM_OTP_INT 1 2 IM_CHG_INT 1 1 IM_HC_INT 1 0 IM_UV_INT 1 Register 4018h System Interrupts Mask REGISTER ADDRESS R16409 (4019h) Interrupt Status 1 Mask BIT 15 LABEL IM_PPM_SYSL O_EINT DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. REFER TO 14 IM_PPM_PWR _SRC_EINT 1 w PP, December 2009, Rev 3.0 195 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Default value is 1 (masked) 13 IM_PPM_USB_ CURR_EINT 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Pre-Production REFER TO 12 IM_ON_PIN_CI NT 1 11 IM_WDOG_TO _EINT 1 10 IM_TCHDATA_ EINT 1 9 IM_TCHPD_EI NT 1 8 IM_AUXADC_ DATA_EINT 1 7 IM_AUXADC_ DCOMP4_EIN T IM_AUXADC_ DCOMP3_EIN T IM_AUXADC_ DCOMP2_EIN T IM_AUXADC_ DCOMP1_EIN T IM_RTC_PER_ EINT 1 6 1 5 1 4 1 3 1 2 IM_RTC_ALM_ EINT 1 1 IM_TEMP_TH W_CINT 1 Register 4019h Interrupt Status 1 Mask w PP, December 2009, Rev 3.0 196 Pre-Production WM8312 BIT 15 LABEL IM_CHG_BATT _HOT_EINT DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. PP, December 2009, Rev 3.0 197 REFER TO REGISTER ADDRESS R16410 (401Ah) Interrupt Status 2 Mask 14 IM_CHG_BATT _COLD_EINT 1 13 IM_CHG_BATT _FAIL_EINT 1 12 IM_CHG_OV_ EINT 1 11 IM_CHG_END _EINT 1 10 IM_CHG_TO_ EINT 1 9 IM_CHG_MOD E_EINT 1 8 IM_CHG_STA RT_EINT 1 7 IM_CS2_EINT 1 6 IM_CS1_EINT 1 5 IM_OTP_CMD _END_EINT 1 4 IM_OTP_ERR_ EINT 1 2 IM_PS_POR_E INT 1 1 IM_PS_SLEEP 1 w WM8312 REGISTER ADDRESS BIT LABEL _OFF_EINT DEFAULT DESCRIPTION 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Pre-Production REFER TO 0 IM_PS_ON_W AKE_EINT Register 401Ah Interrupt Status 2 Mask REGISTER ADDRESS R16411 (401Bh) Interrupt Status 3 Mask BIT 9 LABEL IM_UV_LDO10 _EINT DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) REFER TO 8 IM_UV_LDO9_ EINT 1 7 IM_UV_LDO8_ EINT 1 6 IM_UV_LDO7_ EINT 1 5 IM_UV_LDO6_ EINT 1 4 IM_UV_LDO5_ EINT 1 3 IM_UV_LDO4_ EINT 1 2 IM_UV_LDO3_ EINT 1 1 IM_UV_LDO2_ EINT 1 0 IM_UV_LDO1_ EINT 1 Register 401Bh Interrupt Status 3 Mask w PP, December 2009, Rev 3.0 198 Pre-Production WM8312 BIT 9 LABEL IM_HC_DC2_E INT DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) REFER TO REGISTER ADDRESS R16412 (401Ch) Interrupt Status 4 Mask 8 IM_HC_DC1_E INT 1 3 IM_UV_DC4_E INT 1 2 IM_UV_DC3_E INT 1 1 IM_UV_DC2_E INT 1 0 IM_UV_DC1_E INT 1 Register 401Ch Interrupt Status 4 Mask REGISTER ADDRESS R16413 (401Dh) Interrupt Status 5 Mask BIT 15 LABEL IM_GP16_EIN T DEFAULT 1 DESCRIPTION Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. REFER TO 14 IM_GP15_EIN T 1 13 IM_GP14_EIN T 1 12 IM_GP13_EIN T 1 11 IM_GP12_EIN T 1 10 IM_GP11_EIN T 1 w PP, December 2009, Rev 3.0 199 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Default value is 1 (masked) 9 IM_GP10_EIN T 1 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Default value is 1 (masked) Pre-Production REFER TO 8 IM_GP9_EINT 1 7 IM_GP8_EINT 1 6 IM_GP7_EINT 1 5 IM_GP6_EINT 1 4 IM_GP5_EINT 1 3 IM_GP4_EINT 1 2 IM_GP3_EINT 1 1 IM_GP2_EINT 1 0 IM_GP1_EINT 1 Register 401Dh Interrupt Status 5 Mask REGISTER ADDRESS R16416 (4020h) RTC Write Counter BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO RTC_WR_CNT 0000_0000 RTC Write Counter. [15:0] _0000_000 This random number is updated on every write to the 0 RTC_TIME registers. Register 4020h RTC Write Counter w PP, December 2009, Rev 3.0 200 Pre-Production REGISTER ADDRESS R16417 (4021h) RTC Time 1 BIT 15:0 LABEL DEFAULT DESCRIPTION WM8312 REFER TO RTC_TIME[15: 0000_0000 RTC Seconds counter (MSW) 0] _0000_000 RTC_TIME increments by 1 every second. This is the 0 16 MSBs. Register 4021h RTC Time 1 REGISTER ADDRESS R16418 (4022h) RTC Time 2 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO RTC_TIME[15: 0000_0000 RTC Seconds counter (LSW) 0] _0000_000 RTC_TIME increments by 1 every second. This is the 0 16 LSBs. Register 4022h RTC Time 2 REGISTER ADDRESS R16419 (4023h) RTC Alarm 1 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO RTC_ALM[15:0 0000_0000 RTC Alarm time (MSW) ] _0000_000 16 MSBs of RTC_ALM 0 Register 4023h RTC Alarm 1 REGISTER ADDRESS R16420 (4024h) RTC Alarm 2 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO RTC_ALM[15:0 0000_0000 RTC Alarm time (LSW) ] _0000_000 16 LSBs of RTC_ALM 0 Register 4024h RTC Alarm 2 REGISTER ADDRESS R16421 (4025h) RTC Control BIT 15 LABEL RTC_VALID DEFAULT 0 DESCRIPTION RTC Valid status 0 = RTC_TIME has not been set since Power On Reset 1 = RTC_TIME has been written to since Power On Reset RTC Busy status 0 = Normal 1 = Busy The RTC registers should not be written to when RTC_SYNC_BUSY = 1. RTC Alarm Enable 0 = Disabled 1 = Enabled RTC Periodic Interrupt timeout period 000 = Disabled 001 = 1s 010 = 2s 011 = 4s 100 = 8s 101 = 16s 110 = 32s REFER TO 14 RTC_SYNC_B USY 0 10 RTC_ALM_EN A RTC_PINT_FR EQ[2:0] 0 6:4 000 w PP, December 2009, Rev 3.0 201 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT 111 = 64s Register 4025h RTC Control DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16422 (4026h) RTC Trim BIT 9:0 LABEL DEFAULT DESCRIPTION REFER TO RTC_TRIM[9:0] 00_0000_0 RTC frequency trim. Value is a 10bit fixed point <4,6> 2's complement number. MSB Scaling = -8Hz. 000 The register indicates the error (in Hz) with respect to the ideal 32768Hz) of the input crystal frequency. Protected by security key. Register 4026h RTC Trim REGISTER ADDRESS R16424 (4028h) Touch Control 1 BIT 15 LABEL TCH_ENA DEFAULT 0 DESCRIPTION Touch Panel Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Touch Panel Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (TCH_RATE = 0), setting this bit will initiate a set of conversion; the bit is reset at the end of the conversion. Touch Panel SLEEP Enable 0 = Disabled 1 = Controlled by TCH_ENA Enables Z-axis touch panel measurements. (Z-axis is the pressure axis - 4-wire only.) 0 = Disabled 1 = Enabled Enables Y-axis touch panel measurements 0 = Disabled 1 = Enabled Enables X-axis touch panel measurements 0 = Disabled 1 = Enabled Settling time between X, Y and Z measurements. (Nominal timing only; typically +/-20% of quoted values.) 000 = 30us 001 = 60us 010 = 120us 011 = 240us 100 = 480us 101 = 960us 110 = 1920us 111 = 3840us REFER TO 14 TCH_CVT_EN A 0 12 TCH_SLPENA 0 10 TCH_Z_ENA 0 9 TCH_Y_ENA 0 8 TCH_X_ENA 0 7:5 TCH_DELAY[2: 0] 010 w PP, December 2009, Rev 3.0 202 Pre-Production REGISTER ADDRESS BIT 4:0 LABEL TCH_RATE[4:0 ] DEFAULT 0_0000 DESCRIPTION Touch-panel Conversion Rate 0 = Manual 1 = 16 packets/s 2 = 32 packets/s 3 = 48 packets/s ... 31 = 496 packets/s WM8312 REFER TO Register 4028h Touch Control 1 REGISTER ADDRESS R16425 (4029h) Touch Control 2 BIT 13 LABEL TCH_PD_WK DEFAULT 0 DESCRIPTION WAKE transition select for Pen Down event 0 = Disabled 1 = Enabled Touch Panel control mode 0 = 4-wire 1 = 5-wire Select Automatic conversions only when Pen Down is detected. (No effect on Manual conversion.) 0 = Normal 1 = Pen-Down only Pressure measurement current select 0 = 200uA 1 = 400uA Note - this applies to 4-wire mode only Pen-Down sensitivity (pull-up resistor) 0000 = 64k (most sensitive) 0001 = 64k / 2 0010 = 64k / 3 0011 = 64k / 4 .... 1111 = 64k / 16 (least sensitive) REFER TO 12 TCH_5WIRE 0 11 TCH_PDONLY 0 8 TCH_ISEL 0 3:0 TCH_RPU[3:0] 0111 Register 4029h Touch Control 2 REGISTER ADDRESS R16426 (402Ah) Touch Data X BIT 15 LABEL TCH_PD1 DEFAULT 0 DESCRIPTION Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected REFER TO 11:0 TCH_X[11:0] 0000_0000 Touch panel X-axis data _0000 (12-bit unsigned binary number) Register 402Ah Touch Data X w PP, December 2009, Rev 3.0 203 WM8312 REGISTER ADDRESS R16427 (402Bh) Touch Data Y BIT 15 LABEL TCH_PD2 DEFAULT 0 DESCRIPTION Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected Pre-Production REFER TO 11:0 TCH_Y[11:0] 0000_0000 Touch panel Y-axis data _0000 (12-bit unsigned binary number) Register 402Bh Touch Data Y REGISTER ADDRESS R16428 (402Ch) Touch Data Z BIT 15 LABEL TCH_PD3 DEFAULT 0 DESCRIPTION Pen down status (indicates if the Pen Down was detected prior to the TP measurement) 0 = Pen Down not detected 1 = Pen Down detected REFER TO 11:0 TCH_Z[11:0] 0000_0000 Touch panel Z-axis data _0000 (12-bit unsigned binary number) Register 402Ch Touch Data Z REGISTER ADDRESS R16429 (402Dh) AuxADC Data BIT 15:12 LABEL AUX_DATA_S RC[3:0] DEFAULT 0000 DESCRIPTION AUXADC Data Source 0 = Reserved 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage 8 = USB voltage 9 = BATT voltage 10 = WALL voltage 11 = Backup Battery voltage 12 = Reserved 13 = Reserved 14 = Reserved 15 = Calibration source (internal 0.8V) REFER TO 11:0 AUX_DATA[11: 0000_0000 AUXADC Measurement Data 0] _0000 Voltage (mV) = AUX_DATA x 1.465 ChipTemp (C) = (512.18 - AUX_DATA) / 1.0983 BattTemp (C) = (value is dependent on NTC thermistor) Register 402Dh AuxADC Data w PP, December 2009, Rev 3.0 204 Pre-Production REGISTER ADDRESS R16430 (402Eh) AuxADC Control BIT 15 LABEL AUX_ENA DEFAULT 0 DESCRIPTION AUXADC Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. AUXADC Conversion Enable 0 = Disabled 1 = Enabled In automatic mode, conversions are enabled by setting this bit. In manual mode (AUX_RATE = 0), setting this bit will initiate a conversion; the bit is reset at the end of the conversion. AUXADC SLEEP Enable 0 = Disabled 1 = Controlled by AUX_ENA AUXADC Conversion Rate 0 = Manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s ... 31 = 62 samples/s 32 = Reserved 33 = 16 samples/s 34 = 32 samples/s 35 = 48 samples/s ... 63 = 496 samples/s WM8312 REFER TO 14 AUX_CVT_EN A 0 12 AUX_SLPENA 0 5:0 AUX_RATE[5:0 ] 00_0000 Register 402Eh AuxADC Control REGISTER ADDRESS R16431 (402Fh) AuxADC Source BIT 10 LABEL AUX_BKUP_B ATT_SEL AUX_WALL_S EL AUX_BATT_S EL AUX_USB_SE L AUX_SYSVDD _SEL AUX_BATT_TE MP_SEL AUX_CHIP_TE MP_SEL DEFAULT 0 DESCRIPTION AUXADC BACKUP input select 0 = Disable BACKUPVDD measurement 1 = Enable BACKUPVDD measurement AUXADC WALL input select 0 = Disable WALLVDD measurement 1 = Enable WALLVDD measurement AUXADC BATT input select 0 = Disable BATTVDD measurement 1 = Enable BATTVDD measurement AUXADC USB input select 0 = Disable USBVDD measurement 1 = Enable USBVDD measurement AUXADC SYSVDD input select 0 = Disable SYSVDD measurement 1 = Enable SYSVDD measurement AUXADC Battery Temp input select 0 = Disable Battery Temp measurement 1 = Enable Battery Temp measurement AUXADC Chip Temp input select 0 = Disable Chip Temp measurement REFER TO 9 0 8 0 7 0 6 0 5 0 4 0 w PP, December 2009, Rev 3.0 205 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1 = Enable Chip Temp measurement 3 AUX_AUX4_S EL AUX_AUX3_S EL AUX_AUX2_S EL AUX_AUX1_S EL 0 AUXADCIN4 input select 0 = Disable AUXADCIN4 measurement 1 = Enable AUXADCIN4 measurement AUXADCIN3 input select 0 = Disable AUXADCIN3 measurement 1 = Enable AUXADCIN3 measurement AUXADCIN2 input select 0 = Disable AUXADCIN2 measurement 1 = Enable AUXADCIN2 measurement AUXADCIN1 input select 0 = Disable AUXADCIN1 measurement 1 = Enable AUXADCIN1 measurement Pre-Production REFER TO 2 0 1 0 0 0 Register 402Fh AuxADC Source REGISTER ADDRESS R16432 (4030h) Comparator Control BIT 11 LABEL DCOMP4_STS DEFAULT 0 DESCRIPTION Digital Comparator 4 status 0 = Comparator 4 threshold not detected 1 = Comparator 4 threshold detected (Trigger is controlled by DCMP4_GT) Digital Comparator 3 status 0 = Comparator 3 threshold not detected 1 = Comparator 3 threshold detected (Trigger is controlled by DCMP3_GT) Digital Comparator 2 status 0 = Comparator 2 threshold not detected 1 = Comparator 2 threshold detected (Trigger is controlled by DCMP2_GT) Digital Comparator 1 status 0 = Comparator 1 threshold not detected 1 = Comparator 1 threshold detected (Trigger is controlled by DCMP1_GT) Digital Comparator 4 Enable 0 = Disabled 1 = Enabled Digital Comparator 3 Enable 0 = Disabled 1 = Enabled Digital Comparator 2 Enable 0 = Disabled 1 = Enabled Digital Comparator 1 Enable 0 = Disabled 1 = Enabled REFER TO 10 DCOMP3_STS 0 9 DCOMP2_STS 0 8 DCOMP1_STS 0 3 DCMP4_ENA 0 2 DCMP3_ENA 0 1 DCMP2_ENA 0 0 DCMP1_ENA 0 Register 4030h Comparator Control w PP, December 2009, Rev 3.0 206 Pre-Production REGISTER ADDRESS R16433 (4031h) Comparator 1 BIT 15:13 LABEL DCMP1_SRC[2 :0] DEFAULT 000 DESCRIPTION Digital Comparator 1 source select 0 = USB voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold WM8312 REFER TO 12 DCMP1_GT 0 11:0 DCMP1_THR[1 0000_0000 Digital Comparator 1 threshold 1:0] _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4031h Comparator 1 REGISTER ADDRESS R16434 (4032h) Comparator 2 BIT 15:13 LABEL DCMP2_SRC[2 :0] DEFAULT 000 DESCRIPTION Digital Comparator 2 source select 0 = WALL voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold REFER TO 12 DCMP2_GT 0 11:0 DCMP2_THR[1 0000_0000 Digital Comparator 2 threshold 1:0] _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4032h Comparator 2 REGISTER ADDRESS R16435 (4033h) Comparator 3 BIT 15:13 LABEL DCMP3_SRC[2 :0] DEFAULT 000 DESCRIPTION Digital Comparator 3 source select 0 = BATT voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold REFER TO 12 DCMP3_GT 0 11:0 DCMP3_THR[1 0000_0000 Digital Comparator 3 threshold 1:0] _0000 (12-bit unsigned binary number; coding is the same as PP, December 2009, Rev 3.0 207 w WM8312 REGISTER ADDRESS BIT LABEL DEFAULT AUX_DATA) Register 4033h Comparator 3 DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16436 (4034h) Comparator 4 BIT 15:13 LABEL DCMP4_SRC[2 :0] DEFAULT 000 DESCRIPTION Digital Comparator 4 source select 0 = Backup Battery voltage 1 = AUXADCIN1 2 = AUXADCIN2 3 = AUXADCIN3 4 = AUXADCIN4 5 = Chip Temperature 6 = Battery Temperature 7 = SYSVDD voltage Digital Comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold REFER TO 12 DCMP4_GT 0 11:0 DCMP4_THR[1 0000_0000 Digital Comparator 4 threshold 1:0] _0000 (12-bit unsigned binary number; coding is the same as AUX_DATA) Register 4034h Comparator 4 REGISTER ADDRESS R16440 (4038h) GPIO1 Control BIT 15 LABEL GP1_DIR DEFAULT 1 DESCRIPTION GPIO1 pin direction 0 = Output 1 = Input GPIO1 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=1) or falling edge triggered (if GP1_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO1 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO1 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO1 Output pin configuration 0 = CMOS 1 = Open Drain GPIO1 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO1 Pin Function Input functions: REFER TO 14:13 GP1_PULL[1:0] 01 12 GP1_INT_MO DE 0 11 GP1_PWR_DO M GP1_POL 0 10 1 9 GP1_OD 0 7 GP1_ENA 0 3:0 GP1_FN[3:0] 0000 w PP, December 2009, Rev 3.0 208 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4038h GPIO1 Control WM8312 REFER TO REGISTER ADDRESS R16441 (4039h) GPIO2 Control BIT 15 LABEL GP2_DIR DEFAULT 1 DESCRIPTION GPIO2 pin direction 0 = Output 1 = Input GPIO2 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=1) or falling edge triggered (if GP2_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO2 Power Domain select 0 = DBVDD REFER TO 14:13 GP2_PULL[1:0] 01 12 GP2_INT_MO DE 0 11 GP2_PWR_DO M 0 w PP, December 2009, Rev 3.0 209 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1 = PMICVDD (LDO12) 10 GP2_POL 1 GPIO2 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO2 Output pin configuration 0 = CMOS 1 = Open Drain GPIO2 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO2 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4039h GPIO2 Control Pre-Production REFER TO 9 GP2_OD 0 7 GP2_ENA 0 3:0 GP2_FN[3:0] 0000 w PP, December 2009, Rev 3.0 210 Pre-Production REGISTER ADDRESS R16442 (403Ah) GPIO3 Control BIT 15 LABEL GP3_DIR DEFAULT 1 DESCRIPTION GPIO3 pin direction 0 = Output 1 = Input GPIO3 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO3 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP3_POL=1) or falling edge triggered (if GP3_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO3 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO3 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO3 Output pin configuration 0 = CMOS 1 = Open Drain GPIO3 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO3 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done WM8312 REFER TO 14:13 GP3_PULL[1:0] 01 12 GP3_INT_MO DE 0 11 GP3_PWR_DO M GP3_POL 0 10 1 9 GP3_OD 0 7 GP3_ENA 0 3:0 GP3_FN[3:0] 0000 w PP, December 2009, Rev 3.0 211 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Ah GPIO3 Control Pre-Production REFER TO REGISTER ADDRESS R16443 (403Bh) GPIO4 Control BIT 15 LABEL GP4_DIR DEFAULT 1 DESCRIPTION GPIO4 pin direction 0 = Output 1 = Input GPIO4 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO4 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP4_POL=1) or falling edge triggered (if GP4_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO4 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO4 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO4 Output pin configuration 0 = CMOS 1 = Open Drain GPIO4 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO4 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input REFER TO 14:13 GP4_PULL[1:0] 01 12 GP4_INT_MO DE 0 11 GP4_PWR_DO M GP4_POL 0 10 1 9 GP4_OD 0 7 GP4_ENA 0 3:0 GP4_FN[3:0] 0000 w PP, December 2009, Rev 3.0 212 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Bh GPIO4 Control WM8312 REFER TO REGISTER ADDRESS R16444 (403Ch) GPIO5 Control BIT 15 LABEL GP5_DIR DEFAULT 1 DESCRIPTION GPIO5 pin direction 0 = Output 1 = Input GPIO5 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO5 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP5_POL=1) or falling edge triggered (if GP5_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO5 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO5 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO5 Output pin configuration 0 = CMOS 1 = Open Drain GPIO5 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO5 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input REFER TO 14:13 GP5_PULL[1:0] 01 12 GP5_INT_MO DE 0 11 GP5_PWR_DO M GP5_POL 0 10 1 9 GP5_OD 0 7 GP5_ENA 0 3:0 GP5_FN[3:0] 0000 w PP, December 2009, Rev 3.0 213 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Ch GPIO5 Control Pre-Production REFER TO REGISTER ADDRESS R16445 (403Dh) GPIO6 Control BIT 15 LABEL GP6_DIR DEFAULT 1 DESCRIPTION GPIO6 pin direction 0 = Output 1 = Input GPIO6 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO6 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP6_POL=1) or falling edge triggered (if GP6_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO6 Power Domain select 0 = DBVDD 1 = SYSVDD REFER TO 14:13 GP6_PULL[1:0] 01 12 GP6_INT_MO DE 0 11 GP6_PWR_DO M 0 w PP, December 2009, Rev 3.0 214 Pre-Production REGISTER ADDRESS BIT 10 LABEL GP6_POL DEFAULT 1 DESCRIPTION GPIO6 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO6 Output pin configuration 0 = CMOS 1 = Open Drain GPIO6 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO6 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Dh GPIO6 Control WM8312 REFER TO 9 GP6_OD 0 7 GP6_ENA 0 3:0 GP6_FN[3:0] 0000 w PP, December 2009, Rev 3.0 215 WM8312 REGISTER ADDRESS R16446 (403Eh) GPIO7 Control BIT 15 LABEL GP7_DIR DEFAULT 1 DESCRIPTION GPIO7 pin direction 0 = Output 1 = Input GPIO7 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO7 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP7_POL=1) or falling edge triggered (if GP7_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO7 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO7 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO7 Output pin configuration 0 = CMOS 1 = Open Drain GPIO7 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO7 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done Pre-Production REFER TO 14:13 GP7_PULL[1:0] 01 12 GP7_INT_MO DE 0 11 GP7_PWR_DO M GP7_POL 0 10 1 9 GP7_OD 0 7 GP7_ENA 0 3:0 GP7_FN[3:0] 0000 w PP, December 2009, Rev 3.0 216 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Eh GPIO7 Control WM8312 REFER TO REGISTER ADDRESS R16447 (403Fh) GPIO8 Control BIT 15 LABEL GP8_DIR DEFAULT 1 DESCRIPTION GPIO8 pin direction 0 = Output 1 = Input GPIO8 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO8 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP8_POL=1) or falling edge triggered (if GP8_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO8 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO8 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO8 Output pin configuration 0 = CMOS 1 = Open Drain GPIO8 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO8 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) REFER TO 14:13 GP8_PULL[1:0] 01 12 GP8_INT_MO DE 0 11 GP8_PWR_DO M GP8_POL 0 10 1 9 GP8_OD 0 7 GP8_ENA 0 3:0 GP8_FN[3:0] 0000 w PP, December 2009, Rev 3.0 217 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 403Fh GPIO8 Control Pre-Production REFER TO REGISTER ADDRESS R16448 (4040h) GPIO9 Control BIT 15 LABEL GP9_DIR DEFAULT 1 DESCRIPTION GPIO9 pin direction 0 = Output 1 = Input GPIO9 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO9 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP9_POL=1) or falling edge triggered (if GP9_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO9 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO9 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO9 Output pin configuration 0 = CMOS 1 = Open Drain GPIO9 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO9 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input REFER TO 14:13 GP9_PULL[1:0] 01 12 GP9_INT_MO DE 0 11 GP9_PWR_DO M GP9_POL 0 10 1 9 GP9_OD 0 7 GP9_ENA 0 3:0 GP9_FN[3:0] 0000 w PP, December 2009, Rev 3.0 218 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4040h GPIO9 Control WM8312 REFER TO REGISTER ADDRESS R16449 (4041h) GPIO10 Control BIT 15 LABEL GP10_DIR DEFAULT 1 DESCRIPTION GPIO10 pin direction 0 = Output 1 = Input GPIO10 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO10 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP10_POL=1) or falling edge triggered (if GP10_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO10 Power Domain select 0 = DBVDD 1 = SYSVDD REFER TO 14:13 GP10_PULL[1: 0] 01 12 GP10_INT_MO DE 0 11 GP10_PWR_D OM 0 w PP, December 2009, Rev 3.0 219 WM8312 REGISTER ADDRESS BIT 10 LABEL GP10_POL DEFAULT 1 DESCRIPTION GPIO10 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO10 Output pin configuration 0 = CMOS 1 = Open Drain GPIO10 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO10 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4041h GPIO10 Control Pre-Production REFER TO 9 GP10_OD 0 7 GP10_ENA 0 3:0 GP10_FN[3:0] 0000 w PP, December 2009, Rev 3.0 220 Pre-Production REGISTER ADDRESS R16450 (4042h) GPIO11 Control BIT 15 LABEL GP11_DIR DEFAULT 1 DESCRIPTION GPIO11 pin direction 0 = Output 1 = Input GPIO11 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO11 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP11_POL=1) or falling edge triggered (if GP11_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO11 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO11 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO11 Output pin configuration 0 = CMOS 1 = Open Drain GPIO11 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO11 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete WM8312 REFER TO 14:13 GP11_PULL[1: 0] 01 12 GP11_INT_MO DE 0 11 GP11_PWR_D OM GP11_POL 0 10 1 9 GP11_OD 0 7 GP11_ENA 0 3:0 GP11_FN[3:0] 0000 w PP, December 2009, Rev 3.0 221 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4042h GPIO11 Control Pre-Production REFER TO REGISTER ADDRESS R16451 (4043h) GPIO12 Control BIT 15 LABEL GP12_DIR DEFAULT 1 DESCRIPTION GPIO12 pin direction 0 = Output 1 = Input GPIO12 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO12 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP12_POL=1) or falling edge triggered (if GP12_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO12 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO12 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO12 Output pin configuration 0 = CMOS 1 = Open Drain GPIO12 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO12 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input REFER TO 14:13 GP12_PULL[1: 0] 01 12 GP12_INT_MO DE 0 11 GP12_PWR_D OM GP12_POL 0 10 1 9 GP12_OD 0 7 GP12_ENA 0 3:0 GP12_FN[3:0] 0000 w PP, December 2009, Rev 3.0 222 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4043h GPIO12 Control WM8312 REFER TO REGISTER ADDRESS R16452 (4044h) GPIO13 Control BIT 15 LABEL GP13_DIR DEFAULT 1 DESCRIPTION GPIO13 pin direction 0 = Output 1 = Input GPIO13 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO13 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP13_POL=1) or falling edge triggered (if GP13_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO13 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO13 Output pin configuration 0 = CMOS 1 = Open Drain GPIO13 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO13 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request REFER TO 14:13 GP13_PULL[1: 0] 01 12 GP13_INT_MO DE 0 10 GP13_POL 1 9 GP13_OD 0 7 GP13_ENA 0 3:0 GP13_FN[3:0] 0000 w PP, December 2009, Rev 3.0 223 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4044h GPIO13 Control Pre-Production REFER TO REGISTER ADDRESS R16453 (4045h) GPIO14 Control BIT 15 LABEL GP14_DIR DEFAULT 1 DESCRIPTION GPIO14 pin direction 0 = Output 1 = Input GPIO14 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO14 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP14_POL=1) or falling edge triggered (if GP14_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO14 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO14 Output pin configuration REFER TO 14:13 GP14_PULL[1: 0] 01 12 GP14_INT_MO DE 0 10 GP14_POL 1 9 GP14_OD 0 w PP, December 2009, Rev 3.0 224 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT 0 = CMOS 1 = Open Drain 7 GP14_ENA 0 GPIO14 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO14 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4045h GPIO14 Control DESCRIPTION WM8312 REFER TO 3:0 GP14_FN[3:0] 0000 REGISTER ADDRESS R16454 (4046h) GPIO15 Control BIT 15 LABEL GP15_DIR DEFAULT 1 DESCRIPTION GPIO15 pin direction 0 = Output 1 = Input GPIO15 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved REFER TO 14:13 GP15_PULL[1: 0] 01 w PP, December 2009, Rev 3.0 225 WM8312 REGISTER ADDRESS BIT 12 LABEL GP15_INT_MO DE DEFAULT 0 DESCRIPTION GPIO15 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP15_POL=1) or falling edge triggered (if GP15_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO15 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO15 Output pin configuration 0 = CMOS 1 = Open Drain GPIO15 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO15 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4046h GPIO15 Control Pre-Production REFER TO 10 GP15_POL 1 9 GP15_OD 0 7 GP15_ENA 0 3:0 GP15_FN[3:0] 0000 w PP, December 2009, Rev 3.0 226 Pre-Production REGISTER ADDRESS R16455 (4047h) GPIO16 Control BIT 15 LABEL GP16_DIR DEFAULT 1 DESCRIPTION GPIO16 pin direction 0 = Output 1 = Input GPIO16 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO16 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP16_POL=1) or falling edge triggered (if GP16_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO16 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO16 Output pin configuration 0 = CMOS 1 = Open Drain GPIO16 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO16 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 WM8312 REFER TO 14:13 GP16_PULL[1: 0] 01 12 GP16_INT_MO DE 0 10 GP16_POL 1 9 GP16_OD 0 7 GP16_ENA 0 3:0 GP16_FN[3:0] 0000 w PP, December 2009, Rev 3.0 227 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset Register 4047h GPIO16 Control Pre-Production REFER TO REGISTER ADDRESS R16456 (4048h) Charger Control 1 BIT 15 LABEL CHG_ENA DEFAULT 0 DESCRIPTION Battery Charger Enable 0 = Disable 1 = Enable Protected by security key. Force charging 0 = Normal behaviour 1 = Force charging CHG_FRC enables charging even if the battery voltage is above the restart threshold. It is not recommended to use this feature; there are safety implications in its use. This bit should be reset to 0 after charging has started. Host processor should monitor CHG_MODE_EINT to confirm that charging has started. Protected by security key. Battery End of Charge current threshold 000 = 20mA 001 = 30mA 010 = 40mA 011 = 50mA 100 = 60mA 101 = 70mA 110 = 80mA 111 = 90mA Protected by security key. Battery Fast Charge Enable 0 = Disable 1 = Enable Protected by security key. Enable battery charge current monitor at AUXADCIN1. 0 = Disabled 1 = Enabled (Note - a resistor is required between AUXADCIN1 and GND in order to measure the charge current using the AUXADC. The recommended resistor value is 10k.) Protected by security key. Battery Charger Thermal warning select 0 = Thermal Warning is ignored 1 = Thermal Warning pauses Battery Charger Protected by security key. REFER TO 14 CHG_FRC 0 12:10 CHG_ITERM[2: 0] 000 5 CHG_FAST 0 1 CHG_IMON_E NA 0 0 CHG_CHIP_TE MP_MON 1 Register 4048h Charger Control 1 w PP, December 2009, Rev 3.0 228 Pre-Production REGISTER ADDRESS R16457 (4049h) Charger Control 2 BIT 14 LABEL CHG_OFF_MS K DEFAULT 0 DESCRIPTION Battery Charger OFF mask select 0 = OFF requests not masked 1 = OFF requests masked during Charging Protected by security key. Battery charger timeout 0000 = 60min 0001 = 90min 0010 = 120min 0011 = 150min 0100 = 180min 0101 = 210min 0110 = 240min 0111 = 270min 1000 = 300min 1001 = 330min 1010 = 360min 1011 = 390min 1100 = 420min 1101 = 450min 1110 = 480min 1111 = 510min Protected by security key. Battery Trickle Charge current limit 00 = 50mA 01 = 100mA 10 = 150mA 11 = 200mA Protected by security key. Battery Charger target voltage 00 = 4.05V 01 = 4.10V 10 = 4.15V 11 = 4.20V Note that incorrect setting of this register may lead to a safety hazard condition. Protected by security key. Battery Fast Charge current limit 0000 = 0mA 0001 = 50mA 0010 = 100mA 0011 = 150mA 0100 = 200mA 0101 = 250mA 0110 = 300mA 0111 = 350mA 1000 = 400mA 1001 = 450mA 1010 = 500mA 1011 = 600mA 1100 = 700mA 1101 = 800mA 1110 = 900mA 1111 = 1000mA Protected by security key. WM8312 REFER TO 11:8 CHG_TIME[3:0 ] 0110 7:6 CHG_TRKL_ILI M[1:0] 00 5:4 CHG_VSEL[1:0 ] 00 3:0 CHG_FAST_ILI M[3:0] 0010 Register 4049h Charger Control 2 w PP, December 2009, Rev 3.0 229 WM8312 REGISTER ADDRESS R16458 (404Ah) Charger Status BIT 15 LABEL BATT_OV_ST S CHG_STATE[2 :0] DEFAULT 0 DESCRIPTION Battery Overvoltage status 0 = Normal 1 = Battery Overvoltage Battery Charger state 000 = Off 001 = Trickle Charge 010 = Fast Charge 011 = Trickle Charge overtemperature 100 = Fast Charge overtemperature 101 = Defective 110 = Reserved 111 = Reserved Battery Hot status 0 = Normal 1 = Battery Hot Battery Cold status 0 = Normal 1 = Battery Cold Battery Charger constant-voltage charge mode status 0 = Constant-voltage mode not active 1 = Constant-voltage mode is active Battery Charger status 0 = Not charging 1 = Charging Pre-Production REFER TO 14:12 000 11 BATT_HOT_S TS BATT_COLD_ STS CHG_TOPOFF 0 10 0 9 0 8 CHG_ACTIVE 0 7:0 CHG_TIME_EL 0000_0000 Battery charger elapsed time APSED[7:0] 00h = 0min 01h = 2min 02h = 4min 03h = 6min ... FFh = 510min Register 404Ah Charger Status REGISTER ADDRESS R16459 (404Bh) Backup Charger Control BIT 15 LABEL BKUP_CHG_E NA DEFAULT 0 DESCRIPTION Backup Charger Enable 0 = Disable 1 = Enable Note - this bit is reset to 0 when the OFF power state is entered. Protected by security key. Backup Charger status 0 = Not charging 1 = Charging Backup Charger mode 0 = Constant current and Constant voltage modes enabled 1 = Constant current mode only Protected by security key. Backup Battery detection enable 0 = Disable 1 = Enable REFER TO 14 BKUP_CHG_S TS BKUP_CHG_M ODE 0 12 0 11 BKUP_BATT_ DET_ENA 0 w PP, December 2009, Rev 3.0 230 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Note - this bit is reset to 0 when the OFF power state is entered. 10 BKUP_BATT_ STS BKUP_CHG_V LIM 0 Backup Battery detection status 0 = Backup battery not present 1 = Backup battery is present Backup Charger voltage limit 0 = 2.5V 1 = 3.1V Protected by security key. Backup Charger current limit 00 = 100uA 01 = 200uA 10 = 300uA 11 = 400uA Protected by security key. WM8312 REFER TO 4 0 1:0 BKUP_CHG_IL IM[1:0] 00 Register 404Bh Backup Charger Control REGISTER ADDRESS R16460 (404Ch) Status LED 1 BIT 15:14 LABEL LED1_SRC[1:0 ] DEFAULT 11 DESCRIPTION LED1 Source (Selects the LED1 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program LED1 Mode (Controls LED1 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence LED1 Pulse Sequence Length (when LED1_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses LED1 On time (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms LED1 Duty Cycle (On:Off ratio) (when LED1_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) REFER TO 9:8 LED1_MODE[1 :0] 00 5:4 LED1_SEQ_LE N[1:0] 10 3:2 LED1_DUR[1:0 ] 01 1:0 LED1_DUTY_ CYC[1:0] 10 Register 404Ch Status LED 1 w PP, December 2009, Rev 3.0 231 WM8312 REGISTER ADDRESS R16461 (404Dh) Status LED 2 BIT 15:14 LABEL LED2_SRC[1:0 ] DEFAULT 11 DESCRIPTION LED2 Source (Selects the LED2 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED2 also indicates an OTP Auto Program Error condition LED2 Mode (Controls LED2 in Manual Mode only.) 00 = Off 01 = Constant 10 = Continuous Pulsed 11 = Pulsed Sequence LED2 Pulse Sequence Length (when LED2_MODE = Pulsed Sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses LED2 On time (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms LED2 Duty Cycle (On:Off ratio) (when LED2_MODE = Continuous Pulsed or Pulsed Sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) Pre-Production REFER TO 9:8 LED2_MODE[1 :0] 00 5:4 LED2_SEQ_LE N[1:0] 10 3:2 LED2_DUR[1:0 ] 01 1:0 LED2_DUTY_ CYC[1:0] 10 Register 404Dh Status LED 2 REGISTER ADDRESS R16462 (404Eh) Current Sink 1 BIT 15 LABEL CS1_ENA DEFAULT 0 DESCRIPTION Current Sink 1 Enable (ISINK1 pin) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Current Sink 1 output drive enable 0 = Disabled 1 = Enabled Current Sink 1 status 0 = Normal 1 = Sink current cannot be regulated Current Sink 1 SLEEP Enable 0 = Disabled 1 = Controlled by CS1_ENA REFER TO 14 CS1_DRIVE 0 13 CS1_STS 0 12 CS1_SLPENA 0 w PP, December 2009, Rev 3.0 232 Pre-Production REGISTER ADDRESS BIT 11:10 LABEL CS1_OFF_RA MP[1:0] DEFAULT 01 DESCRIPTION ISINK1 Switch-Off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. ISINK1 Switch-On ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. ISINK1 current. Current = 2.0A x 2^(CS1_ISEL/4), where CS1_ISEL is an unsigned binary number. Alternatively, CS1_ISEL = 13.29 x LOG(current/2.0A) 00_0000 = 2.0A 11_0111 = 27.6mA Values greater than 11_0111 will result in the maximum current of approx 27.6mA. Register 404Eh Current Sink 1 WM8312 REFER TO 9:8 CS1_ON_RAM P[1:0] 01 5:0 CS1_ISEL[5:0] 00_0000 REGISTER ADDRESS R16463 (404Fh) Current Sink 2 BIT 15 LABEL CS2_ENA DEFAULT 0 DESCRIPTION Current Sink 2 Enable (ISINK2 pin) 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. Current Sink 2 output drive enable 0 = Disabled 1 = Enabled Current Sink 2 status 0 = Normal 1 = Sink current cannot be regulated Current Sink 2 SLEEP Enable 0 = Disabled 1 = Controlled by CS2_ENA ISINK2 Switch-Off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales REFER TO 14 CS2_DRIVE 0 13 CS2_STS 0 12 CS2_SLPENA 0 11:10 CS2_OFF_RA MP[1:0] 01 w PP, December 2009, Rev 3.0 233 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION according to the extent of the change in current drive setting. 9:8 CS2_ON_RAM P[1:0] 01 ISINK2 Switch-On ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) The time quoted in brackets is valid for the maximum change in current drive setting. The actual time scales according to the extent of the change in current drive setting. ISINK2 current. Current = 2.0A x 2^(CS2_ISEL/4), where CS2_ISEL is an unsigned binary number. Alternatively, CS2_ISEL = 13.29 x LOG(current/2.0A) 00_0000 = 2.0A 11_0111 = 27.6mA Values greater than 11_0111 will result in the maximum current of approx 27.6mA. Register 404Fh Current Sink 2 Pre-Production REFER TO 5:0 CS2_ISEL[5:0] 00_0000 REGISTER ADDRESS R16464 (4050h) DCDC Enable BIT 7 LABEL EPE2_ENA DEFAULT 0 DESCRIPTION EPE2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE2_STS) EPE1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in EPE1_STS) DC-DC4 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC4_STS) DC-DC3 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC3_STS) DC-DC2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC2_STS) DC_DC1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in DC1_STS) REFER TO 6 EPE1_ENA 0 3 DC4_ENA 0 2 DC3_ENA 0 1 DC2_ENA 0 0 DC1_ENA 0 Register 4050h DCDC Enable w PP, December 2009, Rev 3.0 234 Pre-Production REGISTER ADDRESS R16465 (4051h) LDO Enable BIT 10 LABEL LDO11_ENA DEFAULT 0 DESCRIPTION LDO11 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO11_STS) LDO10 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO10_STS) LDO9 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO9_STS) LDO8 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO8_STS) LDO7 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO7_STS) LDO6 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO6_STS) LDO5 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO5_STS) LDO4 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO4_STS) LDO3 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO3_STS) LDO2 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO2_STS) LDO1 Enable request 0 = Disabled 1 = Enabled (Note that the actual status is indicated in LDO1_STS) WM8312 REFER TO 9 LDO10_ENA 0 8 LDO9_ENA 0 7 LDO8_ENA 0 6 LDO7_ENA 0 5 LDO6_ENA 0 4 LDO5_ENA 0 3 LDO4_ENA 0 2 LDO3_ENA 0 1 LDO2_ENA 0 0 LDO1_ENA 0 Register 4051h LDO Enable w PP, December 2009, Rev 3.0 235 WM8312 REGISTER ADDRESS R16466 (4052h) DCDC Status BIT 7 LABEL EPE2_STS DEFAULT 0 EPE2 Status 0 = Disabled 1 = Enabled EPE1 Status 0 = Disabled 1 = Enabled DC-DC4 Status 0 = Disabled 1 = Enabled DC-DC3 Status 0 = Disabled 1 = Enabled DC-DC2 Status 0 = Disabled 1 = Enabled DC-DC1 Status 0 = Disabled 1 = Enabled DESCRIPTION Pre-Production REFER TO 6 EPE1_STS 0 3 DC4_STS 0 2 DC3_STS 0 1 DC2_STS 0 0 DC1_STS 0 Register 4052h DCDC Status REGISTER ADDRESS R16467 (4053h) LDO Status BIT 10 LABEL LDO11_STS DEFAULT 0 LDO11 Status 0 = Disabled 1 = Enabled LDO10 Status 0 = Disabled 1 = Enabled LDO9 Status 0 = Disabled 1 = Enabled LDO8 Status 0 = Disabled 1 = Enabled LDO7 Status 0 = Disabled 1 = Enabled LDO6 Status 0 = Disabled 1 = Enabled LDO5 Status 0 = Disabled 1 = Enabled LDO4 Status 0 = Disabled 1 = Enabled LDO3 Status 0 = Disabled 1 = Enabled LDO2 Status 0 = Disabled 1 = Enabled DESCRIPTION REFER TO 9 LDO10_STS 0 8 LDO9_STS 0 7 LDO8_STS 0 6 LDO7_STS 0 5 LDO6_STS 0 4 LDO5_STS 0 3 LDO4_STS 0 2 LDO3_STS 0 1 LDO2_STS 0 w PP, December 2009, Rev 3.0 236 Pre-Production REGISTER ADDRESS BIT 0 LABEL LDO1_STS DEFAULT 0 LDO1 Status 0 = Disabled 1 = Enabled DESCRIPTION WM8312 REFER TO Register 4053h LDO Status REGISTER ADDRESS R16468 (4054h) DCDC UV Status BIT 13 LABEL DC2_OV_STS DEFAULT 0 DESCRIPTION DC-DC2 Overvoltage Status 0 = Normal 1 = Overvoltage DC-DC1 Overvoltage Status 0 = Normal 1 = Overvoltage DC-DC2 High Current Status 0 = Normal 1 = High Current DC-DC1 High Current Status 0 = Normal 1 = High Current DC-DC4 Undervoltage Status 0 = Normal 1 = Undervoltage DC-DC3 Undervoltage Status 0 = Normal 1 = Undervoltage DC-DC2 Undervoltage Status 0 = Normal 1 = Undervoltage DC-DC1 Undervoltage Status 0 = Normal 1 = Undervoltage REFER TO 12 DC1_OV_STS 0 9 DC2_HC_STS 0 8 DC1_HC_STS 0 3 DC4_UV_STS 0 2 DC3_UV_STS 0 1 DC2_UV_STS 0 0 DC1_UV_STS 0 Register 4054h DCDC UV Status REGISTER ADDRESS R16469 (4055h) LDO UV Status BIT 15 LABEL INTLDO_UV_S TS LDO10_UV_ST S LDO9_UV_ST S LDO8_UV_ST S LDO7_UV_ST S LDO6_UV_ST DEFAULT 0 DESCRIPTION LDO13 (Internal LDO) Undervoltage Status 0 = Normal 1 = Undervoltage LDO10 Undervoltage Status 0 = Normal 1 = Undervoltage LDO9 Undervoltage Status 0 = Normal 1 = Undervoltage LDO8 Undervoltage Status 0 = Normal 1 = Undervoltage LDO7 Undervoltage Status 0 = Normal 1 = Undervoltage LDO6 Undervoltage Status REFER TO 9 0 8 0 7 0 6 0 5 0 w PP, December 2009, Rev 3.0 237 WM8312 REGISTER ADDRESS BIT LABEL S 4 LDO5_UV_ST S LDO4_UV_ST S LDO3_UV_ST S LDO2_UV_ST S LDO1_UV_ST S 0 DEFAULT 0 = Normal 1 = Undervoltage LDO5 Undervoltage Status 0 = Normal 1 = Undervoltage LDO4 Undervoltage Status 0 = Normal 1 = Undervoltage LDO3 Undervoltage Status 0 = Normal 1 = Undervoltage LDO2 Undervoltage Status 0 = Normal 1 = Undervoltage LDO1 Undervoltage Status 0 = Normal 1 = Undervoltage DESCRIPTION Pre-Production REFER TO 3 0 2 0 1 0 0 0 Register 4055h LDO UV Status REGISTER ADDRESS R16470 (4056h) DC1 Control 1 BIT 15:14 LABEL DC1_RATE[1:0 ] DEFAULT 10 DESCRIPTION DC-DC1 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz 10 = Reserved 11 = 4.0MHz DC-DC1 Output float 0 = DC-DC1 output discharged when disabled 1 = DC-DC1 output floating when disabled DC-DC1 Soft-Start Control (Current limiting is stepped through 8 intermediate steps.) 00 = 31.25us steps (250us max total) 01 = 62.5us steps (500us max total) 10 = 125us steps (1000us max total) 11 = 250us steps (2000us max total) REFER TO 12 DC1_PHASE 0 9:8 DC1_FREQ[1:0 ] 00 7 DC1_FLT 0 5:4 DC1_SOFT_S TART[1:0] 00 1:0 DC1_CAP[1:0] 00 DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved Register 4056h DC1 Control 1 w PP, December 2009, Rev 3.0 238 Pre-Production REGISTER ADDRESS R16471 (4057h) DC1 Control 2 BIT 15:14 LABEL DC1_ERR_AC T[1:0] DEFAULT 00 DESCRIPTION DC-DC1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC1 Hardware Control Voltage select 0 = Set by DC1_ON_VSEL 1 = Set by DC1_SLP_VSEL DC-DC1 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode DC-DC1 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA DC-DC1 High Current detect enable 0 = Disabled 1 = Enabled WM8312 REFER TO 12:11 DC1_HWC_SR C[1:0] 00 10 DC1_HWC_VS EL DC1_HWC_M ODE[1:0] 0 9:8 11 6:4 DC1_HC_THR[ 2:0] 000 0 DC1_HC_IND_ ENA 0 Register 4057h DC1 Control 2 REGISTER ADDRESS R16472 (4058h) DC1 ON Config BIT 15:13 LABEL DC1_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 DC-DC1 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC1 ON Voltage select DC1_ON_VSEL[6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. REFER TO 9:8 DC1_ON_MOD E[1:0] 01 6:2 DC1_ON_VSE L[4:0] 0_0000 w PP, December 2009, Rev 3.0 239 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION DC1_ON_VSEL[6:2] also exist in DBE/OTP memory, controlling the voltage in 50mV steps. DC1_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 1:0 DC1_ON_VSE L[1:0] 00 DC-DC1 ON Voltage select DC1_ON_VSEL[6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. See DC1_ON_VSEL[6:2] for definition. Pre-Production REFER TO Register 4058h DC1 ON Config REGISTER ADDRESS R16473 (4059h) DC1 SLEEP Control BIT 15:13 LABEL DC1_SLP_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. DC-DC1 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC1 SLEEP Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V REFER TO 9:8 DC1_SLP_MO DE[1:0] 11 6:0 DC1_SLP_VSE L[6:0] 000_0000 w PP, December 2009, Rev 3.0 240 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 4059h DC1 SLEEP Control WM8312 REFER TO REGISTER ADDRESS R16474 (405Ah) DC1 DVS Control BIT 12:11 LABEL DC1_DVS_SR C[1:0] DEFAULT 00 DESCRIPTION DC-DC1 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 DC-DC1 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). REFER TO 6:0 DC1_DVS_VS EL[6:0] 000_0000 Register 405Ah DC1 DVS Control REGISTER ADDRESS R16475 (405Bh) DC2 Control 1 BIT 15:14 LABEL DC2_RATE[1:0 ] DEFAULT 10 DESCRIPTION DC-DC2 Voltage Ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = Immediate voltage change DC-DC2 Clock Phase Control 0 = Normal 1 = Inverted DC-DC2 Switching Frequency 00 = Reserved 01 = 2.0MHz 10 = Reserved 11 = 4.0MHz DC-DC2 Output float 0 = DC-DC2 output discharged when disabled 1 = DC-DC2 output floating when disabled DC-DC2 Soft-Start Control (Current limiting is stepped through 8 intermediate steps.) 00 = 31.25us steps (250us max total) 01 = 62.5us steps (500us max total) 10 = 125us steps (1000us max total) 11 = 250us steps (2000us max total) REFER TO 12 DC2_PHASE 1 9:8 DC2_FREQ[1:0 ] 00 7 DC2_FLT 0 5:4 DC2_SOFT_S TART[1:0] 00 1:0 DC2_CAP[1:0] 00 DC-DC2 Output Capacitor PP, December 2009, Rev 3.0 241 w WM8312 REGISTER ADDRESS BIT LABEL DEFAULT 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved Register 405Bh DC2 Control 1 DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16476 (405Ch) DC2 Control 2 BIT 15:14 LABEL DC2_ERR_AC T[1:0] DEFAULT 00 DESCRIPTION DC-DC2 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC2 Hardware Control Voltage select 0 = Set by DC2_ON_VSEL 1 = Set by DC2_SLP_VSEL DC-DC2 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode DC-DC2 High Current threshold 000 = 125mA 001 = 250mA 010 = 375mA 011 = 500mA 100 = 625mA 101 = 750mA 110 = 875mA 111 = 1000mA DC-DC2 High Current detect enable 0 = Disabled 1 = Enabled REFER TO 12:11 DC2_HWC_SR C[1:0] 00 10 DC2_HWC_VS EL DC2_HWC_M ODE[1:0] 0 9:8 11 6:4 DC2_HC_THR[ 2:0] 000 0 DC2_HC_IND_ ENA 0 Register 405Ch DC2 Control 2 REGISTER ADDRESS R16477 (405Dh) DC2 ON Config BIT 15:13 LABEL DC2_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 REFER TO w PP, December 2009, Rev 3.0 242 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 111 = Controlled by Hardware Enable 2 9:8 DC2_ON_MOD E[1:0] 01 DC-DC2 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC2 ON Voltage select DC2_ON_VSEL[6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. DC2_ON_VSEL[6:2] also exist in DBE/OTP memory, controlling the voltage in 50mV steps. DC2_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 1:0 DC2_ON_VSE L[1:0] 00 DC-DC2 ON Voltage select DC2_ON_VSEL[6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. See DC2_ON_VSEL[6:2] for definition. WM8312 REFER TO 6:2 DC2_ON_VSE L[4:0] 0_0000 Register 405Dh DC2 ON Config REGISTER ADDRESS R16478 (405Eh) DC2 SLEEP Control BIT 15:13 LABEL DC2_SLP_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC2 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC2 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. DC-DC2 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC2 SLEEP Voltage select REFER TO 9:8 DC2_SLP_MO DE[1:0] 11 6:0 DC2_SLP_VSE L[6:0] 000_0000 w PP, December 2009, Rev 3.0 243 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). Register 405Eh DC2 SLEEP Control Pre-Production REFER TO REGISTER ADDRESS R16479 (405Fh) DC2 DVS Control BIT 12:11 LABEL DC2_DVS_SR C[1:0] DEFAULT 00 DESCRIPTION DC-DC2 DVS Control Source 00 = Disabled 01 = Enabled 10 = Controlled by Hardware DVS1 11 = Controlled by Hardware DVS2 DC-DC2 DVS Voltage select 0.6V to 1.8V in 12.5mV steps 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). REFER TO 6:0 DC2_DVS_VS EL[6:0] 000_0000 Register 405Fh DC2 DVS Control REGISTER ADDRESS R16480 (4060h) DC3 Control 1 BIT 12 LABEL DC3_PHASE DEFAULT 0 DESCRIPTION DC-DC3 Clock Phase Control 0 = Normal 1 = Inverted DC-DC3 Output float 0 = DC-DC3 output discharged when disabled 1 = DC-DC3 output floating when disabled DC-DC3 Soft-Start Control (Current limiting is stepped through 4 intermediate steps.) 00 = Immediate start-up 01 = 4 x 400us (1600us total) 10 = 4 x 4ms (16ms total) 11 = 4 x 40ms (160ms total) REFER TO 7 DC3_FLT 0 5:4 DC3_SOFT_S TART[1:0] 01 w PP, December 2009, Rev 3.0 244 Pre-Production REGISTER ADDRESS BIT 3:2 LABEL DC3_STNBY_L IM [1:0] DEFAULT 01 DESCRIPTION DC-DC3 Current Limit Sets the maximum DC output current in Hysteretic Mode 00 = 100mA 01 = 200mA 10 = 400mA 11 = 800mA Protected by security key. DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF WM8312 REFER TO 1:0 DC3_CAP[1:0] 00 Register 4060h DC3 Control 1 REGISTER ADDRESS R16481 (4061h) DC3 Control 2 BIT 15:14 LABEL DC3_ERR_AC T[1:0] DEFAULT 00 DESCRIPTION DC-DC3 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC3 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC3 Hardware Control Voltage select 0 = Set by DC3_ON_VSEL 1 = Set by DC3_SLP_VSEL DC-DC3 Hardware Control Operating Mode 00 = Forced Continuous Conduction Mode 01 = Disabled 10 = LDO Mode 11 = Hysteretic Mode DC-DC3 Overvoltage Protection 0 = Disabled 1 = Enabled REFER TO 12:11 DC3_HWC_SR C[1:0] 00 10 DC3_HWC_VS EL DC3_HWC_M ODE[1:0] 0 9:8 11 7 DC3_OVP 0 Register 4061h DC3 Control 2 w PP, December 2009, Rev 3.0 245 WM8312 REGISTER ADDRESS R16482 (4062h) DC3 ON Config BIT 15:13 LABEL DC3_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 DC-DC3 ON Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping 10 = LDO Mode 11 = Hysteretic Mode DC-DC3 ON Voltage select DC3_ON_VSEL[6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL[6:2] also exist in DBE/OTP memory, controlling the voltage in 100mV steps. DC3_ON_VSEL[6:0] is coded as follows: 00h = 0.85V 01h = 0.875V ... 65h = 3.375V 66h to 7Fh = 3.4V 1:0 DC3_ON_VSE L[1:0] 00 DC3 ON Voltage select DC3_ON_VSEL[6:0] selects the DC3 output voltage from 0.85V to 3.4V in 25mV steps. See DC3_ON_VSEL[6:2] for definition. Pre-Production REFER TO 9:8 DC3_ON_MOD E[1:0] 01 6:2 DC3_ON_VSE L[4:0] 0_0000 Register 4062h DC3 ON Config REGISTER ADDRESS R16483 (4063h) DC3 SLEEP Control BIT 15:13 LABEL DC3_SLP_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC3 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If DC-DC3 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the converter enters its SLEEP condition. DC-DC3 SLEEP Operating Mode 00 = Forced Continuous Conduction Mode 01 = Continuous / Discontinuous Conduction with Pulse-Skipping REFER TO 9:8 DC3_SLP_MO DE[1:0] 11 w PP, December 2009, Rev 3.0 246 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10 = LDO Mode 11 = Hysteretic Mode 6:0 DC3_SLP_VSE L[6:0] 000_0000 DC-DC3 SLEEP Voltage select 0.85V to 3.4V in 25mV steps 00h = 0.85V 01h = 0.875V ... 65h = 3.375V 66h to 7Fh = 3.4V Register 4063h DC3 SLEEP Control WM8312 REFER TO REGISTER ADDRESS R16484 (4064h) DC4 Control BIT 15:14 LABEL DC4_ERR_AC T[1:0] DEFAULT 00 DESCRIPTION DC-DC4 Error Action (Undervoltage) 00 = Ignore 01 = Shut down converter 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. DC-DC4 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 DC-DC4 Hardware Control Operating Mode 0 = DC-DC4 is disabled when Hardware Control Source is asserted 1 = DC-DC4 is controlled by DC4_ENA Selects the voltage range for DC-DC4 00 = 20V < VOUT <= 30V 01 = 10V < VOUT <= 20V 10 = 5V < VOUT <= 10V 11 = VOUT <=5V Protected by security key. DC-DC4 Voltage Feedback source 0 = ISINK1 1 = ISINK2 REFER TO 12:11 DC4_HWC_SR C[1:0] 00 8 DC4_HWC_M ODE 1 3:2 DC4_RANGE[1 :0] 01 0 DC4_FBSRC 0 Register 4064h DC4 Control REGISTER ADDRESS R16485 (4065h) DC4 SLEEP Control BIT 8 LABEL DC4_SLPENA DEFAULT 0 DESCRIPTION DC-DC4 SLEEP Enable 0 = Disabled 1 = Controlled by DC4_ENA REFER TO Register 4065h DC4 SLEEP Control w PP, December 2009, Rev 3.0 247 WM8312 REGISTER ADDRESS R16486 (4066h) EPE1 Control BIT 15:13 LABEL EPE1_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 EPE1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 EPE1 Hardware Control Enable 0 = EPE1 is controlled by EPE1_ENA (Hardware Control input(s) are ignored) 1 = EPE1 is controlled by HWC inputs (Hardware Control input(s) force EPE1 to be de-asserted) EPE1 SLEEP Slot select 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Pre-Production REFER TO 12:11 EPE1_HWC_S RC[1:0] 00 8 EPE1_HWCEN A 0 7:5 EPE1_SLP_SL OT[2:0] 000 Register 4066h EPE1 Control REGISTER ADDRESS R16487 (4067h) EPE2 Control BIT 15:13 LABEL EPE2_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION EPE2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 EPE2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 EPE2 Hardware Control Enable 0 = EPE2 is controlled by EPE2_ENA (Hardware Control input(s) are ignored) 1 = EPE2 is controlled by HWC inputs (Hardware Control input(s) force EPE2 to be de-asserted) EPE2 SLEEP Slot select 000 = No action REFER TO 12:11 EPE2_HWC_S RC[1:0] 00 8 EPE2_HWCEN A 0 7:5 EPE2_SLP_SL OT[2:0] 000 w PP, December 2009, Rev 3.0 248 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action Register 4067h EPE2 Control WM8312 REFER TO REGISTER ADDRESS R16488 (4068h) LDO1 Control BIT 15:14 LABEL LDO1_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO1 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO1 Hardware Control Voltage select 0 = Set by LDO1_ON_VSEL 1 = Set by LDO1_SLP_VSEL LDO1 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO1_ON_MODE LDO1 Output float 0 = LDO1 output discharged when disabled 1 = LDO1 output floating when disabled LDO1 Switch Mode 0 = LDO mode 1 = Switch mode LDO1 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. REFER TO 12:11 LDO1_HWC_S RC[1:0] 00 10 LDO1_HWC_V SEL LDO1_HWC_M ODE[1:0] 0 9:8 10 7 LDO1_FLT 0 6 LDO1_SWI 0 0 LDO1_LP_MO DE 0 Register 4068h LDO1 Control w PP, December 2009, Rev 3.0 249 WM8312 REGISTER ADDRESS R16489 (4069h) LDO1 ON Control BIT 15:13 LABEL LDO1_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO1 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 4069h LDO1 ON Control Pre-Production REFER TO 8 LDO1_ON_MO DE LDO1_ON_VS EL[4:0] 0 4:0 0_0000 REGISTER ADDRESS R16490 (406Ah) LDO1 SLEEP Control BIT 15:13 LABEL LDO1_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO1 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO1 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO1 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO1 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... REFER TO 8 LDO1_SLP_M ODE LDO1_SLP_VS EL[4:0] 1 4:0 0_0000 w PP, December 2009, Rev 3.0 250 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 406Ah LDO1 SLEEP Control DESCRIPTION WM8312 REFER TO REGISTER ADDRESS R16491 (406Bh) LDO2 Control BIT 15:14 LABEL LDO2_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO2 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO2 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO2 Hardware Control Voltage select 0 = Set by LDO2_ON_VSEL 1 = Set by LDO2_SLP_VSEL LDO2 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO2_ON_MODE LDO2 Output float 0 = LDO2 output discharged when disabled 1 = LDO2 output floating when disabled LDO2 Switch Mode 0 = LDO mode 1 = Switch mode LDO2 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. REFER TO 12:11 LDO2_HWC_S RC[1:0] 00 10 LDO2_HWC_V SEL LDO2_HWC_M ODE[1:0] 0 9:8 10 7 LDO2_FLT 0 6 LDO2_SWI 0 0 LDO2_LP_MO DE 0 Register 406Bh LDO2 Control REGISTER ADDRESS R16492 (406Ch) LDO2 ON Control BIT 15:13 LABEL LDO2_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 REFER TO w PP, December 2009, Rev 3.0 251 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 111 = Controlled by Hardware Enable 2 8 LDO2_ON_MO DE LDO2_ON_VS EL[4:0] 0 LDO2 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO2 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 406Ch LDO2 ON Control Pre-Production REFER TO 4:0 0_0000 REGISTER ADDRESS R16493 (406Dh) LDO2 SLEEP Control BIT 15:13 LABEL LDO2_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO2 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO2 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO2 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO2 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 8 LDO2_SLP_M ODE LDO2_SLP_VS EL[4:0] 1 4:0 0_0000 Register 406Dh LDO2 SLEEP Control w PP, December 2009, Rev 3.0 252 Pre-Production REGISTER ADDRESS R16494 (406Eh) LDO3 Control BIT 15:14 LABEL LDO3_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO3 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO3 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO3 Hardware Control Voltage select 0 = Set by LDO3_ON_VSEL 1 = Set by LDO3_SLP_VSEL LDO3 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO3_ON_MODE LDO3 Output float 0 = LDO3 output discharged when disabled 1 = LDO3 output floating when disabled LDO3 Switch Mode 0 = LDO mode 1 = Switch mode LDO3 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. WM8312 REFER TO 12:11 LDO3_HWC_S RC[1:0] 00 10 LDO3_HWC_V SEL LDO3_HWC_M ODE[1:0] 0 9:8 10 7 LDO3_FLT 0 6 LDO3_SWI 0 0 LDO3_LP_MO DE 0 Register 406Eh LDO3 Control REGISTER ADDRESS R16495 (406Fh) LDO3 ON Control BIT 15:13 LABEL LDO3_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO3 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO3 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... REFER TO 8 LDO3_ON_MO DE LDO3_ON_VS EL[4:0] 0 4:0 0_0000 w PP, December 2009, Rev 3.0 253 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 406Fh LDO3 ON Control DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16496 (4070h) LDO3 SLEEP Control BIT 15:13 LABEL LDO3_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO3 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO3 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO3 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO3 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 8 LDO3_SLP_M ODE LDO3_SLP_VS EL[4:0] 1 4:0 0_0000 Register 4070h LDO3 SLEEP Control REGISTER ADDRESS R16497 (4071h) LDO4 Control BIT 15:14 LABEL LDO4_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO4 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO4 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 REFER TO 12:11 LDO4_HWC_S RC[1:0] 00 w PP, December 2009, Rev 3.0 254 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10 = Hardware Control 2 11 = Hardware Control 1 or 2 10 LDO4_HWC_V SEL LDO4_HWC_M ODE[1:0] 0 LDO4 Hardware Control Voltage select 0 = Set by LDO4_ON_VSEL 1 = Set by LDO4_SLP_VSEL LDO4 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO4_ON_MODE LDO4 Output float 0 = LDO4 output discharged when disabled 1 = LDO4 output floating when disabled LDO4 Switch Mode 0 = LDO mode 1 = Switch mode LDO4 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. WM8312 REFER TO 9:8 10 7 LDO4_FLT 0 6 LDO4_SWI 0 0 LDO4_LP_MO DE 0 Register 4071h LDO4 Control REGISTER ADDRESS R16498 (4072h) LDO4 ON Control BIT 15:13 LABEL LDO4_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO4 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO4 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 8 LDO4_ON_MO DE LDO4_ON_VS EL[4:0] 0 4:0 0_0000 Register 4072h LDO4 ON Control w PP, December 2009, Rev 3.0 255 WM8312 REGISTER ADDRESS R16499 (4073h) LDO4 SLEEP Control BIT 15:13 LABEL LDO4_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO4 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO4 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO4 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO4 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 4073h LDO4 SLEEP Control Pre-Production REFER TO 8 LDO4_SLP_M ODE LDO4_SLP_VS EL[4:0] 1 4:0 0_0000 REGISTER ADDRESS R16500 (4074h) LDO5 Control BIT 15:14 LABEL LDO5_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO5 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO5 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO5 Hardware Control Voltage select 0 = Set by LDO5_ON_VSEL 1 = Set by LDO5_SLP_VSEL LDO5 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO5_ON_MODE REFER TO 12:11 LDO5_HWC_S RC[1:0] 00 10 LDO5_HWC_V SEL LDO5_HWC_M ODE[1:0] 0 9:8 10 w PP, December 2009, Rev 3.0 256 Pre-Production REGISTER ADDRESS BIT 7 LABEL LDO5_FLT DEFAULT 0 DESCRIPTION LDO5 Output float 0 = LDO5 output discharged when disabled 1 = LDO5 output floating when disabled LDO5 Switch Mode 0 = LDO mode 1 = Switch mode LDO5 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. WM8312 REFER TO 6 LDO5_SWI 0 0 LDO5_LP_MO DE 0 Register 4074h LDO5 Control REGISTER ADDRESS R16501 (4075h) LDO5 ON Control BIT 15:13 LABEL LDO5_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO5 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO5 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO5 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 8 LDO5_ON_MO DE LDO5_ON_VS EL[4:0] 0 4:0 0_0000 Register 4075h LDO5 ON Control REGISTER ADDRESS R16502 (4076h) LDO5 SLEEP Control BIT 15:13 LABEL LDO5_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO5 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in REFER TO w PP, December 2009, Rev 3.0 257 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO5 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. 8 LDO5_SLP_M ODE LDO5_SLP_VS EL[4:0] 1 LDO5 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO5 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 4076h LDO5 SLEEP Control Pre-Production REFER TO 4:0 0_0000 REGISTER ADDRESS R16503 (4077h) LDO6 Control BIT 15:14 LABEL LDO6_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO6 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO6 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO6 Hardware Control Voltage select 0 = Set by LDO6_ON_VSEL 1 = Set by LDO6_SLP_VSEL LDO6 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO6_ON_MODE LDO6 Output float 0 = LDO6 output discharged when disabled 1 = LDO6 output floating when disabled LDO6 Switch Mode 0 = LDO mode 1 = Switch mode LDO6 Low Power Mode Select 0 = 50mA (reduced quiescent current) 1 = 20mA (minimum quiescent current) REFER TO 12:11 LDO6_HWC_S RC[1:0] 00 10 LDO6_HWC_V SEL LDO6_HWC_M ODE[1:0] 0 9:8 10 7 LDO6_FLT 0 6 LDO6_SWI 0 0 LDO6_LP_MO DE 0 w PP, December 2009, Rev 3.0 258 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Selects which Low Power mode is used in ON, SLEEP, or under HWC modes. Register 4077h LDO6 Control WM8312 REFER TO REGISTER ADDRESS R16504 (4078h) LDO6 ON Control BIT 15:13 LABEL LDO6_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO6 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO6 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO6 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 8 LDO6_ON_MO DE LDO6_ON_VS EL[4:0] 0 4:0 0_0000 Register 4078h LDO6 ON Control REGISTER ADDRESS R16505 (4079h) LDO6 SLEEP Control BIT 15:13 LABEL LDO6_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO6 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO6 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO6 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode REFER TO 8 LDO6_SLP_M ODE 1 w PP, December 2009, Rev 3.0 259 WM8312 REGISTER ADDRESS BIT 4:0 LABEL LDO6_SLP_VS EL[4:0] DEFAULT 0_0000 DESCRIPTION LDO6 SLEEP Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 4079h LDO6 SLEEP Control Pre-Production REFER TO REGISTER ADDRESS R16506 (407Ah) LDO7 Control BIT 15:14 LABEL LDO7_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO7 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO7 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO7 Hardware Control Voltage select 0 = Set by LDO7_ON_VSEL 1 = Set by LDO7_SLP_VSEL LDO7 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO7_ON_MODE LDO7 Output float 0 = LDO7 output discharged when disabled 1 = LDO7 output floating when disabled LDO7 Switch Mode 0 = LDO mode 1 = Switch mode REFER TO 12:11 LDO7_HWC_S RC[1:0] 00 10 LDO7_HWC_V SEL LDO7_HWC_M ODE[1:0] 0 9:8 10 7 LDO7_FLT 0 6 LDO7_SWI 0 Register 407Ah LDO7 Control w PP, December 2009, Rev 3.0 260 Pre-Production REGISTER ADDRESS R16507 (407Bh) LDO7 ON Control BIT 15:13 LABEL LDO7_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO7 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V WM8312 REFER TO 8 LDO7_ON_MO DE LDO7_ON_VS EL[4:0] 0 4:0 0_0000 Register 407Bh LDO7 ON Control REGISTER ADDRESS R16508 (407Ch) LDO7 SLEEP Control BIT 15:13 LABEL LDO7_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO7 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO7 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO7 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO7 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... REFER TO 8 LDO7_SLP_M ODE LDO7_SLP_VS EL[4:0] 1 4:0 0_0000 w PP, December 2009, Rev 3.0 261 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V Register 407Ch LDO7 SLEEP Control DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16509 (407Dh) LDO8 Control BIT 15:14 LABEL LDO8_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO8 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO8 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO8 Hardware Control Voltage select 0 = Set by LDO8_ON_VSEL 1 = Set by LDO8_SLP_VSEL LDO8 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO8_ON_MODE LDO8 Output float 0 = LDO8 output discharged when disabled 1 = LDO8 output floating when disabled LDO8 Switch Mode 0 = LDO mode 1 = Switch mode REFER TO 12:11 LDO8_HWC_S RC[1:0] 00 10 LDO8_HWC_V SEL LDO8_HWC_M ODE[1:0] 0 9:8 10 7 LDO8_FLT 0 6 LDO8_SWI 0 Register 407Dh LDO8 Control REGISTER ADDRESS R16510 (407Eh) LDO8 ON Control BIT 15:13 LABEL LDO8_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO8 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO8 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO8 ON Voltage select REFER TO 8 LDO8_ON_MO DE LDO8_ON_VS 0 4:0 0_0000 w PP, December 2009, Rev 3.0 262 Pre-Production REGISTER ADDRESS BIT LABEL EL[4:0] DEFAULT DESCRIPTION 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V WM8312 REFER TO Register 407Eh LDO8 ON Control REGISTER ADDRESS R16511 (407Fh) LDO8 SLEEP Control BIT 15:13 LABEL LDO8_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO8 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO8 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO8 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO8 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V REFER TO 8 LDO8_SLP_M ODE LDO8_SLP_VS EL[4:0] 1 4:0 0_0000 Register 407Fh LDO8 SLEEP Control w PP, December 2009, Rev 3.0 263 WM8312 REGISTER ADDRESS R16512 (4080h) LDO9 Control BIT 15:14 LABEL LDO9_ERR_A CT[1:0] DEFAULT 00 DESCRIPTION LDO9 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO9 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO9 Hardware Control Voltage select 0 = Set by LDO9_ON_VSEL 1 = Set by LDO9_SLP_VSEL LDO9 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO9_ON_MODE LDO9 Output float 0 = LDO9 output discharged when disabled 1 = LDO9 output floating when disabled LDO9 Switch Mode 0 = LDO mode 1 = Switch mode Pre-Production REFER TO 12:11 LDO9_HWC_S RC[1:0] 00 10 LDO9_HWC_V SEL LDO9_HWC_M ODE[1:0] 0 9:8 10 7 LDO9_FLT 0 6 LDO9_SWI 0 Register 4080h LDO9 Control REGISTER ADDRESS R16513 (4081h) LDO9 ON Control BIT 15:13 LABEL LDO9_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO9 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO9 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO9 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V REFER TO 8 LDO9_ON_MO DE LDO9_ON_VS EL[4:0] 0 4:0 0_0000 w PP, December 2009, Rev 3.0 264 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT 1Fh = 3.50V Register 4081h LDO9 ON Control DESCRIPTION WM8312 REFER TO REGISTER ADDRESS R16514 (4082h) LDO9 SLEEP Control BIT 15:13 LABEL LDO9_SLP_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO9 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO9 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO9 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO9 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V REFER TO 8 LDO9_SLP_M ODE LDO9_SLP_VS EL[4:0] 1 4:0 0_0000 Register 4082h LDO9 SLEEP Control REGISTER ADDRESS R16515 (4083h) LDO10 Control BIT 15:14 LABEL LDO10_ERR_ ACT[1:0] DEFAULT 00 DESCRIPTION LDO10 Error Action (Undervoltage) 00 = Ignore 01 = Shut down regulator 10 = Shut down system (Device Reset) 11 = Reserved Note that an Interrupt is always raised. LDO10 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 LDO10 Hardware Control Voltage select 0 = Set by LDO10_ON_VSEL REFER TO 12:11 LDO10_HWC_ SRC[1:0] 00 10 LDO10_HWC_ VSEL 0 w PP, December 2009, Rev 3.0 265 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1 = Set by LDO10_SLP_VSEL 9:8 LDO10_HWC_ MODE[1:0] 10 LDO10 Hardware Control Operating Mode 00 = Low Power mode 01 = Turn converter off 10 = Low Power mode 11 = Set by LDO10_ON_MODE LDO10 Output float 0 = LDO10 output discharged when disabled 1 = LDO10 output floating when disabled LDO10 Switch Mode 0 = LDO mode 1 = Switch mode Pre-Production REFER TO 7 LDO10_FLT 0 6 LDO10_SWI 0 Register 4083h LDO10 Control REGISTER ADDRESS R16516 (4084h) LDO10 ON Control BIT 15:13 LABEL LDO10_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO10 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO10 ON Operating Mode 0 = Normal mode 1 = Low Power mode LDO10 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V REFER TO 8 LDO10_ON_M ODE LDO10_ON_V SEL[4:0] 0 4:0 0_0000 Register 4084h LDO10 ON Control w PP, December 2009, Rev 3.0 266 Pre-Production REGISTER ADDRESS R16517 (4085h) LDO10 SLEEP Control BIT 15:13 LABEL LDO10_SLP_S LOT[2:0] DEFAULT 000 DESCRIPTION LDO10 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO10 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO10 SLEEP Operating Mode 0 = Normal mode 1 = Low Power mode LDO10 SLEEP Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V WM8312 REFER TO 8 LDO10_SLP_M ODE LDO10_SLP_V SEL[4:0] 1 4:0 0_0000 Register 4085h LDO10 SLEEP Control REGISTER ADDRESS R16519 (4087h) LDO11 ON Control BIT 15:13 LABEL LDO11_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO11 Force Enable (forces LDO11 to be enabled at all times in the OFF, ON and SLEEP states) 0 = Disabled 1 = Enabled LDO11 Voltage Select source 0 = Normal (LDO11 settings) 1 = Same as DC-DC Converter 1 LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V REFER TO 12 LDO11_FRCE NA 0 7 LDO11_VSEL_ SRC LDO11_ON_V SEL[3:0] 0 3:0 0000 w PP, December 2009, Rev 3.0 267 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT 2h = 0.90V ... Eh = 1.50V Fh = 1.55V Register 4087h LDO11 ON Control DESCRIPTION Pre-Production REFER TO REGISTER ADDRESS R16520 (4088h) LDO11 SLEEP Control BIT 15:13 LABEL LDO11_SLP_S LOT[2:0] DEFAULT 000 DESCRIPTION LDO11 SLEEP Slot select 000 = SLEEP voltage / operating mode transition in Timeslot 5 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = SLEEP voltage / operating mode transition in Timeslot 3 111 = SLEEP voltage / operating mode transition in Timeslot 1 If LDO11 is assigned to a Hardware Enable Input, then codes 001-101 select in which timeslot the regulator enters its SLEEP condition. LDO11 SLEEP Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V ... Eh = 1.50V Fh = 1.55V REFER TO 3:0 LDO11_SLP_V SEL[3:0] 0000 Register 4088h LDO11 SLEEP Control REGISTER ADDRESS R16526 (408Eh) Power Good Source 1 BIT 3 LABEL DC4_OK DEFAULT 0 DESCRIPTION DC-DC4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled DC-DC1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled REFER TO 2 DC3_OK 1 1 DC2_OK 1 0 DC1_OK 1 Register 408Eh Power Good Source 1 w PP, December 2009, Rev 3.0 268 Pre-Production REGISTER ADDRESS R16527 (408Fh) Power Good Source 2 BIT 9 LABEL LDO10_OK DEFAULT 1 DESCRIPTION LDO10 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO9 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO8 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO7 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO6 status selected selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO5 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO4 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO3 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO2 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled LDO1 status selected as an input to PWR_GOOD 0 = Disabled 1 = Enabled WM8312 REFER TO 8 LDO9_OK 1 7 LDO8_OK 1 6 LDO7_OK 1 5 LDO6_OK 1 4 LDO5_OK 1 3 LDO4_OK 1 2 LDO3_OK 1 1 LDO2_OK 1 0 LDO1_OK 1 Register 408Fh Power Good Source 2 REGISTER ADDRESS R16528 (4090h) Clock Control 1 BIT 15 LABEL CLKOUT_ENA DEFAULT 0 DESCRIPTION CLKOUT output enable 0 = Disabled 1 = Enabled Protected by security key CLKOUT pin configuration 0 = CMOS 1 = Open Drain CLKOUT output enable ON slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Do not enable 111 = Do not enable REFER TO 13 CLKOUT_OD 0 10:8 CLKOUT_SLO T[2:0] 000 w PP, December 2009, Rev 3.0 269 WM8312 REGISTER ADDRESS BIT 6:4 LABEL CLKOUT_SLP SLOT[2:0] DEFAULT 000 DESCRIPTION CLKOUT output SLEEP slot select 000 = Controlled by CLKOUT_ENA 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = Controlled by CLKOUT_ENA 111 = Controlled by CLKOUT_ENA CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Pre-Production REFER TO 0 CLKOUT_SRC 0 Register 4090h Clock Control 1 REGISTER ADDRESS R16529 (4091h) Clock Control 2 BIT 15 LABEL XTAL_INH DEFAULT 0 DESCRIPTION Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=1, the `ON' transition is inhibited until the crystal oscillator is valid Crystal Oscillator Enable 0 = Disabled at all times 1 = Enabled in OFF, ON and SLEEP states (Note that the BACKUP behaviour is determined by XTAL_BKUPENA.) Selects the RTC and 32.768kHz oscillator in BACKUP state 0 = RTC unclocked in BACKUP 1 = RTC maintained in BACKUP (Note that XTAL_ENA must also be set if the RTC is to be maintained in BACKUP.) FLL Automatic Mode Enable 0 = Manual configuration mode 1 = Automatic configuration mode (To enable the FLL output, FLL_ENA must also be set in Automatic mode) FLL Automatic Mode Frequency select 000 = 2.048MHz 001 = 11.2896MHz 010 = 12MHz 011 = 12.288MHz 100 = 19.2MHz 101 = 22.5792MHz 110 = 24MHz 111 = 24.576MHz REFER TO 13 XTAL_ENA 0 12 XTAL_BKUPE NA 1 7 FLL_AUTO 1 2:0 FLL_AUTO_FR EQ[2:0] 000 Register 4091h Clock Control 2 w PP, December 2009, Rev 3.0 270 Pre-Production REGISTER ADDRESS R16530 (4092h) FLL Control 1 BIT 2 LABEL FLL_FRAC DEFAULT 0 DESCRIPTION Fractional enable 0 = Integer Mode 1 = Fractional Mode Integer mode offers reduced power consumption. Fractional mode offers best FLL performance, provided also that N.K is a non-integer value. FLL Enable 0 = Disabled 1 = Enabled Note - this bit is reset to 0 when the OFF power state is entered. WM8312 REFER TO 0 FLL_ENA 0 Register 4092h FLL Control 1 REGISTER ADDRESS R16531 (4093h) FLL Control 2 BIT 13:8 LABEL FLL_OUTDIV[5 :0] DEFAULT 00_0000 DESCRIPTION FOUT clock divider 000000 = Reserved 000001 = Reserved 000010 = Reserved 000011 = 4 000100 = 5 000101 = 6 ... 111110 = 63 111111 = 64 (FOUT = FVCO / FLL_OUTDIV) Frequency of the FLL control block 000 = FVCO / 1 (Recommended value) 001 = FVCO / 2 010 = FVCO / 3 011 = FVCO / 4 100 = FVCO / 5 101 = FVCO / 6 110 = FVCO / 7 111 = FVCO / 8 Recommended that this register is not changed from default. REFER TO 6:4 FLL_CTRL_RA TE[2:0] 000 2:0 FLL_FRATIO[2 :0] 000 FVCO clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1XX = 16 000 recommended for high FREF 011 recommended for low FREF Register 4093h FLL Control 2 w PP, December 2009, Rev 3.0 271 WM8312 REGISTER ADDRESS R16532 (4094h) FLL Control 3 BIT 15:0 LABEL FLL_K[15:0] DEFAULT DESCRIPTION Pre-Production REFER TO 0000_0000 Fractional multiply for FREF _0000_000 (MSB = 0.5) 0 Register 4094h FLL Control 3 REGISTER ADDRESS R16533 (4095h) FLL Control 4 BIT 14:5 3:0 LABEL FLL_N[9:0] FLL_GAIN[3:0] DEFAULT DESCRIPTION REFER TO 01_0111_0 Integer multiply for FREF 111 (LSB = 1) 0000 Gain applied to error 0000 = x 1 (Recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1XXX = x 256 Recommended that this register is not changed from default. Register 4095h FLL Control 4 REGISTER ADDRESS R16534 (4096h) FLL Control 5 BIT 4:3 LABEL FLL_CLK_REF _DIV[1:0] DEFAULT 00 DESCRIPTION FLL Clock Reference Divider 00 = 1 01 = 2 10 = 4 11 = 8 CLKIN must be divided down to <=13.5MHz. For lower power operation, the reference clock can be divided down further if desired. REFER TO 1:0 FLL_CLK_SRC [1:0] 00 FLL Clock source 00 = 32.768kHz xtal oscillator 01 = CLKIN 10 = Reserved 11 = Reserved Register 4096h FLL Control 5 REGISTER ADDRESS R30720 (7800h) Unique ID 1 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 7 :0] _0000_000 0 Register 7800h Unique ID 1 w PP, December 2009, Rev 3.0 272 Pre-Production REGISTER ADDRESS R30721 (7801h) Unique ID 2 BIT 15:0 LABEL DEFAULT DESCRIPTION WM8312 REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 6 :0] _0000_000 0 Register 7801h Unique ID 2 REGISTER ADDRESS R30722 (7802h) Unique ID 3 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 5 :0] _0000_000 0 Register 7802h Unique ID 3 REGISTER ADDRESS R30723 (7803h) Unique ID 4 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 4 :0] _0000_000 0 Register 7803h Unique ID 4 REGISTER ADDRESS R30724 (7804h) Unique ID 5 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 3 :0] _0000_000 0 Register 7804h Unique ID 5 REGISTER ADDRESS R30725 (7805h) Unique ID 6 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 2 :0] _0000_000 0 Register 7805h Unique ID 6 REGISTER ADDRESS R30726 (7806h) Unique ID 7 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 1 :0] _0000_000 0 Register 7806h Unique ID 7 REGISTER ADDRESS R30727 (7807h) Unique ID 8 BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO UNIQUE_ID[15 0000_0000 Unique ID, Word 0 :0] _0000_000 0 Register 7807h Unique ID 8 w PP, December 2009, Rev 3.0 273 WM8312 REGISTER ADDRESS R30728 (7808h) Factory OTP ID BIT 15:1 0 LABEL DEFAULT DESCRIPTION Pre-Production REFER TO OTP_FACT_ID 000_0000_ [No description available] [14:0] 0000_0000 OTP_FACT_FI NAL 0 [No description available] Register 7808h Factory OTP ID REGISTER ADDRESS R30729 (7809h) Factory OTP 1 BIT 15:12 11:6 5:0 LABEL DC3_TRIM[3:0] DC2_TRIM[5:0] DC1_TRIM[5:0] DEFAULT 0000 00_0000 00_0000 DESCRIPTION [No description available] [No description available] [No description available] REFER TO Register 7809h Factory OTP 1 REGISTER ADDRESS R30730 (780Ah) Factory OTP 2 BIT 15:0 LABEL CHIP_ID[15:0] DEFAULT DESCRIPTION REFER TO 0000_0000 [No description available] _0000_000 0 Register 780Ah Factory OTP 2 REGISTER ADDRESS R30731 (780Bh) Factory OTP 3 BIT 10:7 6:3 2:0 LABEL OSC_TRIM[3:0 ] BG_TRIM[3:0] LPBG_TRIM[2: 0] DEFAULT 0000 0000 000 DESCRIPTION [No description available] [No description available] [No description available] REFER TO Register 780Bh Factory OTP 3 REGISTER ADDRESS R30732 (780Ch) Factory OTP 4 BIT 7:1 0 LABEL CHILD_I2C_A DDR[6:0] CH_AW DEFAULT 000_0000 0 DESCRIPTION [No description available] [No description available] REFER TO Register 780Ch Factory OTP 4 REGISTER ADDRESS R30733 (780Dh) Factory OTP 5 BIT 5:0 LABEL CHARGE_TRI M[5:0] DEFAULT 00_0000 DESCRIPTION [No description available] REFER TO Register 780Dh Factory OTP 5 w PP, December 2009, Rev 3.0 274 Pre-Production REGISTER ADDRESS R30736 (7810h) Customer OTP ID BIT 15 LABEL OTP_AUTO_P ROG DEFAULT 0 DESCRIPTION If this bit is set when bootstrap data is loaded from DBE (in development mode), then the DBE contents will be programmed in the OTP. WM8312 REFER TO 14:1 OTP_CUST_ID 00_0000_0 This field is checked when an `ON' transition is [13:0] 000_0000 requested. A non-zero value is used to confirm valid data. OTP_CUST_FI NAL 0 If OTP_CUST_FINAL is set in the OTP and also set in the DORW, then no further Writes are possible to the OTP. 0 Register 7810h Customer OTP ID REGISTER ADDRESS R30737 (7811h) DC1 OTP Control BIT 15:13 LABEL DC1_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 DC-DC1 Switching Frequency 00 = Reserved 01 = 2.0MHz 10 = Reserved 11 = 4.0MHz DC-DC1 Clock Phase Control 0 = Normal 1 = Inverted DC-DC1 ON Voltage select DC1_ON_VSEL[6:0] selects the DC-DC1 output voltage from 0.6V to 1.8V in 12.5mV steps. DC1_ON_VSEL[6:2] controls the voltage in 50mV steps. DC1_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). REFER TO 9:8 DC1_FREQ[1:0 ] 00 7 DC1_PHASE 0 6:2 DC1_ON_VSE L[4:0] 0_0000 1:0 DC1_CAP[1:0] 00 DC-DC1 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved Register 7811h DC1 OTP Control w PP, December 2009, Rev 3.0 275 WM8312 REGISTER ADDRESS R30738 (7812h) DC2 OTP Control BIT 15:13 LABEL DC2_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 DC-DC2 Switching Frequency 00 = Reserved 01 = 2.0MHz 10 = Reserved 11 = 4.0MHz DC-DC2 Clock Phase Control 0 = Normal 1 = Inverted DC-DC2 ON Voltage select DC2_ON_VSEL[6:0] selects the DC-DC2 output voltage from 0.6V to 1.8V in 12.5mV steps. DC2_ON_VSEL[6:2] controls the voltage in 50mV steps. DC2_ON_VSEL[6:0] is coded as follows: 00h to 08h = 0.6V 09h = 0.6125V ... 48h = 1.4V (see note) ... 67h = 1.7875V 68h to 7Fh = 1.8V Note - Maximum output voltage selection in 4MHz switching mode is 48h (1.4V). 1:0 DC2_CAP[1:0] 00 DC-DC2 Output Capacitor 00 = 4.7uF to 20uF 01 = Reserved 10 = 22uF to 47uF 11 = Reserved Pre-Production REFER TO 9:8 DC2_FREQ[1:0 ] 00 7 DC2_PHASE 1 6:2 DC2_ON_VSE L[4:0] 0_0000 Register 7812h DC2 OTP Control REGISTER ADDRESS R30739 (7813h) DC3 OTP Control BIT 15:13 LABEL DC3_ON_SLO T[2:0] DEFAULT 000 DESCRIPTION DC-DC3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 REFER TO w PP, December 2009, Rev 3.0 276 Pre-Production REGISTER ADDRESS BIT 7 LABEL DC3_PHASE DEFAULT 0 DESCRIPTION DC-DC3 Clock Phase Control 0 = Normal 1 = Inverted DC-DC3 ON Voltage select DC3_ON_VSEL[6:0] selects the DC-DC3 output voltage from 0.85V to 3.4V in 25mV steps. DC3_ON_VSEL[6:2] controls the voltage in 100mV steps. DC3_ON_VSEL[6:0] is coded as follows: 00h = 0.85V 01h = 0.875V ... 65h = 3.375V 66h to 7Fh = 3.4V 1:0 DC3_CAP[1:0] 00 DC-DC3 Output Capacitor 00 = 10uF to 20uF 01 = 10uF to 20uF 10 = 22uF to 45uF 11 = 47uF to 100uF WM8312 REFER TO 6:2 DC3_ON_VSE L[6:2] 0_0000 Register 7813h DC3 OTP Control REGISTER ADDRESS R30740 (7814h) LDO1/2 OTP Control BIT 15:13 LABEL LDO2_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO2 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 12:8 LDO2_ON_VS EL[4:0] 0_0000 7:5 LDO1_ON_SL OT[2:0] 000 LDO1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 PP, December 2009, Rev 3.0 277 w WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 111 = Controlled by Hardware Enable 2 4:0 LDO1_ON_VS EL[4:0] 0_0000 LDO1 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 7814h LDO1/2 OTP Control Pre-Production REFER TO REGISTER ADDRESS R30741 (7815h) LDO3/4 OTP Control BIT 15:13 LABEL LDO4_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO4 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO4 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 12:8 LDO4_ON_VS EL[4:0] 0_0000 7:5 LDO3_ON_SL OT[2:0] 000 LDO3 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO3 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 4:0 LDO3_ON_VS EL[4:0] 0_0000 w PP, December 2009, Rev 3.0 278 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 7815h LDO3/4 OTP Control DESCRIPTION WM8312 REFER TO REGISTER ADDRESS R30742 (7816h) LDO5/6 OTP Control BIT 15:13 LABEL LDO6_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO6 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO6 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V REFER TO 12:8 LDO6_ON_VS EL[4:0] 0_0000 7:5 LDO5_ON_SL OT[2:0] 000 4:0 LDO5_ON_VS EL[4:0] 0_0000 LDO5 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO5 ON Voltage select 0.9V to 1.6V in 50mV steps 1.7V to 3.3V in 100mV steps 00h = 0.90V 01h = 0.95V ... 0Eh = 1.60V 0Fh = 1.70V ... 1Eh = 3.20V 1Fh = 3.30V Register 7816h LDO5/6 OTP Control w PP, December 2009, Rev 3.0 279 WM8312 REGISTER ADDRESS R30743 (7817h) LDO7/8 OTP Control BIT 15:13 LABEL LDO8_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO8 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO8 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V LDO7 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO7 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V Pre-Production REFER TO 12:8 LDO8_ON_VS EL[4:0] 0_0000 7:5 LDO7_ON_SL OT[2:0] 000 4:0 LDO7_ON_VS EL[4:0] 0_0000 Register 7817h LDO7/8 OTP Control w PP, December 2009, Rev 3.0 280 Pre-Production REGISTER ADDRESS R30744 (7818h) LDO9/10 OTP Control BIT 15:13 LABEL LDO10_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO10 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO10 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V LDO9 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO9 ON Voltage select 1.0V to 1.6V in 50mV steps 1.7V to 3.5V in 100mV steps 00h = 1.00V 01h = 1.05V 02h = 1.10V ... 0Ch = 1.60V 0Dh = 1.70V ... 1Eh = 3.40V 1Fh = 3.50V WM8312 REFER TO 12:8 LDO10_ON_V SEL[4:0] 0_0000 7:5 LDO9_ON_SL OT[2:0] 000 4:0 LDO9_ON_VS EL[4:0] 0_0000 Register 7818h LDO9/10 OTP Control w PP, December 2009, Rev 3.0 281 WM8312 REGISTER ADDRESS R30745 (7819h) LDO11/EPE Control BIT 15:13 LABEL LDO11_ON_SL OT[2:0] DEFAULT 000 DESCRIPTION LDO11 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 LDO11 ON Voltage select 0.80V to 1.55V in 50mV steps 0h = 0.80V 1h = 0.85V 2h = 0.90V ... Eh = 1.50V Fh = 1.55V EPE2 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 Sets the device behaviour when starting up under USB power, when USB_ILIM = 010b (100mA) 00 = Normal 01 = Soft-Start 10 = Only start if BATTVDD > 3.1V 11 = Only start if BATTVDD > 3.4V In the 1X modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. The start-up request is delayed until the battery voltage threshold has been met. Pre-Production REFER TO 11:8 LDO11_ON_V SEL[3:0] 0000 7:5 EPE2_ON_SL OT[2:0] 000 4:2 EPE1_ON_SL OT[2:0] 000 1:0 USB100MA_S TARTUP[1:0] 00 Register 7819h LDO11/EPE Control w PP, December 2009, Rev 3.0 282 Pre-Production REGISTER ADDRESS R30746 (781Ah) GPIO1 OTP Control BIT 15 LABEL GP1_DIR DEFAULT 1 DESCRIPTION GPIO1 pin direction 0 = Output 1 = Input GPIO1 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO1 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP1_POL=1) or falling edge triggered (if GP1_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO1 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO1 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO1 Output pin configuration 0 = CMOS 1 = Open Drain GPIO1 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO1 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done WM8312 REFER TO 14:13 GP1_PULL[1:0] 01 12 GP1_INT_MO DE 0 11 GP1_PWR_DO M GP1_POL 0 10 1 9 GP1_OD 0 8 GP1_ENA 0 7:4 GP1_FN[3:0] 0000 w PP, December 2009, Rev 3.0 283 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3 CLKOUT_SRC 0 CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Crystal Start-Up Inhibit 0 = Disabled 1 = Enabled When XTAL_INH=1, the `ON' transition is inhibited until the crystal oscillator is valid Battery Charger Enable 0 = Disable 1 = Enable Protected by security key. Pre-Production REFER TO 1 XTAL_INH 0 0 CHG_ENA 0 Register 781Ah GPIO1 OTP Control REGISTER ADDRESS R30747 (781Bh) GPIO2 OTP Control BIT 15 LABEL GP2_DIR DEFAULT 1 DESCRIPTION GPIO2 pin direction 0 = Output 1 = Input GPIO2 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO2 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP2_POL=1) or falling edge triggered (if GP2_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO2 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO2 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO2 Output pin configuration 0 = CMOS 1 = Open Drain GPIO2 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO2 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input REFER TO 14:13 GP2_PULL[1:0] 01 12 GP2_INT_MO DE 0 11 GP2_PWR_DO M GP2_POL 0 10 1 9 GP2_OD 0 8 GP2_ENA 0 7:4 GP2_FN[3:0] 0000 w PP, December 2009, Rev 3.0 284 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 CLKOUT_SLO T[2:0] 000 CLKOUT output enable slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 Watchdog Timer Enable 0 = Disabled 1 = Enabled (enables the watchdog; does not reset it) Protected by security key. WM8312 REFER TO 0 WDOG_ENA 1 Register 781Bh GPIO2 OTP Control w PP, December 2009, Rev 3.0 285 WM8312 REGISTER ADDRESS R30748 (781Ch) GPIO3 OTP Control BIT 15 LABEL GP3_DIR DEFAULT 1 DESCRIPTION GPIO3 pin direction 0 = Output 1 = Input GPIO3 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO3 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP3_POL=1) or falling edge triggered (if GP3_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO3 Power Domain select 0 = DBVDD 1 = PMICVDD (LDO12) GPIO3 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO3 Output pin configuration 0 = CMOS 1 = Open Drain GPIO3 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO3 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done Pre-Production REFER TO 14:13 GP3_PULL[1:0] 01 12 GP3_INT_MO DE 0 11 GP3_PWR_DO M GP3_POL 0 10 1 9 GP3_OD 0 8 GP3_ENA 0 7:4 GP3_FN[3:0] 0000 w PP, December 2009, Rev 3.0 286 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 FLL_AUTO_FR EQ[2:0] 000 FLL Automatic Mode Frequency select 000 = 2.048MHz 001 = 11.2896MHz 010 = 12MHz 011 = 12.288MHz 100 = 19.2MHz 101 = 22.5792MHz 110 = 24MHz 111 = 24.576MHz WM8312 REFER TO Register 781Ch GPIO3 OTP Control REGISTER ADDRESS R30749 (781Dh) GPIO4 OTP Control BIT 15 LABEL GP4_DIR DEFAULT 1 DESCRIPTION GPIO4 pin direction 0 = Output 1 = Input GPIO4 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO4 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP4_POL=1) or falling edge triggered (if GP4_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO4 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO4 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO4 Output pin configuration 0 = CMOS 1 = Open Drain GPIO4 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO4 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request REFER TO 14:13 GP4_PULL[1:0] 01 12 GP4_INT_MO DE 0 11 GP4_PWR_DO M GP4_POL 0 10 1 9 GP4_OD 0 8 GP4_ENA 0 7:4 GP4_FN[3:0] 0000 w PP, December 2009, Rev 3.0 287 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:2 LED1_SRC[1:0 ] 11 LED1 Source Selects the LED1 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED1 also indicates completion of OTP Auto Program LED2 Source Selects the LED2 function.) 00 = Off 01 = Power State Status 10 = Charger Status 11 = Manual Mode Note - LED2 also indicates an OTP Auto Progam Error condition Pre-Production REFER TO 1:0 LED2_SRC[1:0 ] 11 Register 781Dh GPIO4 OTP Control w PP, December 2009, Rev 3.0 288 Pre-Production REGISTER ADDRESS R30750 (781Eh) GPIO5 OTP Control BIT 15 LABEL GP5_DIR DEFAULT 1 DESCRIPTION GPIO5 pin direction 0 = Output 1 = Input GPIO5 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO5 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP5_POL=1) or falling edge triggered (if GP5_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO5 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO5 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO5 Output pin configuration 0 = CMOS 1 = Open Drain GPIO5 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO5 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done WM8312 REFER TO 14:13 GP5_PULL[1:0] 01 12 GP5_INT_MO DE 0 11 GP5_PWR_DO M GP5_POL 0 10 1 9 GP5_OD 0 8 GP5_ENA 0 7:4 GP5_FN[3:0] 0000 w PP, December 2009, Rev 3.0 289 WM8312 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 USB_ILIM[2:0] 010 Sets the USB current limit 000 = 0mA (USB switch is open) 001 = 2.5mA 010 = 100mA 011 = 500mA 100 = 900mA 101 = 1500mA 110 = 1800mA 111 = 550mA Pre-Production REFER TO Register 781Eh GPIO5 OTP Control REGISTER ADDRESS R30751 (781Fh) GPIO6 OTP Control BIT 15 LABEL GP6_DIR DEFAULT 1 DESCRIPTION GPIO6 pin direction 0 = Output 1 = Input GPIO6 Pull-Up / Pull-Down configuration 00 = No pull resistor 01 = Pull-down enabled 10 = Pull-up enabled 11 = Reserved GPIO6 Interrupt Mode 0 = GPIO interrupt is rising edge triggered (if GP6_POL=1) or falling edge triggered (if GP6_POL=0) 1 = GPIO interrupt is triggered on rising and falling edges GPIO6 Power Domain select 0 = DBVDD 1 = SYSVDD GPIO6 Polarity select 0 = Inverted (active low) 1 = Non-Inverted (active high) GPIO6 Output pin configuration 0 = CMOS 1 = Open Drain GPIO6 Enable control 0 = GPIO pin is tri-stated 1 = Normal operation GPIO6 Pin Function Input functions: 0 = GPIO input (long de-bounce) 1 = GPIO input 2 = Power On/Off request 3 = Sleep/Wake request 4 = Sleep/Wake request (long de-bounce) REFER TO 14:13 GP6_PULL[1:0] 01 12 GP6_INT_MO DE 0 11 GP6_PWR_DO M GP6_POL 0 10 1 9 GP6_OD 0 8 GP6_ENA 0 7:4 GP6_FN[3:0] 0000 w PP, December 2009, Rev 3.0 290 Pre-Production REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5 = Sleep request 6 = Power On request 7 = Watchdog Reset input 8 = DVS1 input 9 = DVS2 input 10 = HW Enable1 input 11 = HW Enable2 input 12 = HW Control1 input 13 = HW Control2 input 14 = HW Control1 input (long de-bounce) 15 = HW Control2 input (long de-bounce) Output functions: 0 = GPIO output 1 = 32.768kHz oscillator output 2 = ON state 3 = SLEEP state 4 = Power State Change 5 = Reserved 6 = Touch Panel Pen Down 7 = Touch Panel Conversion complete 8 = DC-DC1 DVS Done 9 = DC-DC2 DVS Done 10 = External Power Enable1 11 = External Power Enable2 12 = System Supply Good (SYSOK) 13 = Converter Power Good (PWR_GOOD) 14 = External Power Clock (2MHz) 15 = Auxiliary Reset 3:1 SYSOK_THR[2 :0] 101 SYSOK threshold (rising SYSVDD) This is the rising SYSVDD voltage at which SYSLO will be de-asserted 000 = 2.8V 001 = 2.9V ... 111 = 3.5V WM8312 REFER TO Register 781Fh GPIO6 OTP Control REGISTER ADDRESS R30759 (7827h) DBE CHECK DATA BIT 15:0 LABEL DEFAULT DESCRIPTION REFER TO DBE_VALID_D 0000_0000 This field is checked in development mode when an ATA[15:0] _0000_000 `ON' transition is requested. A value of A596h is required to confirm valid data. 0 Register 7827h DBE CHECK DATA w PP, December 2009, Rev 3.0 291 WM8312 30 APPLICATIONS INFORMATION 30.1 TYPICAL CONNECTIONS SYSVDD Pre-Production CPU ARM Core CPU Internal Logic & Caches Memory NOR / DDR_SDRAM Backlight LED Supply R1 R2 White LED backlight SYSVDD CPU ALIVE LDO11VOUT LDO10VOUT LDO9VOUT LDO8VOUT LDO7VOUT LDO6VOUT LDO5VOUT LDO4VOUT LDO3VOUT LDO2VOUT LDO1VOUT ISINK2 ISINK1 LED2 CC Sink CPU_PLL Charger ON Power status WiFi LED1 XOSCGND ISINKGND DBGND GND TPVDD TPGND AUXADCIN4 AUXADCIN3 AUXADCIN2 AUXADCIN1 HD Radio RF HD Radio Core Mobile TV CPU_IO_Block CPU_DAC LDO13VOUT CPU_ADC CPU_RTC External voltage measurement inputs CPU_OTG WM8312 Resistive Touch Panel General Purpose Input/Output pins GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 SDOUT SDA2 SCLK2 SDA1 SCLK1 / CS CIFMODE PROGVDD CLKOUT CLKIN VREFC IREFR REFGND LDO13VOUT LDO12VOUT LDO10VDD LDO9VDD DBVDD PVDD LDO8VDD LDO7VDD LDO6VDD LDO5VDD LDO4VDD LDO3VDD LDO2VDD LDO1VDD DCDC3VDD DCDC2VDD DCDC1VDD DCDC3VOUT DCDC3VOUT Configuration data loaded from internal OTP 2 wire I2C slave Device ID 34h 2 wire I2C 12.288MHz MCLK OUT 32kHz IN Backup Battery NTC USB Power In SingleCell Li-ion Battery System Power In Figure 40 WM8312 Typical Connections Diagram For detailed schematics, bill of materials and recommended external components refer to the WM8312 evaluation board users manual. w PP, December 2009, Rev 3.0 292 Pre-Production WM8312 30.2 VOLTAGE AND CURRENT REFERENCE COMPONENTS A decoupling capacitor is required between VREFC and REFGND; a 100nF X5R capacitor is recommended (available in 0201 package size). A current reference resistor is required between IREFR and REFGND; a 100k (1%) resistor is recommended. 30.3 DC-DC (STEP-DOWN) CONVERTER EXTERNAL COMPONENTS The recommended connections to the DC-DC (Step-Down) Converters are illustrated in Figure 41. Figure 41 DC-DC (Step-Down) Converters External Components When selecting suitable capacitors, is it imperative that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. It should be noted that some components' capacitance changes significantly depending on the DC voltage applied. Ceramic X7R or X5R types are recommended. The choice of output capacitor varies depending on the required transient response. Larger values may be required for optimum performance under large load transient conditions. Smaller values may be sufficient for a steady load, or in applications without stringent requirements on output voltage accuracy during load transients. For layout and size reasons, users may choose to implement large values of output capacitance by connecting two or more capacitors in parallel. To ensure stable operation, the DCm_CAP register fields must be set according to the output capacitance, as described in Section 15.6. When selecting a suitable output inductor, the inductance value and the saturation current must be compatible with the operating conditions of the converter. The magnitude of the inductor current ripple is dependant on the inductor value and can be determined by the following equation: w PP, December 2009, Rev 3.0 293 WM8312 Pre-Production As a minimum requirement, the DC current rating should be equal to the maximum load current plus one half of the inductor current ripple: To be suitable for the application, the chosen inductor must have a saturation current that is higher than the peak inductor current given by the above equation. To maximise the converter efficiency, the inductor should also have a low DC Resistance (DCR), resulting in minimum conduction losses. Care should also be taken to ensure that the component's inductance is valid at the applicable operating temperature. Wolfson recommends the following external components for use with DC-DC Converters 1 and 2. The output inductor must be consistent with the DCm_FREQ register settings. For 4MHz (best transient performance) operation, the inductor must be 0.5H. For 2MHz (best efficiency), the inductor must be 2.2H. Note that for output voltages greater than 1.4V, the 2MHz mode must be used. The output capacitor must be consistent with the DCm_CAP register settings. For best performance, the 47F component is recommended. For typical applications, the 22F is suitable. The alternative values may be used for size or cost reasons if preferred. COMPONENT L VALUE 0.5H 2.2H COUT 47F 22F 10F 4.7F CIN 10F PART NUMBER Coilcraft XPL2010-501MLB Coilcraft LPS3010-222ML TDK VLS252012T-2R2M1R3 MuRata GRM21CR60J476ME15 MuRata GRM21AR60J226UE80 MuRata GRM188R60J106ME84 MuRata GRM188R60J475ME84 MuRata GRM188R60J106ME84 SIZE 2 x 2.5 x 1mm 3 x 3 x 1mm 2 x 1.25 x 1.2mm 0805 0805 0603 0603 0603 Table 115 Recommended External Components - DC-DC1, DC-DC2 Wolfson recommends the following external components for use with DC-DC Converter 3. Note that the switching frequency of DC-DC3 is fixed at 2MHz and the output inductor must be 2.2H in all cases. The output capacitor must be consistent with the DC3_CAP register setting. For best performance, the 47F component is recommended. For typical applications, the 22F is suitable. The alternative values may be used for size or cost reasons if preferred. COMPONENT L COUT VALUE 2.2H 47F 22F 10F CIN 4.7F PART NUMBER Coilcraft LPS3010-222ML TDK VLS252012T-2R2M1R3 MuRata GRM21CR60J476ME15 MuRata GRM21AR60J226UE80 MuRata GRM188R60J106ME84 MuRata GRM188R60J475ME84 SIZE 3 x 3 x 1mm 2 x 1.25 x 1.2mm 0805 0805 0603 0603 Table 116 Recommended External Components - DC-DC3 w PP, December 2009, Rev 3.0 294 Pre-Production WM8312 The recommended connections to the DC-DC (Step-Up) Converter are illustrated in Figure 42. 2.7V - 5.5V L VO 30.4 DC-DC (STEP-UP) CONVERTER EXTERNAL COMPONENTS CIN DC4VDD DC4LX COUT WM8312 DC-DC4 DC4_FBSRC = 0 (ISINK1) DC4_FBSRC = 1 (ISINK2) DC4GND ISINKn R1 DC4FB R2 Figure 42 DC-DC (Step-Up) Converters External Components In the constant current mode, the DC-DC Converter output voltage is controlled by the WM8312 in order to achieve the required current in ISINK1 or ISINK2. The required current is set by the CSn_ISEL register fields, as described in Section 16.2.2. A typical application for this mode would be a white LED driver, where several LEDs are connected in series to achieve uniform brightness. The DC-DC (Step-Up) Converter is capable of generating output voltages of up to 30V. The maximum output voltage is determined by the two external resistors R1 and R2, which form a resistive divider between load connection and the voltage feedback pin DC4FB. The maximum output voltage is set as described in the following equation: Setting R2 to 47k is recommended for most applications; R1 can be calculated using the following equation, given the required output voltage: Note that the resistors determine the maximum output voltage. The actual voltage will be determined by the selected ISINK current, subject to the device limits. When selecting a suitable capacitor, is it imperative that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. Ceramic X7R or X5R types are recommended.The choice of output capacitor for DC-DC4 varies depending on the required output voltage. See Table 117 for further details. w PP, December 2009, Rev 3.0 295 WM8312 Pre-Production When selecting a suitable output inductor, the inductance value and the saturation current must be compatible with the operating conditions of the converter. The magnitude of the inductor current ripple is dependent on the inductor value and can be determined by the following equation: IL = VOUT - VIN L . FSW IL VOUT VIN L FSW = Inductor ripple current = Output voltage = Input voltage = Inductance = Switching frequency The inductor current is also a function of the DC-DC Converter maximum input current, which can be determined by the following equation: As a minimum requirement, the DC current rating should be equal to the maximum input current plus one half of the inductor current ripple. To be suitable for the application, the chosen inductor must have a saturation current that is higher than the peak inductor current given by the above equation. To maximise the converter efficiency, the inductor should also have a low DC Resistance (DCR), resulting in minimum conduction losses. Care should also be taken to ensure that the component's inductance is suitable at the applicable operating temperature. When ISINK1 or ISINK2 is used in conjunction with DC-DC Converter 4, the ISINK should always be switched on before the DC-DC Converter is switched on. Conversely, the DC-DC Converter should always be switched off before the ISINK is switched off. Wolfson recommends the following external components for use with DC-DC Converter 4. The output capacitor COUT must be selected according to the required output voltage. For 10V output, 4.7F is recommended. For 15V output, 3.3F is recommended. For 20-30V output, 1.5F is recommended. The resistors R1 and R2 must be selected according to the required output voltage - refer to the equations above. The values quoted below are suitable for 20V output. COMPONENT L COUT VALUE 10H 4.7F 3.3F 1.5F CIN FET 2.2F PART NUMBER Taiyo-Yuden NR3015T100M Murata GRM31CR61C475KA01 Murata GRM31CR71C335KA01 MuRata GRM31CR71H225KA88 MuRata GRM188R61A5KE34 Vishay SIA814DJ-T1-GE3 SIZE 3 x 3 x 1.5mm 1206 1206 1206 0603 SC-70-6 2.05 x 2.05 x 0.75mm 0603 0603 R1 R2 1.8M 47k Phycomp 2322 7046 1805 Multicomp MIC 0.063W 0603 1% 47K Table 117 Recommended External Components - DC-DC4 w PP, December 2009, Rev 3.0 296 Pre-Production WM8312 The recommended connections to the LDO Regulators are illustrated in Figure 43. 30.5 LDO REGULATOR EXTERNAL COMPONENTS 1.5V - 5.5V CIN LDO1VDD WM8312 LDO1 LDO1VOUT COUT GND VO Load Note: Equivalent circuit applies for LDO2 through to LDO10. Figure 43 LDO Regulators External Components When selecting suitable capacitors, is it imperative that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. Ceramic X7R or X5R types are recommended. Wolfson recommends the following external components for use with LDO Regulators 1 to 6. COMPONENT COUT CIN VALUE 2.2F 1.0F PART NUMBER Kemet C0402C225M9PAC MuRata GRM155R61A105KE15 SIZE 0402 0402 Table 118 Recommended External Components - LDO1 to LDO6 Wolfson recommends the following external components for use with LDO Regulators 7 to 10. COMPONENT COUT CIN VALUE 1.0F 1.0F PART NUMBER MuRata GRM155R61A105KE15 MuRata GRM155R61A105KE15 SIZE 0402 0402 Table 119 Recommended External Components - LDO7 to LDO10 Wolfson recommends the following external components for use with LDO Regulators 11 to 13. COMPONENT COUT (LDO11) COUT (LDO12) COUT (LDO13) VALUE 0.1F 0.1F 2.2F PART NUMBER MuRata GRM033R60J104KE19 MuRata GRM033R60J104KE19 Kemet C0402C225M9PAC SIZE 0201 0201 0402 Table 120 Recommended External Components - LDO11 to LDO13 w PP, December 2009, Rev 3.0 297 WM8312 30.6 BATTERY TEMPERATURE MONITORING COMPONENTS Pre-Production Battery temperature monitoring is performed using a reference voltage output on the NTCBIAS pin. A potential divider is formed between the NTC bias resistor and the NTC thermistor component within the battery pack. The voltage present at the NTCMON pin is used to determine the battery temperature. The recommended connections and the derivation of VNTCMON is shown in Figure 44. VNTCMON = Main battery connection Battery monitor source RNTC 100k + RNTC x VNTCBIAS BATTVDD NTCBIAS 100K WM8312 Battery temperature measurement NTC bias resistor RBIAS (100k) NTCMON NTC thermistor RNTC (100k at 25 C) NTC Single-cell lithium battery GND Figure 44 Battery Temperature Monitoring The voltage thresholds for the Hot/Cold Battery Temperature conditions are fixed in the WM8312: The Cold Battery condition is detected when VNTCMON > 0.765 x VNTCBIAS The Hot Battery condition is detected when VNTCMON < 0.348 x VNTCBIAS If the NTC thermistor has a nominal resistance of 100k at 25C, and follows the Vishay ResistanceTemperature Curve 1, then the above equations result in the Hot Battery threshold = 40C and the Cold Battery threshold = 0C. For example, if the NTC thermistor resistance is 53.4k at 40C, then VNTCMON is given by the following equation: The upper and lower temperature thresholds can be adjusted by modification of the NTC bias resistor and/or the addition of another resistor between the battery pack and the NTCMON pin. If only the NTC bias resistor is adjusted, then either the upper or lower threshold can be selected, but not both; the other threshold will be determined by the thermistor characteristics. If an additional resistor is inserted between the battery pack and the NTCMON pin, then the upper and lower thresholds can be independently selected, with the constraint that the upper and lower thresholds must be at least 40C apart. w PP, December 2009, Rev 3.0 298 Pre-Production WM8312 To select a specific Hot Battery threshold, the required NTC bias resistor value may be calculated using the following equation: RBIAS = (rHOT / 0.534) x R25 rHOT is the NTC thermistor resistance ratio at the desired temperature threshold R25 is the NTC thermisor resistance at 25C For example, at 60C the Vishay Curve 1 resistance ratio, rHOT, is 0.2488. Therefore, to implement a 60C Hot Battery threshold, assuming a 100k NTC thermistor (at 25C), the required NTC bias resistor is 46.6k (nearest E12 value 47k). The resultant Cold Battery threshold is given using the rCOLD equation below. The rCOLD value needs to be referenced to the Vishay Curve 1 resistance chart in order to find the corresponding temperature. To select a specific Cold Battery threshold, the required NTC bias resistor value may be calculated using the following equation: RBIAS = (rCOLD / 3.255) x R25 rCOLD is the NTC thermistor resistance ratio at the desired temperature threshold R25 is the NTC thermisor resistance at 25C For example, at 5C the Vishay Curve 1 resistance ratio, rCOLD, is 2.540. Therefore, to implement a 5C Cold Battery threshold, assuming a 100k NTC thermistor (at 25C), the required NTC bias resistor is 78k (nearest E12 value 82k). The resultant Hot Battery threshold is given using the rHOT equation below. The rHOT value needs to be referenced to the Vishay Curve 1 resistance chart in order to find the corresponding temperature. To select both the Hot Battery threshold and the Cold Battery threshold, an additional resistor, R1, is required, as illustrated in Figure 45. Figure 45 Battery Temperature Threshold Selection w PP, December 2009, Rev 3.0 299 WM8312 Pre-Production Under the circuit configuration above, the NTC bias resistors RBIAS and R1 are calculated using the following equations: RBIAS = ((rCOLD - rHOT) / 2.721) x R25 R1 = (0.534 x RBIAS) - (rHOT x R25) For example, to select a 45C Hot Battery threshold and a 0C Cold Battery threshold, the applicable resistance ratios are rHOT = 0.4368 and rCOLD = 3.266. Assuming a 100k NTC thermistor (at 25C), then R25 = 100k. From the equations above, it follows that RBIAS = 104k (nearest E12 value 100k). Assuming the E12 (100k) value of RBIAS, then R1 = 9.72k (nearest E12 value 10k). w PP, December 2009, Rev 3.0 300 Pre-Production WM8312 Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. Poor regulation and instability can result. Simple design rules can be implemented to negate these effects: External input and output capacitors should be placed as close to the device as possible using short wide traces between the external power components. Route output voltage feedback as an independent connection to the top of the output capacitor to create a true sense of the output voltage, routing away from noisy signals such as the LX connection. Use a local ground island for each individual converter connected at a single point onto a fully flooded ground plane. Current loop areas should be kept as small as possible with loop areas changing little during alternating switching cycles. The layout in Figure 46, for example, shows DC-DC1 layout with external components C3, L3 and C6. The input capacitor, C6, is close into the IC and shares a small ground island with the output capacitor C3. The inductor, L3, is situated in close proximity to C3 in order to keep loop area small and current flowing in the same direction during alternating switching cycles. Note also the use of short wide traces with all power tracking on a single (top) layer. 30.7 PCB LAYOUT Figure 46 PCB Layout w PP, December 2009, Rev 3.0 301 WM8312 31 PACKAGE DIAGRAM B: 169 BALL BGA PLASTIC PACKAGE 7 X 7 X 1.17 mm BODY, 0.50 mm BALL PITCH Pre-Production DM062.B 5 D 2 A A2 A B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2 DETAIL 1 1 4 A1 CORNER e 6 E1 E 2X e D1 2X 0.10 Z 0.10 Z DETAIL 2 SIDE VIEW TOP VIEW BOTTOM VIEW SOLDER BALL bbb Z aaa Z 1 Z A1 b DETAIL 2 3 DETAIL 1 ccc Z X Y ddd Z Symbols MIN A A1 A2 b D D1 E E1 e aaa bbb ccc ddd REF: 0.17 0.91 0.25 NOM 1.17 0.21 0.96 0.30 Dimensions (mm) MAX 1.27 0.26 1.01 0.35 NOTE 7.00 BSC 6.00 BSC 7.00 BSC 6.00 BSC 0.50 BSC Tolerances of Form and Position 0.08 0.10 0.15 0.05 JEDEC, MO-195 6 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS . 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT `A1'. 3. DIMENSION `b' IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM -Z-. 4. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY . 6. `e' REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 8. FALLS WITHIN JEDEC, MO-195 w PP, December 2009, Rev 3.0 302 Pre-Production WM8312 32 IMPORTANT NOTICE Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PP, December 2009, Rev 3.0 303 |
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