View QL901M-6PS680_415749.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

QL901M QuickMIPSTM Data Sheet
* * * * * * QuickMIPS ESP Family 1.0 Overview
The QuickMIPSTM Embedded Standard Products (ESPs) family provides an out-of-the box solution consisting of the QL901M QuickMIPS chip and the QuickMIPS development environment. The development environment includes a Reference Design Kit (RDK) with drivers, real-time operating systems, and QuickMIPS system model. With the RDK, software and hardware engineers can evaluate, debug, and emulate their system in parallel.
* 16 Kbytes of on-chip, high-speed SRAM for *
* * *
use by multiple AHB Bus Masters 32-bit 66/33 MHz PCI Host and Satellite (Master/Target) operation with DMA channels and FIFO for full bandwidth Two MAC10/100s with MII ports connect easily to external transceivers/PHY devices One AHB 32-bit master port/one AHB 32-bit slave port to Programmable Fabric Global System Configuration and Interrupt Controller
CPU
* High-performance MIPS 4Kc processor runs
Peripheral Bus (AMBA APB)
* 32-bit APB runs at half the CPU clock
* * * *
up to 133 MHz in .25 (173 Dhrystone MIPS) 1.3 Dhrystone MIPS per MHz MDU supports MAC instructions for DSP functions 16 Kbytes of Instruction Cache (4-way set associative) 16 Kbytes of Data Cache (4-way set associative) with lockout capability per line
frequency (the same as the AHB clock) * Three APB slave ports in the programmable fabric * Two serial ports (one with Modem control signals and one with IRDA-compliant signals) * Four general-purpose 32-bit timer/counters on one APB port
16 Kbytes SRAM MIPS 4Kc w/Caches 32-bit PCI 66/33 MHz Ethernet 10/100 MAC Ethernet 10/100 MAC Memory Controller Interrupt Controller
High-Performance Bus (AMBA AHB)
* High-performance 32-bit AMBA AHB bus
ECI to AHB
* *
* * *
standard for high-speed system bus running at half the CPU clock High-bandwidth memory controller for SDRAM, SRAM, and EPROM SDRAM support for standard SDRAMs up to 256 MBytes with auto refresh, up to 4 banks non-interleaved Support for PC100 type memories with up to two chip enables EPROM controller for boot code 8-bit, 16-bit, and 32-bit device width support
32-bit Advanced High-Performance Bus
AHB to APB Two 16550 UARTs Four 32-bit Timer/Counters
32-bit Advanced Peripheral Bus
3 APB Slave I/F
36 RAM Blocks (Configurations 128x18; 256x9; 512x4; or 1024x2)
1 AHB Master I/F 1 AHB Slave I/F
Via-Link Programmable Fabric
Configurable Logic Analyzer Monitor (CLAM)
JTAG
18 ECU Blocks-- 8x8 Multiply, 16-bit carry/add
Figure 1: Embedded QuickMIPS Block Diagram
* * * * * *
QL901M QuickMIPSTM Data Sheet Rev B
1
Programmable Via-Link Fabric
* Embedded memory configurable as RAM or FIFO * 252 programmable I/Os * High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with
3-bit instructions * Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3
Table 1: Programmable Fabric Features Maximum System Gates*
536,472
Logic Arrays Maximum Logic Cells RAM Blocks** RAM Bits Columns x Rows Flip-Flops
72x28 2,016 4,788 36 82,944
ECU Blocks***
18
* 75K ASIC gates
** Possible Configurations: 128x18, 256x9, 512x4, or 1024x2
*** 8x8 Multiply, 16-bit carry-add
On-Chip Debug Blocks
* On-chip instrumentation blocks for debug and trace capabilities * Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look
at selected signals from IP function in fabric
Development and Programming
* Complete QuickLogic software suite of development tools enables rapid implementation of IP
* * * * * * *
functions for complete SOC solution * Complete chip simulation of user-defined programmable-logic IP functions with the processor, caches, memory, and all hardwired functions on-chip * Synthesis of IP functions into the programmable fabric * Place-and-Route tool for efficient implementation of IP functions in the programmable fabric * Extensive timing analysis of IP functions with the rest of the chip to ensure full chip functionality * Programming and debug support of the entire chip through JTAG port * Integrated debug support for the MIPS 4Kc processor MIPS Language and Debug tool support for the MIPS 4Kc processor from approved third party MIPS vendors ECU support for a variety of DSP algorithms and functions QuickLogic library of standard IP functions for plug-and-play implementation of standard IP functions in the programmable fabric for a complete SOC solution QuickMIPS Reference Design Kit (RDK) provides a complete Board Support Package for chip evaluation Programming and debug support Device-driver support for standard IP functions Boot-up code and diagnostics
2
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Design Tools Platform Support
* QuickWorks, the complete product suite, supports Windows 95/98/NT/2000. It includes SpDE
(layout including place & route, timing analysis, and back-annotation), Synplify-Lite (synthesis), Turbo Writer (HDL-enhanced text editor), etc. * QuickTool supports Solaris. It has only the layout software (SpDE). * QuickMIPS simulation is enabled through either: * a SmartModel (VMC-generated model, encrypted RTL, relatively slow). This option supports both Verilog and VHDL. * SaiLAhead co-verification platform from Saivision (very fast C model). This option only supports Verilog (no VHDL) at this time.
Table 2: Design Tools Platform Support Solaris
Synthesis Layout SmartModel Verilog XL/NC Simulation ModelSim SaiLAhead Verilog XL/NC X X X X X X Synplify-Lite SpDE ModelSim/VCS X (in QuickTool) X
Windows NT
Windows 2000
Linux
X (in QuickWorks) X (in QuickWorks) X (in QuickWorks) X (in QuickWorks) X
SaiLAhead Platform
The "SaiLAhead for QuickMIPS" co-verification platform is tailored for QuickMIPS devices. It enables simulation of user-defined logic functions that are to be implemented in the QuickMIPS programmable fabric with the rest of the QuickMIPS fixed system logic functions, which verifies overall QuickMIPS functionality. Simultaneously, the SaiLAhead platform has a powerful, feature-rich debugger, which enables QuickMIPS users to develop and debug their application code (C and MIPS assembly). The SaiLAhead platform accelerates the speed of simulation of the QuickMIPS device in a simulator such as NC-Verilog by using C models for various fixed system logic functions in the QuickMIPS device. This platform also provides a standalone C environment offering additional speed-up of simulation of the entire QuickMIPS design. Please refer to ht t p : // ww w. s a iv is i o n. c o m for more information on the SaiLAhead platform.
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
3
2.0 Embedded Computational Units (ECUs)
Traditional programmable logic architectures do not implement arithmetic functions efficiently or effectively. These functions require high logic cell usage while garnering only moderate performance results. By embedding a dynamically reconfigurable computational unit, the QuickMIPS chip can address various arithmetic functions efficiently and effectively providing for a robust DSP platform. This approach offers greater performance than traditional programmable logic implementations. The ECU block is ideal for complex DSP, filtering, and algorithmic functions. The QuickMIPS architecture allows functionality above and beyond that achievable using DSP processors or programmable logic devices. The embedded block is implemented at the transistor level with the following block diagram in Figure 2.
Abus Xbus Ybus
16 8 8
Multiply
I bus Sign
Add
Register
3
2 1
17
Rbus
Sequencer
Memory
Logic Cell
Figure 2: Embedded Computational Unit (ECU) Block Diagram
Table 3: ECU Comparisons Function Description
16 bit Adder 32 bit 64 bit 8x8 Multiplier 16 x 16 System Clock 12ns 200 MHz 6.7 ns 400 MHz
Slowest Speed Grade
8 ns 10 ns 12 ns 10 ns
Fastest Speed Grade
2.5 ns 5.6 ns 6.7 ns 4.3 ns
Implementation of the equivalent ECU block as HDL in a programmable logic architecture requires 205 logic cells with a 10 ns delay in a -4 speed grade. There are a maximum of 18 ECU blocks and a minimum of 10 ECU blocks in the QuickMIPS chip. The ECU blocks are placed next to the RAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Eighteen 8-bit Multiply Accumulate functions can be implemented per cycle for a total of 2.6 billion MACs/s when clocked at 144 MHz. Further Multiply Accumulate functions also can be implemented in the programmable logic.
4
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 4. The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.
Table 4: ECU Mode Select Criteria Instruction Set
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Operation
Multiply Multiply - Add Accumulate Add Multiply (registered) Multiply - Add (registered) Multiple - Accumulate Add (registered)
The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an external software driven algorithm, or an internal state machine. This flexibility allows the designer to reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock cycle, such as adaptive filtering.
3.0 Design Flow
The QuickMIPS design flow, similar to ASIC design flow, is shown in Figure 3.
MIPS Programming
Compiler, Assembler, Linker Debugger
EJTAG
System Configuration
Global Register Configuration
Customer IP Design in FPGA
RTL Synthesis Place & Route Timing Analysis Final Netlist & Timing
Timing Lib QuickIP Models
Synthesis Lib
QuickMIPS System Model
Board-level Support Package
QuickIP Netlist
Full-System Functional Co-simulation with Timing
Chip Programming
Figure 3: QuickMIPS Hardware/Software Co-Development Flow
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
5
A typical design process goes through the flow shown above. After passing postlayout simulation, QuickMIPS devices can be programmed for testing on the hardware testbench. Because QuickLogic devices are One-Time-Programmable (OTP), it is recommended that these devices are programmed only after they pass postlayout simulation to minimize development cost and reduce bench debugging time. The QuickMIPS design flow is supported by QuickLogic's QuickWorksTM (for Microsoft Windows) and QuickToolTM (for UNIX) design software suites version 9.2 and up. Many third-party synthesis and simulation tools are also supported. The QuickWorks software suite can be downloaded from QuickLogic's Web site ( ww w. q ui ckl og i c . c om ). Please contact a QuickLogic sales representative to obtain a license or get QuickTool software. Both Verilog and VHDL design methodologies are fully supported. The flow described below assumes that the QuickWorks or QuickTool 9.2 software has been installed.
3.1 Simulation
QuickLogic provides the system simulation environment. This environment includes the QuickMIPS VMC model, ROM and RAM models, reset and clock generation, boot code, and sample programs (read and write to memory). This environment allows customers to focus on their RTL code and not have to worry about bringing up the system simulation environment. The simulation behavior of the QuickMIPS ESP core is provided by the VMC model. VMC (Verilog Model Compiler) is a tool from Synopsys that compiles Verilog RTL (Register-Transfer-Level) code into binary code. A VMC model (the binary code) implements the same logic functions as the RTL code while providing IP protection. In simulation, it communicates to the simulator via PLI (Programmable Language Interface) for Verilog or FLI (Foreign Language Interface) for VHDL. Because of the VMC model, the Silos III Verilog simulator and Active-HDL VHDL simulator bundled in QuickWorks are not supported in QuickMIPS simulation flow. A third-party simulator must be used. The currently supported simulators include:
* Verilog simulators: Verilog-XL, NC Verilog, VCS, ModelSim * VHDL simulators: VSS, ModelSim
3.2 Synthesis
Synthesis is the process of turning the HDL code describing the fabric behavior into gates. Three thirdparty synthesis tools are supported:
* Synplify-Lite from Synplicity (bundled in QuickWorks) * Exemplar Leonardo Spectrum * Synopsys Design Compiler
Refer to the corresponding QuickNotes on the QuickLogic support Web site for further information.
6
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
3.3 Layout
Layout is performed in SpDE, which is the QuickLogic layout environment in both QuickWorks and QuickTool. The input to the layout is a netlist from synthesis. SpDE can accept netlists in both the QuickLogic format (.qdf) and industry standard EDIF.
3.4 Programming
Once it has been determined that the design is functionally correct and meets the desired timing constraints, run the sequencer and save the .chp file. You can either import the design into QuickPro if you want to program it yourself, or submit the file to QuickLogic's WebASIC service to obtain programmed devices overnight at the following URL: w ww. qu ickl og ic .co m/ we bas ic . QuickPro is the software to program a .chp file into QuickLogic devices. It is freeware and does not require a license. You can download it from the QuickLogic Web site. It runs only on Microsoft Windowsbased PCs. To program your device, you also need a programmer called DeskFab and a programming adapter for the package you are using. Please contact a QuickLogic sales representative when you are handling the programming.
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
7
4.0 AC Characteristics at Vcc = 2.5V, TA=25 C (K=0.74)
The AC Specifications, Logic Cell diagrams, and waveforms are provided below.
Figure 4: QuickMIPS Logic Cell
Table 5: Logic Cells Symbol Logic Cells
tPD tSU thl tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial delay: time taken by the combinatorial circuit to output Setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge Hold time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge Clock to out delay: the amount of time the synchronous input of the flip flop must be stable after the active clock edge Clock High Time: the length of time that the clock stays high Clock Low Time: the length of time that the clock stays low Set Delay: amount of time between when the flip flop is "set" (high) and when Q is consequent "set" (high) Reset Delay: amount of time between when the flip flop is "reset" (low) and when Q is consequent "reset" (low) Set Width: length of time that the SET signal remains high (low if active low) Reset Width: length of time that the RESET signal remains high (low if active low)
Parameter
Propagation delay (ns)
0.257 0.22 0 0.255 0.46 0.46 0.18 0.09 0.3 0.3
8
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
SET D CLK RESET
Figure 5: Logic Cell Flip Flop
Q
CLK
tCWI (min) tCWLO (min)
SET
RESET
Q
tRESET tRW tSET
tSW
Figure 6: Logic Cell Flip Flop Timings - First Waveform
CLK
D
tSU
tHL
Q
tCLK
Figure 7: Logic Cell Flip Flop Timings - Second Waveform
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
9
Figure 8: QuickMIPS Global Clock Structure
Table 6: QuickMIPS Clock Performance Clock Performance Global
Macro I/O Skew
1.51 ns 2.06 ns 0.55 ns
Dedicated
1.59 ns 1.73 ns 0.14 ns
Table 7: QuickMIPS Input Register Cell Symbol Parameter Input Register Cell Only
tGCKP GCKB Global clock pin delay to quad net Global clock buffer delay (quad net to flip flop) 1.34 0.56
Propagation delay (ns)
Programmable Clock Hardware Clock
Global Clock Buffer
Global Clock
tPGCK
tBGCK
Figure 9: Global Clock Structure Schematic
10
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
[9:0] [17:0]
WA WD WE WCLK
RE RCLK RA RD ASYNCRD [9:0] [17:0]
[1:0]
MODE
QuickRAM Module
Figure 10: RAM Module
Table 8: RAM Cell Synchronous Write Timing Symbol RAM Cell Synchronous Write Timing
tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: the amount of time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: the amount of time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: the amount of time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: the amount of time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: the amount of time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA=RA): the amount of time between the active WRITE CLOCK edge and the time when the data is available at RD
Parameter
Propagation delay (ns)
0.675 0 0.654 0 0.623 0 4.38
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
11
WCLK
WA
tSWA tHWA
WD
tSWD tHWD
WE
tSWE tHWE new data tWCRD
RD
old data
Figure 11: RAM Cell Synchronous Write Timing
Table 9: RAM Cell Synchronous & Asynchronous Read Timing Symbol Parameter Propagation delay (ns)
0.686 0 0.243 0 4.38
RAM Cell Synchronous Read Timing
tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: the amount of time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: the amount of time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: the amount of time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: the amount of time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: the amount of time between the active READ CLOCK edge and the time when the data is available at RD
RAM Cell Asynchronous Read Timing
rPDRD RA to RD: amount of time between when the READ ADDRESS is input and when the DATA is output 2.06
12
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
RCLK
RA
tSRA tHRA
RE
tSRE tHRE new data
RD
old data
tRCRD rPDRD
Figure 12: RAM Cell Synchronous & Asynchronous Read Timing
+ -
INPUT REGISTER
QE R
D
OUTPUT REGISTER
D R
Q
PAD
OUTPUT ENABLE REGISTER
D
EQ R
Figure 13: QuickMIPS Cell I/O
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
13
tIN, tINI
tICLK tISU + tSID
D
QE R
PAD
Figure 14: QuickMIPS Input Register Cell
Table 10: Input Register Cell Symbol Input Register Cell Only
tISU tIH tICLK tIRST tIESU tIEH Input register setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge Input register hold time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge Input register clock to Q: the amount of time taken by the flip flop to output after the active clock edge Input register reset delay: amount of time between when the flip flop is "reset"(low) and when Q is consequently "reset" (low) Input register clock enable setup time: the amount of time "enable" must be stable before the active clock edge Input register clock enable time: the amount of time "enable" must be stable after the active clock edge
Parameter
Propagation delay (ns)
3.12 0 1.08 0.99 0.37 0
14
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 11: Standard Input Delays Symbol Standard Input Delays
tSID (LVTTL) tSID (LVCMOS2) tSID (GTL+) tSID (SSTL3) tSID (SSTL2)
Parameter To get the total input delay and this delay to tISU
LVTTL input delay: Low Voltage TTL for 3.3V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3V SSTL2 input delay: Stub Series Terminated Logic for 2.5V
Propagation delay (ns)
0.34 0.42 0.68 0.55 0.607
R CLK
D Q
tISU
tIHL tICLK tIRST
E
tIESU tIEH
Figure 15: QuickMIPS Input Register Cell Timing
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
15
PAD OUTPUT REGISTER
Figure 16: QuickMIPS Output Register Cell
Table 12: QuickMIPS Output Register Cell Symbol Output Register Cell Only
tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCO Output Delay low to high (10% of H) Output Delay high to low (90% of H) Output Delay 3-state to high (10% of Z) Output Delay 3-state to low (90% of Z) Output Delay high to 3-state Output Delay low to 3-state Clock to out delay
Parameter
Propagation delay (ns)
0.40 0.55 2.94 2.34 3.07 2.53 3.15 (fast slew) 10.2(slow slew)
16
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
H L H Z L H Z L
tOUTLH
H L H tPZH Z L H Z L
tOUTHL
tPZL tPHZ
tPLZ
Figure 17: QuickMIPS Output Register Cell Timing
Table 13: VCCIO = 3.3 V Fast Slew
Rising Edge Falling Edge
2.8 V/ns 2.86 V/ns
Slow Slew
1.0 V/ns 1.0 V/ns
Table 14: VCCIO = 2.5 V Fast Slew
Rising Edge Falling Edge
1.7 V/ns 1.9 V/ns
Slow Slew
0.6 V/ns 0.6 V/ns
Table 15: ESP PLL Timing Parameters Jitter
<200ps
Standby Current (a)
157 a
Frequency Range
40-66.6 MHz
Minimum Lock Frequency
25 MHz
Duty Cycle
60/40
Crystal Accuracy
200 PPM
Lock Time
10 s
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
17
PCI_CLK Tval PCI_AD(output)[31:0] PCI_C_BE_n(output)[3:0] PCI_PAR(output) PCI_FRAME_n(output) PCI_IRDY_n(output) PCI_TRDY_n(output) PCI_STOP_n(output) PCI_DEVSEL_n(output) PCI_SERR_n PCI_PERR_n(output) Tval(ptp) PCI_REQ_n Tsu PCI_AD(input)[31:0] PCI_C_BE_n(input)[3:0] PCI_PAR(input) PCI_FRAME_n(input) PCI_IRDY_n(input) PCI_TRDY_n(input) PCI_STOP_n(input) PCI_DEVSEL_n(input) PCI_IDSEL PCI_PERR_n(input) PCI_LOCK_n Tsu(ptp) PCI_GNT_n Figure 18: PCI Waveforms Th
18
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 16: PCI AC Timing Parametera Min
Tcyc Thigh Tlow - Tval Tval (ptp) Ton Toff Tsu Tsu (ptp) Th Trst Trst-clk Trst-off Trhfa Trhff
c
66 MHz Max Min
30 11 11 4 6 6 1 2 2 2 14 3 5 0 1 100 40 2 5 2 5 7
33 MHz Units Max
ns ns ns 4 11 12 V/ns ns ns ns 28 ns ns ns ns ms
PCI_CLK Cycle Time PCI_CLK High Time PCI_CLK Low Time PCI_CLK Slew Rate PCI_CLK to Signal Valid Delay PCI_CLK to Signal Valid Delay point-to-point signalsb Float to Active Delay Active to Float Delay Input Setup Time to PCI_CLK bused signals Input Setup Time to PCI_CLK point-to-point Input Hold Time from PCI_CLK Reset Active Time after power stable Reset Active Time after PCI_CLK stable Reset Active to output float delay PCI_RST_n high to first configuration access PCI_RST_n high to first PCI_FRAME_n assertion
15 6 6 1.5 2 2 2
10, 12 0 1 100 40
s
ns clocks clocks
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n. b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n. c. All output drivers must be 3-stated when PCI_RST_n is active.
TXCLK(in) TXEN(out) ten_c2q TXD[3:0](out) tdata_h tdata_v
Figure 19: Ethernet MAC Transmit Interface Waveforms
Table 17: Ethernet MAC Transmit Interface AC Timing Parameter
ten_c2q tdata_v tdata_h Time from the rising clock edge of TXCLK to the change in TXEN Time from the rising clock edge of TXCLK to all data signals having valid stable values Time in which the output data is still valid after the rising clock edge of TXCLK 0.0
Min
Max
8.0 9.0
Units
ns ns ns
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
19
RXCLK(in) RXDV(in) tdv_h RXER(in) ter_h RXD[3:0](in) tdata_s tdata_h
Figure 20: Ethernet MAC Receive Interface Waveforms
tdv_s ter_s
Table 18: Ethernet MAC Receive Interface AC Timing Parameter
tdv_s tdv_h ter_s ter_h tdata_s tdata_h RXDV (receive data valid) to RXCLK setup time RXDV (receive data valid) from RXCLK hold time RXER (receive data error) to RXCLK setup time RXER (receive data error) from RXCLK hold time RXD (receive data) to RXCLK setup time RXD (receive data) from RXCLK hold time
Min
2.0 2.0 2.0 2.0 2.0 2.0
Max
Units
ns ns ns ns ns ns
The timing of the MII Management Interface listed below depends on the system clock frequency. The numbers displayed are correct for a processor clock frequency of 100 MHz and an AMBA bus system clock frequency of 50 MHz. Note that for a system clock of 133 MHz, the mandatory MDC minimum clock cycle of 400ns for some PHY devices will not be met.
20
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
tmdc_cyc tmdc_h MDC(out) MDIO(out) tmdozv tmdovh tmdovs tmdovz
Figure 21: MII Management Interface Waveforms (1 of 2)
tmdc_l
Table 19: MII Management Interface AC Timing (1 of 2) Parameter
tmdc_cyc tmdc_h tmdc_l tmdozv tmdovz tmdos tmdovh MDC cycle time MDC high time MDC low time MDIO output high impedance to valid time from rising edge of MDC MDIO output valid to high impedance time from rising edge of MDC MDIO output valid before MDC rising edge MDIO output valid from MDC rising edge
Min
520 260 260 40 40 440 40
Max
Units
ns ns ns ns ns ns ns
MDC(out) MDIO(in) tmdis tmdih
Figure 22: MII Management Interface Waveforms (2 of 2)
Table 20: MII Management Interface AC Timing (2 of 2) Parameter
tmdis tmdih MDIO setup time to MDC MDIO hold time to MDC
Min
25 0
Max
Units
ns ns
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
21
SD_CLKIN Tco_sdram ADDR[23:0] SD_CS_n[3:0] SD_CKE[3:0] SD_DQM[3:0] SD_RAS_n SD_CAS_n SD_WE_n DATA(output)[31:0] Tsu_sdram DATA(input[31:0] Th_sdram
Figure 23: SDRAM Waveforms
Table 21: SDRAM AC Timing Parameter
Tco Tsu Th
a
Min
2 12 2
Max
8
Units
ns ns ns
DATA, ADDR, SD_RAS_n, SD_CAS_n, SD_CS_n[3:0], SD_DQM[3:0], SD_WE_n, SD_CKE[3:0] DATA DATA
a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF load except for SD_CLKOUT, which has a load of 15 pF.
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n WEN_n D0 D1 DATA[31:0] read data Figure 24: SRAM Read Waveforms addr byte lane select
22
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Internal_AHB_Clock CS_n ADDR[31:0] BLS_n[3:0] OEN_n D0 D1 WEN_n DATA[31:0] write data Figure 25: SRAM Write Waveforms Table 22 and Table 23 below list the synchronous and asynchronous timing for the QuickMIPS Fabric addr byte lane select
interface port. Note the following with regards to the fabric timing:
1 2 3 4
fb_int is asynchronous and is synchronized inside the core. fb_bigendian is a static signal and reflects the value on the CPU_BIGENDIAN pin. pm_* and si_* signals are synchronous to the internal MIPS clock which is twice the hclk frequency. Because this internal clock is not brought to the outside, these signals are considered asynchronous. All AF_PCI_* signals are static. Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk) Setup Time (Tsu)
hresetn x
a
Hold Time (Thold)
x
Clock-to-out Time (Tco)
5.11
Fabric AHB Slave Ports
ahbs_hsel ahbs_haddr ahbs_htrans ahbs_hwrite ahbs_hsize ahbs_hburst ahbs_hprot ahbs_hwdata ahbs_hrdata ahbs_hready_out ahbs_hresp X X X X X X X X 5.94 9.55 10.39 X X X X X X X X 0 0 0 10.73 10.56 11.35 8.32 9.50 9.12 9.66 13.07 X X X
Fabric AHB Master Ports
ahbm_haddr ahbm_htrans ahbm_hwrite ahbm_hsize 11.94 11.33 10.39 10.58 0 0 0 0 X X X X
(Sheet 1 of 2) * * * * * *
QL901M QuickMIPSTM Data Sheet Rev B
23
Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk) (Continued) Setup Time (Tsu)
ahbm_hburst ahbm_hprotb ahbm_hwdata ahbm_hrdata ahb_hready_in ahbm_hresp ahbm_hbusreq ahbm_hgrant 10.79 - 10.39 X X X 7.40 X
Hold Time (Thold)
0 - 0 X X X 0 X
Clock-to-out Time (Tco)
X X X 16.28 11.82 9.02 X 16.64
Fabric APB Slave Ports
apbs_paddr apbs_pwdata apbs_penable apbs_pwrite apbs_psel0 apbs_psel1 apbs_psel2 apbs_prdata0 apbs_prdata1 apbs_prdata2 X X X X X X X 7.44 6.79 6.97 X X X X X X X 0 0 0 4.52 4.66 2.87 4.13 3.80 3.43 3.25 X X X
Timer Ports
tm_fbenable tm_overflow2 tm_overflow3 tm_overflow4 0.23 X X X 0 X X X X 4.35 4.48 5.00
(Sheet 2 of 2) a. "x" indicates that this timing delay does not apply to the signal. b. The ahbm_hprot signal is NOT used by any slave within the standard cell part of the chip. None of the masters besides the processor-AHB-bridge generates this signal. Therefore there is no setup or hold timing for ahbm_hprot.
24
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 23: QuickMIPS Interface Port Asynchronous Timing Start Port
ahbm_haddr ahbm_haddr ahbm_htrans ahbm_hwrite ahbm_hsize ahbm_hburst ahbm_hprot ahbm_hwdata ahbs_hrdata ahbs_hready_out ahbs_hresp ahbm_hbusreq ahbs_hresp apbs_prdata0 apbs_prdata1 apbs_prdata2
End Port
ahbs_haddr ahbs_hsel ahbs_htrans ahbs_hwrite ahbs_hsize ahbs_hburst ahbs_hprot ahbs_hwdata ahbm_hrdata ahb_hready_in ahbm_hresp ahbm_hgrant ahbm_hgrant ahbm_hrdata ahbm_hrdata ahbm_hrdata
Propagation Delay (Tprop)
8.39 7.71 6.48 6.21 6.04 5.70 7.07 8.15 5.78 5.03 4.98 10.14 10.50 8.28 7.51 7.57
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
25
5.0 DC Characteristics
The DC specifications are provided in Table 24 through Table 26.
Table 24: Absolute Maximum Ratings VCC Voltage VCCIO Voltage VREF Voltage Input Voltage Latch-up Immunity
-0.5 to 3.6V -0.5 to 4.6V 2.7V -0.5V to VCCIO +0.5V 100 mA
DC Input Current ESD Pad Protection Storage Temperature Maximum Lead Temperature
20 mA 2000V -65C to +150C
300C
Table 25: Operating Range Symbol Parameter Industrial Min
VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature
-4 Speed Grade -5 Speed Grade 2.3 2.3 -40
Commercial Min
2.3 2.3 0
Unit
Max
2.7 3.6 85
Max
2.7 3.6 70 V V C C
0.43 0.43 0.43 0.43
2.16 1.80 1.26 1.14
0.47 0.46 0.46 0.46
2.11 1.76 1.23 1.11
n/a n/a n/a n/a
K
Delay Factor -6 Speed Grade -7 Speed Grade
Table 26: DC Input and Output Levels VREF VMIN
LVTTL LVCMOS2 GTL+ PCI SSTL2 SSTL3 n/a n/a 0.88 n/a 1.15 1.3
VIL VMIN
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3
VIH VMIN
2.0 1.7 VREF+0.2 0.5xVCC VREF+0.18 VREF+0.2
VOL VMAX
VCCIO-0.3 VCCIO-0.3 VCCIO-0.3 VCCIO-0.5 VCCIO+0.3 VCCIO+0.3
VOH VMIN
24. 1.7 n/a 0.9xVC 1.76 1.90
IOL mA
2.0 2.0 40 1.5 7.6 9
IOH mA
-2.0 -2.0 n/a -0.5 -7.6 -8
VMAX
n/a n/a 1.12 n/a 1.35 1.7
VMAX
0.8 0.7 VREF-0.2 0.3xVCC VREF-0.18 VREF-0.2
VMAX
0.4 0.7 0.6 0.1xVCC 0.74 1.10
26
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
6.0 Pin Descriptions
Table 27 defines the QuickMIPS chip pins.
Table 27: Pin Descriptions Pin I/O
PCI Signals PCI Address and Data. PCI_AD[31:0] contain the multiplexed address and data. A bus transaction consists of a single address phase (or two address phases for 64-bit addresses) followed by one or more data phases. The QuickMIPS chip supports both read and write bursts. The address phase occurs in the first clock cycle when PCI_FRAME_n is asserted. During the address phase, PCI_AD[31:0] contain a 32-bit physical address. For I/O, this is a byte address; for configuration and memory, it is a DWORD (32-bit) address. During data phases, PCI_AD[7:0] contain the leastsignificant byte, and PCI_AD[31:24] contain the most-significant byte. Write data is stable and valid when PCI_IRDY_n is asserted; read data is stable and valid when PCI_TRDY_n is asserted. Data is transferred when both PCI_IRDY_n and PCI_TRDY_n are asserted. Bus Command and Byte Enables. Bus commands and byte enables are multiplexed on PCI_C_BE_n[3:0]. During the address phase of a transaction (PCI_FRAME_n is asserted), PCI_C_BE_n[3:0] define the bus command as shown in the following table (only valid combinations are shown). PCI_C_BE_n[3:0] 0000 0001 0010 0011 0110 PCI_C_BE_n[3:0] I/O 0111 1010 1011 1100 1101 1110 1111 Bus Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
Function
PCI_AD[31:0]
I/O
During each data phase, PCI_C_BE_n[3:0] are byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. PCI_C_BE_n[0] applies to byte 0 (PCI_AD[7:0]) and PCI_C_BE_n[3] applies to byte 3 (PCI_AD[31:24]). PCI_DEVSEL_n I/O PCI Device Select. When asserted low, PCI_DEVSEL_n indicates the driving device has decoded its address as the target of the current access. As an input, PCI_DEVSEL_n indicates whether any device on the bus has responded. PCI Cycle Frame. The current master asserts PCI_FRAME_n to indicate the beginning and duration of a bus transaction. While PCI_FRAME_n is asserted, data transfers continue. When PCI_FRAME_n is deasserted, the transaction is in the final data phase or has completed.
PCI_FRAME_n
I/O
(Sheet 1 of 6)
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
27
Table 27: Pin Descriptions (Continued) Pin
PCI_GNT_n PCI_IDSEL
I/O
I I
Function
PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been granted. PCI_GNT_n is ignored while PCI_RST_n is asserted. PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write transactions (PCI_C_BE_n[3:0] = 1010 or 1011). PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip. PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains asserted until the interrupt is cleared. Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only. However, such an interrupt controller can be built into the fabric. PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator) asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD[31:0] during a write, or that it is ready to accept data on PCI_AD[31:0] during a read.
PCI_INTA_n
O
PCI_IRDY_n
I/O
A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD[31:0]. During a read, a low assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. PCI Lock. A low assertion on PCI_LOCK_n indicates an atomic operation to a bridge that might take multiple transactions to complete. When PCI_LOCK_n is asserted, non-exclusive transactions can proceed to a bridge that is not currently locked. Control of PCI_LOCK_n is obtained under its own protocol in conjunction with PCI_GNT_n. It is possible for different agents to use PCI while a single master retains ownership of PCI_LOCK_n. Locked transactions can be initiated only by host bridges, PCI-to-PCI bridges, and expansion bus bridges. PCI Parity. Parity is driven high or low to create even parity across PCI_AD[31:0] and PCI_C_BE_n[3:0]. The master drives PCI_PAR for address and write data phases; the target drives PCI_PAR for read data phases. PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI transactions except a Special Cycle. The QuickMIPS chip drives PCI_PERR_n low two clocks following the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n is one clock for each data phase that a data parity error is detected. (If sequential data phases each have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.) PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals. PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus. PCI_REQ_n is 3-stated while PCI_RST_n is asserted. PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset). The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK. PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data parity error on the Special Cycle command, or any other system error where the result is catastrophic. PCI_SERR_n is open drain and is actively driven for a single PCI clock. The assertion of PCI_SERR_n is synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can take two to three clock periods to fully restore PCI_SERR_n. PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop the current transaction.
PCI_LOCK_n
I
PCI_PAR
I/O
PCI_PERR_n
I/O
PCI_REQ_n
O
PCI_RST_n
I
PCI_SERR_n
O
PCI_STOP_n
I/O
(Sheet 2 of 6)
28
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 27: Pin Descriptions (Continued) Pin I/O Function
PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave (target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD[31:0] during a read, or that it is ready to accept data on PCI_AD[31:0] during a write. PCI_TRDY_n I/O A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD[31:0]. During a write, a low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both PCI_IRDY_n and PCI_TRDY_n are asserted together. PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz.
PCI_CLK
I
Ethernet MAC Signals
Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon detection of a collision on the medium. COL remains asserted while the collision condition persists. M1_COL/M2_COL I The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK. The QuickMIPS MAC core ignores the COL signal when operating in the full-duplex mode. Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of a collision condition. The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK. Ethernet Management Data Clock. MDC is sourced by the MAC110 core to the Ethernet PHY Controller as the timing reference for transfer of information on the MDIO signals. MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and RXCLK. Ethernet Management Data In/Out. When used as an input, MDIO is the data input signal from the Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock during the read cycles. M1_MDIO/M2_MDIO I/O When used as an output, MDIO is the data output signal from the MAC110 core that drives the control information during the Read/Write cycles to the External PHY Controller. The MAC110 core drives the MDIO signal synchronously with respect to the MDC. Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference for the transfer of the RXDV and RXD[3:0] signals from the Ethernet PHY Controller to the MAC110 core. The Ethernet PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the received signal on the Ethernet cable. Ethernet Receive Data. RXD[3:0] transition synchronously with respect to RXCLK. The Ethernet PHY Controller chip drives RXD[3:0]. For each RXCLK period in which RXDV is asserted, RXD[3:0] transfer four bits of recovered data from the PHY to the MAC110 core. RXD0 is the least-significant bit. While RXDV is deasserted low, RXD[3:0] has no effect on the MAC110 core. Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the MAC110 core that it is presenting the recovered and decoded data bits on RXD[3:0] and that the data on RXD[3:0] is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXDV remains asserted continuously from the first recovered nibble of the frame through the final recovered nibble, and is deasserted low prior to the first RXCLK that follows the final nibble. Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK periods to indicate to the MAC110 core that an error (a coding error or any error that the PHY is capable of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame presently being transferred from the PHY to the MAC110 core. RXER transitions synchronously with respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC110 core.
M1_CRS/M2_CRS
I
M1_MDC/M2_MDC
O
M1_RXCLK/M2_RXCLK
I
M1_RXD[3:0]/M2_RXD[3:0]
I
M1_RXDV/M2_RXDV
I
M1_RXER/M2_RXER
I
(Sheet 3 of 6)
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
29
Table 27: Pin Descriptions (Continued) Pin I/O Function
Ethernet Transmit Clock. TXCLK is a continuous clock that provides a timing reference for the transfer of the TXEN and TXD signals from the MAC110 core to the Ethernet PHY Controller. The Ethernet PHY Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps. Ethernet Transmit Data. The QuickMIPS MAC110 core drives TXD[3:0]. TXD[3:0] transition synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD[3:0] have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit. While TXEN is deasserted, ignore the data presented on TXD[3:0]. Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC110 core is presenting nibbles on the MII for transmission. The QuickMIPS MAC110 core asserts TXEN with the first nibble of the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII. TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is transitions synchronously with respect to TXCLK.
M1_TXCLK/M2_TXCLK
I
M1_TXD[3:0]/M2_TXD[3:0]
O
M1_TXEN/M2_TXEN
O
Memory Controller Interface Signals
BLS_n[3:0] CS_n[7:0] ADDR[23:0] DATA[31:0] OEN_n SD_CAS_n SD_CKE[3:0] SD_CLKIN SD_CLKOUT SD_CS_n[3:0] SD_DQM[3:0] SD_RAS_n SD_WE_n WEN_n O O O I/O O O O I O O O O O O Byte Enables. These signals determine the validity of the bytes on the DATA bus. Chip Selects. These signals are the active-low chip selects for the SRAM. Memory Address. This 24-bit address contains the memory address. Memory Data. This 32-bit bus contains the memory data. SRAM Output Enable. OEN_n is the active-low output enable to the external SRAM. SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external SDRAM. SDRAM Output Clock Enables. SD_CKE[3:0] determine whether the next clock is valid or not. SDRAM Input Clock. SD_CLKIN is the external SDRAM clock. SDRAM Output Clock. SD_CLKOUT is the clock from the QuickMIPS chip to the external SDRAMs. SDRAM Output Chip Select. SD_CS_n[3:0] are the active-low chip selects for the external SDRAMs. SDRAM Data Mask. SD_DQM[3:0] are the data masks for DATA[31:0] SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external SDRAM. SDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs. SRAM Transfer Direction. WEN_n indicates whether transactions between the QuickMIPS chip and the external SRAM are reads (WEN_n is high) or writes (WEN_n is low).
UART Interface Signals
U1_CTS_n U1_DCD_n U1_DSR_n U1_DTR_n U1_RI_n U1_RTS_n U1_RXD_SIRIN I I I O I O I UART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data. UART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected. UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the link to the QuickMIPS UART. UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to establish the external communication link. UART1 Ring Indicator. This input is an active-low ring indicator. UART1 Request To Send. The QuickMIPS chip asserts this signal low to inform the external device that the UART is ready to send data. UART1 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the UART or the IrDA block.
(Sheet 4 of 6)
30
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 27: Pin Descriptions (Continued) Pin
U1_TXD_SIROUT_n U2_RXD_SIRIN U2_TXD_SIROUT_n
I/O
O I O
Function
UART1 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from either the UART or the IrDA block. UART2 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the UART or the IrDA block. UART2 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from either the UART or the IrDA block.
Test Interface Signals
EJTAG_TCK I EJTAG Test Clock. This clock controls the updates to the TAP controller and the shifts through the Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are used. EJTAG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register. This input is sampled on the rising edge of EJTAG_TCK. EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or data register. This signal changes on the falling edge of EJTAG_TCK. EJTAG Test Mode Select. This input is the control signal for the TAP controller. It is sampled on the rising edge of EJTAG_TCK. EJTAG Test Reset. This signal is asserted high asynchronously to reset the TAP controller, Instruction register, and EJTAGBOOT indication. Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be used to bring the chip out of low power mode. Debug Exception Request. Assertion high of this input indicates a debug exception request is pending. The request is cleared when debug mode is entered. Requests that occur while the chip is in debug mode are ignored.
EJTAG_TDI EJTAG_TDO EJTAG_TMS EJTAG_TRST EJTAG_DEBUGM
I O I I O
EJTAG_DINT
I
Fabric Interface Signals
I/O53:0 I/O71:0 I/O71:0 I/O53:0 CLK<8:0> INREF IOCTRL TCLK TDI TDO TMS TRSTB I/O I/O I/O I/O I/O I/O I/O I I O O I Programmable Input/Output/3-State/Bidirectional pin in Bank A. Programmable Input/Output/3-State/Bidirectional pin in Bank B. Programmable Input/Output/3-State/Bidirectional pin in Bank C. Programmable Input/Output/3-State/Bidirectional pin in Bank D. Programmable Global Clock Pin. Tie to VCC or GND if unused. Differential I/O Reference Voltage. Connect to GND when using TTL, PCI or LVCMOS. Low Skew I/O Control Pins. Tie to GND if unused. JTAG Clock. Tie to GND if unused. JTAG Data In. Tie to VCC if unused. JTAG Data Out. Leave unconnected if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset. Tie to GND if unused.
Timer Interface Signals
TM_OVERFLOW TM_ENABLE O I Timer Overflow. This output is asserted high when an internal timer overflows. Timer Enable. This signal is asserted high to enable the internal timer.
Miscellaneous Signals
BOOT<1:0> I Boot chip size. 00 = 8 bit, 01 = 16 bit, 10 = 32 bit, and 11 = reserved.
(Sheet 5 of 6)
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
31
Table 27: Pin Descriptions (Continued) Pin
CPU_BIGENDIAN CPU_EXTINT_n<6:0> PL_BYPASS PL_CLKOUT PL_CLOCKIN
I/O
I I I O I
Function
Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates little-endian byte ordering. CPU Interrupts. Asserting Low any of these inputs causes an interrupt to the QuickMIPS chip. PLL Bypass. When High, the 2X multiplication of the input clock is not performed and the output clocks are half their normal frequencies. Output Clock from PLL. Input Clock to PLL. PLL Enable. A High assertion of this signal powers down the PLL when it is not being used to reduce overall device power and puts the QuickMIPS chip into a quiescent current testing mode. When PL_ENABLE is Low, the PLL is not functional, but the clock outputs can be used if the PL_BYPASS input is High. PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid output clocks. PLL Reset. PLL Warm Reset. QuickLogic Reserved pin. Tie to GND on the PCB.
PL_ENABLE
I
PL_LOCK PL_RESET_n PL_WARMRESET_n STM
O I I I
Power and Ground Signals
GND GNDPLL VCCIO VCCIO VCCPLL VCC I I I I I I Ground pin. Tie to GND on the PCB. Ground for the PLL. Supply pin for I/O. Set to 2.5V for 2.5V I/O, 3.3V for 3.3V compliant I/O, or refer to the I/O Standards table. VCCIO port for each of the four I/O banks. Supply for the PLL. Supply pin. Tie to 2.5V supply.
(Sheet 6 of 6)
QL 901M- 6 PS680 C QuickLogic device Operating Range C = Commercial I = Industrial
QuickMIPS device part number Package Code PS680 = 680-pin BGA (1.0mm)
Speed Grade 6 = Faster
Figure 26: Ordering Information
32
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
7.0 680 PBGA Pinout Diagram
Pin A1 Corner
Top
QuickMIPS
QL901M
Figure 27: 680-Pin PBGA Package Marking (Top View)
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
Pin A1 Corner
Figure 28: 680-Pin PBGA Package Marking (Bottom View)
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
33
8.0 680 PBGA Pinout Table
Table 28: 680 PBGA Pinout Table
680 PBGA
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25
Function
GND GND I/O I/O I/O I/O INREF I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND CLK<5> I/O I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O GND GND GND GND I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O I/O I/O CLK<8> CLK<7> I/O I/O I/O I/O I/O I/O I/O
680 PBGA
B26 B27 B28 B29 B30 B31 B32 B33 B34 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
Function
INREF I/O I/O I/O I/O I/O I/O GND GND GND I/O GND I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O TMS CLK<6> I/O I/O I/O I/O I/O I/O IOCTRL I/O I/O I/O I/O I/O I/O GND I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
680 PBGA
D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 F1 F2 F3 F4 F5 F30 F31
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O VCC VCC VCCIO I/O I/O I/O I/O VCC VCCIO VCC I/O I/O I/O I/O VCC VCCIO VCC I/O I/O I/O I/O VCCIO VCC VCC I/O I/O VCC VCC GND I/O I/O VCC I/O VCC VCC I/O
680 PBGA
F32 F33 F34 G1 G2 G3 G4 G5 G30 G31 G32 G33 G34 H1 H2 H3 H4 H5 H30 H31 H32 H33 H34 J1 J2 J3 J4 J5 J30 J31 J32 J33 J34 K1 K2 K3 K4 K5 K30 K31 K32 K33 K34 L1 L2 L3 L4 L5 L30 L31 L32 L33 L34 M1 M2 M3 M4 M5 M30
Function
GND I/O I/O I/O I/O I/O I/O VCC VCC GND I/O I/O I/O I/O I/O I/O I/O VCCIO VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOCTRL INREF IOCTRL I/O I/O I/O
680 PBGA
M31 M32 M33 M34 N1 N2 N3 N4 N5 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N30 N31 N32 N33 N34 P1 P2 P3 P4 P5 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22
Function
I/O IOCTRL I/O INREF I/O I/O I/O I/O VCC GND VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO GND VCC IOCTRL I/O I/O I/O I/O I/O I/O I/O VCCIO VCCIO GND GND GND GND GND GND GND GND VCCIO VCCIO I/O I/O I/O I/O I/O I/O I/O I/O VCC VCCIO GND GND GND GND GND GND GND GND VCCIO
680 PBGA
R30 R31 R32 R33 R34 T1 T2 T3 T4 T5 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T30 T31 T32 T33 T34 U1 U2 U3 U4 U5 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 V13 V14 V15 V16 V17 V18 V19 V20 V21
Function
VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCCIO GND GND GND GND GND GND GND GND
(Sheet 1 of 2) * * * * * *
34
www.quicklogic.com
(c) 2001 QuickLogic Corporation
Table 28: 680 PBGA Pinout Table (Continued)
680 PBGA
V22 V30 V31 V32 V33 V34 W1 W2 W3 W4 W5 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W30 W31 W32 W33 W34 Y1 Y2 Y3 Y4 Y5 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y30 Y31 Y32 Y33 Y34 AA1 AA2 AA3 AA4 AA5 AA13 AA14 AA15 AA16
Function
VCCIO I/O I/O I/O I/O GND I/O I/O I/O I/O GNDPLL VCCIO GND GND GND GND GND GND GND GND VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O PL_CLOCKIN VCCIO GND GND GND GND GND GND GND GND VCCIO CLK<4> I/O I/O I/O I/O I/O CLK<0> CLK<1> VCCIO VCCPLL VCCIO GND GND GND
680 PBGA
AA17 AA18 AA19 AA20 AA21 AA22 AA30 AA31 AA32 AA33 AA34 AB1 AB2 AB3 AB4 AB5 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB30 AB31 AB32 AB33 AB34 AC1 AC2 AC3 AC4 AC5 AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD30 AD31 AD32 AD33 AD34 AE1 AE2 AE3 AE4
Function
GND GND GND GND GND VCCIO VCCIO EJTAG_DEBUGM CLK<3> I/O I/O TCK TDI GND STM VCC GND VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO GND VCC CS_n<0> GND TRSTB CLK<2> VCC TDO PL_CLKOUT PL_BYPASS BOOT<0> CS_n<5> CS_n<2> NC EJTAG_DINT VCC PL_LOCK PL_ENABLE PL_WARMRESET_n M2_MDIO M2_TXD<2> BLS_n<2> CS_n<7> CS_n<4> CS_n<1> NC PL_RESET_n BOOT<1> M2_TXD<3> M2_TXD<0>
680 PBGA
AE5 AE30 AE31 AE32 AE33 AE34 AF1 AF2 AF3 AF4 AF5 AF30 AF31 AF32 AF33 AF34 AG1 AG2 AG3 AG4 AG5 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH30 AH31 AH32 AH33 AH34 AJ1 AJ2 AJ3 AJ4 AJ5 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9
Function
M2_RXDV ADDR<2> OEN_n BLS_n<0> CS_n<6> CS_n<3> M2_TXEN M2_TXD<1> M2_RXER M2_RXD<2> M2_RXD<0> ADDR<7> ADDR<4> ADDR<0> BLS_n<1> WEN_n M2_MDC M2_TXCLK M2_RXD<1> M2_CRS VCCIO VCCIO ADDR<12> ADDR<5> ADDR<1> BLS_n<3> M2_RXD<3> M2_RXCLK M1_MDIO M1_MDC VCC VCC ADDR<16> ADDR<9> ADDR<6> ADDR<3> M2_COL M1_TXEN M1_TXD<1> M1_TXCLK M1_COL ADDR<21> ADDR<17> ADDR<13> ADDR<10> ADDR<8> M1_TXD<3> M1_TXD<2> M1_RXER M1_RXD<3> NC GND VCC VCCIO PCI_AD<23>
680 PBGA
AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30
Function
PCI_AD<17> PCI_FRAME_n PCI_PAR VCC VCCIO EJTAG_TRST EJTAG_TDO CPU_EXTINT _n<1> CPU_ BIGENDIAN U1_RI_n U1_DCD_n VCCIO VCC SD_CLKIN DATA<28> DATA<24> DATA<16> VCCIO VCC DATA<2> DATA<1> ADDR<22> ADDR<18> ADDR<14> ADDR<11> M1_TXD<0> M1_RXCLK M1_CRS GND M1_RXD<2> PCI_RST_n M1_RXD<0> PCI_IDSEL PCI_CLK PCI_AD<20> PCI_C_BE _n<2> PCI_STOP_n PCI_AD<14> PCI_AD<8> PCI_AD<7> PCI_AD<3> EJTAG_TMS CPU_EXTINT _n<4> U2_RXD_SIRIN U1_CTS_n SD_WE_n SD_CS_n<1> SD_DQM<3> DATA<31> DATA<25> DATA<19> DATA<11> DATA<6> DATA<7> DATA<3>
680 PBGA
AL31 AL32 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17
Function
GND ADDR<23> ADDR<20> ADDR<15> M1_RXDV NC GND M1_RXD<1> TM_OVERFLOW PCI_GNT_n PCI_AD<30> PCI_AD<26> PCI_AD<21> PCI_C_BE _n<3> PCI_DEVSEL_n PCI_SERR_n PCI_AD<15> PCI_AD<11> PCI_AD<5> PCI_AD<1> EJTAG_TDI CPU_EXTINT _n<5> CPU_EXTINT_n <0> U1_DTR_n SD_CKE<3> SD_CKE<0> SD_CS_n<3> SD_DQM<2> SD_CLKOUT DATA<26> DATA<20> DATA<15> DATA<13> DATA<9> DATA<5> GND DATA<0> ADDR<19> GND GND TM_ENABLE PCI_REQ_n PCI_AD<31> PCI_AD<28> PCI_AD<25> PCI_AD<19> PCI_AD<16> PCI_TRDY_n PCI_PERR_n PCI_C_BE_n<0> PCI_AD<12> PCI_AD<9> PCI_AD<4> PCI_AD<0> EJTAG_TCK
680 PBGA
AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34
Function
CPU_EXTINT_n<6> CPU_EXTINT_n<2> U1_RTS_n U1_TXD _SIROUT_n SD_CKE<2> SD_CAS_n SD_CS_n<2> SD_DQM<1> DATA<30> DATA<23> DATA<21> DATA<17> DATA<12> DATA<8> DATA<4> GND GND GND GND PCI_INTA_n PCI_AD<29> PCI_AD<27> PCI_AD<24> PCI_AD<22> PCI_AD<18> PCI_IRDY_n PCI_LOCK_n PCI_C_BE_n<1> PCI_AD<13> PCI_AD<10> PCI_AD<6> PCI_AD<2> GND GND GND CPU_EXTINT_n<3> U2_TXD _SIROUT_n U1_DSR_n U1_RXD_SIRIN SD_CKE<1> SD_RAS_n SD_CS_n<0> SD_DQM<0> DATA<29> DATA<27> DATA<22> DATA<18> DATA<14> DATA<10> GND GND
(Sheet 2 of 2) * * * * * *
QL901M QuickMIPSTM Data Sheet Rev B
35
9.0 Mechanical Drawings
Figure 29 provides the mechanical dimensions of the 680-pin Plastic Ball Grid Array (PBGA) package.
Figure 29: 680-pin PBGA Package Mechanical Drawing
36
* * * * * *
www.quicklogic.com
(c) 2001 QuickLogic Corporation
10.0 Revision History
Table 29: Revision History Revision
A B
Date
Dec 2001 Dec 19 2001
Comments
First release. PLL information re-evaluated
Copyright (c) 2001 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, pASIC, and ViaLink are registered trademarks, and QuickMIPS, SpDE and QuickWorks are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc. SaiLAheadTM is a registered trademark of Saivision.
QL901M QuickMIPSTM Data Sheet Rev B
* * * * * *
37

▲Up To Search▲

Price & Availability of QL901M-6PS680

	To Download QL901M-6PS680 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .