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Preliminary GS815218/36/72B-225/200/180/166/150/133 119- and 209-Pin BGA Commercial Temp Industrial Temp Features
* FT pin for user-configurable flow through or pipeline operation * Single/Dual Cycle Deselect selectable * IEEE 1149.1 JTAG-compatible Boundary Scan * On-chip read parity checking; even or odd selectable * ZQ mode pin for user-selectable high/low output drive * On-chip parity encoding and error detection * 3.3 V +10%/-5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to SCD x18/x36 Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 119- and 209-bump BGA package
1M x 18, 512K x 36, 256K x 72 16Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
200 MHz-133MHz 3.3 V VDD 2.5 V or 3.3 V I/O
either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS815218/36/72B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.
Flow tKQ Through tCycle 2-1-1-1 Curr (x18) Curr (x36) Curr (x72) Pipeline tKQ 3-1-1-1 tCycle Curr (x18) Curr (x36) Curr (x72)
-225 -200 -180 -166 7.0 7.5 8.0 8.5 8.5 10.0 10.0 10.0 205 185 185 185 240 210 210 210 325 285 285 285 2.5 4.4 350 410 570 3.0 5.0 315 370 515 3.2 5.5 290 340 470 3.5 6.0 270 315 435
-150 10.0 10.0 185 210 285 3.8 6.7 250 290 400
-133 11.0 15.0 140 160 205 4.0 7.5 230 260 360
Unit ns ns mA mA mA ns ns mA mA mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Functional Description
Applications
The GS815218/36/72B is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
ByteSafeTM Parity Functions
The GS815218/36/72B features ByteSafe data security functions. See the detailed discussion following.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS815218/36/72B operates on a 3.3 V power supply. All input are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V- and 2.5 V-compatible.
Rev: 1.01 11/2000
1/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815272 Pad Out 209 Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U V W Rev 9.7 DQG5 DQG6 DQG7 DQG8 DQG9 DQC4 DQC3 DQC2 DQC1 NC DQH1 DQH2 DQH3 DQH4 DQD9 DQD8 DQD7 DQD6 DQD5 2 DQG1 DQG2 DQG3 DQG4 DQC9 DQC8 DQC7 DQC6 DQC5 NC DQH5 DQH6 DQH7 DQH8 DQH9 DQD4 DQD3 DQD2 DQD1 3 A15 BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A9 TMS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A14 A8 TDI 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A12 A1 A0 7 ADV A16 NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD PE A11 A6 A2 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 BF BA VSS VDDQ VSS VDDQ VSS VDDQ DP VDDQ VSS VDDQ VSS VDDQ VSS NC A4 TCK 10 DQB1 DQB2 DQB3 DQB4 DQF9 DQF8 DQF7 DQF6 DQF5 NC DQA5 DQA6 DQA7 DQA8 DQA9 DQE4 DQE3 DQE2 DQE1 11 DQB5 DQB6 DQB7 DQB8 DQB9 DQF4 DQF3 DQF2 DQF1 QE DQA1 DQA2 DQA3 DQA4 DQE9 DQE8 DQE7 DQE6 DQE5
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.01 11/2000
2/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815272 BGA Pin Description
Pin Location
W6, V6 W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6, U5, U4, A3, B7, A9 L11, M11, N11, P11, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, VV2, U2, T2, W1, V1, U1, T1, R1 W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2 C9, B8, B3, C4, C8, B9, B4, C3 B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K10, T4, T5, T8, U3, U9 K3 D7 C6, A8 A4 D6 A7 A5, A6 P6 L6 T6 N6 G6 H6, J6, K6, M6 T7
Symbol
A0, A1 An DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 DQE1-DQE9 DQF1-DQF9 DQG1-DQG9 DQH1-DQH9 BA, BB, BC,BD, BE, BF, BG,BH NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL PE
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins (x36 Version)
I I I I I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
I
Rev: 1.01 11/2000
3/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815272 BGA Pin Description
Pin Location
K9 K11 F6 W2 W4 W8 W9 E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 C3, C9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 E3, E4, E8, E0, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
Symbol
DP QE ZQ TMS TDI TDO TCK VDD VSS VDDQ
Type
I O I I I O I I I I
Description
Data Parity Mode Input; 1 = Even, 0 = Odd Parity Error Out; Open Drain Output FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 1.01 11/2000
4/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815236 Pad Out
119 Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ
2
A6 A18 A5 DQC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD7 DQD8 DQD9 A2 NC TMS
3
A7 A4 A3 VSS VSS VSS BC VSS DP VSS BD VSS VSS VSS LBO A10 TDI
4
ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A11 TCK
5
A8 A15 A14 VSS VSS VSS BB VSS QE VSS BA VSS VSS VSS FT A12 TDO
6
A9 A17 A16 DQB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQA9 A13 NC NC
7
VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 PE ZZ VDDQ
Rev: 1.01 11/2000
5/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815218 Pad Out
119 Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ
2
A6 A18 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQB9 A2 A10 TMS
3
A7 A4 A3 VSS VSS VSS BB VSS DP VSS NC VSS VSS VSS LBO A11 TDI
4
ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD NC TCK
5
A8 A15 A14 VSS VSS VSS NC VSS QE VSS BA VSS VSS VSS FT A12 TDO
6
A9 A17 A16 DQA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A19 NC
7
VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 PE ZZ VDDQ
BPR1999.05.18
Rev: 1.01 11/2000
6/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
GS815218/36 (PE = 0) Block Diagram
Register
A0-An
D
Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q 36 D 36
Register
D BB
Q 4 4
Register
D BC
Q
Register
D
Q
Register
Register 4
D BD
Q
Register
36 36 36
D
Q
Register
E1
D
Q
32 Parity Encode 4 Parity Compare 36 36
Register
D
Q
FT G Power Down Control
SCD
ZZ
DQx0-DQx9
QE
D DP
Note: Only x36 version shown for simplicity.
Rev: 1.01 11/2000
7/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q
Q D
Register
Preliminary GS815218/36/72B-225/200/180/166/150/133
GS815218/36 (PE = 1) x32 Mode Block Diagram
Register
A0-An
D
Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q 36 D 36
4 Parity Encode 32
Register
D BB
Q 4
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
32 36 Register 36
D
Q
Register
D
Q
4 32 Parity Encode 4 Parity Compare
E1
D
Q
32 Register
Register
D
Q
D
Q
FT G Power Down Control
32
SCD
ZZ
DQx0-DQx8
QE
DP
Note: Only x36 version shown for simplicity.
Rev: 1.01 11/2000
8/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control Single / Dual Cycle Deselect Control ByteSafe Data Parity Control Parity Enable FLXDrive Output Impedance Control
Pin Name
LBO FT ZZ SCD DP PE ZQ
State
L H L H or NC L or NC H L H or NC L H or NC L or NC H L H or NC
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect Check for Odd Parity Check for Even Parity Activate 9th I/O's (x18/36 Mode) Deactivate 9th I/O's (x16/32 Mode) High Drive (Low Impedance) Low Drive (High Impedance)
Note: There are pull-up devices on the ZQ, SCD DP, and FT pins and pull-down devices on the PE and ZZ pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 11/2000
9/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Byte Write Truth Table Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version.
Rev: 1.01 11/2000
10/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X X X R R W CR CR CW CW
E1
H L L L L L X H X H X H X H
ADSP
X L H L H H H X H X H X H X
ADSC
L X L X L L H H H H H H H H
ADV
X X X X X X L L L L H H H H
W3
X X X X F T F F T T F F T T
DQ4
High-Z High-Z High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 11/2000
11/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low.
Rev: 1.01 11/2000
12/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 1.01 11/2000
13/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
oC oC
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Parameter
Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
VDD VDDQ VIH VIL TA TA
Min.
3.135 2.375 1.7 -0.3 0 -40
Typ.
3.3 2.5 -- -- 25 25
Max.
3.6 VDD VDD +0.3 0.8 70 85
Unit
V V V V C C
Notes
1 2 2 3 3
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V VDDQ 2.375 V (i.e., 2.5 V I/O) and 3.6 V VDDQ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.01 11/2000
14/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Undershoot Measurement and Timing
VIH VDD + 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD
Overshoot Measurement and Timing
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6 (x36) 12 (x18)
Max.
5 7 (x36) 12 (x18)
Unit
pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Layer Board
single four --
Symbol
RJA RJA RJC
Max
40 24 9
Unit
C/W C/W C/W
Notes
1,2 1,2 3
Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.01 11/2000
15/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 VT = 1.25 V
* Distributed Test Jig Capacitance
Output Load 2 2.5 V 30pF* DQ 5pF* 225 225
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IINZZ IINM IOL VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 2.375 V IOH = -4 mA, VDDQ = 3.135 V IOL = 4 mA
Min
-1 uA -1 uA -1 uA -300 uA -1 uA -1 uA 1.7 V 2.4 V --
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA -- -- 0.4 V
Rev: 1.01 11/2000
16/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-225 Mode Symbol 0 to 70C -40 to 85C Unit 431 159 254 88 345 84 209 49 320 47 196 29 20 20 85 65 50 75 80 55 10 20 10 70 50 10 20 10 20 20 75 55 166 17 176 27 166 17 176 27 166 17 10 10 64 50 281 33 291 43 258 30 268 40 242 27 252 37 176 27 20 20 70 55 177 33 187 43 177 33 187 43 177 33 187 43 177 33 223 25 166 17 10 10 60 50 303 66 313 76 278 59 288 69 260 55 270 65 240 50 250 60 187 43 233 35 176 27 20 20 65 55 215 66 225 76 215 66 225 76 215 66 225 76 215 66 225 76 160 44 218 44 134 22 204 22 127 11 10 10 50 45 380 132 390 142 347 119 357 129 324 110 334 120 298 99 308 109 269 88
279 98 170 54 228 54 144 32 214 32 137 21 20 20 55 50 mA mA mA mA mA mA mA mA mA mA
-200 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
-180
-166
-150
-133
Rev: 1.01 11/2000 Pipeline (x72) Flow Through Pipeline (x36) Flow Through IDDQ IDD IDDQ IDD IDDQ ISB 10 10 80 60 ISB IDD IDD 186 19 310 37 Pipeline (x18) Flow Through Pipeline -- Flow Through Pipeline -- Flow Through IDD 199 39 IDD IDDQ 335 74 IDD IDDQ 244 78 IDD IDDQ 421 149
Parameter
Test Conditions
Operating Current
Device Selected; All other inputs VIH or VIL Output open
17/38
Standby Current
ZZ VDD - 0.2 V
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Deselect Current
Device Deselected; All other inputs VIH or VIL
Preliminary GS815218/36/72B-225/200/180/166/150/133
(c) 2000, Giga Semiconductor, Inc.
Preliminary GS815218/36/72B-225/200/180/166/150/133 AC Electrical Characteristics
Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ
1
-225 Min 4.4 -- 1.5 1.5 8.5 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 2.5 -- -- -- 7.0 -- -- -- -- 2.5 2.5 -- 2.5 -- -- -- -- --
-200 Min 5.0 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.0 -- -- -- 7.5 -- -- -- -- 3.0 3.2 -- 3.0 -- -- -- -- --
-180 Min 5.5 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.2 -- -- -- 8.0 -- -- -- -- 3.2 3.2 -- 3.2 -- -- -- -- --
-166 Min 6.0 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.5 -- -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 -- -- -- -- --
-150 Min 6.7 -- 1.5 1.5 10.0 -- 3.0 3.0 1.5 1.7 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 3.8 -- -- -- 10.0 -- -- -- -- 3.8 3.8 -- 3.8 -- -- -- -- --
-133 Min 7.5 -- 1.5 1.5 15.0 -- 3.0 3.0 1.7 2 1.5 -- 0 -- 1.5 0.5 5 1 100 Max -- 4.0 -- -- -- 11.0 -- -- -- -- 4.0 4.0 -- 4.0 -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.01 11/2000
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Write Cycle Timing
Single Write
Burst Write
Write
Deselected
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV
tS tH ADV must be inactive for ADSP Write
WR2 WR3
A0-An
WR1
tS tH
GW
tS tH
BW
tS tH
BA-BD
tS tH
WR1 WR1
WR2
WR3 WR3
E1 masks ADSP
E1
E1 only sampled with ADSP or ADSC
G
tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B D2C D2D D3A
DQA-DQD
Hi-Z
D1A
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Flow Through Read Cycle Timing
Single Read tKL
Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH Suspend Burst Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW BA-BD
tS tH
E1 masks ADSP
E1
tOE tOHZ
G
tOLZ tKQX Q1A tLZ tHZ tKQ Q2A Q2B Q2c Q2D Q3A tKQX
DQA-DQD
Hi-Z
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Flow Through Read-Write Cycle Timing
Single Read Single Write
Burst Read
CK
tS tH tKH tKL tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS
tH
GW
tS tH
BW
tS tH
BA-BD
tS tH
WR1
E1 masks ADSP
E1
tOE tOHZ
G
tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A Hi-Z
DQA-DQD
D1A
Burst wrap around to it's initial state
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Pipelined SCD Read Cycle Timing
Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E inactive
CK
tS tH
ADSP ADSC
tS tH
Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW
BWA-BWD
tS tH
E1 masks ADSP
E1
tOE
G DQA-DQD
Hi-Z tOLZ Q1A tLZ
tOHZ tKQX Q2A Q2B Q2c Q2D
tKQX Q3A tHZ
tKQ
Rev: 1.01 11/2000
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Pipelined SCD Read-Write Cycle Timing
Single Read tKL Single Write Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS tH
GW
tS tH
BW
tS tH
BWA- BWD
tS tH
WR1
E1 masks ADSP
E1
tOE
tOHZ
G DQA-DQD
Hi-Z tKQ Q1A tS tH D1A Q2A Q2B Q2c Q2D
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Pipelined DCD Read Cycle Timing
Single Read tKL Burst Read
CK
tS tH tKH tKC ADSP is blocked by E1 inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH Suspend Burst
ADV
tS tH
A0-An GW
RD1 tS
RD2
RD3 tH
tS
tH
BW BA-BD
tS tH
E1 masks ADSP
E1
tOE
G
tOHZ Hi-Z tOLZ Q1A tLZ tHZ tKQ tKQX Q2A Q2B Q2c Q2D tKQX Q3A
DQA-DQD
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Pipelined DCD Read-Write Cycle Timing
Single Write Single Read tKL Burst Read
CK
tS tH tKH tKC ADSP is blocked by E1 inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS tH
GW
tS tH tS tH
BW
BA-BD
tS tH
WR1
E1 masks ADSP
E1
tOE tOHZ
G DQA-DQD
Hi-Z tKQ Q1A tS tH
D1A
Q2A
Q2B
Q2c
Q2D
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Sleep Mode Timing Diagram
CK
tS tH tKC tKH tKL
ADSP ADSC
tZZS
~ ~~~~ ~ ~~~~ ~
tZZH
tZZR
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Unlike JTAG implementations that have been common among SRAM vendors for the last several years, this implementation does offer a form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test program compiler errors caused by previous non-compliant implementations. The JTAG Port interfaces with conventional 2.5 V CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
JTAG TAP Block Diagram
0
Bypass Register
210
Instruction Register TDI ID Code Register
31 30 29
TDO
*
***
210
Boundary Scan Register
n
******
***
210
TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Presence Register 0 1 1 1 1
Die Revision Code
Not Used
I/O Configuration
GSI Technology JEDEC Vendor ID Code 1 10 9 8 7 6 5 4 3 2 1 1 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001
Bit #
x36 x32 x18 x16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1 compliant because some of the mandatory instructions are uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This Rev: 1.01 11/2000 28/38 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
device will not perform INTEST or the preload portion of the SAMPLE / PRELOAD command. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions
BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O Rev: 1.01 11/2000 29/38 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the UpdateDR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This functionality is not Standard 1149.1 compliant. EXTEST (EXTEST-A) EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. The EXTEST implementation in this device does not, without further user intervention, actually move the contents of the scan chain onto the RAM's output pins. Therefore, this device is not strictly 1149.1-compliant. Nevertheless, this RAM's TAP does respond to an all 0s instruction, EXTEST (000), by overriding the RAM's control inputs and activating the Data I/O output drivers. The RAM's main clock (CK) may then be used to transfer Boundary Scan Register contents associated with each I/O from the scan register to the RAM's output drivers and onto the I/O pins. A single CK transition is sufficient to transfer the data, but more transitions will do no harm. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST-A IDCODE SAMPLE-Z
Code
000 001 010
Description
Places the Boundary Scan Register between TDI and TDO. This RAM implements an Clock Assisted EXTEST function. *Not 1149.1 Compliant * Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant * GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1
RFU
011
1
SAMPLE/ PRELOAD GSI RFU BYPASS
100
1
101 110 111
1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 11/2000 30/38 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage
Symbol
VIHT VILT IINTH IINTL IOLT VOHT VOLT
Min.
0.7 * VDD -0.3 -300 -1 -1 1.7 --
Max.
VDD +0.3 0.3 * VDD 1 1 1 -- 0.4
Unit Notes
V V uA uA uA V V 1, 2 1, 2 3 4 5 6, 7 6, 8
Note: 1. This device features input buffers compatible with 2.5 V I/O drivers. 2. Input Under/overshoot voltage must be -2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tTKC. 3. VDD VIN VIL 4. 0 V VIN VIL 5. Output Disable, VOUT = 0 to VDD 6. The TDO output driver is served by the VDD supply. 7. IOH = -4 mA 8. IOL = + 4 mA
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V DQ
JTAG Port AC Test Load
50 VT = 1.25 V
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted.
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
JTAG Port Timing Diagram
tTKH TCK
tTKL
tTKC
tTS TMS TDI TDO tTKQ
tTH
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time
Symbol
tTKC tTKQ tTKH tTKL tTS tTH
Min
20 -- 10 10 5 5
Max
-- 10 -- -- -- --
Unit
ns ns ns ns ns ns
Rev: 1.01 11/2000
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(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 GS815218/36B BGA Boundary Scan Register
Order Order x36
PE PH = 0 A10 A11 A12 A13 A14 A15 A16
x36 = DQA9 x32 = NA = 0
x18
x36 x18
x36
x36 = DQB9 x32 = NA = 0
x18
A19
Order
Bump
7R n/a 3T 3T 4T 2T 5T 6R 5C 5B 6C
Bump
x36 x18 6D 6T
x36
DQC1 FT DP SCD DQD1 DQD2 DQD3 DQD4 DQD5 DQD6 DQD7 DQD8
x36 = DQD9 x32 = NA = 0
x18
DQB4
Bump
x36 x18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
1H 5R 3J 4L
A9 A8 ADV ADSP ADSC G BW GW CK PH = 1 PH = 0 A17 BA BB BC BD A18 E1 A7 A6
x36 =DQC9 x32 = NA = 0
6A 5A 4G 4A 4B 4F 4M 4H 4K n/a n/a 6B BA BB NC = 1 NC = 1 5L 5G 3G 3G 5G 3L 2B 4E 3A 2A NC = 1 NC = 1 NC = 1 NC = 1 NC = 1 DQB1 DQB2 DQB3 2D 1E 2F 1G 2H 1D 2E 2G
DQB5 DQB6 DQB7 DQB8
2K 1L 2M 1N
2P
NC = 1 NC = 1 NC = 1 NC = 1 NC = 1 DQA1 DQA2 DQA3 DQA4
6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 5J
x18 = DQB9 1K x16 = NA = 0
NC = 1 NC = 1 NC = 1 NC = 1
2L 2N 1P 2P 1K 3R 2C 3B 3C 2R 4N 4P 4D
DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 ZZ QE
LBO A5 A4 A3 A2 A1 A0 ZQ
DQA5 DQA6 DQA7 DQA8 x18 =DQA9
x16 = NA = 0
6H 7G 6F 7E
7H 6D
BPR 1999.12.10
DQC8 DQC7 DQC6 DQC5 DQC4 DQC3 DQC2
NC = 1 NC = 1 NC = 1
6G 6E 7D
Note: 1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset. 2. Registers are listed in exit order (i.e. Location 1 is the first out of the TDO pin. 3. NC = No Connect, NA = Not Active Rev: 1.01 11/2000 33/38 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 209 BGA Package Drawing
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A aaa D D1
Side View
e
Bottom View
E1 b e Symbol A A1 b c D D1 E E1 e aaa Rev 1.0 Rev: 1.01 11/2000 34/38 13.9 0.40 0.50 0.31 21.9 0.50 0.60 0.36 22.0 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15 14.1 Min Typ Max 1.70 0.60 0.70 0.38 22.1 Units mm mm mm mm mm mm mm mm mm mm
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
(c) 2000, Giga Semiconductor, Inc.
E
Preliminary GS815218/36/72B-225/200/180/166/150/133 Package Dimensions--119-Pin PBGA
Pin 1 Corner
A
7654321
G
P
B
S
D
A B C D E F G H J K L M N P R T U
N
Top View
R Bottom View
Package Dimensions--119-Pin PBGA
Symbol A B C D E F G Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height Min. 13.8 21.8 -- 0.60 0.50 -- -- 0.80 -- -- -- -- -- Nom. 14.0 22.0 -- 0.75 0.60 1.46 1.27 0.90 12.00 19.50 7.62 20.32 0.15 Max 14.2 22.2 2.40 0.90 0.70 1.70 -- 1.00 -- -- -- -- --
T
K
K N
E
P R S T Unit: mm
F
Side View
Rev: 1.01 11/2000
C
35/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133 Ordering Information for GSI Synchronous Burst RAMs
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 256k x 72 256k x 72 256k x 72 256k x 72 256k x 72 256k x 72 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS815218B-225 GS815218B-200 GS815218B-180 GS815218B-166 GS815218B-150 GS815218B-133 GS815236B-225 GS815236B-200 GS815236B-180 GS815236B-166 GS815236B-150 GS815236B-133 GS815272B-225 GS815272B-200 GS815272B-180 GS815272B-166 GS815272B-150 GS815272B-133 GS815218B-225I GS815218B-200I GS815218B-180I GS815218B-166I GS815218B-150I GS815218B-133I GS815236B-225I GS815236B-200I GS815236B-180I GS815236B-166I GS815236B-150I GS815236B-133I
Type
ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through
Package
BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA
Speed2 (MHz/ns)
225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11 225/7 200/7.5 180/8 166/8.5 150/10 133/11
TA3
C C C C C C C C C C C C C C C C C C I I I I I I I I I I I I
Status
Not Available Not Available
Not Available Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS815218B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 11/2000 36/38 (c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
Org
256k x 72 256k x 72 256k x 72 256k x 72 256k x 72 256k x 72
Part Number1
GS815272B-225I GS815272B-200I GS815272B-180I GS815272B-166I GS815272B-150I GS815272B-133I
Type
ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through ByteSafe S/DCD Pipeline/Flow Through
Package
BGA BGA BGA BGA BGA BGA
Speed2 (MHz/ns)
225/7 200/7.5 180/8 166/8.5 150/10 133/11
TA3
I I I I I I
Status
Not Available Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS815218B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.01 11/2000
37/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS815218/36/72B-225/200/180/166/150/133
0.18u 16M Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old; New 815218_r1 815218_r1; 815218_r1_01 Content Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet * Update Features list on page 1 * Completely change table on page 1 * Update Mode Pin Functions table on page 9
Rev: 1.01 11/2000
38/38
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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