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| SPLC564A High-Voltage Durable 240-Channel Common Driver for Dot-Matrix STN LCD MAY. 16 2005 Version: 1.1 Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which may appear in this document. Contact Sunplus Technology. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. SPLC564A Table of Contents PAGE 1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3 2. FEATURES .................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3.1. INTERNAL BLOCK DIAGRAM .................................................................................................................................................................... 4 3.1.1. LCD drive circuit........................................................................................................................................................................ 4 3.1.2. Level shifter............................................................................................................................................................................... 4 3.1.3. Shift register.............................................................................................................................................................................. 4 3.1.4. Alternating signal generating circuit .......................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5 4.1. PIN FUNCTIONS (CONT) ......................................................................................................................................................................... 6 5. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 5.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 5.1.1. Power ON ................................................................................................................................................................................. 9 5.1.2. Shut down ................................................................................................................................................................................. 9 5.2. DC CHARACTERISTICS 1 ........................................................................................................................................................................ 9 5.3. AC CHARACTERISTICS 1 .......................................................................................................................................................................11 5.4. AC CHARACTERISTICS 2 .......................................................................................................................................................................11 5.5. AC CHARACTERISTICS 3 .......................................................................................................................................................................11 5.6. TERMINAL CONFIGURATION .................................................................................................................................................................. 13 5.6.1. Terminal configuration (1) ....................................................................................................................................................... 13 5.6.2. Terminal Configuration (2)....................................................................................................................................................... 14 6. APPLICATION CIRCUIT ........................................................................................................................................................................... 15 6.1. APPLICATION EXAMPLE ........................................................................................................................................................................ 15 6.2. POWER SUPPLY CIRCUIT EXAMPLE....................................................................................................................................................... 16 7. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17 7.1. PACKAGE/PAD LOCATIONS................................................................................................................................................................... 17 7.2. ORDERING INFORMATION ..................................................................................................................................................................... 17 8. DISCLAIMER............................................................................................................................................................................................. 18 9. REVISION HISTORY ................................................................................................................................................................................. 19 id se f nU o C ER sN lu I pM nT uR SA P r o F n e ti l a O ly n (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 2 MAY. 16, 2005 Version: 1.1 SPLC564A HIGH-VOLTAGE DURABLE 240-CHANNEL COMMON DRIVER FOR DOT-MATRIX STN LCD 1. GENERAL DESCRIPTION The SPLC564A is a 240-channel common driver which drives a dot matrix STN LCD panel. By changing the mode, this can be Through the applied to 240- and 200- and 160-channel output. 2. FEATURES Display duty: Up to 1/240 LCD drive voltage: 43V max Built-in switching circuit (to generate -21.5V) Number of LCD drive circuit: 240 Operating voltage: 2.5V to 5.5V Intermediate voltage I/F use of a 43V high-voltage CMOS process technology, a high-voltage drive of +21.5V and -21.5V, centering on VM is possible. used. -21.5V generated from +21.5V with built-in switching Low logic-drive voltage (3.0V) is circuit and external capacity. SPLC563A. Built-in alternating signal generation circuit Pin programmable Output mode change: 240-output mode 160-output mode This device is used together with the segment driver 3. BLOCK DIAGRAM *2, *3 VHL VLL VML *1, *3 VLCDL, R VEEL, R VCC GND id se f nU o C ER sN lu I pM nT uR SA P r o F Built-in display-off function Flex TCP n e 200-output mode ti l a O ly n X1 - X240 LCD Drive Circuit VHR VLR VMR Level shifter Level Shifter Shift register Shift register Shift register Shift register Shift register Logic DISPOFF M/S D Q D Q D Q D Q D Q SR1 ~ SR20 ^ SR21 ~ SR40 SR41 ~ SR200 SR201 ~ SR220 SR221 ~ SR240 Logic Logic Q ^ D Q ^ ^ D Q ^ ^ D Logic Q ^ ^ D Logic Q ^ ^ D Logic Switch circuit Logic Alternating signal generating circuit SHL MODE1 DIO1 DIO2 MODE0 VEO AMP C1 CCL C2 CL M MWS 0 - 4 RESET Logic DOC *1 VLCDL and VLCDR, and VEEL and VEER are internally connected. *2 VHL and VHR, VLL and VLR, and VML and VMR are internally connected. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 3 MAY. 16, 2005 Version: 1.1 SPLC564A 3.1. Internal Block Diagram 3.1.1. LCD drive circuit This circuit selects and outputs the three level signals for the LCD drive. circuit. By a combination of the data in the shift register and M, either VH, VL, or VM is selected and transmitted to the output 3.1.4. Alternating signal generating circuit This circuit generates an alternating signal (M signal) for LCD display. To suppress cross-talk, the signal is alternated in a unit By connecting MWS0 from several lines to several tens of lines. be alternated. to MWS4 pins to VCC or GND, the desired number of signals can When alternating signals are externally input, all pins (MWS0 to MWS4) are connected to GND. 3.1.2. Level shifter This boosts a 2.5V - 5.5V signal to a high-voltage signal for LCD drive. 3.1.3. Shift register This is a 240-bit bidirectional shift register circuit. sequentially shifted by shift clock CL. determined by the SHL pin. The first line marker signal output from the DIO1, pin and DIO2 pin is id se f nU o C ER sN lu I pM nT uR SA P r o F The shift direction is n e ti l a O ly n (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 4 MAY. 16, 2005 Version: 1.1 SPLC564A 4. SIGNAL DESCRIPTIONS Classification Power supply Symbol VLCDL VLCDR VEEL VEER VCC, GND VHL VHR VLL VHR VML VMR VEO PIN No. 238 286 243 281 265 276 239 285 242 282 240, 241 284, 283 244, 245 VEEL, R Output Power supply Input Power supply for LCD drive level VHL, VHR: Selected level (Set to the same voltage as VLCDL, VLCDR.) VEER.) VLL, VLR: Selected level (Set to the same voltage as VEEL, VML, VMR: Non-selected level connect to VEEL, VEER pins. between VLCD and VM. Connected to Power supply I/O Functions VLCDL, VLCDR-VEEL, VEER: Power supply for LCD drive VLCDL, VLCDR: Power supply for switch circuit VCC -GND: Power supply for logic circuit When use built-in switching circuit and generate VEE, VEO pin and reversed and output the voltage input to the voltage Control signal id se f nU o C ER sN lu I pM nT uR SA P r o F don't connect any lines to this pin. C1 C2 246, 247 248, 249 Capacitance switch circuit for generate VEE. this pin. CL M 277 252 MPU Input I/O Shift clock input. clock CL of the shift register. Extension driver or MPU MWS0 264 262 260 258 256 Input MWS1 MWS2 MWS3 MWS4 in the unit of the number of lines. specify the number of lines as zero. Number of lines 0 1 2 3 : 31 MWS4 0 0 0 0 : 1 MWS3 0 0 0 0 : 1 MWS2 0 0 0 0 : 1 MWS1 0 0 1 1 : 1 MWS0 0 1 0 1 : 1 n e ti l a VM voltage is point of reference O ly n If built-in switching circuit is not used, External capacitance should be connected here when using the If built-in switching circuit is not used, don't connect any lines to Data is shifted at the falling edge of shift Inputs or outputs the alternating current for LCD drive output. This pin specifies the cycle of the alternating signal (M signal) The number of lines, which is an integer from 2 to 31, is specified as follows. Usually, specify the number of lines within a range from 10 to 31. When the SPLC564A is driven by an external alternating signal, Line alternating waveform Prohibited 2 lines alternated 3 lines alternated : 31 lines alternated M-pin status Input Output (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 5 MAY. 16, 2005 Version: 1.1 SPLC564A 4.1. PIN Functions (cont) Class Control signal Symbol MODE0 MODE1 PIN No. 267 266 Connected to Type Input Functions Switch terminals for the number of LCD drive output pins MODE0 "H" "H" "L" "L" MODE1 "H" "L" "H" "L" Shift direction 240-output (X1, X2, X3......X238, X239, X240) 200-output (X21, X22, X23......X218, X219, X220) 160-output (X41, X42, X43......X198, X199, X200) Prohibited DIO1 DIO2 280 250 Extension driver or MPU I/O Serial data input output pin SHL "H" level "L" level DIO1 Serial output pin Serial iutput pin DISPOFF id se f nU o C ER sN lu I pM nT uR SA P r o F GND. AMP 273 Input Built-in switching circuit on-off control. VCC. fixex to GND. CCL 278 MPU Input Built-in switching circuit clock input. switching circuit and generate VEE, this pin connect CL pin. If built-in switching circuit is not used, CCL must be fixed to n e ti DIO2 Serial iutput pin Serial output pin l a When use built-in O ly n When use built-in switching circuit, this pin must be fixed to If built-in switching circuit is not used, this pin must be RESET 254 MPU or VCC Input Setting this pin to GND sets initializes the alternating signal (M signal) circuit. A VCC level RESET is normally used. Setting this pin to GND sets LCD drive output X1 to X240 to the VM level. Controls the display-off function, and display-off signal output 271 MPU - Input M/S 279 Input from DOC pin. DOC 269 - Output M/S DOC "H" level When DISPOFF is low level, output low level When DISPOFF is high level, output high level "L" level DISPOFF Until serial data input 16 times output low level from DOC pin 1 2 3 4 5 14 15 16 DIO1, 2 DOC When using M/S is low level, DOC pin should be connect to SEG LSI Dispoff control pin. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 6 MAY. 16, 2005 Version: 1.1 SPLC564A Class Symbol SHL PIN No. 275 Connected to Type Input Functions This pin switches shift directions. SHL MODE0 MODE1 Shift direction Right shift "H" level "H" "H" "L" "H" "L" "H" DIO2->SR1->......->SR240->DIO1 DIO2->SR21->......->SR220->DIO1 DIO2->SR41->......->SR200->DIO1 Left shift "L" level "H" "H" "L" "H" "L" "H" DIO1->SR240->......->SR1->DIO2 DIO1->SR220->......->SR21->DIO2 DIO1->SR200->......->SR41->DIO2 SR1, SR2***SR240 correspond to X1, X2***X240. Note: The 40 or 80 pins invalidated at the 200-output or 160-output mode output the non- selected level synchronized every time; LCD drive output X1 to X12 X13 to x220 X221 to X234 X235 to X240 Note1: Configuring the LCD panel using the SPLC564A when using the selected SEGMENT driver. id se f nU o C ER sN lu I pM nT uR SA P r o F release these pins. 236 - 225 223 - 16 14 - 1 LCD Output LCD drive output n e 1 0 VM ti l a O 0 VM ly n By a combination of the display data and the M signal, when DISPOFF is set to VCC, either VH, VL, or VM is selected and 0 292 - 287 transmitted to the output circuit. M D 1 1 Output level VL VH Note: VH = VHL = VHR VL = VLL = VLR VM = VML = VMR (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 7 MAY. 16, 2005 Version: 1.1 SPLC564A 5. ELECTRICAL SPECIFICATIONS 5.1. Absolute Maximum Ratings Item Power supply voltage for logic circuits Power supply voltage for LCD drive circuits Input voltage 1 Input voltage 2 Input voltage 3 Input voltage 4 Operating temperature Storage temperature Symbol VCC VLCD VEE VT1 VH VL VM TOPR TSTG Rating -0.3 to + 7.0 -0.3 to + 25 -20 to + 0.3 -0.3 to VCC + 0.3 -0.3 to VLCD + 0.3 to VEE -0.3 to + 5.0 -30 to +75 -55 to +110 Unit V V V V Notes 1, 8 1, 3, 8 1, 4, 8 1, 2 1, 5, 8 1, 6, 8 1, 7, 8 Notes: If the LSI is used beyond the above maximum ratings, it may be permanently damaged. Note: 1. Voltage from GND It should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability. 2. Applicable to DIO1, DISPOFF , SHL, M, NWS0, NWS1, NWS2, NWS3, NWS4, RESET , MODE0, MODE1, CL, M/S , AMP, CCL, DIO2 3. Applicable to VLCDL, R pins. 4. Applicable to VEEL , R pins. 5. Applicable to VHL, R pins. 6. Applicable to VLL, R pins. (Caution) 7. Applicable to VML, R pins. Operating the LSI in excess of the absolute maximum rating will result in permanent damage. reliability. Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI 8. Observe the sequence of activation and inactivation for the following power supplies and signals. And this sequence apply to use built-in switching circuit. If the sequence is not observed, it may cause LSI malfunction, permanent damage, or adverse effects. id se f nU o C ER sN lu I pM nT uR SA P r o F VCC 2.5V 2.5V 0ms VLCD, VH 0ms 0ms VM VEE, VL 0ms 0ms 0ms 0ms DISPOFF Input signal, clock, or data Undefined Initialization (Longer than one frame) n e ti l a V V C C V O ly n (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 8 MAY. 16, 2005 Version: 1.1 SPLC564A 5.1.1. Power ON 1). Turn on the power supply in the order of GND - VCC, GND -VLCD (VH), and VM. input GND to the DISPOFF pin. 2). The LCD level forcibly outputs the VM level by the DISPOFF function. 3). The DISPOFF function has a priority even if input signal distortion occurs immediately after VCC input. 4). Then input the predetermined signals to initialize the driver registers. 5). Preparation for normal display is thus completed. In this case, assure a period for more than one frame. At this point, Cancel the DISPOFF function by setting the DISPOFF pin to VCC. VM-VEE is generated automatically. In this case, the levels of VEE (VL), VLCD (VH) and VM must has reached the predetermined respective voltage. 5.1.2. Shut down As a rule, shut down in order opposite to that used for power on. 1). Set the DISPOFF pin to GND. 2). At first shut off the LCD power supply GND-VLCD (VH), at same time GND-VEE (VL) get to VM. 3). Set VCC and the input signal to GND. At this point, VEE (VL), VLCD (VH) and VM pin input must completely drop to 0V. Therefore, an incorrect display may appear at shut down or power on. Since the DISPOFF function is inactivated when the VCC level drops to GND, the LCD output may output a level other than VM. 5.2. DC Characteristics 1 Item Input high voltage Input low voltage Output high-level voltage Output low-level voltage ON resistance between Vi - Yj Input leakage current (1) id se f nU o C ER sN lu I pM nT uR SA P r o F Symbol VIH PINs Min. Typ. Max. VCC Unit V DIO1, DISPOFF , SHL, 0.7 x VCC M, M/S , MWS0-4, n e Next shut off the VM. ti l a O ly n Notes (VCC = 2.5V to 5.5V, GND = 0V, VLCD - VEE = 15V to 43V, TA = -30 to +75) Test Condition RESET VIL CL, MODE0, MODE1, 0 - 0.3 x VCC V DOC , AMP, CCL, DIO2 VOH VOL M, DOC , DIO1, DIO2 VCC - 0.4 - - - V IOH = -0.4mA IOL = 0.4mA ION = 150A 1 M, DOC , DIO1, DIO2 X1 to X240, V pin - 0.4 V RON IIL1 - 0.7 - 2.0 K A DIO1, DISPOFF , SHL, M, M/S , MWS0-4, -5.0 5.0 VIN = VCC to GND RESET , CL, MODE0, MODE1, DOC , AMP, CCL, DIO2 Input leakage current (2) Input leakage consumption (1) ICC1 VCC 10 40 A VCC = 3.3V, VLCD - VEE = 40V, fCL = 19.2KHz, fM = 1.5KHz (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 9 MAY. 16, 2005 Version: 1.1 2 IIL2 VH, VL, VM, C1, C2 -25 25 A SPLC564A Item Current consumption (2) Symbol ICC2 VCC PINs Min. Typ. 20 Max. 50 Unit A Test Condition VCC = 5.0V, VLCD - VEE = 40V, fCL = 19.2KHz, fM = 1.5KHz Current consumption (3) ILCD VLCD 25 50 A VCC = 3.3V, VLCD - VEE = 40V, fCL = 19.2KHz, fM = 1.5KHz Note1: This is a resistance value between the X and V pins (either of VH, VL, or VM) when a load current is applied to one of X1 to X240 pins. These values are regulated under the conditions of VLCD = VH = 21.75V, VEE = VL = -18.5V, VM = 1.75V, GND = 0V, Use VH, VL, and VM in the range of VLCD VMVH-VM = 21.5 to 7.5V, VEE - VMVL - VM = -21.5 to -7.5V, with the relation of VH > VM > VL. Note2: The current applied between the input and output is excluded. When an input to a CMOS gate is at an intermediate level, through current flows between the power supplies and the power supply current increases. Therefore, use VIH = VCC and VIL = GND. Note3: The voltage relationship of each signal is as follows: Segment Voltage Notes V0 (5.0V) VCC (3.3V) VM (3.0V) V1 (1.0V) GND (0.0V) id se f nU o C ER sN lu I pM nT uR SA P r o F Segment wavform Common wavform Normal display period Display-off period Normal display period Display-off period n e ti l a Common Voltage VH (23.0V) O ly n VCC (3.3V) VM (3.0V) GND (0.0V) VL (-17.0V) (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 10 MAY. 16, 2005 Version: 1.1 SPLC564A 5.3. AC Characteristics 1 (VCC = 2.5V to 5.5V, GND = 0V, VLCD - VEE = 15V to 43V, TA = -30C to +75C) Item Clock cycle time Clock high-level width Clock low-level width CL rising time CL falling time Data setup time Data hold time Data output delay time M output delay time M setup time M hold time Symbol tCYC tCWH tCWL tr tf tDS tDH tDD tMD tMS tMH PINs CL CL CL CL CL DIO1, DIO2, CL DIO1, DIO2, CL DIO1, DIO2, CL M, CL M, CL M, CL Min. 400 25 370 100 10 20 20 Max. 30 30 Unit ns ns ns ns ns Note 200 DOC delay time 1 DOC delay time 2 5.4. AC Characteristics 2 Item Output delay time 1 5.5. AC Characteristics 3 Item Output delay time 1 Notes: *1, *2. The following timing is regulated with the circuit at the right connected. id se f nU o C ER sN lu I pM nT uR SA P r o F tDOC1 tDOC2 DISPOFF , DOC n e Max. 1.2 200 ti l a ns ns ns ns ns ns ns 300 O ly n *1 *1 *2 *2 Note *2 DIO1, DIO2, DOC - 300 ns (VCC = 2.5V to 4.5V, GND = 0V, VLCD - VEE = 43V, TA = -30C to +75C) Min. Unit s Symbol tpd1 PINs X (n), M (VCC = 4.5V to 5.5V, GND = 0V, VLCD - VEE = 43V, TA = -30C to +75C) Min. Max. 0.7 Unit s Note *2 Symbol tpd1 PINs X (n), M Test Point *1: 30pF *2: 100pF Figure 4: Load circuit (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 11 MAY. 16, 2005 Version: 1.1 SPLC564A tf 0.7 x VCC tCWL tr tCWH tCYC CL 0.3 x VCC tDS tDH DIO1 DIO2 0.7 x VCC 0.3 x VCC tDD DIO1 DIO2 VOH VOL M (During output) X(n) CL M (During input) id se f nU o C ER sN lu I pM nT uR SA P r o F tMD VOH VOL n e ti l a O ly n tpd1 0.7 x VH 0.3 x VH 0.7 x VL 0.3 x VL 0.7 x VCC 0.3 x VCC tMS tMH 0.7 x VCC 0.3 x VCC 0.7 x VCC 0.3 x VCC DISPOFF 0.3 x VCC DIO1 DIO2 (During input) tDOC1 0.3 x VCC tDOC2 0.7 x VCC DOC 0.3 x VCC (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 12 MAY. 16, 2005 Version: 1.1 SPLC564A 5.6. Terminal Configuration 5.6.1. Terminal configuration (1) VCC V LC D Input Data Input Terminal 1 Applicable terminals: CL, CCL, SHL, MODE0, 1, AMP DISPOFF, RESET, MWS0-4, M/S V LC D id se f nU o C ER sN lu I pM nT uR SA P r o F Input Terminal 3 Applicable terminals: V HR, L V LC D VM Level VEE VEE Input Terminal 2 GND n e ti VEE l a VH Level O VL ly n *VHR terminal connect with V HL terminal in LSI. Level Input Terminal 2 Applicable terminals: VMR, L *VMR terminal connect with V ML terminal in LSI. Applicable terminals: VMR, L *VMR terminal connect with V ML terminal in LSI. Output Terminal 1 Applicable terminals: DOC (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 13 MAY. 16, 2005 Version: 1.1 SPLC564A 5.6.2. Terminal Configuration (2) VCC Input Data VCC GND I/O id se f nU o C ER sN lu I pM nT uR SA P r o F GND I/O Terminal 1 Applicable terminals: DIO1, DIO2, M VLCD VM V LCD V LCD VLCD VEE VLCD I/O VEE VEE n e ti l a Data Output enable O ly n VM VEE V LCD VM VEE VEE VM I/O Terminal 2 Applicable terminals: C1 I/O Terminal 3 Applicable terminals: C2 V LCD VH VM V LCD I/O VEE VEE VL VM LCD drive Output Terminal Applicable terminals: X1 to X240 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 14 MAY. 16, 2005 Version: 1.1 SPLC564A 6. APPLICATION CIRCUIT 6.1. Application Example Figure 1 shows an application example 320 x 3 (collar) x 240 dot Half VGA Size STN color panel. This panel configured SPLC564A X 1 piece and SPLC563 x 3 pieces. SPLC564A generates M signal and DOC signal. VEO pin is connected VEE pin and VL pin. M signal pin is connected M signal pin of SPLC563A. SPLC564A is able to generates - voltage by external capacitor. CA Note1: When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1F for each IC (between VCC and GND, V0 and GND, VLCD and GND, and VEE and GND) Note2: In addition, for the power supply circuit, connect a capacitor of several F or several tens of F between the liquid-crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid-crystal drive power supply and level power supply in turned on and when it is turned off. Note3: When using external capacitor to generate VEE, you must connect a capacitor of several F or several tens of F between the VEE and GND. id se f nU o C ER sN lu I pM nT uR SA P r o F C0 CL CCL RESET DISPOFF AMP M/S DOC M NWS4-0 VHL, R VML, R VLL, R C1 C2 COM1 COM2 COM3 LCD panel 320 x 3 (collar) x 240 1/240 duty VLCD V0 Y320 - Y1 Y320 - Y1 Y320 - Y1 SHL SHL SHL VCC VM V1 GND EIO2 MODE GND SPLC563A (No. 1) EIO1 EIO2 MODE GND SPLC563A (No. 2) EIO1 EIO2 MODE GND SPLC563A (No. 3) EIO1 VCC VCC VCC Controller Figure 1: Application Example (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 15 SEG958 SEG959 SEG960 SEG1 SEG2 SEG3 COM238 COM239 COM240 n e ti V0L, R l a O ly n SHL DIO1 VLCDL.R GND VEEL,R VEO VCC SPLC564A DIO2 Power supply circuit X1 - X240 M CL1 CL2 D11-0 BS DISPOFF VML, R M CL1 CL2 D11-0 BS DISPOFF VML, R M CL1 CL2 D11-0 BS DISPOFF VML, R V0L, R V1L, R V0L, R V1L, R V1L, R MWS4 - 0 FLM DISP D11-0 CL2 CL1 MAY. 16, 2005 Version: 1.1 SPLC564A 6.2. Power Supply Circuit Example +21V VLCD VH DC-DC CONVERTER +3.0V ~ 5.0V VCC +2.7V ~ 5.5V V0 SEG Driver id se f nU o C ER sN lu I pM nT uR SA P r o F V1 GND GND VL External Capacitor (2.2~4.7F) VEE VM n e ti l a COM Driver SPLC564A O ly n VEO C1 C2 External Capacitor (2.2~4.7F) Figure 2: Power Supply Circuit Example (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 16 MAY. 16, 2005 Version: 1.1 SPLC564A 7. PACKAGE/PAD LOCATIONS 7.1. Package/PAD Locations Please contact Sunplus sales representatives for more information. 7.2. Ordering Information Product Number SPLC564A-C SPLC564A-PT112 SPLC564A-PJ061 Package Type Chip form Package form - TCP 5SP, 70W Package form - COF 5SP, 70W id se f nU o C ER sN lu I pM nT uR SA P r o F n e ti l a O ly n (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 17 MAY. 16, 2005 Version: 1.1 SPLC564A 8. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders. Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only. id se f nU o C ER sN lu I pM nT uR SA P r o F n e ti l a O ly n (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 18 MAY. 16, 2005 Version: 1.1 SPLC564A 9. REVISION HISTORY Date MAY. 16, 2005 Revision # 1.1 Description 1. Add package information "SPLC564A-PJ061" 2. Modify Terminal configuration (1) 3. Modify Terminal Configuration (2) 4. Correct PIN No. 5. Delete SPLC564A-PC011 ordering information FEB. 20, 2004 1.0 1. Add package information 2. Remove "Preliminary" JUN. 19, 2003 0.3 1. Correct "4.2 Ordering Information" 2. Remove "7. PACKAGE/PAD LOCATIONS" JAN. 29, 2003 0.2 1. Correct type error 2. Correct "Bumped pad height": 17 to 18 Original Page 17 13 14 5-7 17 JUL. 11, 2001 id se f nU o C ER sN lu I pM nT uR SA P r o F 0.1 n e ti l a O 7 ly n 7 17 3 17 24 (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 19 MAY. 16, 2005 Version: 1.1 |
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